WO2015035955A1 - 内存模组访问方法及装置 - Google Patents

内存模组访问方法及装置 Download PDF

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Publication number
WO2015035955A1
WO2015035955A1 PCT/CN2014/086592 CN2014086592W WO2015035955A1 WO 2015035955 A1 WO2015035955 A1 WO 2015035955A1 CN 2014086592 W CN2014086592 W CN 2014086592W WO 2015035955 A1 WO2015035955 A1 WO 2015035955A1
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Prior art keywords
memory
scheduler
channel
access request
memory access
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PCT/CN2014/086592
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English (en)
French (fr)
Inventor
张立新
王聪
侯锐
张科
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to JP2016541798A priority Critical patent/JP2016531372A/ja
Priority to KR1020167009479A priority patent/KR20160054007A/ko
Priority to EP14844807.9A priority patent/EP3035193A4/en
Publication of WO2015035955A1 publication Critical patent/WO2015035955A1/zh
Priority to US15/070,532 priority patent/US20160196073A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a memory module access method and apparatus.
  • the multi-channel memory system includes a plurality of memory channels, and the memory controller communicates with the memory modules through a plurality of memory channels.
  • the mapping relationship between the memory address and the channel is determined in advance according to the division of the memory module, so that the load of each channel is balanced.
  • the corresponding channel is determined as the target channel according to the memory address in the memory access request, and the memory access request is sent through the target channel.
  • the mapping relationship between the memory address and the channel can be determined by the value of a certain bit in the memory address. For example, a memory access request with the seventh bit of the memory address being "0" is sent to the target memory module through channel 0; a memory access request with the seventh bit of the memory address being "1" is sent to the target memory module through channel 1.
  • the channels between the memory module and the memory controller are independent of each other, when multiple memory access requests are distributed unevenly among multiple channels, for example, n consecutive memory access requests are received through the channel. 1 Sending to the target memory module will cause channel 1 to be congested. Other channels are idle, causing waste of bandwidth resources and resulting in low memory access bandwidth.
  • the embodiment of the present invention provides a method and an apparatus for accessing a memory module, which can solve the problem of waste of bandwidth resources when a plurality of memory access requests received are unbalanced among multiple channels in the prior art, resulting in memory Access to lower bandwidth issues.
  • an embodiment of the present invention provides a memory module access method, which is applied to a memory system, the memory system includes at least a first scheduler and a second scheduler, the first scheduler corresponds to a first memory channel, the second scheduler corresponds to a second memory channel, and each memory channel corresponds to a memory a module, the memory system includes a plurality of memory modules, a transmission link is established between the plurality of memory modules, and a transmission link is established between the first scheduler and the second scheduler;
  • the method includes:
  • the first scheduler receives a memory access request, and sends the memory access request by using a second memory channel corresponding to the second scheduler.
  • the first scheduler receives a memory access request, and sends the memory access request by using a second memory channel corresponding to the second scheduler, including:
  • the first scheduler receives at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request;
  • the second memory access request When the first memory access request is sent by the first memory channel corresponding to the first scheduler, the second memory access request is in a to-be-sent state; if the second memory channel corresponding to the second scheduler is in a In the idle state, the first scheduler sends the second memory access by using a second memory channel corresponding to the second scheduler.
  • the first scheduler sends a memory channel occupation request to the second scheduler to request to use the second memory channel corresponding to the second scheduler to send the second memory access request;
  • the first scheduler receives an acknowledgement response returned by the second scheduler regarding the memory channel occupancy request.
  • the destination address of the second memory access request is located in a memory module corresponding to the first memory channel.
  • the first scheduling The device is configured with at least two paths through which the first memory channel and the second memory channel are connected.
  • an embodiment of the present invention provides a memory module access method, which is applied to a memory system, where the memory system includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to a first memory channel.
  • the second scheduler corresponds to a second memory channel, and each memory channel corresponds to one memory module;
  • the memory system includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules;
  • the method includes:
  • the first scheduler receives at least two memory access requests, including a first memory access request and a second memory access request;
  • the first scheduler sends the first memory access request through the first memory channel, and sends the second memory access request through the second memory channel.
  • the first scheduler sends the second memory access request by using the second memory channel, including:
  • the method before the sending, by the second memory channel, the second memory access request, the method includes:
  • the first scheduler sends a memory channel occupation request to the second scheduler to request to use the second memory channel corresponding to the second scheduler to send the second memory access request;
  • the destination address of the second memory access request is located in a memory module corresponding to the first memory channel.
  • each scheduler configuration There are multiple paths through which a connection is established with each memory channel.
  • an embodiment of the present invention provides a memory module access method, which is applied to a memory system, where the memory system includes at least a first memory channel and a second memory channel, each of which The storage channel corresponds to a memory module; the memory system includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules;
  • the method includes:
  • Receiving at least two memory access requests including a first memory access request and a second memory access request, where the destination addresses of the first memory access request and the second memory access request are located in a memory module corresponding to the first memory channel;
  • the sending, by the second memory channel, the second memory access request includes:
  • the memory system includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to the first memory channel, where The second scheduler corresponds to the second memory channel;
  • the method further includes:
  • the first scheduler sends a memory channel occupation request to the second scheduler to request to use the second memory channel corresponding to the second scheduler to send the second memory access request;
  • each scheduler is configured with multiple paths, by using the multiple The paths establish a connection with each memory channel.
  • a fourth aspect of the present invention provides a memory controller, which is applied to a memory system, where the memory controller includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to a first memory channel.
  • the second scheduler corresponds to the second memory channel, and each memory channel corresponds to one memory module;
  • the memory system includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules, A transmission chain is established between a scheduler and a second scheduler road;
  • the first scheduler is configured to acquire the number of memory access requests to be sent by the second scheduler
  • the first scheduler is further configured to receive a memory access request, and send the memory access request by using a second memory channel corresponding to the second scheduler.
  • the first scheduler is configured to receive at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request;
  • the first scheduler is further configured to: when the second memory request is in a to-be-sent state, if the second memory channel corresponding to the second scheduler is in an idle state, the second scheduler corresponds to the second The second memory channel sends the second memory access request.
  • the first scheduler is further configured to send a memory channel occupation request to the second scheduler to request to occupy the second scheduler Transmitting, by the corresponding second memory channel, the second memory access request;
  • the first scheduler is further configured to receive an acknowledgement response returned by the second scheduler regarding the memory channel occupation request.
  • the destination address of the second memory access request received by the first scheduler is located in a memory module corresponding to the first memory channel.
  • the first scheduling The device is configured with at least two paths through which the first memory channel and the second memory channel are connected.
  • an embodiment of the present invention provides a memory controller, where the memory controller includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to a first memory channel, and the second scheduler Corresponding to a second memory channel, each memory channel corresponding to a memory module; the memory controller includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules;
  • the first scheduler is configured to receive at least two memory access requests, including a first memory access Requesting a request and a second memory access request; transmitting the first memory access request through the first memory channel, and transmitting the second memory access request through the second memory channel.
  • the first scheduler is configured to send the second memory access request by using the second memory channel when the second memory channel is in an idle state.
  • the first scheduler is further configured to send a memory channel occupation request to the second scheduler to request to occupy the second scheduler Transmitting, by the corresponding second memory channel, the second memory access request;
  • the destination address of the second memory access request received by the first scheduler is located in a memory module corresponding to the first memory channel .
  • the memory controller Each of the schedulers is configured with a plurality of paths through which a connection is established with each of the memory channels.
  • an embodiment of the present invention provides a memory controller, where the memory controller includes at least a first memory channel and a second memory channel, and each memory channel corresponds to one memory module; a memory module, a transmission link is established between the plurality of memory modules;
  • the memory controller is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, where the destination addresses of the first memory access request and the second memory access request are located in the first memory channel Memory module
  • the memory controller is further configured to send the first memory access request by using the first memory channel, and send the second memory access request by using the second memory channel.
  • the memory controller is specifically configured to send the second memory access request by using the second memory channel when the second memory channel is in an idle state.
  • the memory controller includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to the first memory channel The second scheduler corresponds to the second memory channel;
  • the first scheduler is configured to send a memory channel occupation request to the second scheduler to request to use the second memory channel corresponding to the second scheduler to send the second memory access request;
  • the first scheduler is further configured to receive an acknowledgement response returned by the second scheduler regarding the memory channel occupation request.
  • a third possible implementation manner how many schedulers are configured in the memory controller And a path through which the connection is established with each of the memory channels.
  • an embodiment of the present invention provides a central processing unit CPU, which is applied to a memory system, where the CPU includes a memory controller, and the memory controller includes at least a first scheduler and a second scheduler, where a scheduler corresponding to the first memory channel, the second scheduler corresponding to the second memory channel, each memory channel corresponding to a memory module; the memory system comprising a plurality of memory modules, between the plurality of memory modules Establishing a transmission link, and establishing a transmission link between the first scheduler and the second scheduler;
  • the first scheduler is configured to acquire the number of memory access requests to be sent by the second scheduler
  • the first scheduler is further configured to receive a memory access request, and send the memory access request by using a second memory channel corresponding to the second scheduler.
  • the first scheduler is configured to receive at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request;
  • the first scheduler is further configured to: when the second memory request is in a to-be-sent state, if the second memory channel corresponding to the second scheduler is in an idle state, the second scheduler corresponds to the second The second memory channel sends the second memory access request.
  • the first scheduler is further configured to send a memory channel occupation request to the second scheduler to request occupation Sending, by the second memory channel corresponding to the second scheduler, the second memory access request;
  • the first scheduler is further configured to receive an acknowledgement response returned by the second scheduler regarding the memory channel occupation request.
  • the destination address of the second memory access request received by the first scheduler is located in a memory module corresponding to the first memory channel,
  • the first memory channel is a memory channel corresponding to the first scheduler.
  • the first scheduling The device is configured with at least two paths through which the first memory channel and the second memory channel are connected.
  • an embodiment of the present invention provides a CPU, including a memory controller, where the memory controller includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to a first memory channel, The second scheduler corresponds to the second memory channel, and each of the memory channels corresponds to one memory module; the memory controller includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules;
  • the first scheduler is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, and send the first memory access request through the first memory channel, by using the second memory The channel sends the second memory access request.
  • the first scheduler is configured to send the second memory access request by using the second memory channel when the second memory channel is in an idle state.
  • the first scheduler is further configured to send a memory channel occupation request to the second scheduler to request to occupy the second scheduler Transmitting, by the corresponding second memory channel, the second memory access request;
  • the destination address of the second memory access request received by the first scheduler is located in a memory module corresponding to the first memory channel .
  • the memory controller Each of the schedulers is configured with a plurality of paths through which a connection is established with each of the memory channels.
  • an embodiment of the present invention provides a CPU, including a memory controller, where the memory controller includes at least a first memory channel and a second memory channel, and each memory channel corresponds to one memory module;
  • the device includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules;
  • the memory controller is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, where the destination addresses of the first memory access request and the second memory access request are located in the first memory channel Memory module
  • the memory controller is further configured to send the first memory access request by using the first memory channel, and send the second memory access request by using the second memory channel.
  • the memory controller is specifically configured to send the second memory access request by using the second memory channel when the second memory channel is in an idle state.
  • the memory controller includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to the first memory channel The second scheduler corresponds to the second memory channel;
  • the first scheduler is configured to send a memory channel occupation request to the second scheduler to request to use the second memory channel corresponding to the second scheduler to send the second memory access request;
  • the first scheduler is further configured to receive an acknowledgement response returned by the second scheduler regarding the memory channel occupation request.
  • a third possible implementation manner how many schedulers are configured in the memory controller And a path through which the connection is established with each of the memory channels.
  • Memory module access method and device provided by embodiment of the present invention when receiving multiple memories When accessing a request, multiple memory access requests received can be sent through multiple memory channels. According to the method provided by the embodiment of the present invention, even when a plurality of received memory access requests are distributed unevenly among a plurality of memory channels, the received memory access requests can be performed by using other memory channels in an idle state. Send, thereby increasing bandwidth resource utilization and increasing memory access bandwidth.
  • FIG. 1 and FIG. 2 are schematic flowcharts of a method for accessing a memory module according to Embodiment 1 of the present invention
  • FIG. 3 and FIG. 4 are block diagrams showing the structure of a memory controller according to Embodiment 2 of the present invention.
  • FIG. 5 and FIG. 6 are block diagrams showing the structure of a CPU according to Embodiment 3 of the present invention.
  • FIG. 7 and FIG. 8 are schematic flowcharts of a method for accessing a memory module according to Embodiment 4 of the present invention.
  • FIG. 9 is a structural block diagram of a memory controller according to Embodiment 5 of the present invention.
  • FIG. 10 is a structural block diagram of a CPU according to Embodiment 6 of the present invention.
  • FIG. 11 and FIG. 12 are schematic flowcharts of a method for accessing a memory module according to Embodiment 7 of the present invention.
  • FIG. 13 is a structural block diagram of a memory controller according to Embodiment 8 of the present invention.
  • FIG. 14 and FIG. 15 are block diagrams showing the structure of a CPU according to Embodiment 9 of the present invention.
  • FIG. 16 is a structural diagram of a dual channel memory system according to Embodiment 10 of the present invention.
  • FIG. 17 is a structural diagram of a three-channel memory system according to Embodiment 11 of the present invention.
  • An embodiment of the present invention provides a memory module access method, which is applied to a memory system, where the memory system includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to a first memory channel, and the first The second scheduler corresponds to the second memory channel, and each of the memory channels corresponds to one memory module; the memory system includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules, the first schedule A transmission link is established between the second scheduler and the second scheduler.
  • the method includes:
  • the first scheduler acquires, by the second scheduler, the number of memory access requests to be sent.
  • the first scheduler receives a memory access request, and sends the memory access request by using a second memory channel corresponding to the second scheduler.
  • the memory system includes multiple schedulers, and a communication link is established between the multiple schedulers, so that each scheduler can acquire the number of memory access requests to be sent in other schedulers. Therefore, after receiving the memory access request, the idle memory channel can be determined, and the memory access request is sent through the free memory channel.
  • the embodiment of the present invention further provides a more detailed memory module access method. As shown in FIG. 2, the method includes:
  • the first scheduler obtains the number of the memory access requests to be sent by the other scheduler in real time, where the first scheduler is any one of the multiple schedulers, and the other scheduler is the The remaining schedulers of the plurality of schedulers except the first scheduler.
  • the first scheduler receives at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request.
  • the destination address of the memory access request received by the first scheduler is located in the memory module corresponding to the first scheduler itself, that is, if the first scheduler is to be The memory channel is recorded as the first memory channel, and the destination addresses of the first memory access request and the second memory access request are all located in the memory module corresponding to the first memory channel.
  • the first scheduler sends the first memory access request by using the first memory channel, and the second memory access request is in a to-be-sent state.
  • the first scheduler queries a status of a memory channel corresponding to another scheduler, and determines The auxiliary scheduler, where the corresponding memory channel of the auxiliary scheduler is in an idle state.
  • the first scheduler may determine the auxiliary scheduler by using the following method: the first scheduler queries the number of memory access requests to be sent by other schedulers, and determines that the number of memory access requests to be sent is 0. Auxiliary scheduler.
  • the determined auxiliary scheduler is recorded as the second scheduler, and the current number of memory access requests to be sent by the second scheduler is 0, and the memory channel corresponding to the second scheduler is used. Is in an idle state.
  • the current number of memory access requests to be sent by the second scheduler is 0, indicating that the memory channel corresponding to the second scheduler is in an absolute idle state. It should be emphasized that, as an alternative, when the memory channel corresponding to the second scheduler is in a relatively idle state (for example, the number of memory access requests to be sent in the second scheduler is not 0, but the second The number of memory access requests to be sent in the scheduler is much lower than the number of memory access requests to be sent in the first scheduler, and the first scheduler may still determine the second scheduler as a secondary scheduler. A part of the memory access request received by itself is sent through the memory channel corresponding to the second scheduler.
  • part of the to-be-sent memory access requests in the first scheduler may be forwarded to the auxiliary scheduler in time, so that the first The scheduler caches more memory access requests and increases the communication capacity of the memory system.
  • the first scheduler sends a memory channel occupation request to the second scheduler to request to use the second memory channel corresponding to the second scheduler to send the second memory access request.
  • the second scheduler determines that the corresponding memory channel is in an idle state, allowing the first scheduler to occupy a second memory channel corresponding to the second scheduler, and sending the memory channel to the first scheduler. Occupy the confirmation response of the request.
  • the first scheduler receives an acknowledgement response returned by the second scheduler regarding the memory channel occupation request.
  • the first scheduler sends the second memory access request by using a second memory channel corresponding to the second scheduler.
  • the first scheduler when the first scheduler receives multiple memory access requests in one scheduling time slot, the first memory access request received is sent through its corresponding memory channel.
  • the second received memory access request is sent through the memory channel corresponding to the other scheduler.
  • the first scheduler may also send the first received memory access request through a memory channel corresponding to another scheduler, and access the second received memory access.
  • the request is sent through its corresponding memory channel.
  • the first scheduler may send the received multiple memory access requests preferentially through the memory channels corresponding to the other schedulers, as long as there are enough free memory channels.
  • the method provided by this embodiment may be used to send a memory access request received by any of the schedulers through any idle memory channel. The specific method for allocating the memory channel is not limited in this embodiment.
  • the memory module corresponding to the second scheduler receives the second memory access request, and according to the destination address in the second memory access request, the first link is performed through a transmission link between the memory modules.
  • the second memory access request is sent to the destination memory module, that is, the memory module corresponding to the first scheduler.
  • each scheduler is configured with multiple paths, and a connection is established with the multiple memory channels through the multiple paths, so that each scheduler can pass the memory corresponding to other schedulers.
  • the channel sends a memory access request.
  • the memory module access method provided in this embodiment can be applied to all multi-channel memory systems with interconnected paths.
  • multiple schedulers in this embodiment may be integrated into one total scheduler, thereby further improving the degree of association between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • each scheduler can obtain the number of memory access requests to be sent in other schedulers; when multiple memory access requests are received, multiple memory access requests can be received. Send through multiple memory channels.
  • multiple received memory access requests can be allocated to multiple memory channels for transmission, thereby improving bandwidth resource utilization and improving memory access bandwidth.
  • the embodiment of the present invention provides a memory controller, which is applied to a memory system, and can implement the memory module access method shown in FIG. 1 and FIG. 2.
  • the memory controller includes at least a first scheduler. 31 and the second scheduler 32, the first scheduler 31 corresponds to the first memory channel, the second scheduler 32 corresponds to the second memory channel, and each memory channel corresponds to one memory module; a memory module, a transmission link is established between the plurality of memory modules, and a transmission link is established between the first scheduler 31 and the second scheduler 32;
  • the first scheduler 31 is configured to acquire the number of memory access requests to be sent by the second scheduler.
  • the first scheduler 31 is further configured to receive a memory access request, and send the memory access request by using a second memory channel corresponding to the second scheduler.
  • the memory controller includes a plurality of schedulers. As shown in FIG. 4, the memory controller may further include a plurality of schedulers, such as a third scheduler 33, a fourth scheduler 34, and the like.
  • a communication link is established between the schedulers in the memory system, so that each scheduler can acquire the number of memory access requests to be sent in other schedulers, so that after receiving the memory access request, it can be determined.
  • the first scheduler 31 is configured to receive at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request;
  • the first scheduler 31 is further configured to: when the second memory request is in a to-be-sent state, if the second memory channel corresponding to the second scheduler 32 is in an idle state, pass the second scheduler 32. The corresponding second memory channel sends the second memory access request.
  • the first scheduler 31 is further configured to send a memory channel occupation request to the second scheduler 32 to request to occupy the second memory channel corresponding to the second scheduler 32 to send the second memory access. Request;
  • the first scheduler 31 is further configured to receive an acknowledgement response returned by the second scheduler 32 regarding the memory channel occupation request.
  • the first scheduler 31 when the first scheduler 31 receives multiple memory accesses in one scheduling time slot, please When the time is up, the first scheduler 31 sends the received first memory access request through its corresponding memory channel, and sends the second received memory access request through the memory channel corresponding to the other scheduler.
  • the first scheduler 31 may also send the first received memory access request through a memory channel corresponding to another scheduler, and the second received memory.
  • the access request is sent through its corresponding memory channel.
  • the first scheduler 31 may preferentially send the received multiple memory access requests through the memory channels corresponding to other schedulers as long as there are enough free memory channels.
  • the method provided by this embodiment may be used to send a memory access request received by any of the schedulers through any idle memory channel. The specific method for allocating the memory channel is not limited in this embodiment.
  • the destination address of the second memory access request received by the first scheduler 31 is located in a memory module corresponding to the first memory channel.
  • each scheduler is configured with multiple paths, and the multiple channels are connected to the multiple memory channels, so that each scheduler can pass the memory corresponding to other schedulers.
  • the channel sends a memory access request.
  • the first scheduler 31 is configured with at least two paths, and the first memory channel and the second memory channel are connected through the at least two paths.
  • the memory controller provided in this embodiment can be applied to all multi-channel memory systems with interconnected paths.
  • multiple schedulers in the memory controller can be integrated into one total scheduler, thereby further improving the degree of connection between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • Each scheduler in the memory controller provided by the embodiment of the present invention may acquire the number of memory access requests to be sent in other schedulers; when receiving multiple memory access requests, the received multiple memory access requests may be received. Multiple memory channels are sent.
  • the memory controller provided by the embodiment of the present invention can allocate a plurality of received memory access requests to multiple memory channels for transmission when receiving multiple memory access requests, thereby improving bandwidth resource utilization and improving memory access. bandwidth.
  • the embodiment of the present invention provides a CPU, which is applied to a memory system, and can implement the method shown in FIG. 1 and FIG. 2.
  • the CPU includes a memory controller 50
  • the memory controller 50 includes a first scheduler 51 and a second scheduler 52
  • the first scheduler 51 corresponds to a first memory channel
  • the second scheduler 52 corresponds to a second memory channel
  • each memory channel corresponds to a memory module
  • the memory system includes a plurality of memory modules, a transmission link is established between the plurality of memory modules, and a transmission link is established between the first scheduler 51 and the second scheduler 52;
  • the first scheduler 51 is configured to acquire the number of memory access requests to be sent by the second scheduler 52.
  • the first scheduler 51 is further configured to receive a memory access request, and send the memory access request by using a second memory channel corresponding to the second scheduler.
  • the memory controller includes a plurality of schedulers. As shown in FIG. 6, the memory controller may further include a plurality of schedulers, such as a third scheduler 53, a fourth scheduler 54, and the like.
  • a communication link is established between the schedulers in the memory system, so that each scheduler can acquire the number of memory access requests to be sent in other schedulers, so that after receiving the memory access request, it can be determined.
  • the first scheduler 51 is configured to receive at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request.
  • the first scheduler 51 is further configured to: when the second memory request is in a to-be-sent state, if the memory channel corresponding to the second scheduler 52 is in an idle state, the second scheduler 52 corresponds to The memory channel sends the second memory access request.
  • the first scheduler 51 is further configured to send a memory channel occupation request to the second scheduler 52 to request to occupy the second memory channel corresponding to the second scheduler 52 to send the second memory access. Request;
  • the first scheduler 51 is further configured to receive an acknowledgement response returned by the second scheduler 52 regarding the memory channel occupation request.
  • the destination address of the second memory access request received by the first scheduler 51 is located in a memory module corresponding to the first memory channel.
  • the first scheduler when the first scheduler receives multiple memory access requests in one scheduling time slot, the first memory access request received is sent through its corresponding memory channel, and the second received memory is received. Access requests are sent through the memory channel corresponding to other schedulers.
  • the first scheduler may also send the first received memory access request through a memory channel corresponding to another scheduler, and access the second received memory access.
  • the request is sent through its corresponding memory channel.
  • the first scheduler may send the received multiple memory access requests preferentially through the memory channels corresponding to the other schedulers, as long as there are enough free memory channels.
  • the method provided by this embodiment may be used to send a memory access request received by any of the schedulers through any idle memory channel. The specific method for allocating the memory channel is not limited in this embodiment.
  • each scheduler in the memory controller of this embodiment is configured with multiple paths through which the connection is established with the plurality of memory channels.
  • the first scheduler is configured with at least two paths, and the first memory channel and the second memory channel are connected through the at least two paths.
  • multiple schedulers in the memory controller 50 can be integrated into one total scheduler, thereby further improving the degree of connection between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • the CPU provided by the embodiment of the present invention includes a memory controller, and each of the memory controllers can acquire the number of memory access requests to be sent in other schedulers; when receiving multiple memory access requests, the receiver can receive Multiple memory access requests are sent over multiple memory channels.
  • the CPU provided by the embodiment of the present invention can allocate a plurality of received memory access requests to multiple memory channels for transmission when receiving multiple memory access requests, thereby improving bandwidth resource utilization and improving memory access bandwidth.
  • An embodiment of the present invention provides a memory module access method, which is applied to a memory system, where the memory system includes at least a first scheduler and a second scheduler, where the first scheduler corresponds to a first memory channel, and the first The second scheduler corresponds to the second memory channel, and each memory channel corresponds to one memory module; the memory system includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules.
  • the method includes:
  • the first scheduler receives at least two memory access requests, including a first memory access request and a second memory access request.
  • the first scheduler sends the first memory access request by using the first memory channel, and sends the second memory access request by using the second memory channel.
  • the memory access requests received by the multiple schedulers can be shared by multiple memory channels of the memory system, thereby improving the bandwidth resource utilization of the memory channel.
  • the embodiment of the present invention further provides a more detailed memory module access method. As shown in FIG. 8, the method includes:
  • the first scheduler receives at least two memory access requests, where the at least two memory access requests include a first memory access request and a second memory access request.
  • the destination address of the memory access request received by the first scheduler is located in the memory module corresponding to the first scheduler itself, that is, if the first scheduler is to be The memory channel is recorded as the first memory channel, and the destination addresses of the first memory access request and the second memory access request are all located in the memory module corresponding to the first memory channel.
  • the first scheduler sends the first memory access request by using the first memory channel, and the second memory access request is in a to-be-sent state.
  • the first scheduler sends a memory channel occupation request to the second scheduler to request to use the second memory channel corresponding to the second scheduler to send the second memory access request.
  • the second scheduler is among multiple schedulers in the memory system. Any scheduler.
  • the first scheduler receives multiple memory access requests, it may send a memory channel occupation request to all schedulers in the memory system.
  • the second scheduler is taken as an example for specific example.
  • the second scheduler detects whether the corresponding memory channel is in an idle state; if yes, execute 805; if not, execute 809.
  • the second scheduler allows the first scheduler to occupy a second memory channel corresponding to the second scheduler, and send an acknowledgement response regarding the memory channel occupation request to the first scheduler.
  • the first scheduler receives an acknowledgement response returned by the second scheduler regarding the memory channel occupation request.
  • the first scheduler sends the second memory access request by using a second memory channel corresponding to the second scheduler.
  • the first scheduler when the first scheduler receives multiple memory access requests in one scheduling time slot, the first memory access request received is sent through its corresponding memory channel, and the second received memory is received. Access requests are sent through the memory channel corresponding to other schedulers.
  • the first scheduler may also send the first received memory access request through a memory channel corresponding to another scheduler, and access the second received memory access.
  • the request is sent through its corresponding memory channel.
  • the first scheduler may send the received multiple memory access requests preferentially through the memory channels corresponding to the other schedulers, as long as there are enough free memory channels.
  • the method provided by this embodiment may be used to send a memory access request received by any of the schedulers through any idle memory channel. The specific method for allocating the memory channel is not limited in this embodiment.
  • the memory module corresponding to the second scheduler receives the second memory access request, and according to the destination address in the second memory access request, the first link is performed through a transmission link between the memory modules.
  • the second memory access request is sent to the destination memory module, that is, the memory module corresponding to the first scheduler.
  • the second scheduler rejects the memory channel occupation request sent by the first scheduler.
  • each scheduler is configured with multiple paths, and a connection is established with the multiple memory channels through the multiple paths, so that each scheduler can pass the memory corresponding to other schedulers.
  • the channel sends a memory access request.
  • the memory module access method provided in this embodiment can be applied to all multi-channel memory systems with interconnected paths.
  • multiple schedulers in this embodiment may be integrated into one total scheduler, thereby further improving the degree of association between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • the memory module access method provided by the embodiment of the present invention can share the memory access request received by multiple schedulers through multiple memory channels of the memory system when receiving multiple memory access requests, and pass multiple memory The channel sends the multiple memory access requests to improve bandwidth resource utilization of the memory channel and improve memory access bandwidth.
  • the embodiment of the present invention provides a memory controller, which can implement the method shown in FIG. 7 and FIG. 8.
  • the memory controller includes at least a first scheduler 91 and a second scheduler 92.
  • the first scheduler 91 corresponds to the first memory channel
  • the second scheduler 92 corresponds to the second memory channel
  • each memory channel corresponds to one or more memory modules, and a transmission link is established between the memory modules. .
  • the first scheduler 91 is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, and send the first memory access request by using the first memory channel, by using the The second memory channel sends the second memory access request.
  • the first scheduler 91 is configured to send the second memory access request by using the second memory channel when the second memory channel is in an idle state.
  • the first scheduler 91 is further configured to send a memory channel occupation request to the second scheduler 92 to request to occupy the second memory channel corresponding to the second scheduler 92 to send the second memory access. Request;
  • the destination address of the second memory access request received by the first scheduler 91 is located in a memory module corresponding to the first memory channel.
  • the first scheduler 91 receives multiple memory access requests in one scheduling time slot, the first memory access request received is sent through its corresponding memory channel, and the second received one is received. Memory access requests are sent through the memory channel corresponding to other schedulers.
  • the first scheduler 91 may also send the first received memory access request through a memory channel corresponding to another scheduler, and the second received memory.
  • the access request is sent through its corresponding memory channel.
  • the first scheduler 91 may preferentially send the received multiple memory access requests through the memory channels corresponding to other schedulers as long as there are enough free memory channels.
  • the memory controller provided in this embodiment can be used to send a memory access request received by any of the schedulers through any idle memory channel.
  • the specific allocation method of the memory channel is not limited in this embodiment.
  • each scheduler in the memory controller is configured with multiple paths through which a connection is established with each of the memory channels.
  • the memory controller provided in this embodiment can be applied to all multi-channel memory systems with interconnected paths.
  • multiple schedulers in the memory controller can be integrated into one total scheduler, thereby further improving the degree of connection between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • the memory controller provided by the embodiment of the present invention can share the memory access request received by multiple schedulers through multiple memory channels of the memory system when receiving multiple memory access requests, and through multiple memory channel pairs.
  • the plurality of memory access requests are sent, thereby improving bandwidth resource utilization of the memory channel and improving memory access bandwidth.
  • the embodiment provides a CPU, which can implement the method shown in FIG. 7 and FIG. 8.
  • the CPU includes a memory controller 1000, and the memory controller 1000 includes at least a package.
  • the first scheduler 1001 and the second scheduler 1002 the first scheduler corresponds to a first memory channel
  • the second scheduler corresponds to a second memory channel
  • each scheduler corresponds to one memory channel, and each memory channel Corresponding to one or more memory modules
  • the memory controller includes a plurality of memory modules, and the plurality of memory modules are pre-established with a transmission link.
  • the first scheduler 1001 is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, and send the first memory access request by using the first memory channel, by using the The second memory channel sends the second memory access request.
  • the first scheduler 1001 is configured to send the second memory access request by using the second memory channel when the second memory channel is in an idle state.
  • the first scheduler 1001 receives multiple memory access requests in one scheduling time slot, the first memory access request received is sent through its corresponding memory channel, and the second received one is received. Memory access requests are sent through the memory channel corresponding to other schedulers.
  • the first scheduler 1001 may also send the first received memory access request through a memory channel corresponding to another scheduler, and the second received memory.
  • the access request is sent through its corresponding memory channel.
  • the first scheduler 1001 may preferentially send the received multiple memory access requests through the memory channels corresponding to other schedulers, as long as there are enough free memory channels.
  • the CPU provided in this embodiment may be configured to send a memory access request to any of the schedulers through any idle memory channel. The specific method for allocating the memory channel is not limited in this embodiment.
  • the first scheduler 1001 is further configured to send a memory channel occupation request to the second scheduler 1002 to request to occupy the second memory channel corresponding to the second scheduler 1002 to send the second memory access. Request;
  • the destination address of the second memory access request received by the first scheduler 1001 is located in a memory module corresponding to the first memory channel.
  • each of the schedulers in the memory controller 1000 is configured with multiple paths, and a connection is established with each of the memory channels through the multiple paths.
  • the memory controller provided in this embodiment can be applied to all multi-channel memory systems with interconnected paths.
  • multiple schedulers in the memory controller can be integrated into one total scheduler, thereby further improving the degree of connection between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • the CPU provided by the embodiment of the present invention when receiving multiple memory access requests, can share the memory access requests received by the multiple schedulers through multiple memory channels of the memory system, and the multiple memory channels are used to share the Multiple memory access requests are sent to improve bandwidth resource utilization of memory channels and increase memory access bandwidth.
  • the embodiment of the present invention provides a memory module access method, which is applied to a memory system.
  • the memory system includes at least a first memory channel and a second memory channel, and each memory channel corresponds to a memory module; the memory system includes a plurality of memory modules, wherein a transmission link is established between the plurality of memory modules.
  • the method includes:
  • the first scheduler receives at least two memory access requests, including a first memory access request and a second memory access request, where the destination addresses of the first memory access request and the second memory access request are located at the first The memory module corresponding to the memory channel.
  • the memory module access method provided in this embodiment when the first scheduler receives a plurality of memory access requests, may send the receiving through a memory channel corresponding to another scheduler (for example, the second scheduler in this embodiment). Multiple memory access requests to.
  • the embodiment of the present invention further provides a more detailed memory module access method. As shown in FIG. 12, the method includes:
  • the first scheduler receives at least two memory access requests, including a first memory access request and a second memory access request, where the destination addresses of the first memory access request and the second memory access request are located A memory module corresponding to a memory channel.
  • the first scheduler sends the first memory access request by using the first memory channel, and the second memory access request is in a to-be-sent state.
  • the first scheduler sends a memory channel occupation request to the second scheduler to request to use the second memory channel corresponding to the second scheduler to send the second memory access request.
  • the second scheduler is any one of a plurality of schedulers in the memory system.
  • the first scheduler may send a memory channel occupation request to all schedulers in the memory system.
  • the second embodiment is taken as an example for specific example.
  • the second scheduler detects whether the corresponding memory channel is in an idle state; if yes, execute 1205, and if not, execute 1209.
  • the second scheduler allows the first scheduler to occupy a memory channel corresponding to the second scheduler, and send an acknowledgement response regarding the memory channel occupation request to the first scheduler.
  • the first scheduler receives an acknowledgement response about the memory channel occupation request returned by the second scheduler.
  • the first second memory access request is sent by using a second memory channel corresponding to the second scheduler.
  • the first scheduler when the first scheduler receives multiple memory access requests in one scheduling time slot, the first memory access request received is sent through its corresponding memory channel, and the second received memory is received. Access requests are sent through the memory channel corresponding to other schedulers.
  • the first scheduler may also send the first received memory access request through a memory channel corresponding to another scheduler, and access the second received memory access.
  • the request is sent through its corresponding memory channel.
  • the first scheduler may send the received multiple memory access requests preferentially through the memory channels corresponding to the other schedulers, as long as there are enough free memory channels.
  • the method provided by this embodiment may be used to send a memory access request received by any of the schedulers through any idle memory channel. The specific method for allocating the memory channel is not limited in this embodiment.
  • the memory module corresponding to the second scheduler receives the second memory access request, and according to the destination address in the second memory access request, the first link is performed through a transmission link between the memory modules.
  • the second memory access request is sent to the destination memory module, that is, the memory module corresponding to the first scheduler.
  • the second scheduler rejects the memory channel occupation request sent by the first scheduler.
  • each scheduler is configured with multiple paths, and a connection is established with the multiple memory channels through the multiple paths, so that each scheduler can pass the memory corresponding to other schedulers.
  • the channel sends a memory access request.
  • the memory module access method provided in this embodiment can be applied to all multi-channel memory systems with interconnected paths.
  • multiple schedulers in this embodiment may be integrated into one total scheduler, thereby further improving the degree of association between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • the memory module access method provided by the embodiment of the present invention when the first scheduler receives multiple memory access requests, may receive the multiple received by a memory channel corresponding to another scheduler (for example, the second scheduler). Memory access requests are sent to improve bandwidth resource utilization of memory channels and increase memory access bandwidth.
  • the embodiment of the invention provides a memory controller, which can implement the method shown in FIG. 10 and FIG. 11 , the memory controller includes at least a first memory channel and a second memory channel, and each memory channel corresponds to one or more a memory module; the memory controller includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules.
  • the memory controller is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, where the destination address of the first memory access request and the second memory access request are located in the first memory.
  • the memory module corresponding to the channel;
  • the memory controller is further configured to send the first memory access request by using the first memory channel, and send the second memory access request by using the second memory channel.
  • the memory controller is configured to send the second memory access request by using the second memory channel when the second memory channel is in an idle state.
  • the memory controller includes at least a first scheduler 1301 and a second scheduler 1302, where the first scheduler 1301 corresponds to the first memory channel, and the second scheduler 1302 corresponds to Said second memory channel;
  • the first scheduler 1301 is configured to send a memory channel occupation request to the second scheduler 1302 to request to occupy the second memory channel corresponding to the second scheduler 1302 to send the second memory access request;
  • the first scheduler 1301 is further configured to receive an acknowledgement response returned by the second scheduler 1302 regarding the memory channel occupation request.
  • the first scheduler 1301 receives multiple memory access requests in one scheduling time slot, the first memory access request received is sent through its corresponding memory channel, and the second received one is received. Memory access requests are sent through the memory channel corresponding to other schedulers.
  • the first scheduler 1301 may also send the first received memory access request through a memory channel corresponding to another scheduler, and the second received memory.
  • the access request is sent through its corresponding memory channel.
  • the first scheduler 1301 may preferentially send the received multiple memory access requests through the memory channels corresponding to other schedulers, as long as there are enough free memory channels.
  • the memory controller provided in this embodiment can be used to send a memory access request received by any of the schedulers through any idle memory channel.
  • the specific allocation method of the memory channel is not limited in this embodiment.
  • each scheduler in the memory controller in this embodiment is configured with multiple paths, and a connection is established with each memory channel through the multiple paths.
  • the memory controller provided in this embodiment can be applied to all multi-channel memory systems with interconnected paths.
  • multiple schedulers in the memory controller can be integrated into one total scheduler, thereby further improving the degree of connection between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • the memory controller when the first scheduler in the memory controller receives multiple memory access requests, may receive the memory channel pair corresponding to another scheduler (for example, the second scheduler).
  • the plurality of memory access requests are sent, thereby improving bandwidth resource utilization of the memory channel and improving memory access bandwidth.
  • the embodiment of the present invention provides a CPU, which can implement the method shown in FIG. 10 and FIG. 11.
  • the CPU includes a memory controller 1400, and the memory controller 1400 includes at least a first memory channel and a second memory channel, each memory channel corresponding to one or more memory modules; the memory controller 1400 includes a plurality of memory modules, and a transmission link is established between the plurality of memory modules.
  • the memory controller 1400 is configured to receive at least two memory access requests, including a first memory access request and a second memory access request, where the destination addresses of the first memory access request and the second memory access request are located in the first memory channel Corresponding memory module;
  • the memory controller 1400 is further configured to send the first memory access request by using the first memory channel, and send the second memory access request by using the second memory channel.
  • the memory controller 1400 is specifically configured to send the second memory access request by using the second memory channel when the second memory channel is in an idle state.
  • the memory controller 1400 includes at least a first scheduler 1401 and a second scheduler 1402, where the first scheduler 1401 corresponds to the first memory channel, and the second scheduler 1402 corresponds to The second memory channel;
  • the first scheduler 1401 is configured to send a memory channel occupation request to the second scheduler 1402 to request to occupy the second memory channel corresponding to the second scheduler 1402 to send the second memory access request;
  • the first scheduler 1401 is further configured to receive an acknowledgement response returned by the second scheduler 1402 regarding the memory channel occupation request.
  • the first scheduler 1401 receives multiple memory access requests in one scheduling time slot
  • the first memory access request received is sent through its corresponding memory channel, and the second received one is received.
  • Memory access requests are sent through the memory channel corresponding to other schedulers.
  • the first scheduler 1401 may also send the first received memory access request through a memory channel corresponding to another scheduler, and the second received memory.
  • the access request is sent through its corresponding memory channel.
  • the first scheduler 1401 may preferentially send the received multiple memory access requests through the memory channels corresponding to other schedulers, as long as there are enough free memory channels.
  • the CPU provided in this embodiment may be configured to send a memory access request to any of the schedulers through any idle memory channel. The specific method for allocating the memory channel is not limited in this embodiment.
  • each scheduler in the memory controller 1400 in the embodiment is configured with multiple paths, and a connection is established with each memory channel through the multiple paths.
  • the memory controller provided in this embodiment can be applied to all multi-channel memory systems with interconnected paths.
  • multiple schedulers in the memory controller can be integrated into one total scheduler, thereby further improving the degree of connection between multiple memory channels, and all the memory channels are uniformly scheduled by the total scheduler. Memory access requests maximize memory channel utilization.
  • the CPU provided by the embodiment of the present invention includes a memory controller.
  • the memory channel pair corresponding to another scheduler for example, the second scheduler
  • the received multiple memory access requests are sent to improve bandwidth resource utilization of the memory channel and improve memory access bandwidth.
  • this embodiment uses two schedulers as an example to describe the technical solution provided by the present invention.
  • the memory system includes a scheduler 0 and a scheduler 1; the scheduler 0 corresponds to a memory channel 0, and the scheduler
  • the memory channel 1 is connected to the memory module 0, the memory module 2, and the memory module 4, and the memory channel 1 is connected to the memory module 1, the memory module 3, and the memory module 5. .
  • a transmission chain is established between the scheduler 0 and the scheduler 1.
  • the scheduler 0 is configured with a path 1 and a path 2, the path 1 is connected to a memory channel 0, and the path 2 is connected to the memory channel 1
  • the scheduler 1 is configured with a path 1 and a path 2, the path 1 is connected to the memory channel 1, and the path 2 is connected to the memory channel 0;
  • a transmission is established between the memory module 0 and the memory module 1
  • the link 162 is configured to communicate between the memory module 0 and the memory module 1.
  • the memory module access method provided in this embodiment includes:
  • the scheduler 0 and the scheduler 1 exchange each other's number of memory access requests to be transmitted through the transmission link 161.
  • the scheduler 0 When the scheduler 0 receives at least two memory access requests, the first memory access request is sent through the path 1, and at the same time, the query scheduler 1 currently has a memory access request to be sent; if the scheduler 1 does not currently have If a memory access request needs to be sent, a second memory access request is sent through path 2 in the same scheduling slot.
  • the destination address of the memory access request received by the scheduler 0 is located in the memory module corresponding to the memory channel 0, that is, the memory module 0, the memory module 2, or the memory module 4; the scheduler 1 The destination address of the received memory access request is located in the memory module corresponding to the memory channel 1, that is, the memory module 1, the memory module 3, or the memory module 5.
  • the second memory access request is sent to the memory channel 1 through the path 2 of the scheduler 0.
  • the memory module 1 receives the second memory access request and forwards it to the memory module through the transmission link 152.
  • Group 0 is forwarded to the destination memory module through memory module 0.
  • S1 - S3 share the memory access request received by the scheduler 0 through the memory channel corresponding to the scheduler 1 (ie, the memory channel 1).
  • the scheduler 1 in this embodiment can share the memory access request received by the scheduler 0 through the memory channel corresponding to the scheduler 0 in the same manner, and details are not described herein again.
  • each scheduler can obtain the number of memory access requests to be sent in other schedulers; when multiple memory access requests are received, multiple memory access requests can be received. Send through multiple memory channels.
  • multiple received memory access requests can be allocated to multiple memory channels for transmission, thereby improving bandwidth resource utilization and improving memory access bandwidth.
  • FIG. 16 is a dual channel memory system as an example.
  • the memory module access method provided by the present invention is applicable to a multi-channel system.
  • the embodiment is further described by taking an N-channel memory system as an example.
  • N schedulers there are N schedulers, N memory channels, and N memory modules; wherein the N schedulers can be recorded as: scheduler 0, scheduler 1, ..., scheduler N-1; N memory channels are recorded as: memory channel 0, memory channel 1, ..., memory channel N-1; N memory modules are recorded as: memory module 0, memory module 1, ... , memory module N-1.
  • the scheduler, the memory channel, and the memory module are in one-to-one correspondence.
  • the scheduler 0 corresponds to the memory channel 0
  • the memory channel 0 corresponds to the memory module 0.
  • Each of the schedulers is configured with N paths (which can be referred to as: path 1, path 2, ..., path N), and the N paths are respectively connected to the N memory channels.
  • the connection relationship between the path and the memory channel can be set according to a preset rule.
  • the path m (0 ⁇ m ⁇ N) and the memory channel according to the scheduler n (0 ⁇ n ⁇ N-1) can be used.
  • (n+m) mod N phase connection method to set the connection relationship between the path and the memory channel. Among them, mod is used to represent the remainder.
  • x memory access requests can be sequentially passed through the local path 1, path 2, ..., path (n+x) mod. N is sent.
  • x ⁇ N the x memory access requests may be sent to the memory module in one scheduling time slot; when N ⁇ x ⁇ 2N, the x memory access requests are sent to the memory module; and so on, so I won't go into details here.
  • the memory system includes a scheduler 0, a scheduler 1, and a scheduler 2; the scheduler 0 corresponds to a memory channel 0.
  • the scheduler 1 corresponds to the memory channel 1
  • the scheduler 2 corresponds to the memory channel 2; the memory channel 0 is connected to the memory module 0, and the memory channel 1 is connected to the memory module 1, and the memory channel 2 is The memory module 2 is connected.
  • a transmission link 171 is established between the scheduler 0 and the scheduler 1
  • a transmission link 172 is established between the scheduler 1 and the scheduler 2
  • the scheduler 0 A transmission link 173 is established with the scheduler 2, and the transmission links 171-173 are used for the supply
  • the scheduler 0, the scheduler 1 and the scheduler 2 communicate with each other.
  • the scheduler 0 is configured with a path 1, a path 2 and a path 3, the path 1 is connected to a memory channel 0, the path 2 is connected to a memory channel 1, and the path 3 is connected to a memory channel 2; the scheduler 1 is provided with a path 1, a path 2 and a path 3, the path 1 being connected to a memory channel 1, the path 2 being connected to a memory channel 3, the path 3 being connected to a memory channel 0; the scheduler 2 being provided with a path 1. Path 2 and path 3, said path 1 being connected to a memory channel 2, said path 2 being connected to a memory channel 0, said channel 3 being connected to a memory channel 1.
  • a transmission link 174 is formed between the memory module 0 and the memory module 1 for communication between the memory module 0 and the memory module 1; between the memory module 1 and the memory module 2 A transmission link 175 is established for the memory module 1 and the memory module 2 to communicate.
  • the memory module access method is specifically implemented as follows:
  • the scheduler n When the scheduler n receives a plurality of memory access requests, the first memory access request to be sent is sent through the path 1;
  • the scheduler n If the scheduler n has a third prepared request, and the scheduler (n+1) mod3 does not currently have a memory access request to be sent, the scheduler (n+2) mod3 does not currently have a memory access request to be sent, Then the scheduler n sends the second memory to be sent to the path 2, and sends the third memory request to be sent to the path 3.
  • each scheduler can obtain the number of memory access requests to be sent in other schedulers; when multiple memory access requests are received, multiple memory access requests can be received. Send through multiple memory channels.
  • multiple received memory access requests can be allocated to multiple memory channels for transmission, thereby improving bandwidth resource utilization and improving memory access bandwidth.
  • the present invention can be implemented by means of software plus necessary general hardware, and of course, by hardware, but in many cases, the former is a better implementation. .
  • the technical solution of the present invention which is essential or contributes to the prior art, can be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer.
  • a hard disk or optical disk, etc. includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention.

Abstract

本发明公开了一种内存模组访问方法及装置，涉及计算机技术领域，用于解决多通道内存系统中带宽资源利用率较低，导致内存访问带宽较低的问题。本发明提供的方法包括：第一调度器获取第二调度器的待发送内存访问请求的数量；所述第一调度器接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。本发明适用于计算机技术领域，用于实现内存模组访问。

Description

一种监控视频播放的方法及设备、系统
本申请要求于2013年9月16日提交中国专利局、申请号为201310422993.7、发明名称为“内存模组访问方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及计算机技术领域，尤其涉及一种内存模组访问方法及装置。
背景技术
在计算机技术领域中，为了提高内存访问带宽，很多计算机采用多通道内存系统。多通道内存系统中包括多个内存通道，内存控制器通过多个内存通道与内存模组进行通信。在多通道内存系统中，会按照内存模组的划分预先确定内存地址与通道的映射关系，以使得各通道的负载均衡。当接收内存访问请求时，根据内存访问请求中的内存地址确定对应的通道作为目标通道，通过所述目标通道发送所述内存访问请求。以内存系统包括2个内存模组为例，则可以以内存地址中某一比特位的取值确定该内存地址与通道的映射关系。例如，内存地址第7位为“0”的内存访问请求通过通道0发送至目标内存模组；内存地址第7位为“1”的内存访问请求通过通道1发送至目标内存模组。
在实现本发明的过程中，发明人发现现有技术中至少存在如下问题：
由于内存模组与内存控制器之间的通道相互独立，当接收到的多个内存访问请求在多个通道之间分布不平衡时，例如，连续接收到的n个内存访问请求都是通过通道1发送至目标内存模组，会导致通道1拥堵，其他通道处于闲置状态，造成带宽资源的浪费，同时导致内存访问带宽较低。
发明内容
本发明的实施例提供一种内存模组访问方法及装置，能够解决现有技术中当接收到的多个内存访问请求在多个通道之间分布不平衡时，造成带宽资源的浪费，导致内存访问带宽较低的问题。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，本发明实施例提供了一种内存模组访问方法，应用于内 存系统，所述内存系统至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路，所述第一调度器和第二调度器之间建立有传输链路；
所述方法包括：
第一调度器获取所述第二调度器的待发送内存访问请求的数量；
所述第一调度器接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
在第一种可能的实现方式中，所述第一调度器接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求，包括：
所述第一调度器接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求；
当通过所述第一调度器对应的第一内存通道发送所述第一内存访问请求时，所述第二内存访问请求处于待发送状态；如果所述第二调度器对应的第二内存通道处于空闲状态，则所述第一调度器通过所述第二调度器对应的第二内存通道发送所述第二内存访问。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述第一调度器通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求之前，还包括：
所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；
所述第一调度器接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第二种可能的实现方式，在第三种可能的实现方式中，所述第二内存访问请求的目的地址位于第一内存通道对应的内存模组。
结合第一方面或第一方面的第一种可能的实现方式、或第二种可能的实现方式、或第三种可能的实现方式，在第四种可能的实现方式中，所述第一调度器配置有至少2个通路，通过所述至少2个通路与所述第一内存通道和第二内存通道建立连接。
第二方面，本发明实施例提供了一种内存模组访问方法，应用于内存系统，所述内存系统至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路；
所述方法包括：
所述第一调度器接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求；
所述第一调度器通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
在第一种可能的实现方式中，所述第一调度器通过所述第二内存通道发送所述第二内存访问请求，包括：
当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述通过所述第二内存通道发送所述第二内存访问请求之前，包括：
所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；
接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第二种可能的实现方式，在第三种可能的实现方式中，所述第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
结合第二方面或第二方面的第一种可能的实现方式、或第二种可能的实现方式、或第三种可能的实现方式，在第四种可能的实现方式中，每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
第三方面，本发明实施例提供了一种内存模组访问方法，应用于内存系统，所述内存系统至少包括第一内存通道和第二内存通道，每个内 存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路；
所述方法包括：
接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组；
通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
在第一种可能的实现方式中，所述通过所述第二内存通道发送所述第二内存访问请求，包括：
当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述内存系统至少包括第一调度器和第二调度器，所述第一调度器对应所述第一内存通道，所述第二调度器对应所述第二内存通道；
所述通过所述第二内存通道发送所述第二内存访问请求之前，还包括：
所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；
接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第三方面或第三方面的第一种可能的实现方式、或第二种可能的实现方式，在第三种可能的实现方式中，每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
第四方面，本发明实施例提供一种内存控制器，应用于内存系统，所述内存控制器至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路，所述第一调度器和第二调度器之间建立有传输链 路；
所述第一调度器用于获取所述第二调度器的待发送内存访问请求的数量；
所述第一调度器还用于接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
在第一种可能的实现方式中，所述第一调度器用于接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求；
所述第一调度器还用于当所述第二内存请求处于待发送状态时，如果所述第二调度器对应的第二内存通道处于空闲状态，则通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述第一调度器还用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
所述第一调度器还用于接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第二种可能的实现方式，在第三种可能的实现方式中，所述第一调度器接收的所述第二内存访问请求的目的地址位于第一内存通道对应的内存模组。
结合第一方面或第一方面的第一种可能的实现方式、或第二种可能的实现方式、或第三种可能的实现方式，在第四种可能的实现方式中，所述第一调度器配置有至少2个通路，通过所述至少2个通路与所述第一内存通道和第二内存通道建立连接。
第五方面，本发明实施例提供了一种内存控制器，所述内存控制器至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存控制器中包括多个内存模组，所述多个内存模组之间建立有传输链路；
所述第一调度器用于接收至少两个内存访问请求，包括第一内存访 问请求和第二内存访问请求；通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
在第一种可能的实现方式中，所述第一调度器用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述第一调度器还用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第二种可能的实现方式，在第三种可能的实现方式中，所述第一调度器接收到的所述第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
结合第五方面或第五方面的第一种可能的实现方式、或第二种可能的实现方式、或第三种可能的实现方式，在第四种可能的实现方式中，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
第六方面，本发明实施例提供了一种内存控制器，所述内存控制器至少包括第一内存通道和第二内存通道，每个内存通道对应一个内存模组；所述内存控制器包括多个内存模组，所述多个内存模组之间建立有传输链路；
所述内存控制器用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于第一内存通道对应的内存模组；
所述内存控制器还用于通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
在第一种可能的实现方式中，所述内存控制器具体用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述内存控制器中至少包括第一调度器和第二调度器，所述第一调度器对应所述第一内存通道，所述第二调度器对应所述第二内存通道；
所述第一调度器用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
所述第一调度器还用于接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第六方面或第六方面的第一种可能的实现方式、或第二种可能的实现方式，在第三种可能的实现方式中，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
第七方面，本发明实施例提供了一种中央处理器CPU，应用于内存系统，所述CPU包括内存控制器，所述内存控制器至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模块，所述多个内存模组之间建立有传输链路，所述第一调度器和第二调度器之间建立有传输链路；
所述第一调度器用于获取所述第二调度器的待发送内存访问请求的数量；
所述第一调度器还用于接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
在第一种可能的实现方式中，所述第一调度器用于接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求；
所述第一调度器还用于当所述第二内存请求处于待发送状态时，如果所述第二调度器对应的第二内存通道处于空闲状态，则通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述第一调度器还用于向所述第二调度器发送内存通道占用请求，以请求占用 所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
所述第一调度器还用于接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第二种可能的实现方式，在第三种可能的实现方式中，所述第一调度器接收的所述第二内存访问请求的目的地址位于第一内存通道对应的内存模组，所述第一内存通道为所述第一调度器对应的内存通道。
结合第七方面或第七方面的第一种可能的实现方式、或第二种可能的实现方式、或第三种可能的实现方式，在第四种可能的实现方式中，所述第一调度器配置有至少2个通路，通过所述至少2个通路与所述第一内存通道和第二内存通道建立连接。
第八方面，本发明实施例提供了一种CPU，包括内存控制器，所述内存控制器至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存控制器中包括多个内存模组，所述多个内存模组之间建立有传输链路；
所述第一调度器用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求；通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
在第一种可能的实现方式中，所述第一调度器用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述第一调度器还用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第二种可能的实现方式，在第三种可能的实现方式中，所述第一调度器接收到的所述第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
结合第八方面或第八方面的第一种可能的实现方式、或第二种可能的实现方式、或第三种可能的实现方式，在第四种可能的实现方式中，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
第九方面，本发明实施例提供了一种CPU，包括内存控制器，所述内存控制器至少包括第一内存通道和第二内存通道，每个内存通道对应一个内存模组；所述内存控制器包括多个内存模组，所述多个内存模组之间建立有传输链路；
所述内存控制器用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于第一内存通道对应的内存模组；
所述内存控制器还用于通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
在第一种可能的实现方式中，所述内存控制器具体用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
结合第一种可能的实现方式，在第二种可能的实现方式中，所述内存控制器中至少包括第一调度器和第二调度器，所述第一调度器对应所述第一内存通道，所述第二调度器对应所述第二内存通道；
所述第一调度器用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
所述第一调度器还用于接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
结合第九方面或第九方面的第一种可能的实现方式、或第二种可能的实现方式，在第三种可能的实现方式中，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
本发明实施例提供的内存模组访问方法及装置，当接收到多个内存 访问请求时，可以将接收到的多个内存访问请求通过多个内存通道进行发送。采用本发明实施例提供的方法，即使当接收到的多个内存访问请求在多个内存通道之间分布不平衡时，能够利用其他处于空闲状态的内存通道对接收到的多个内存访问请求进行发送，从而提高带宽资源利用率，提高内存访问带宽。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1、图2为本发明实施例一提供的内存模组访问方法的流程示意图；
图3、图4为本发明实施例二提供的内存控制器的结构框图；
图5、图6为本发明实施例三提供的CPU的结构框图；
图7、图8为本发明实施例四提供的内存模组访问方法的流程示意图；
图9为本发明实施例五提供的内存控制器的结构框图；
图10为本发明实施例六提供的CPU的结构框图；
图11、图12为本发明实施例七提供的内存模组访问方法的流程示意图；
图13为本发明实施例八提供的内存控制器的结构框图；
图14、图15为本发明实施例九提供的CPU的结构框图；
图16为本发明实施例十提供的双通道内存系统的结构图；
图17为本发明实施例十一提供的三通道内存系统的结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本 发明保护的范围。
实施例一
本发明实施例提供了一种内存模组访问方法，应用于内存系统，所述内存系统至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路，所述第一调度器和第二调度器之间建立有传输链路。
如图1所示，所述方法包括：
101、第一调度器获取第二调度器的待发送内存访问请求的数量。
102、所述第一调度器接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
本实施例中，所述内存系统包括多个调度器，所述多个调度器之间建立有通信链路，以使得每个调度器能够获取其他调度器中的待发送内存访问请求的数量，从而在接收到内存访问请求后，能够确定空闲的内存通道，通过该空闲内存通道发送内存访问请求。
进一步的，在图1所示方法的基础上，本发明实施例还提供了一种较为详细的内存模组访问方法，如图2所示，所述方法包括：
201、第一调度器实时获取其他调度器的待发送内存访问请求的数量，其中，所述第一调度器为所述多个调度器中的任一调度器，所述其他调度器为所述多个调度器中除所述第一调度器之外的剩余调度器。
202、所述第一调度器接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求。
值得说明的是，一般的，所述第一调度器接收到的内存访问请求的目的地址均位于所述第一调度器自身所对应的内存模组，即：如果将所述第一调度器对应的内存通道记作第一内存通道，则所述第一内存访问请求和第二内存访问请求的目的地址均位于第一内存通道对应的内存模组。
203、所述第一调度器通过所述第一内存通道发送所述第一内存访问请求，则所述第二内存访问请求处于待发送状态。
204、所述第一调度器查询其他调度器对应的内存通道的状态，确定 辅助调度器，所述辅助调度器对应的内存通道处于空闲状态。
具体的，所述第一调度器可以采用如下方法确定辅助调度器：所述第一调度器查询其他调度器的待发送内存访问请求的数量，确定待发送内存访问请求数量为0的调度器作为辅助调度器。
为了便于理解，本实施例中将确定的辅助调度器记作第二调度器，则所述第二调度器当前的待发送内存访问请求的数量为0，所述第二调度器对应的内存通道处于空闲状态。
值得说明的是，所述第二调度器当前的待发送内存访问请求数量为0，表示所述第二调度器对应的内存通道处于绝对的空闲状态。需要强调的是，作为一种可选方案，当所述第二调度器对应的内存通道处于相对的空闲状态时(例如第二调度器中的待发送内存访问请求数量不为0，但第二调度器中的待发送内存访问请求数量远低于所述第一调度器中的待发送内存访问请求数量)，所述第一调度器仍然可以将所述第二调度器确定为辅助调度器，将自身接收的一部分内存访问请求通过所述第二调度器对应的内存通道进行发送。采用这样的方法，当第一调度器中接收到大量内存访问请求时，可以及时的将第一调度器中的部分待发送内存访问请求转存到所述辅助调度器中，这样可以使得第一调度器缓存更多的内存访问请求，提高内存系统的通信容量。
205、所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
206、所述第二调度器确定自身对应的内存通道处于空闲状态，允许所述第一调度器占用第二调度器对应的第二内存通道，向所述第一调度器发送关于所述内存通道占用请求的确认响应。
207、所述第一调度器接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
208、所述第一调度器通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
一般的，当第一调度器在一个调度时隙内接收到多个内存访问请求时，将接收到的第一个内存访问请求通过自身对应的内存通道进行发送， 将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的方法，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
209、所述第二调度器对应的内存模组接收所述第二内存访问请求，根据所述第二内存访问请求中的目的地址，通过内存模组之间的传输链路，将所述第二内存访问请求发送至目的内存模组，即第一调度器对应的内存模组。
值得说明的是，本实施例中，每个调度器配置有多个通路，通过所述多个通路与所述多个内存通道建立连接，以使得每个调度器能够通过其他调度器对应的内存通道发送内存访问请求。
需要强调的是，本实施例提供的内存模组访问方法，可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将本实施例中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的内存模组访问方法，每个调度器可以获取其他调度器中待发送内存访问请求的数量；当接收到多个内存访问请求时，可以将接收到的多个内存访问请求通过多个内存通道进行发送。采用本发明实施例提供的方法，当接收到多个内存访问请求时，能够将接收到的多个内存访问请求分配给多个内存通道进行发送，从而提高带宽资源利用率，提高内存访问带宽。
实施例二
本发明实施例提供了一种内存控制器，应用于内存系统，能够实现图1和图2所示的内存模组访问方法，如图3所示，所述内存控制器至少包括第一调度器31和第二调度器32，所述第一调度器31对应第一内存通道，所述第二调度器32对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路，所述第一调度器31和第二调度器32之间建立有传输链路；
所述第一调度器31用于获取所述第二调度器的待发送内存访问请求的数量；
所述第一调度器31还用于接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
值得说明的是，图3中的第一调度器31和第二调度器32仅为举例说明。实际应用中，所述内存控制器包括多个调度器，如图4所示，所述内存控制器还可以包括第三调度器33、第四调度器34…等多个调度器。其中，所述内存系统中的调度器之间建立有通信链路，以使得每个调度器能够获取其他调度器中的待发送内存访问请求的数量，从而在接收到内存访问请求后，能够确定空闲的内存通道，通过该空闲内存通道发送内存访问请求。
具体的，所述第一调度器31用于接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求；
所述第一调度器31还用于当所述第二内存请求处于待发送状态时，如果所述第二调度器32对应的第二内存通道处于空闲状态，则通过所述第二调度器32对应的第二内存通道发送所述第二内存访问请求。
具体的，所述第一调度器31还用于向所述第二调度器32发送内存通道占用请求，以请求占用所述第二调度器32对应的第二内存通道发送所述第二内存访问请求；以及
所述第一调度器31还用于接收所述第二调度器32返回的关于所述内存通道占用请求的确认响应。
一般的，当第一调度器31在一个调度时隙内接收到多个内存访问请 求时，所述第一调度器31将接收到的第一个内存访问请求通过自身对应的内存通道进行发送，将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器31也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器31可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的方法，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
其中，所述第一调度器31接收的所述第二内存访问请求的目的地址位于第一内存通道对应的内存模组。
值得说明的是，本实施例中每个调度器都配置有多个通路，通过所述多个通路与所述多个内存通道建立连接，以使得每个调度器能够通过其他调度器对应的内存通道发送内存访问请求。例如，所述第一调度器31配置有至少2个通路，通过所述至少2个通路与所述第一内存通道和第二内存通道建立连接。
需要强调的是，本实施例提供的内存控制器可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将内存控制器中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的内存控制器中的每个调度器可以获取其他调度器中待发送内存访问请求的数量；当接收到多个内存访问请求时，可以将接收到的多个内存访问请求通过多个内存通道进行发送。采用本发明实施例提供的内存控制器，当接收到多个内存访问请求时，能够将接收到的多个内存访问请求分配给多个内存通道进行发送，从而提高带宽资源利用率，提高内存访问带宽。
实施例三
本发明实施例提供了一种CPU，应用于内存系统，能够实现上述图1和图2所示的方法，如图5所示，所述CPU包括内存控制器50，所述内存控制器50包括第一调度器51和第二调度器52，所述第一调度器51对应第一内存通道，所述第二调度器52对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模块，所述多个内存模组之间建立有传输链路，所述第一调度器51和第二调度器52之间建立有传输链路；
具体的，所述第一调度器51用于获取所述第二调度器52的待发送内存访问请求的数量；
所述第一调度器51还用于接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
值得说明的是，图5中的第一调度器51和第二调度器52仅为举例说明。实际应用中，所述内存控制器包括多个调度器，如图6所示，所述内存控制器还可以包括第三调度器53、第四调度器54…等多个调度器。其中，所述内存系统中的调度器之间建立有通信链路，以使得每个调度器能够获取其他调度器中的待发送内存访问请求的数量，从而在接收到内存访问请求后，能够确定空闲的内存通道，通过该空闲内存通道发送内存访问请求。
具体的，所述第一调度器51用于接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求。
所述第一调度器51还用于当所述第二内存请求处于待发送状态时，如果所述第二调度器52对应的内存通道处于空闲状态，则通过所述第二调度器52对应的内存通道发送所述第二内存访问请求。
具体的，所述第一调度器51还用于向所述第二调度器52发送内存通道占用请求，以请求占用所述第二调度器52对应的第二内存通道发送所述第二内存访问请求；以及
所述第一调度器51还用于接收所述第二调度器52返回的关于所述内存通道占用请求的确认响应。
其中，所述第一调度器51接收的所述第二内存访问请求的目的地址位于第一内存通道对应的内存模组。
一般的，当第一调度器在一个调度时隙内接收到多个内存访问请求时，将接收到的第一个内存访问请求通过自身对应的内存通道进行发送，将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的方法，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
值得说明的是，本实施例内存控制器中的每个调度器配置有多个通路，通过所述多个通路与所述多个内存通道建立连接。例如，所述第一调度器配置有至少2个通路，通过所述至少2个通路与所述第一内存通道和第二内存通道建立连接。
需要强调的是，本实施例提供的CPU可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将内存控制器50中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的CPU包括内存控制器，所述内存控制器中的每个调度器可以获取其他调度器中待发送内存访问请求的数量；当接收到多个内存访问请求时，可以将接收到的多个内存访问请求通过多个内存通道进行发送。采用本发明实施例提供的CPU，当接收到多个内存访问请求时，能够将接收到的多个内存访问请求分配给多个内存通道进行发送，从而提高带宽资源利用率，提高内存访问带宽。
实施例四
本发明实施例提供了一种内存模组访问方法，应用于内存系统，所述内存系统至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路。
如图7所示，所述方法包括：
701、所述第一调度器接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求。
702、所述第一调度器通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
通过本实施例中的方法，能够通过内存系统的多个内存通道，对多个调度器接收到的内存访问请求进行分担，提高内存通道的带宽资源利用率。
进一步的，在图7所示方法的基础上，本发明实施例还提供了一种较为详细的内存模组访问方法，如图8所示，所述方法包括：
801、所述第一调度器接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求。
值得说明的是，一般的，所述第一调度器接收到的内存访问请求的目的地址均位于所述第一调度器自身所对应的内存模组，即：如果将所述第一调度器对应的内存通道记作第一内存通道，则所述第一内存访问请求和第二内存访问请求的目的地址均位于第一内存通道对应的内存模组。
802、所述第一调度器通过所述第一内存通道发送所述第一内存访问请求，则所述第二内存访问请求处于待发送状态。
803、所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
值得说明的是，所述第二调度器是所述内存系统中多个调度器中的 任一调度器。当所述第一调度器接收到多个内存访问请求时，可以向内存系统中的所有调度器发送内存通道占用请求。本实施例中以第二调度器为例进行具体的举例说明。
804、所述第二调度器检测自身对应的内存通道是否处于空闲状态；若是，则执行805，若否，则执行809。
805、所述第二调度器允许所述第一调度器占用第二调度器对应的第二内存通道，向所述第一调度器发送关于所述内存通道占用请求的确认响应。
806、所述第一调度器接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
807、所述第一调度器通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
一般的，当第一调度器在一个调度时隙内接收到多个内存访问请求时，将接收到的第一个内存访问请求通过自身对应的内存通道进行发送，将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的方法，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
808、所述第二调度器对应的内存模组接收所述第二内存访问请求，根据所述第二内存访问请求中的目的地址，通过内存模组之间的传输链路，将所述第二内存访问请求发送至目的内存模组，即第一调度器对应的内存模组。
809、所述第二调度器拒绝所述第一调度器发送的所述内存通道占用请求。
值得说明的是，本实施例中，每个调度器配置有多个通路，通过所述多个通路与所述多个内存通道建立连接，以使得每个调度器能够通过其他调度器对应的内存通道发送内存访问请求。
需要强调的是，本实施例提供的内存模组访问方法，可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将本实施例中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的内存模组访问方法，当接收到多个内存访问请求时，能够通过内存系统的多个内存通道，对多个调度器接收到的内存访问请求进行分担，通过多个内存通道对所述多个内存访问请求进行发送，从而提高内存通道的带宽资源利用率，提高内存访问带宽。
实施例五
本发明实施例提供了一种内存控制器，能够实现图7和图8所示的方法，如图9所示，所述内存控制器至少包括第一调度器91和第二调度器92，所述第一调度器91对应第一内存通道，所述第二调度器92对应第二内存通道，每个内存通道对应一个或多个内存模组，所述内存模组之间建立有传输链路。
所述第一调度器91用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求；通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
具体的，所述第一调度器91用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
进一步的，所述第一调度器91还用于向所述第二调度器92发送内存通道占用请求，以请求占用所述第二调度器92对应的第二内存通道发送所述第二内存访问请求；以及
接收所述第二调度器92返回的关于所述内存通道占用请求的确认响应。
其中，所述第一调度器91接收到的所述第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
一般的，当第一调度器91在一个调度时隙内接收到多个内存访问请求时，将接收到的第一个内存访问请求通过自身对应的内存通道进行发送，将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器91也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器91可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的内存控制器，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
具体的，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
需要强调的是，本实施例提供的内存控制器可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将内存控制器中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的内存控制器，当接收到多个内存访问请求时，能够通过内存系统的多个内存通道，对多个调度器接收到的内存访问请求进行分担，通过多个内存通道对所述多个内存访问请求进行发送，从而提高内存通道的带宽资源利用率，提高内存访问带宽。
实施例六
本实施例提供了一种CPU，能够实现图7和图8所示的方法，如图10所示，所述CPU包括内存控制器1000，所述内存控制器1000至少包 括第一调度器1001和第二调度器1002，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个调度器对应一个内存通道，每个内存通道对应一个或多个内存模组；所述内存控制器中包括多个内存模组，所述多个内存模组预先之间建立有传输链路。
所述第一调度器1001用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求；通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
具体的，所述第一调度器1001用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
一般的，当第一调度器1001在一个调度时隙内接收到多个内存访问请求时，将接收到的第一个内存访问请求通过自身对应的内存通道进行发送，将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器1001也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器1001可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的CPU，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
进一步的，所述第一调度器1001还用于向所述第二调度器1002发送内存通道占用请求，以请求占用所述第二调度器1002对应的第二内存通道发送所述第二内存访问请求；以及
接收所述第二调度器1002返回的关于所述内存通道占用请求的确认响应。
其中，所述第一调度器1001接收到的所述第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
本实施例中，所述内存控制器中1000中的的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
需要强调的是，本实施例提供的内存控制器可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将内存控制器中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的CPU，当接收到多个内存访问请求时，能够通过内存系统的多个内存通道，对多个调度器接收到的内存访问请求进行分担，通过多个内存通道对所述多个内存访问请求进行发送，从而提高内存通道的带宽资源利用率，提高内存访问带宽。
实施例七
本发明实施例提供了一种内存模组访问方法，应用于内存系统，所述内存系统至少包括第一内存通道和第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路。
如图11所示，所述方法包括：
1101、所述第一调度器接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
1102、通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
本实施例提供的内存模组访问方法，当第一调度器接收到多个内存访问请求时，可以通过其他调度器(例如本实施例中的第二调度器)对应的内存通道发送所述接收到的多个内存访问请求。
进一步的，在图11所示方法的基础上，本发明实施例还提供了一种较为详细的内存模组访问方法，如图12所示，所述方法包括：
1201、所述第一调度器接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址均位于所述第一内存通道对应的内存模组。
1202、所述第一调度器通过所述第一内存通道发送所述第一内存访问请求，则所述第二内存访问请求处于待发送状态。
1203、所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
值得说明的是，所述第二调度器是所述内存系统中多个调度器中的任一调度器。当所述第一调度器接收到多个内存访问请求时，可以向内存系统中的所有调度器发送内存通道占用请求。本实施例中以实施例二为例进行具体的举例说明。
1204、所述第二调度器检测自身对应的内存通道是否处于空闲状态；若是，则执行1205，若否，则执行1209。
1205、所述第二调度器允许所述第一调度器占用第二调度器对应的内存通道，向所述第一调度器发送关于所述内存通道占用请求的确认响应。
1206、所述第一调度器接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
1207、所述第一通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
一般的，当第一调度器在一个调度时隙内接收到多个内存访问请求时，将接收到的第一个内存访问请求通过自身对应的内存通道进行发送，将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的方法，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
1208、所述第二调度器对应的内存模组接收所述第二内存访问请求，根据所述第二内存访问请求中的目的地址，通过内存模组之间的传输链路，将所述第二内存访问请求发送至目的内存模组，即第一调度器对应的内存模组。
1209、所述第二调度器拒绝所述第一调度器发送的所述内存通道占用请求。
值得说明的是，本实施例中，每个调度器配置有多个通路，通过所述多个通路与所述多个内存通道建立连接，以使得每个调度器能够通过其他调度器对应的内存通道发送内存访问请求。
需要强调的是，本实施例提供的内存模组访问方法，可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将本实施例中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的内存模组访问方法，当第一调度器接收到多个内存访问请求时，可以通过其他调度器(例如第二调度器)对应的内存通道对接收到的所述多个内存访问请求进行发送，从而提高内存通道的带宽资源利用率，提高内存访问带宽。
实施例八
本发明实施例提供了一种内存控制器，能够实现图10和图11所示的方法，所述内存控制器至少包括第一内存通道和第二内存通道，每个内存通道对应一个或多个内存模组；所述内存控制器包括多个内存模组，所述多个内存模组之间建立有传输链路。
具体的，所述内存控制器用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于第一内存通道对应的内存模组；
所述内存控制器还用于通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
具体的，所述内存控制器用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
如图13所示，所述内存控制器中至少包括第一调度器1301和第二调度器1302，所述第一调度器1301对应所述第一内存通道，所述第二调度器1302对应所述第二内存通道；
所述第一调度器1301用于向所述第二调度器1302发送内存通道占用请求，以请求占用所述第二调度器1302对应的第二内存通道发送所述第二内存访问请求；以及
所述第一调度器1301还用于接收所述第二调度器1302返回的关于所述内存通道占用请求的确认响应。
一般的，当第一调度器1301在一个调度时隙内接收到多个内存访问请求时，将接收到的第一个内存访问请求通过自身对应的内存通道进行发送，将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器1301也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器1301可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的内存控制器，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
值得说明的是，本实施例中的所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
需要强调的是，本实施例提供的内存控制器可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将内存控制器中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的内存控制器，当所述内存控制器中的第一调度器接收到多个内存访问请求时，可以通过其他调度器(例如第二调度器)对应的内存通道对接收到的所述多个内存访问请求进行发送，从而提高内存通道的带宽资源利用率，提高内存访问带宽。
实施例九
本发明实施例提供了一种CPU，能够实现图10和图11所示的方法，如图14所示，所述CPU包括内存控制器1400，所述内存控制器1400至少包括第一内存通道和第二内存通道，每个内存通道对应一个或多个内存模组；所述内存控制器1400包括多个内存模组，所述多个内存模组之间建立有传输链路。
所述内存控制器1400用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于第一内存通道对应的内存模组；
所述内存控制器1400还用于通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
进一步的，所述内存控制器1400具体用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
如图15所示，所述内存控制器1400中至少包括第一调度器1401和第二调度器1402，所述第一调度器1401对应所述第一内存通道，所述第二调度器1402对应所述第二内存通道；
所述第一调度器1401用于向所述第二调度器1402发送内存通道占用请求，以请求占用所述第二调度器1402对应的第二内存通道发送所述第二内存访问请求；以及
所述第一调度器1401还用于接收所述第二调度器1402返回的关于所述内存通道占用请求的确认响应。
一般的，当第一调度器1401在一个调度时隙内接收到多个内存访问请求时，将接收到的第一个内存访问请求通过自身对应的内存通道进行发送，将第二个接收到的内存访问请求通过其他调度器对应的内存通道进行发送。
值得说明的是，作为一种可选方案，所述第一调度器1401也可以将第一个接收到的内存访问请求通过其他调度器对应的内存通道进行发送，将第二个接收到的内存访问请求通过自身对应的内存通道进行发送。作为另一种可选方案，只要存在足够的空闲内存通道，所述第一调度器1401可以将接收到的多个内存访问请求优先通过其他调度器对应的内存通道进行发送。本实施例提供的CPU，对于任一调度器接收到的内存访问请求，可以通过任一空闲的内存通道进行发送，内存通道的具体分配方法本实施例不做限定。
值得说明的是，本实施例中所述内存控制器中1400的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
需要强调的是，本实施例提供的内存控制器可以应用于所有具备互联通路的多通道内存系统。
作为一种优选的方案，可以将内存控制器中的多个调度器整合为一个总调度器，从而进一步提高多个内存通道之间的联系度，由所述总调度器统一调度所有内存通道的内存访问请求，使得内存通道利用率达到最大化。
本发明实施例提供的CPU包括内存控制器，当所述内存控制器中的第一调度器接收到多个内存访问请求时，可以通过其他调度器(例如第二调度器)对应的内存通道对接收到的所述多个内存访问请求进行发送，从而提高内存通道的带宽资源利用率，提高内存访问带宽。
实施例十
为了便于理解，本实施例以两个调度器为例，对本发明提供的技术方案进行说明。
本实施例提供了一种内存模组访问方法，应用于内存系统，如图16所示，所述内存系统包括调度器0和调度器1；所述调度器0对应内存通道0，所述调度器1对应内存通道1；所述内存通道0与内存模组0、内存模组2、内存模组4相连，所述内存通道1与内存模组1、内存模组3、内存模组5相连。
具体的，如图16所示，所述调度器0与调度器1之间建立有传输链 路161，用于供所述调度器0和调度器1进行通信；所述调度器0配置有通路1和通路2，所述通路1与内存通道0相连，所述通路2与内存通道1相连；所述调度器1配置有通路1和通路2，所述通路1与内存通道1相连，所述通路2与内存通道0相连；所述内存模组0和内存模组1之间建立有传输链路162，用于供所述内存模组0和内存模组1进行通信。
结合图16所示的内存系统，本实施例提供的内存模组访问方法包括：
S1、所述调度器0和调度器1通过传输链路161交互彼此的待发送内存访问请求数量。
S2、当所述调度器0接收到至少两个内存访问请求时，通过通路1发送第一个内存访问请求，同时，查询调度器1当前是否存在内存访问请求需要发送；如果调度器1当前没有内存访问请求需要发送，则在同一个调度时隙内通过通路2发送第二个内存访问请求。
值得说明的是，一般的，调度器0接收到的内存访问请求的目的地址位于内存通道0对应的内存模组，即内存模组0、内存模组2、或内存模组4；调度器1接收到的内存访问请求的目的地址位于内存通道1对应的内存模组，即内存模组1、内存模组3、或内存模组5。
S3、所述第二个内存访问请求通过调度器0的通路2发送至内存通道1，所述内存模组1接收所述第二个内存访问请求，将其通过传输链路152转发至内存模组0，通过内存模组0转发至目的内存模组。
值得说明的是，上述S1—S3是以调度器0通过调度器1对应的内存通道(即内存通道1)来分担自身接收到的内存访问请求。本实施例中的调度器1可以按照相同的方法来通过调度器0对应的内存通道来分担自身接收到的内存访问请求，此处不再赘述。
本发明实施例提供的内存模组访问方法，每个调度器可以获取其他调度器中待发送内存访问请求的数量；当接收到多个内存访问请求时，可以将接收到的多个内存访问请求通过多个内存通道进行发送。采用本发明实施例提供的方法，当接收到多个内存访问请求时，能够将接收到的多个内存访问请求分配给多个内存通道进行发送，从而提高带宽资源利用率，提高内存访问带宽。
实施例十一
图16是以双通道内存系统为例进行说明的，本发明提供的内存模组访问方法适用于多通道系统。接下来，本实施例以N通道内存系统为例进行进一步描述。
在N通道内存系统中，包括N个调度器、N个内存通道、N个内存模组；其中，所述N个调度器可以记作：调度器0、调度器1、...、调度器N-1；N个内存通道记作：内存通道0、内存通道1、...、内存通道N-1；N个内存模组记作：内存模组0、内存模组1、...、内存模组N-1。所述调度器、内存通道、内存模组一一对应，例如：调度器0与内存通道0相对应，内存通道0与内存模组0相对应。
其中，每个调度器配置有N个通路(可以记作：通路1、通路2、...、通路N)，所述N个通路分别与所述N个内存通道相连。为了便于统计，可以按照预设规则对通路和内存通道的连接关系进行设定，例如，可以按照调度器n(0≤n≤N-1)的通路m(0≤m≤N)与内存通道(n+m)mod N相连接的方法来设定通路和内存通道的连接关系。其中，mod用于表示求余数。
当调度器n接收到x个内存访问请求时，如果N个通道均处于空闲状态，则可以将x个内存访问请求依次通过本地通路1、通路2、...、通路(n+x)mod N进行发送。其中，当x≤N时，在一个调度时隙内即可将所述x个内存访问请求发送至内存模组；当N＜x≤2N时，在两个调度时隙内即可将所述x个内存访问请求发送至内存模组；依次类推，此处不再赘述。
为了便于理解，接下来以三通道内存系统为例进行举例说明，如图17所示，所述内存系统包括调度器0、调度器1、调度器2；所述调度器0对应内存通道0，所述调度器1对应内存通道1，所述调度器2对应内存通道2；所述内存通道0与内存模组0相连，所述内存通道1与内存模组1相连，所述内存通道2与内存模组2相连。
具体的，如图17所示，所述调度器0与调度器1之间建立有传输链路171，所述调度器1与调度器2之间建立有传输链路172，所述调度器0与调度器2之间建立有传输链路173，所述传输链路171-173用于供所 述调度器0、调度器1和调度器2之间互相进行通信。
所述调度器0配置有通路1、通路2和通路3，所述通路1与内存通道0相连，所述通路2与内存通道1相连，所述通路3与内存通道2相连；所述调度器1配置有通路1、通路2和通路3，所述通路1与内存通道1相连，所述通路2与内存通道3相连，所述通路3与内存通道0相连；所述调度器2配置有通路1、通路2和通路3，所述通路1与内存通道2相连，所述通路2与内存通道0相连，所述通路3与内存通道1相连。
所述内存模组0和内存模组1之间建立有传输链路174，用于供所述内存模组0和内存模组1进行通信；所述内存模组1和内存模组2之间建立有传输链路175，用于供所述内存模组1和内存模组2进行通信。
根据图17所示的三通道内存系统，内存模组访问方法具体实现如下：
(1)调度器n接收到多个内存访问请求时，将第一个需要发送的内存访问请求通过通路1进行发送；
(2)如果调度器n有第二个内存访问请求需要发送，则检测调度器(n+1)mod3当前是否有内存访问请求需要发送；若没有，则把第二个需要发送的内存访问请求发送到通路2；
如果调度器(n+1)mod3当前有内存访问请求需要发送，则检测调度器(n+2)mod3当前是否有内存访问请求需要发送；若没有，则把第二个需要发送的内存访问请求发送到通路3。
(3)如果调度器n有第三个准备好的请求，且调度器(n+1)mod3当前没有内存访问请求需要发送、调度器(n+2)mod3当前也没有内存访问请求需要发送，则调度器n把第二个需要发送的内存发送到通路2，把第三个需要发送的内存请求发送到通路3。
本发明实施例提供的内存模组访问方法，每个调度器可以获取其他调度器中待发送内存访问请求的数量；当接收到多个内存访问请求时，可以将接收到的多个内存访问请求通过多个内存通道进行发送。采用本发明实施例提供的方法，当接收到多个内存访问请求时，能够将接收到的多个内存访问请求分配给多个内存通道进行发送，从而提高带宽资源利用率，提高内存访问带宽。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可借助软件加必需的通用硬件的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在可读取的存储介质中，如计算机的软盘，硬盘或光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述的方法。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (42)

  1. 一种内存模组访问方法，其特征在于，应用于内存系统，所述内存系统至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路，所述第一调度器和第二调度器之间建立有传输链路；
    所述方法包括：
    第一调度器获取所述第二调度器的待发送内存访问请求的数量；
    所述第一调度器接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
  2. 根据权利要求1所述的方法，其特征在于，所述第一调度器接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求，包括：
    所述第一调度器接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求；
    当通过所述第一调度器对应的第一内存通道发送所述第一内存访问请求时，所述第二内存访问请求处于待发送状态；如果所述第二调度器对应的第二内存通道处于空闲状态，则所述第一调度器通过所述第二调度器对应的第二内存通道发送所述第二内存访问。
  3. 根据权利要求2所述的方法，其特征在于，所述第一调度器通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求之前，还包括：
    所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；
    所述第一调度器接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
  4. 根据权利要求3所述的方法，其特征在于，所述第二内存访问请求的目的地址位于第一内存通道对应的内存模组。
  5. 根据权利要求1-4中任一项所述的方法，其特征在于，所述第一调度器配置有至少2个通路，通过所述至少2个通路与所述第一内存通 道和第二内存通道建立连接。
  6. 一种内存模组访问方法，其特征在于，应用于内存系统，所述内存系统至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路；
    所述方法包括：
    所述第一调度器接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求；
    所述第一调度器通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
  7. 根据权利要求6所述的方法，其特征在于，所述第一调度器通过所述第二内存通道发送所述第二内存访问请求，包括：
    当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
  8. 根据权利要求7所述的方法，其特征在于，所述通过所述第二内存通道发送所述第二内存访问请求之前，包括：
    所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；
    接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
  9. 根据权利要求8所述的方法，其特征在于，所述第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
  10. 根据权利要求6-9中任一项所述的方法，其特征在于，每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
  11. 一种内存模组访问方法，其特征在于，应用于内存系统，所述内存系统至少包括第一内存通道和第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路；
    所述方法包括：
    接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组；
    通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
  12. 根据权利要求11所述的方法，其特征在于，所述通过所述第二内存通道发送所述第二内存访问请求，包括：
    当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
  13. 根据权利要求12所述的方法，其特征在于，所述内存系统至少包括第一调度器和第二调度器，所述第一调度器对应所述第一内存通道，所述第二调度器对应所述第二内存通道；
    所述通过所述第二内存通道发送所述第二内存访问请求之前，还包括：
    所述第一调度器向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；
    接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
  14. 根据权利要求11-13中任一项所述的方法，其特征在于，每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
  15. 一种内存控制器，应用于内存系统，其特征在于，所述内存控制器至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模组，所述多个内存模组之间建立有传输链路，所述第一调度器和第二调度器之间建立有传输链路；
    所述第一调度器用于获取所述第二调度器的待发送内存访问请求的数量；
    所述第一调度器还用于接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
  16. 根据权利要求15所述的内存控制器，其特征在于，所述第一调 度器用于接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求；
    所述第一调度器还用于当所述第二内存请求处于待发送状态时，如果所述第二调度器对应的第二内存通道处于空闲状态，则通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
  17. 根据权利要求16所述的内存控制器，其特征在于，所述第一调度器还用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
    所述第一调度器还用于接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
  18. 根据权利要求17所述的内存控制器，其特征在于，所述第一调度器接收的所述第二内存访问请求的目的地址位于第一内存通道对应的内存模组。
  19. 根据权利要求15-18中任一项所述的内存控制器，其特征在于，所述第一调度器配置有至少2个通路，通过所述至少2个通路与所述第一内存通道和第二内存通道建立连接。
  20. 一种内存控制器，其特征在于，所述内存控制器至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存控制器中包括多个内存模组，所述多个内存模组之间建立有传输链路；
    所述第一调度器用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求；通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
  21. 根据权利要求20所述的内存控制器，其特征在于，所述第一调度器用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
  22. 根据权利要求21所述的内存控制器，其特征在于，所述第一调度器还用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
    接收所述第二调度器返回的关于所述内存通道占用请求的确认响 应。
  23. 根据权利要求22所述的内存控制器，其特征在于，所述第一调度器接收到的所述第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
  24. 根据权利要求20-23中任一项所述的内存控制器，其特征在于，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
  25. 一种内存控制器，其特征在于，所述内存控制器至少包括第一内存通道和第二内存通道，每个内存通道对应一个内存模组；所述内存控制器包括多个内存模组，所述多个内存模组之间建立有传输链路；
    所述内存控制器用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于第一内存通道对应的内存模组；
    所述内存控制器还用于通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
  26. 根据权利要求25所述的内存控制器，其特征在于，所述内存控制器具体用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
  27. 根据权利要求26所述的内存控制器，其特征在于，所述内存控制器中至少包括第一调度器和第二调度器，所述第一调度器对应所述第一内存通道，所述第二调度器对应所述第二内存通道；
    所述第一调度器用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
    所述第一调度器还用于接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
  28. 根据权利要求25-27中任一项所述的内存控制器，其特征在于，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
  29. 一种中央处理器CPU，应用于内存系统，其特征在于，所述CPU 包括内存控制器，所述内存控制器至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存系统包括多个内存模块，所述多个内存模组之间建立有传输链路，所述第一调度器和第二调度器之间建立有传输链路；
    所述第一调度器用于获取所述第二调度器的待发送内存访问请求的数量；
    所述第一调度器还用于接收内存访问请求，通过所述第二调度器对应的第二内存通道发送所述内存访问请求。
  30. 根据权利要求29所述的CPU，其特征在于，所述第一调度器用于接收至少两个内存访问请求，所述至少两个内存访问请求包括第一内存访问请求和第二内存访问请求；
    所述第一调度器还用于当所述第二内存请求处于待发送状态时，如果所述第二调度器对应的第二内存通道处于空闲状态，则通过所述第二调度器对应的第二内存通道发送所述第二内存访问请求。
  31. 根据权利要求30所述的CPU，其特征在于，所述第一调度器还用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
    所述第一调度器还用于接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
  32. 根据权利要求31所述的CPU，其特征在于，所述第一调度器接收的所述第二内存访问请求的目的地址位于第一内存通道对应的内存模组。
  33. 根据权利要求29-32中任一项所述的CPU，其特征在于，所述第一调度器配置有至少2个通路，通过所述至少2个通路与所述第一内存通道和第二内存通道建立连接。
  34. 一种中央处理器CPU，其特征在于，包括内存控制器，所述内存控制器至少包括第一调度器和第二调度器，所述第一调度器对应第一内存通道，所述第二调度器对应第二内存通道，每个内存通道对应一个内存模组；所述内存控制器中包括多个内存模组，所述多个内存模组之 间建立有传输链路；
    所述第一调度器用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求；通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
  35. 根据权利要求34所述的CPU，其特征在于，所述第一调度器用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
  36. 根据权利要求35所述的CPU，其特征在于，所述第一调度器还用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
    接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
  37. 根据权利要求36所述的CPU，其特征在于，所述第一调度器接收到的所述第二内存访问请求的目的地址位于所述第一内存通道对应的内存模组。
  38. 根据权利要求34-37中任一项所述的CPU，其特征在于，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
  39. 一种中央处理器CPU，其特征在于，包括内存控制器，所述内存控制器至少包括第一内存通道和第二内存通道，每个内存通道对应一个内存模组；所述内存控制器包括多个内存模组，所述多个内存模组之间建立有传输链路；
    所述内存控制器用于接收至少两个内存访问请求，包括第一内存访问请求和第二内存访问请求，所述第一内存访问请求和第二内存访问请求的目的地址位于第一内存通道对应的内存模组；
    所述内存控制器还用于通过所述第一内存通道发送所述第一内存访问请求，通过所述第二内存通道发送所述第二内存访问请求。
  40. 根据权利要求39所述的CPU，其特征在于，所述内存控制器具体用于当所述第二内存通道处于空闲状态时，通过所述第二内存通道发送所述第二内存访问请求。
  41. 根据权利要求40所述的CPU，其特征在于，所述内存控制器中至少包括第一调度器和第二调度器，所述第一调度器对应所述第一内存通道，所述第二调度器对应所述第二内存通道；
    所述第一调度器用于向所述第二调度器发送内存通道占用请求，以请求占用所述第二调度器对应的第二内存通道发送所述第二内存访问请求；以及
    所述第一调度器还用于接收所述第二调度器返回的关于所述内存通道占用请求的确认响应。
  42. 根据权利要求39-41中任一项所述的CPU，其特征在于，所述内存控制器中的每个调度器配置有多个通路，通过所述多个通路与每个内存通道建立连接。
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