CN103988186A - 内存系统、内存模块、内存模块的访问方法以及计算机系统 - Google Patents

内存系统、内存模块、内存模块的访问方法以及计算机系统 Download PDF

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Publication number
CN103988186A
CN103988186A CN201280001334.XA CN201280001334A CN103988186A CN 103988186 A CN103988186 A CN 103988186A CN 201280001334 A CN201280001334 A CN 201280001334A CN 103988186 A CN103988186 A CN 103988186A
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CN
China
Prior art keywords
memory
memory modules
access
modules
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201280001334.XA
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English (en)
Inventor
张立新
陈明宇
黄永兵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Institute of Computing Technology of CAS
Original Assignee
Huawei Technologies Co Ltd
Institute of Computing Technology of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd, Institute of Computing Technology of CAS filed Critical Huawei Technologies Co Ltd
Publication of CN103988186A publication Critical patent/CN103988186A/zh
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1003—Interface circuits for daisy chain or ring bus memory arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)

Abstract

本发明实施例提供一种内存系统、内存模块、内存模块的访问方法以及计算机系统，通过在内存模块中增加一个或多个内存模块间互连接口，使内存系统中分属于不同内存通道的多个内存模块能够通过该内存模块间互连接口建立通信连接，进而使得该内存系统中的内存模块可以同时被多个内存通道所访问，从而在某一内存通道负载过大的时候，实现通过另一负载较轻的内存通道对该负载过大的内存通道上的内存模块的访问，一定程度上解决了内存通道负载不均衡的情况，有效提高了内存通道的利用率。

Description

PCT国内申请，说明书已公开。

Claims (1)

  1. PCT国内申请，权利要求书已公开。
CN201280001334.XA 2012-10-12 2012-10-12 内存系统、内存模块、内存模块的访问方法以及计算机系统 Pending CN103988186A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2012/082824 WO2014056178A1 (zh) 2012-10-12 2012-10-12 内存系统、内存模块、内存模块的访问方法以及计算机系统

Publications (1)

Publication Number Publication Date
CN103988186A true CN103988186A (zh) 2014-08-13

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CN201280001334.XA Pending CN103988186A (zh) 2012-10-12 2012-10-12 内存系统、内存模块、内存模块的访问方法以及计算机系统

Country Status (4)

Country Link
US (1) US20150261698A1 (zh)
EP (1) EP2887223A4 (zh)
CN (1) CN103988186A (zh)
WO (1) WO2014056178A1 (zh)

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CN104461727A (zh) * 2013-09-16 2015-03-25 华为技术有限公司 内存模组访问方法及装置
CN111858388A (zh) * 2019-04-24 2020-10-30 北京京东尚科信息技术有限公司 数据存储、内存访问控制的方法、系统、设备和存储介质
CN116708571A (zh) * 2023-07-22 2023-09-05 武汉船舶职业技术学院 一种基于5g通信的智能终端服务方法、系统及存储介质

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US10318473B2 (en) * 2013-09-24 2019-06-11 Facebook, Inc. Inter-device data-transport via memory channels
US20150169445A1 (en) * 2013-12-12 2015-06-18 International Business Machines Corporation Virtual grouping of memory
US9697114B2 (en) * 2014-08-17 2017-07-04 Mikhael Lerman Netmory
US9645760B2 (en) * 2015-01-29 2017-05-09 Kabushiki Kaisha Toshiba Storage system and control method thereof
US10127165B2 (en) * 2015-07-16 2018-11-13 Samsung Electronics Co., Ltd. Memory system architecture including semi-network topology with shared output channels
US9786389B2 (en) * 2015-10-16 2017-10-10 SK Hynix Inc. Memory system
US10621119B2 (en) * 2016-03-03 2020-04-14 Samsung Electronics Co., Ltd. Asynchronous communication protocol compatible with synchronous DDR protocol
US10334334B2 (en) * 2016-07-22 2019-06-25 Intel Corporation Storage sled and techniques for a data center
US11403035B2 (en) * 2018-12-19 2022-08-02 Micron Technology, Inc. Memory module including a controller and interfaces for communicating with a host and another memory module
US10996890B2 (en) * 2018-12-19 2021-05-04 Micron Technology, Inc. Memory module interfaces
KR20210046348A (ko) * 2019-10-18 2021-04-28 삼성전자주식회사 복수의 프로세서들에 유연하게 메모리를 할당하기 위한 메모리 시스템 및 그것의 동작 방법
US20210209035A1 (en) * 2020-12-26 2021-07-08 Intel Corporation Memory accesses using a memory hub

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CN104461727A (zh) * 2013-09-16 2015-03-25 华为技术有限公司 内存模组访问方法及装置
CN111858388A (zh) * 2019-04-24 2020-10-30 北京京东尚科信息技术有限公司 数据存储、内存访问控制的方法、系统、设备和存储介质
CN111858388B (zh) * 2019-04-24 2024-06-18 北京京东尚科信息技术有限公司 数据存储、内存访问控制的方法、系统、设备和存储介质
CN116708571A (zh) * 2023-07-22 2023-09-05 武汉船舶职业技术学院 一种基于5g通信的智能终端服务方法、系统及存储介质
CN116708571B (zh) * 2023-07-22 2024-05-14 武汉船舶职业技术学院 一种基于5g通信的智能终端服务方法、系统及存储介质

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WO2014056178A1 (zh) 2014-04-17
EP2887223A1 (en) 2015-06-24
US20150261698A1 (en) 2015-09-17
EP2887223A4 (en) 2015-08-19

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