WO2015027596A1 - 过孔刻蚀方法 - Google Patents

过孔刻蚀方法 Download PDF

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Publication number
WO2015027596A1
WO2015027596A1 PCT/CN2013/088465 CN2013088465W WO2015027596A1 WO 2015027596 A1 WO2015027596 A1 WO 2015027596A1 CN 2013088465 W CN2013088465 W CN 2013088465W WO 2015027596 A1 WO2015027596 A1 WO 2015027596A1
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Prior art keywords
etching
via hole
layer
insulating layer
etching method
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English (en)
French (fr)
Inventor
李炳天
蒋冬华
傅永义
赵吾阳
李淳东
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US14/361,083 priority Critical patent/US9564354B2/en
Publication of WO2015027596A1 publication Critical patent/WO2015027596A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections

Definitions

  • Embodiments of the present invention relate to the field of semiconductor fabrication, and in particular, to a via etching method. Background technique
  • LTPS Low Temperature Poly-Silicon
  • Chinese Low Temperature Polysilicon
  • a-Si amorphous silicon
  • Poly-Si polysilicon
  • the electron mobility of polysilicon materials is increased by more than 100 times, so the use of LTPS technology can make display products have faster response time, higher resolution, and better picture display quality.
  • LTPS technology it is possible to reduce the IC IC, the periphery of the display device, and realize the narrow bezel technology.
  • FIG. 1 provides an array substrate intermediate structure using LTPS, the intermediate structure comprising: a substrate 1, a low temperature polysilicon layer 2, a gate insulating layer 3, a gate metal layer 4, and an interlayer insulating layer 5. And source drain via 6 and the like.
  • the operation as shown in FIG. 1 is formed.
  • the inventors have found that at least the following problems exist in the prior art: To form via holes as shown in FIG. 1, the prior art via etching method requires at least etching of the gate insulating layer and the interlayer insulating layer. Generally, the sum of the thicknesses of the gate insulating layer and the interlayer insulating layer is greater than 0.6 um, and the thickness of the low-temperature polysilicon layer is less than 0.05 um. Therefore, the over-etching phenomenon is extremely likely to occur by the prior art via etching method. Therefore, the low-temperature polysilicon over-etching or even the low-temperature polysilicon is completely etched, which adversely affects the performance of the array substrate.
  • the prior art via etching method accomplishes the preparation of vias by multilayer continuous etching, and thus there may be a problem of via slope angle.
  • a terrace is formed on the via hole, thereby affecting the via slope. angle.
  • further wet etching using a mixture of hydrofluoric acid and ammonia is required, which not only increases the complexity of the etching process, but also has a limited effect on the repair of the slope angle.
  • Embodiments of the present invention provide a via etching method that overcomes the drawbacks of the prior art via etching method that the end point of the via is uncontrollable and the slope angle is unfavorable.
  • the embodiment of the present invention adopts the following technical solutions:
  • a via etching method includes: forming a via etching structure, the via etching structure including a low temperature polysilicon layer, a gate insulating layer, a gate metal layer, and an interlayer insulating layer sequentially formed on the substrate; Forming a mask layer including a via mask pattern on the via etch structure; etching the via etch structure by a first etch process, etching to a first thickness of the gate insulating layer Etching the via etch structure by a second etch process, etching the remaining thickness of the gate insulating layer to expose the low temperature polysilicon layer; removing the mask layer to form a via structure.
  • the first etching method is dry etching
  • the second etching method is dry etching using an organic etching gas
  • the organic etching gas includes CF 4 , H 2 , C 4 a mixed gas of F 8 , Ar, and 0 2 .
  • the etching pressure of the first etching process and the second etching process is 0-20 mtorr, and the etching power is not less than 5000 W.
  • the first thickness of the gate insulating layer is 700 ⁇ 140 ⁇ ⁇ .
  • the material of the gate insulating layer is any one or any of silicon nitride, silicon oxide, and silicon carbide material.
  • the via structure formed may have a slope angle of 55° to 75°.
  • a via etching method is provided in the embodiment of the present invention.
  • the via etching method adopts two etching processes in the process of forming a via hole, thereby being capable of forming a via structure while retaining a low temperature polysilicon layer, and A better via slope angle is formed.
  • the via etching method has a single process, and the via structure is better.
  • 1 is a schematic view showing the final structure of a via etch structure according to an embodiment of the present invention
  • 2 is a schematic structural view of a via etch structure according to an embodiment of the present invention
  • FIG. 3 is a second structural schematic view of a via etch structure according to an embodiment of the present invention.
  • FIG. 4 is a third structural schematic view of a via etch structure according to an embodiment of the present invention.
  • FIG. 5 is a fourth structural diagram of a via etch structure according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a via etching method that overcomes the drawbacks of the prior art via etching method that the end point of the via is uncontrollable and the slope angle is unfavorable.
  • the embodiment of the present invention provides a via etching method.
  • the via etching method includes the following steps: Step S101: forming a via etching structure.
  • the via etching structure includes a substrate 1, a low temperature polysilicon layer 2, a gate insulating layer 3, a gate metal layer 4, and an interlayer insulating layer 5.
  • the generated via etch structure is not limited to the film structure shown in FIG. 3, for example: other insulating film layers may be disposed above the interlayer insulating layer.
  • the via etching method of the embodiment of the present invention further needs to etch away other insulating film layers other than the gate insulating layer and the interlayer insulating layer.
  • only the gate insulating layer and the interlayer insulating layer are included in the via etching structure as an example. It should be understood by those skilled in the art that the fabrication process of the via etch structure and the via etch structure mentioned in the present invention does not constitute a further limitation of the via etching method of the embodiment of the present invention. Make a statement.
  • Step S102 forming a mask layer including a via mask pattern on the via etch structure.
  • a mask layer 7 is formed on the via etching structure of the above step S101, and the mask layer 7 includes a via mask pattern for forming via holes.
  • a masking material is spin-coated on the hole etch structure as shown in FIG. 2, and a masking layer including a via mask pattern is formed by a patterning process.
  • the patterning process comprises gluing, exposing, developing, engraving Etching, photoresist stripping and other steps.
  • Step S103 etching the via etching structure by a first etching process to etch the first thickness of the gate insulating layer.
  • the first etching method is performed on the via etching structure of the above step S102.
  • the first etch process can include dry etch.
  • the via etching structure is etched by a first etching process, and the end point of the etching is at the first thickness of the gate insulating layer 3.
  • the first thickness of the gate insulating layer is defined as D1.
  • the first thickness D1 may be 700 to 140 ⁇ .
  • the etching chamber pressure of the first etching process is 0-20 mtorr, and the etching power is not less than 5000 W.
  • the first etching process since the etching end point of the first etching process is the first thickness of the gate insulating layer, the first etching process needs to etch at least the interlayer insulating layer and a part of the gate insulating layer; When the etched structure further includes other insulating layers disposed above the interlayer insulating layer, the first etch process also needs to etch away other insulating layers.
  • Step S104 etching the via etching structure by using a second etching process, etching the remaining thickness of the gate insulating layer to expose the low temperature polysilicon layer.
  • a second etching process is performed on the via etching structure of the above step S103.
  • the via etching structure is etched by a second etching process, and the second etching process etches away the remaining gate insulating layer of the above step to expose the low temperature polysilicon layer. That is, the second etching process etches away the first thickness gate insulating layer remaining in the above step, and the etching end point of the second etching process is at the corresponding position of the low temperature polysilicon layer.
  • the via etching structure forms a structure as shown in FIG.
  • the second etching process may include dry etching using an organic etching gas, which is a mixed gas including CF 4 , H 2 , C 4 F 8 , Ar, 0 2 . It should be noted that the dry etching using the above organic etching gas can make the second etching process have higher etching selectivity, so that the second etching process can etch away the gate insulating layer to the maximum extent. The low temperature polysilicon layer is retained.
  • an organic etching gas which is a mixed gas including CF 4 , H 2 , C 4 F 8 , Ar, 0 2 .
  • the etching chamber pressure of the second etching process is 0-20 mtorr, and the etching power is not less than 5000 W.
  • Step S105 removing the mask layer to form a via structure.
  • a peeling process is performed on the via etching structure that completes the above step S104, and the mask is removed.
  • the mask material of the layer forms a via structure on the via etch structure.
  • the via etching structure forms a structure as shown in FIG.
  • the gate insulating layer mentioned in the embodiment of the present invention may be any one or any of silicon nitride, silicon oxide, and silicon carbide materials, or may be a person skilled in the art. Other insulating materials commonly used in.
  • the via structure formed by the via etching process in the embodiment of the present invention has a slope angle of 55° to 75°.
  • the embodiment of the invention provides a via etching method.
  • the process of the via etching method is relatively simple, and two etching processes are used in the process of forming via holes.
  • the first etching process and the second etching process are used to form the via structure while retaining the low temperature polysilicon layer, thereby overcoming the defects of the prior art which are easy to overetch low temperature polysilicon; and at the same time, the dry etching process is adopted to ensure The formed vias have a good slope angle.

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  • Drying Of Semiconductors (AREA)

Abstract

一种过孔刻蚀方法，涉及半导体制造领域，克服了现有技术过孔刻蚀方法中过孔终点无法控制且坡度角不利的缺陷。过孔刻蚀方法包括：形成过孔刻蚀结构，过孔刻蚀结构包括依次形成在基板（1）上的低温多晶硅层（2）、栅极绝缘层（3）、栅极金属层（4）、层间绝缘层（5）；在过孔刻蚀结构上形成包括过孔掩膜图形的掩膜层（7）；采用第一刻蚀工艺刻蚀过孔刻蚀结构，刻蚀至栅极绝缘层（3）的第一厚度处；采用第二刻蚀工艺刻蚀过孔刻蚀结构，刻蚀掉剩余厚度的栅极绝缘层（3），露出低温多晶硅层（2）；移除掩膜层（7），形成过孔结构。

Description

过孔刻蚀方法 技术领域
本发明的实施例涉及半导体制造领域， 尤其涉及一种过孔刻蚀方法。 背景技术
近年来， 随着显示产品的应用领域越来越广泛， 对显示技术的研究也变 得越来越深入。 作为一种新型制造工艺， LTPS (英文： Low Temperature Poly-Silicon,中文：低温多晶硅)技术利用准分子激光退火工艺将非晶硅（ a-Si ) 薄膜层转变为多晶硅（Poly-Si )薄膜层。 相比非晶硅材料， 多晶硅材料的电 子迁移率有 100倍以上的增加， 因此使用 LTPS技术可使显示产品具有更快 的响应时间， 具有更高的分辨率， 更佳的画面显示品质。 另外使用 LTPS技 术， 能够减少集成电路 IC, 筒化显示装置的外围， 实现窄边框技术。
如图 1所示， 图 1提供了一种应用 LTPS的阵列基板中间结构， 该中间 结构包括： 基板 1、 低温多晶硅层 2、 栅极绝缘层 3、 栅极金属层 4、 层间绝 缘层 5以及源漏极过孔 6等等。 为制备上述阵列基板中间结构， 形成如图 1 工作。
然而， 发明人发现现有技术中至少存在如下问题： 若要形成如图 1所示 的过孔， 现有技术过孔刻蚀方法至少需要刻蚀栅极绝缘层以及层间绝缘层。 通常来说， 栅极绝缘层以及层间绝缘层的厚度之和大于 0.6um, 而低温多晶 硅层的厚度小于 0.05um, 因此， 利用现有技术过孔刻蚀方法极容易发生过刻 蚀现象， 从而出现低温多晶硅过刻蚀甚至将低温多晶硅全部刻蚀掉的情况， 对阵列基板的性能产生不利影响。 另一方面， 现有技术过孔刻蚀方法通过多 层连续刻蚀完成过孔的制备工作， 因此可能存在过孔坡度角问题。举例来说， 在相邻膜层过渡位置处， 由于现有技术过孔刻蚀方法对不同膜层材质刻蚀速 率的差异， 因此会在过孔上形成了梯台， 从而影响了过孔坡度角。 若要消除 该坡度角问题， 还需进一步利用氢氟酸和氨的混合液进行湿法刻蚀， 不仅增 加了刻蚀工艺的复杂程度， 而且对坡度角的修复效果有限。 发明内容
本发明的实施例提供一种过孔刻蚀方法， 克服了现有技术过孔刻蚀方法 中过孔终点无法控制且坡度角不利的缺陷。
为解决上述技术问题， 本发明的实施例采用如下技术方案：
一种过孔刻蚀方法包括： 形成过孔刻蚀结构， 所述过孔刻蚀结构包括依 次形成在基板上的低温多晶硅层、 栅极绝缘层、 栅极金属层、 层间绝缘层； 在所述过孔刻蚀结构上形成包括过孔掩膜图形的掩膜层； 采用第一刻蚀工艺 刻蚀所述过孔刻蚀结构， 刻蚀至所述栅极绝缘层的第一厚度处； 采用第二刻 蚀工艺刻蚀所述过孔刻蚀结构， 刻蚀掉剩余厚度的所述栅极绝缘层， 露出所 述低温多晶硅层； 移除所述掩膜层， 形成过孔结构。
例如， 所述第一刻蚀方式为干法刻蚀； 所述第二刻蚀方法为利用有机刻 蚀气体的干法刻蚀， 所述有机刻蚀气体为包括 CF4、 H2、 C4F8、 Ar、 02的混 合气体。
例如， 所述第一刻蚀工艺以及所述第二刻蚀工艺方法的刻蚀腔体压力为 0 - 20mtorr, 刻蚀功率不小于 5000W。
例如， 所述栅极绝缘层的所述第一厚度为 700 ~ 140θΑ。
例如， 所述栅极绝缘层的材料为氮化硅、 氧化硅、 碳化硅材料中的任意 一种或任意几种。
此外， 形成的所述过孔结构的坡度角可以为 55° ~ 75°。
本发明实施例提供的一种过孔刻蚀方法， 该过孔刻蚀方法形成过孔的过 程中采用了两次刻蚀工艺， 从而能够在形成过孔结构的同时保留低温多晶硅 层， 而且可以形成较好的过孔坡度角。 该过孔刻蚀方法工艺流程筒单， 形成 的过孔结构较佳。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1为本发明实施例过孔刻蚀结构的最终结构示意图； 图 2为本发明实施例过孔刻蚀结构的结构示意图之一；
图 3为本发明实施例过孔刻蚀结构的结构示意图之二；
图 4为本发明实施例过孔刻蚀结构的结构示意图之三；
图 5为本发明实施例过孔刻蚀结构的结构示意图之四。 具体实施方式
本发明的实施例提供一种过孔刻蚀方法， 克服了现有技术过孔刻蚀方法 中过孔终点无法控制且坡度角不利的缺陷。
以下描述中， 为了说明而不是为了限定， 提出了诸如特定系统结构、 接 口、 技术之类的具体细节， 以便透切理解本发明。 然而， 本领域的技术人员 情况中， 省略对众所周知的装置、 电路以及方法的详细说明， 以免不必要的 细节妨碍本发明的描述。
下面结合下述附图对本发明实施例做详细描述。
本发明实施例提供了一种过孔刻蚀方法， 该过孔刻蚀方法包括： 步骤 S101 : 形成过孔刻蚀结构。
如图 2所示，过孔刻蚀结构包括基板 1、低温多晶硅层 2、栅极绝缘层 3、 栅极金属层 4、层间绝缘层 5。需要说明的是，由于不同的阵列基板制备工艺， 生成的过孔刻蚀结构并不仅限于如图 3所示的膜层结构， 例如： 在层间绝缘 层上方还可能设置有其他的绝缘膜层结构， 此时本发明实施例的过孔刻蚀方 法还需刻蚀掉除栅极绝缘层以及层间绝缘层外的其他绝缘膜层。 在本实施例 中仅以过孔刻蚀结构中包括有栅极绝缘层以及层间绝缘层为例进行介绍。 本 领域技术人员应该可以理解的是， 本发明中所提及的过孔刻蚀结构以及过孔 刻蚀结构的制备工艺并不构成对本发明实施例过孔刻蚀方法的进一步限定， 在此不做赘述。
步骤 S102: 在所述过孔刻蚀结构上形成包括过孔掩膜图形的掩膜层。 如图 3所示， 在完成上述步骤 S101的过孔刻蚀结构上形成掩膜层 7, 该 掩膜层 7中包括有用于形成过孔的过孔掩膜图形。 例如， 在如图 2所示的孔 刻蚀结构上旋转涂覆一层掩膜材料， 利用构图工艺， 生成包括过孔掩膜图形 的掩膜层。 其中， 在本发明实施例中， 构图工艺包括涂胶、 曝光、 显影、 刻 蚀、 光刻胶剥离等步骤。
步骤 S103: 采用第一刻蚀工艺刻蚀所述过孔刻蚀结构， 刻蚀至所述栅极 绝缘层的第一厚度处。
对完成上述步骤 S102 的过孔刻蚀结构进行第一刻蚀方法刻蚀。 例如， 第一刻蚀工艺可包括干法刻蚀。 如图 4所示， 采用第一刻蚀工艺刻蚀过孔刻 蚀结构， 刻蚀的终点为栅极绝缘层 3的第一厚度处。 将所述栅极绝缘层的所 述第一厚度定义为 Dl。 例如， 第一厚度 D1可为 700 ~ 140θΑ。 通过第一刻 蚀工艺， 过孔刻蚀结构形成如图 4所示的结构。
例如， 所述第一刻蚀工艺的刻蚀腔体压力为 0 ~ 20mtorr, 刻蚀功率不小 于 5000W。
需要说明的是，由于第一刻蚀工艺刻蚀终点为栅极绝缘层的第一厚度处， 因此第一刻蚀工艺至少需要刻蚀层间绝缘层以及部分栅极绝缘层； 若过孔刻 蚀结构中还包括设置在层间绝缘层上方的其他绝缘层时， 第一刻蚀工艺还需 要刻蚀掉其他绝缘层。
步骤 S104: 采用第二刻蚀工艺刻蚀所述过孔刻蚀结构， 刻蚀掉剩余厚度 的所述栅极绝缘层， 露出所述低温多晶硅层。
例如， 对完成上述步骤 S103 的过孔刻蚀结构进行第二刻蚀工艺。 采用 第二刻蚀工艺刻蚀过孔刻蚀结构， 第二刻蚀工艺刻蚀掉上述步骤剩余的栅极 绝缘层从而露出低温多晶硅层。 也就是说， 第二刻蚀工艺将上述步骤剩余的 第一厚度栅极绝缘层刻蚀掉， 且第二刻蚀工艺的刻蚀终点为低温多晶硅层的 对应位置处。 通过第二刻蚀工艺， 过孔刻蚀结构形成如图 5所示的结构。
例如， 第二刻蚀工艺可包括为利用有机刻蚀气体的干法刻蚀， 所述有机 刻蚀气体为包括 CF4、 H2、 C4F8、 Ar、 02的混合气体。 需要说明的是， 利用 上述有机刻蚀气体的干法刻蚀可使得第二刻蚀工艺具有较高的刻蚀选择性， 使得第二刻蚀工艺在刻蚀掉栅极绝缘层的同时最大程度地使低温多晶硅层得 到保留。
例如， 所述第二刻蚀工艺的刻蚀腔体压力为 0 ~ 20mtorr, 刻蚀功率不小 于 5000W。
步骤 S105: 移除所述掩膜层， 形成过孔结构。
例如， 对完成上述步骤 S104 的过孔刻蚀结构采用剥离工艺， 移除掩膜 层的掩膜材料， 在过孔刻蚀结构上形成过孔结构。 此时过孔刻蚀结构形成如 图 1所示的结构。
例如， 本发明实施例中提及的栅极绝缘层， 其材料可为氮化硅、 氧化硅、 碳化硅材料中的任意一种或任意几种， 或者也可以为本领域技术人员在本领 域中常用的其他绝缘材料。
例如， 本发明实施例中过孔刻蚀工艺形成的所述过孔结构的坡度角为 55° ~ 75°。
本发明实施例提供了一种过孔刻蚀方法， 该过孔刻蚀方法工艺流程较为 筒单， 形成过孔的过程中采用了两次刻蚀工艺。 通过第一刻蚀工艺以及第二 刻蚀工艺在形成过孔结构的同时保留低温多晶硅层， 克服了现有技术易于过 刻蚀低温多晶硅的缺陷； 同时， 由于采用了干法刻蚀工艺， 保证了形成的过 孔具有较好的坡度角。
以上所述， 仅为本发明的实施方式， 但本发明实施例的保护范围并不局 限于此,任何熟悉本技术领域的技术人员在本发明实施例揭露的技术范围内， 可轻易想到变化或替换， 都应涵盖在本发明实施例的保护范围之内。 因此， 本发明实施例的保护范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种过孔刻蚀方法， 其中， 包括：
形成过孔刻蚀结构， 所述过孔刻蚀结构包括依次形成在基板上的低温多 晶硅层、 栅极绝缘层、 栅极金属层、 层间绝缘层；
在所述过孔刻蚀结构上形成包括过孔掩膜图形的掩膜层；
采用第一刻蚀工艺刻蚀所述过孔刻蚀结构， 刻蚀至所述栅极绝缘层的第 一厚度处；
采用第二刻蚀工艺刻蚀所述过孔刻蚀结构， 刻蚀掉剩余厚度的所述栅极 绝缘层， 露出所述低温多晶硅层；
移除所述掩膜层， 形成过孔结构。
2、根据权利要求 1所述的过孔刻蚀方法， 其中， 所述第一刻蚀方式为干 法刻蚀； 所述第二刻蚀方法为利用有机刻蚀气体的干法刻蚀， 所述有机刻蚀 气体为包括 CF4、 H2、 C4F8、 Ar、 02的混合气体。
3、根据权利要求 1或 2所述的过孔刻蚀方法， 其中， 所述第一刻蚀工艺 以及所述第二刻蚀工艺的刻蚀腔体压力为 0 ~ 20mtorr, 刻蚀功率不小于 5000W。
4、根据权利要求 1所述的过孔刻蚀方法， 其中， 所述栅极绝缘层的所述 第一厚度为 700 ~ 140θΑ。
5、根据权利要求 1所述的过孔刻蚀方法， 其中， 所述栅极绝缘层的材料 为氮化硅、 氧化硅、 碳化硅材料中的任意一种或任意几种。
6、根据权利要求 1所述的过孔刻蚀方法， 其中， 形成的所述过孔结构的 坡度角为 55° ~ 75°。
PCT/CN2013/088465 2013-08-30 2013-12-03 过孔刻蚀方法 Ceased WO2015027596A1 (zh)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030064601A1 (en) * 2001-09-28 2003-04-03 Thompson Keith J. Method for via etching in organo-silica-glass
CN1604288A (zh) * 2003-10-03 2005-04-06 株式会社半导体能源研究所 半导体器件的制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5741741A (en) * 1996-05-23 1998-04-21 Vanguard International Semiconductor Corporation Method for making planar metal interconnections and metal plugs on semiconductor substrates
US6284642B1 (en) * 1999-08-11 2001-09-04 Taiwan Semiconductor Manufacturing Company Integrated method of damascene and borderless via process
US20050260804A1 (en) * 2004-05-24 2005-11-24 Tae-Wook Kang Semiconductor device and method of fabricating the same
JP2007019393A (ja) * 2005-07-11 2007-01-25 Toshiba Matsushita Display Technology Co Ltd 薄膜トランジスタ及びその製造方法
US20070066074A1 (en) * 2005-09-19 2007-03-22 Nace Rossi Shallow trench isolation structures and a method for forming shallow trench isolation structures
CN101894791B (zh) * 2009-05-18 2014-03-12 中芯国际集成电路制造(北京)有限公司 接触孔的形成方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030064601A1 (en) * 2001-09-28 2003-04-03 Thompson Keith J. Method for via etching in organo-silica-glass
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