CN106935545B - 阵列基板及其制备方法和应用 - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 84
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 238000002161 passivation Methods 0.000 claims abstract description 90
- 238000000034 method Methods 0.000 claims abstract description 85
- 238000005530 etching Methods 0.000 claims abstract description 77
- 230000008569 process Effects 0.000 claims abstract description 37
- 238000005468 ion implantation Methods 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
- 239000000203 mixture Substances 0.000 claims abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 28
- -1 aluminum ions Chemical class 0.000 claims description 22
- 230000007704 transition Effects 0.000 claims description 20
- 238000001883 metal evaporation Methods 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 239000010406 cathode material Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 23
- 230000001681 protective effect Effects 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 130
- 239000000463 material Substances 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 19
- 239000002184 metal Substances 0.000 description 19
- 239000007789 gas Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 10
- 238000002513 implantation Methods 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 229910004205 SiNX Inorganic materials 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 229910052593 corundum Inorganic materials 0.000 description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Abstract
本发明提出了阵列基板及其制备方法和应用。该制备阵列基板的方法包括:在衬底基板上形成钝化层;在钝化层远离衬底的一侧形成光刻胶层,并对光刻胶层进行构图工艺形成具有开口图案的光掩膜;对开口图案对应的钝化层区域进行离子注入;刻蚀开口图案对应的钝化层区域,形成贯穿所述钝化层的过孔;剥离光掩膜。本发明所提出的制备方法,通过预先注入离子,使得钝化层刻蚀过程中凹槽的两侧侧壁和底壁形成一层薄薄的保护膜,由于底壁的保护膜相较于两侧壁的更容易被刻蚀掉,从而使垂直方向的刻蚀速度快于侧向的刻蚀速度,从而可有效控制钝化层刻蚀方向,能有效地解决底切不良现象所带来的阵列基板制作良品率降低的问题。
Description
技术领域
本发明涉及显示技术领域,具体的,本发明涉及阵列基板及其制备方法和应用。更具体的,涉及制备阵列基板的方法、阵列基板和显示装置。
背景技术
传统的TFT产品制作过程中,制作钝化层的材质通常会选择SiNx,并且该SiNx钝化层一般分为三层:过渡亚层、主体亚层和顶亚层。其中,过渡亚层的作用是避免钝化层主体与像素电极直接接触产生黑点不良,且过渡亚层的SiNx密度较小;顶亚层的作用是在等离子体刻蚀中起到缓冲作用,并使过孔达到一定的坡度角和尺寸。所以,由于亚层结构的疏松程度不同,造成了各亚层的刻蚀速率不同。
目前,在制作TFT基板的钝化层过孔过程中,由于钝化层的主体亚层与底部过渡亚层的刻蚀速率不同,参考图1,在刻蚀过程中容易出现底切倒角的现象,参考图2,进而容易造成顶部ITO层与S/D电极层之间出现接触跨断的问题,从而可能导致TFT产品显示异常甚至无法显示,最终造成了TFT基板制作的良品率降低。
因此,现阶段的TFT基板的制作方法仍有待改进。
发明内容
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。
本发明是基于发明人的下列发现而完成的:
本发明人在研究过程中发现,传统的制作TFT产品钝化层过孔的步骤中,采用活性等离子体进行刻蚀,等离子体比较容易进入较疏松的顶亚层,而能达到刻蚀的目的;而当刻蚀到过渡亚层时,由于其刻蚀速率与主体亚层的不同则会产生缩进(即过渡亚层的侧向刻蚀程度大于相邻的主体亚层底部),也就产生了底切不良的现象,具体结构示意图参考图1。
为了解决上述技术问题,本发明的发明人经过深入研究发现,在制作完钝化层过孔的光刻胶掩膜图案后,先利用光刻胶掩膜图案为阻挡层,进行金属铝离子注入,使未被光刻胶保护区域的氮化硅中均匀地分布金属铝离子;如此,当利用刻蚀气体刻蚀氮化硅钝化层的过程中,刻蚀凹槽的两侧侧壁表层中的金属铝会生成一层薄薄的抗等离子体刻蚀性强的保护膜,因此,可以保护钝化层在刻蚀过程中不会被过度侧向刻蚀而避免产生底切倒角的技术问题。
有鉴于此,本发明的一个目的在于提出一种能有效控制钝化层刻蚀方向、防止底切不良问题或操作简单的制备阵列基板的方法。
在本发明的第一方面,本发明提出了一种制备阵列基板的方法。
根据本发明的实施例,所述方法包括:在衬底基板上形成钝化层;在所述钝化层远离所述衬底的一侧形成光刻胶层,并对所述光刻胶层进行构图工艺形成具有开口图案的光掩膜;对所述开口图案对应的钝化层区域进行离子注入;刻蚀所述开口图案对应的钝化层区域,形成贯穿所述钝化层的过孔;剥离所述光掩膜。
采用本发明实施例的制备方法,通过预先注入金属离子,使得钝化层刻蚀过程中凹槽的两侧侧壁和底壁形成一层薄薄的保护膜,由于底壁的保护膜相较于两侧壁的更容易被刻蚀掉,从而使垂直方向的刻蚀速度快于侧向的刻蚀速度,从而可有效控制钝化层刻蚀方向,能有效地解决底切不良现象所带来的阵列基板制作良品率降低的问题。
另外,根据本发明上述实施例的制备方法,还可以具有如下附加的技术特征:
根据本发明的实施例,在所述衬底基板上形成钝化层之前,进一步包括:在所述衬底基板上形成源漏电极层,且所述源漏电极层和所述钝化层是形成在所述衬底的同侧。
根据本发明的实施例,形成所述钝化层进一步包括:在所述衬底上的源漏电极层的远离所述衬底的一侧形成过渡亚层;在所述过渡亚层远离所述衬底的一侧形成主体亚层;以及在所述主体亚层远离所述衬底的一侧形成顶亚层。
根据本发明的实施例,所述注入的离子为铝离子。
根据本发明的实施例,所述注入铝离子的方法为金属蒸发真空弧离子注入方法。
根据本发明的实施例,所述金属蒸发真空弧离子注入方法采用的阴极材料是纯度不小于90w/w%的金属铝。
根据本发明的实施例,所述铝离子的注入剂量为4×1016~6×1016ion/cm2。
根据本发明的实施例,所述刻蚀采用的气体为SF6和CF4中的至少一种以及O2。
在本发明的第二方面,本发明提出了一种阵列基板。
根据本发明的实施例,所述阵列基板是通过上述的方法获得的。
本发明实施例的阵列基板,顶层ITO层与S/D电极之间不容易出现接触跨断的问题,其良品率更高。本领域技术人员能够理解的是,前面针对制备阵列基板的方法所描述的特征和优点,仍适用于该阵列基板,在此不再赘述。
在本发明的第三方面,本发明提出了一种显示装置。
根据本发明的实施例,所述显示装置包括上述的阵列基板。
本发明实施例的显示装置,其阵列基板的顶层ITO层与S/D电极之间不会有接触跨断的现象,其良品率更高、显示质量更佳。本领域技术人员能够理解的是,前面针对制备阵列基板的方法、阵列基板所描述的特征和优点,仍适用于该显示装置,在此不再赘述。
本发明的附加方面和优点将在下面的描述中部分给出,部分将从下面的描述中变得明显,或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解,其中:
图1是现有技术一个实施例的钝化层过孔刻蚀的底切不良的结构示意图;
图2是现有技术一个实施例的顶层ITO与S/D电极层之间接触跨断的结构示意图;
图3是本发明一个实施例的制备阵列基板的方法的流程示意图;
图4是本发明一个实施例的衬底的结构示意图;
图5是本发明一个实施例的制备方法步骤S200获得的阵列基板的结构示意图;
图6是本发明一个实施例的制备方法步骤S300的注入金属铝离子的示意图;
图7是本发明一个实施例的制备方法步骤S400的刻蚀过程的示意图;
图8是本发明一个实施例的制备方法步骤S400的形成刻蚀凹槽过程的示意图;
图9是本发明一个实施例的制备方法步骤S400获得的阵列基板的结构示意图;
图10是本发明一个实施例的制备方法步骤S500获得的阵列基板的结构示意图;
图11是本发明一个实施例的制备方法步骤S100获得的衬底的结构示意图。
附图标记
1 底切
100 钝化层
110 过渡亚层
120 主体亚层
130 顶亚层
200 S/D电极层
300 光掩模
400 刻蚀凹槽
410 保护膜
500 过孔
600 顶层ITO
700 衬底基板
具体实施方式
下面详细描述本发明的实施例,本技术领域人员会理解,下面实施例旨在用于解释本发明,而不应视为对本发明的限制。除非特别说明,在下面实施例中没有明确描述具体技术或条件的,本领域技术人员可以按照本领域内的常用的技术或条件或按照产品说明书进行。所用试剂或仪器未注明生产厂商者,均为可通过市购到的常规产品。
在本发明的一个方面,本发明提出了一种制备阵列基板的方法。参照图3~10,对本发明的制备方法进行详细的描述。根据本发明的实施例,参考图3,该制备方法包括:
S100:在衬底基板上形成钝化层。
在该步骤中,参考图11,在衬底基板700上形成钝化层100。根据本发明的实施例,获得该衬底基板700的具体方法不受特别的限制,例如市购或自行制作,只要该衬底基板700满足使用要求即可,本领域技术人员可根据实际的情况进行选择。
根据本发明的实施例,钝化层100可以直接形成在衬底基板700的一侧,钝化层100和衬底基板700之间也可以设置有其他层结构,参考图11(图11中用“...”简略地表示其它层结构),比如S/D电极层、栅极、栅绝缘层和像素电极层等,本领域技术人员可根据该阵列基板的使用要求进行设计和补充,在此不再进行赘述。
在本发明的一些实施例中,衬底基板700和钝化层100之间可进一步包括源漏电极层(S/D电极层)200,其中,源漏电极层200和钝化层100是形成在衬底基板700的同侧,即钝化层100形成在S/D电极层200的远离衬底基板700一侧的表面。如此设置S/D电极层200的位置,在钝化层100形成过孔500后,再通过形成顶层ITO可将其与S/D电极层200直接电相连。在一些具体示例中,过渡层100和衬底基板700之间除了S/D电极层外,还可以包括其他层结构,以底栅结构为例,具体例如栅极、栅绝缘层和像素电极层等,本领域技术人员可根据阵列基板的实际要求进行设计。
根据本发明的实施例,该钝化层100的具体材料不受特别的限制,本领域内任何已知的钝化层材料均可,只要该钝化层100材料满足使用要求即可,本领域技术人员可根据实际的情况进行选择。在本发明的一些实施例中,该钝化层100的材料可以为SiNx,如此,采用上述材料的钝化层对阵列基板具有更好的保护作用。
根据本发明的实施例,参考图4,该钝化层100可以进一步包括:过渡亚层110、主体亚层120以及顶亚层130。其中,过渡亚层110形成在S/D电极层200远离衬底基板700的一侧;主体亚层120形成在过渡亚层110远离衬底基板700的一侧;且顶亚层130形成在主体亚层120远离过渡亚层110的一侧。如此设计,顶亚层130的作用在于使等离子刻蚀过程中的刻蚀凹槽达到一定的坡度角和尺寸,而过渡亚层110的作用是避免主体亚层120与像素电极直接接触容易产生黑点等不良现象,所以选择上述复合结构的钝化层100,能有效地保证过孔500的顺利刻蚀及好的刻蚀效果。
根据本发明的实施例,形成过渡亚层110、主体亚层120以及顶亚层130的具体方法,不受特别的限制,本领域内常规的形成各个钝化层亚层的方法均可,只要该方法能形成上述复合结构的钝化层即可,本领域技术人员可根据实际的制造过程和钝化层的具体设计进行选择,在此不再赘述。
S200:在钝化层远离衬底的一侧形成光刻胶层,并对光刻胶层进行构图工艺形成具有开口图案的光掩膜。
在该步骤中,参考图5,在钝化层100的顶亚层130的远离衬底基板700的一侧表面,形成光掩膜,并且对该光掩膜300进行构图工艺形成具有开口图案的光掩模300。如此,通过具有与过孔500相应的图案的光掩膜300,能使钝化层100在特定的位置形成过孔500(图5中未标出),比如像素电极通过所述过孔与漏极连接。
根据本发明的实施例,光掩膜300的具体材料不受特别的限制,本领域任何内常用的光掩模材料均可,只要该光掩膜的材料能保护非过孔区域的钝化层不被刻蚀即可,本领域技术人员可根据钝化层100的具体材料和后续刻蚀过孔500的具体工艺进行选择。在本发明的一些实施例中,光掩膜300可以为光刻胶材料。如此,采用上述由光刻胶材料形成的光掩膜300,在保证非过孔区域的钝化层不会被后续刻蚀影响的同时,且刻蚀完成后还易被除去,并不会影响钝化层100的使用性能和表面形貌。
根据本发明的实施例,光掩膜300的具体厚度也不受特别的限制,本领域任何内常用的光掩膜厚度均可,只要该光掩膜的厚度能有效地保护非过孔区域的钝化层不被刻蚀即可,本领域技术人员可根据后续刻蚀过孔500的具体工艺进行选择,在此不再赘述。
S300:对开口图案对应的钝化层区域进行离子注入。
在该步骤中,在钝化层100的远离衬底基板700的一侧表面上光掩模300开口图案对应的钝化层区域,注入离子,用于调整和控制后续刻蚀处理的速度和角度。
根据本发明的实施例,注入的离子的具体种类不受特别的限制,只要该离子能在后续的刻蚀过程中有效地调控刻蚀角度即可,本领域技术人员可根据实际的刻蚀过程进行选择。在本发明的一些实施例中,注入的离子可以是铝离子。参考图6,为了形象地表示金属铝离子注入完成后的效果,图6中是将放大后标注出来的示意效果。如此,刻蚀过程中预先注入的金属铝离子能与后续刻蚀处理的刻蚀气体反应生成保护膜,能够调控刻蚀速度和刻蚀角度,从而可以解决过渡亚层和主体亚层的刻蚀速度不同所带来的底切不良的问题。
根据本发明的实施例,注入金属铝离子的具体方法不受特别的限制,只要该方法能使金属铝离子均匀地注入到钝化层即可,本领域技术人员可根据钝化层的具体材料和后续刻蚀过孔500的具体工艺进行选择。在本发明的一些实施例中,注入金属铝离子方法可以采用金属蒸发真空弧离子注入方法。如此,采用金属蒸发真空弧离子注入法,可有效地将金属铝离子更均匀地注入到整个钝化层。
根据本发明的实施例,采用金属蒸发真空弧离子注入法的具体工艺参数不受特别的限制,只要该工艺参数能使金属铝离子均匀地注入到钝化层即可,本领域技术人员可根据钝化层的具体材料和厚度进行设置。在本发明的一些实施例中,金属蒸发真空弧离子注入方法的具体阴极材料可以采用纯度不小于90w/w%的金属铝,如此,采用上述纯度的阴极材料,能使铝离子的注入效果和后续刻蚀调控效果更佳。在本发明的一些实施例中,金属铝离子的具体注入剂量可以为4×1016ion/cm2~6×1016ion/cm2,如此,采用上述的注入剂量,可使金属铝离子更充分均匀地注入到整个钝化层,从而对后续刻蚀的调控效果更佳。在本发明的一些具体示例中,采用金属蒸发真空弧离子注入系统,其阴极材料采用纯度为99.99w/w%的金属铝,在离子注入前先将靶室抽真空至10-4Pa,再在脉冲频率为20Hz、加速电压为40keV和注入剂量为5×1016ion/cm2的离子注入工艺参数下,进行金属铝离子的注入。如此,采用上述金属蒸发真空弧离子注入法的工艺参数,能获得最佳的铝离子的注入效果和后续刻蚀调控效果。
S400:刻蚀开口图案对应的钝化层区域,形成贯穿所述钝化层的过孔。
在该步骤中,对光掩模300的开口图案对应的的钝化层100进行刻蚀处理,以便形成贯穿所述钝化层100的过孔500。
根据本发明的实施例,该刻蚀的具体方法不受特别的限制,只要该刻蚀方法能有效地刻蚀出贯穿钝化层的过孔且不会破坏非过孔区域即可,本领域技术人员可根据钝化层的具体材料进行选择。在本发明的一些实施例中,可采用电感耦合等离子体(ICP)刻蚀设备获得钝化层的过孔。如此,参考图7,该ICP刻蚀设备利用高速向下运动的等离子体,持续地轰击未被光掩模300保护的钝化层100,从而在刻蚀过程中形成刻蚀凹槽400,具体结构示意图参考图8,刻蚀完成后形成过孔500,具体结构示意图参考图9。
根据本发明的实施例,该刻蚀采用的气体不受特别的限制,只要该刻蚀气体能有效地刻蚀掉钝化层且能与预先注入的金属铝离子形成保护膜即可,本领域技术人员可根据钝化层的具体材料和刻蚀处理的具体方法进行选择。在本发明的一些实施例中,刻蚀气体可以为组合气体,即为SF6和CF4中的至少一种以及O2。如此,采用上述组合刻蚀气体,其O2能与预先注入的Al3+形成Al2O3的保护膜,从而可调控刻蚀过程的方向和速度。
参考图8,在刻蚀过程中在刻蚀凹槽400的两侧侧壁和底壁,组合刻蚀气体的O等离子体能与Al3+反应生成一层薄薄的Al2O3保护膜410,由于ICP刻蚀设备形成的等离子体是高速向下运动的,所以刻蚀凹槽400底壁的Al2O3薄膜410更容易被轰击掉从而继续向下刻蚀,而两侧侧壁的刻蚀速度更缓慢,有利于形成具有一定坡度和平滑度的刻蚀凹槽400。因此,预先注入的金属铝离子通过与组合刻蚀气体的O2反应生成Al2O3薄膜,从而可有效地调控刻蚀过程的方向和速度,进而能有效地解决底切不良现象所带来的阵列基板制作良品率降低的问题。
根据本发明的实施例,刻蚀处理的具体工艺参数,例如刻蚀时间等,不受特别的限制,只要该刻蚀处理的工艺参数能使钝化层形成过孔即可,本领域技术人员可根据钝化层的具体材料和厚度以及实际刻蚀情况进行设计和调整,在此不再赘述。
S500:剥离光掩膜。
在该步骤中,完成刻蚀处理后可将光掩膜300从钝化层100的表面剥离,即可获得过孔500,参考图10。根据本发明的实施例,剥离光掩膜300的具体方法不受特别的限制,只要该剥离方法能使光掩膜300有效地离开钝化层未被刻蚀的区域且不会影响钝化层的性能与表面质量即可,本领域技术人员可根据钝化层100和光掩膜300的性能进行选择,在此不再赘述。
综上所述,根据本发明的实施例,本发明提出了一种制备方法,通过预先注入金属铝离子,使得钝化层刻蚀过程中凹槽的两侧侧壁和底壁形成一层薄薄的保护膜,由于底壁的保护膜相较于两侧壁的更容易被刻蚀掉,从而使垂直方向的刻蚀速度快于侧向的刻蚀速度,从而可有效控制钝化层刻蚀方向,能有效地解决底切不良现象所带来的阵列基板制作良品率降低的问题。
在本发明的另一个方面,本发明提出了一种阵列基板。根据本发明的实施例,该阵列基板是通过上述的方法获得的。
综上所述,根据本发明的实施例,本发明提出了一种阵列基板,该阵列基板的顶层ITO层与S/D电极之间不容易出现接触跨断的问题,其良品率更高。本领域技术人员能够理解的是,前面针对制备阵列基板的方法所描述的特征和优点,仍适用于该阵列基板,在此不再赘述。
在本发明的另一个方面,本发明提出了一种显示装置。根据本发明的实施例,该显示装置包括上述的阵列基板。
根据本发明的实施例,该显示装置的具体类型不受特别的限制,本领域内任何已知的显示装置类型均可,具体例如电视、手机、电脑显示屏、平板显示器、游戏机、可穿戴设备及具有显示面板的生活、家用电器等等,本领域技术人员可根据显示装置的实际使用条件进行选择,在此不再赘述。
需要说明的是,该显示装置除了阵列基板还包括其他必要的组成或结构,以LED显示器为例,还可以包括彩膜基板、光源组件、控制组件、电路和外壳,等等,本领域技术人员可根据显示装置的具体类型进行补充和设计,在此不做过多的描述。
综上所述,根据本发明的实施例,本发明提出了一种显示装置,其阵列基板的顶层ITO层与S/D电极之间不会有接触跨断的现象,其良品率更高、显示质量更佳。本领域技术人员能够理解的是,前面针对制备阵列基板的方法、阵列基板所描述的特征和优点,仍适用于该显示装置,在此不再赘述。
在本发明的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。
在本说明书的描述中,参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中,对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且,描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外,在不相互矛盾的情况下,本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例,可以理解的是,上述实施例是示例性的,不能理解为对本发明的限制,本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。
Claims (8)
1.一种制备阵列基板的方法,其特征在于,包括:
在衬底基板上形成钝化层;
在所述钝化层远离所述衬底的一侧形成光刻胶层,并对所述光刻胶层进行构图工艺形成具有开口图案的光掩膜;
对所述开口图案对应的钝化层区域进行离子注入,且所述注入的离子为铝离子;
刻蚀所述开口图案对应的钝化层区域,形成贯穿所述钝化层的过孔,且所述刻蚀采用的气体为SF6和CF4中的至少一种以及O2;
剥离所述光掩膜。
2.根据权利要求1所述的方法,其特征在于,在所述衬底基板上形成钝化层之前,进一步包括:
在所述衬底基板上形成源漏电极层,且所述源漏电极层和所述钝化层是形成在所述衬底的同侧。
3.根据权利要求2所述的方法,其特征在于,在所述衬底基板上形成所述钝化层进一步包括:
在所述源漏电极层的远离所述衬底的一侧形成过渡亚层;
在所述过渡亚层远离所述衬底的一侧形成主体亚层;以及
在所述主体亚层远离所述衬底的一侧形成顶亚层。
4.根据权利要求1所述的方法,其特征在于,所述注入铝离子的方法为金属蒸发真空弧离子注入方法。
5.根据权利要求4所述的方法,其特征在于,所述金属蒸发真空弧离子注入方法采用的阴极材料是纯度不小于90w/w%的金属铝。
6.根据权利要求4所述的方法,其特征在于,所述铝离子的注入剂量为4×1016~6×1016ion/cm2。
7.一种阵列基板,其特征在于,是通过权利要求1-6任一项所述的方法制备的。
8.一种显示装置,其特征在于,包括权利要求7所述的阵列基板。
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