WO2015024317A1 - 栅线驱动方法、栅极驱动电路以及显示装置 - Google Patents

栅线驱动方法、栅极驱动电路以及显示装置 Download PDF

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Publication number
WO2015024317A1
WO2015024317A1 PCT/CN2013/087957 CN2013087957W WO2015024317A1 WO 2015024317 A1 WO2015024317 A1 WO 2015024317A1 CN 2013087957 W CN2013087957 W CN 2013087957W WO 2015024317 A1 WO2015024317 A1 WO 2015024317A1
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Prior art keywords
gate
gate line
time
line driving
display device
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PCT/CN2013/087957
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English (en)
French (fr)
Inventor
时凌云
张�浩
董学
金亨奎
薛子姣
姚金明
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北京京东方光电科技有限公司
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Publication of WO2015024317A1 publication Critical patent/WO2015024317A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the invention relates to a liquid crystal display collar
  • liquid crystal display devices Due to its long life, high luminous efficiency, low radiation, and low power consumption, liquid crystal display devices have gradually replaced traditional ray tube display devices as the research direction of mainstream display device products in recent years.
  • the gate line driving method As a method of driving the gate line of the liquid crystal display device, the gate line driving method provided by the prior art generally uses a driving method of progressive scanning.
  • the progressive scan driving method refers to an image display process in which the liquid crystal display device is completed by scanning the rows of gate lines in sequence within one ⁇ , starting from the first gate line.
  • the inventors found that at least the following problems exist in the prior art: Since the progressive scan driving method sequentially scans each row of gate lines to complete the image Therefore, the driving signals for driving the adjacent gate lines are usually spaced at a small interval, and even overlap may occur in time, which causes the driving signals driving the adjacent gate lines to be easily coupled, eventually causing flicker or data of the displayed image. The phenomenon of crosstalk.
  • Embodiments of the present invention provide a gate line driving method, a gate driving circuit, and a display device, which reduce flicker or data crosstalk during display of an image by a display device, and can effectively reduce line inversion or dot inversion 0 inch. Power consumption.
  • the embodiment of the present invention adopts the following technical solutions:
  • a gate line driving method in which a odd-numbered row gate line is sequentially driven in a first time, and a second driving voltage is sequentially applied to drive an even-numbered row gate line in a second time after the end of the first time, thereby completing one frame time
  • the gate line drive process in which a odd-numbered row gate line is sequentially driven in a first time, and a second driving voltage is sequentially applied to drive an even-numbered row gate line in a second time after the end of the first time, thereby completing one frame time.
  • the opening time intervals of the adjacent odd-numbered gate lines are the same, and in the second time, the opening time intervals of the adjacent even-numbered gate lines are the same.
  • the one frame time includes: the first day interval and the second day interval.
  • the gate line driving method further includes: after completing the gate line driving process in the one frame time, continuing to complete the next frame time according to the manner of repeating the gate line driving process in the one frame time The gate line drive process until the gate line drive process is completed for all frame times.
  • an embodiment of the present invention further provides a gate driving circuit including a bilateral driving circuit, wherein a first side driving circuit of the bilateral driving circuit is connected to an odd row gate line for use in a first time Driving the odd-numbered row gate lines in sequence; the second side driving circuit in the bilateral driving circuit is connected to the even-numbered row-gate lines, and is used to sequentially drive the even-numbered row-gate lines in the second time after the end of the first interval , thereby completing the gate line driving process within one frame time.
  • the opening time intervals of the adjacent odd-numbered gate lines are the same, and in the second time, the opening time intervals of the adjacent even-numbered gate lines are the same.
  • the one frame time includes: the first time and the second time.
  • the gate line driving process in the next frame time is continued to be completed in a manner of repeating the gate line driving process in the one frame time until all the steps are completed.
  • the gate line drive process during the time.
  • an embodiment of the present invention further provides a display device including the above-mentioned gate driving circuit, wherein the display device only inverts in a frame time in a process of displaying an image by dot inversion or line inversion. Display the polarity of the graph at a time.
  • the gate line driving method, the gate driving circuit and the display device provided by the embodiment of the present invention remotely drive the odd-numbered gate lines in the first time, and the second time after the end of the first H-inch period Sub-drive even-numbered gate lines, thereby separating the driving process of odd-numbered gate lines from the driving process of even-numbered gate lines, reducing the possibility of signal crosstalk between adjacent gate lines, and improving the image display effect of the display device
  • the same day through the above-mentioned adjustment gate line driving sequence reducing the number of times the driving voltage electrode is reversed during the gate line driving process, thereby making the display device more power efficient.
  • FIG. 1 is a control sequence diagram of a gate line driving method provided by the prior art
  • FIG. 2 is a timing chart of control of a gate line driving method according to an embodiment of the present invention.
  • FIG. 3 is another timing diagram of control of a gate line driving method according to an embodiment of the present invention.
  • FIG. 4 is a schematic view showing a line inversion image display using a gate line driving method provided by the prior art
  • FIG. 5 is a schematic diagram of performing line inversion image display by applying a gate line driving method according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a gate line driving method, a gate driving circuit, and a display device, which reduce flicker or data crosstalk during display of an image by a display device, and can effectively reduce line inversion or dot inversion. Power consumption.
  • An embodiment of the present invention provides a gate line driving method, where the gate line driving method is within a first time t1, The first driving voltage VI is sequentially driven to drive the odd-numbered gate lines. In the second time t2 after the end of the first time t1, the second driving voltage V2 is loaded to sequentially drive the even-numbered gate lines, thereby completing the gate line driving for a period of time. process. After the gate line driving in one frame period is completed, the above driving process is repeated, and the gate line driving process for the display device can be completed.
  • the first driving voltage VI and the second driving voltage V2 may be the same or different, as long as the gate line of the row is ensured to be turned on.
  • the gate line driving method provided by the embodiment of the present invention, two vertical scans are actually performed in one frame time, that is, the first time t1 is driven to scan the odd-numbered gate lines, and the second time is ⁇ 2. Drives the scan of even-numbered gate lines. Therefore, the sum of the times of the first time t! and the second time t2 is equal to the time of one image display frame.
  • the STV signal is used as a trigger signal for a shift register (GOA) unit connected to the corresponding gate line
  • the CLK signal is used as the CLK signal. Controls the clock signal of the shift output of the GOA unit, and completes the control process of the gate line on/off through the STV signal and the CLK signal.
  • a display device including a 2N row gate line is taken as an example. (where N is any natural number).
  • the on/off of the gate line is determined by the GATE signal provided by the shift register GOA unit connected to the gate line. Further, the GATE signal is generated by the eclipse signal STV and the clock signal CLK after the trigger signal STV is triggered. Specifically, the trigger signal STV is used as an ON signal for the operation of the GOA unit, and the clock signal CLK controls the shift output of the GOA unit.
  • the first side driving circuit in the bilateral driving circuit includes the GOA units respectively connected to the odd-numbered gate lines, for example, the GOAI is connected to the first gate line, GOA3 is connected to the third gate line, and so on; the second side driver circuit of the bilateral driving circuit, wherein the GOA unit is respectively connected with the even row gate line, for example, the GOA2 and the second gate line are connected, the GOA4 and the fourth gate are connected. Line connection..., and so on.
  • the trigger signal may include STV 1R, STV 1L, STV 2R, STV 2L.
  • the STV 1R is used as an ON signal for triggering the operation of the GOA (1) connected to the first gate line in the odd-numbered gate lines, and then shifted to the GOA connected to the fifth gate line, the ninth gate line, and the like (5) ), GOA (9), GOA ( 13 ), .... GOA (4n+l ), where n::::0, 1, 2, , ,; STV 2R is used to trigger odd-numbered gate lines and Triple gate connected GOA (3) The open signal of the operation is then shifted and transmitted to the GOA (7), GOA (11), GO A (15), ..., GOA (4n+) connected to the seventh gate line, the eleventh gate line, and the like.
  • STV !L is used as the turn-on signal of the GOA(2) operation connected to the second gate line in the even-numbered row gate line, and then shifted to the first GOA (6), GOA (10), GOA (14) connected to the six-gate line, the tenth gate line, etc .; STV2L is used as the GOA (4) connected to the fourth gate line in the even-numbered row gate line, and then The shift is transmitted to GOA (8), GOA (12), ..., GOA (4n + 4) connected to the eighth gate line, the twelfth gate line, etc., where ⁇ ! , 2,,,.
  • the clock signals include CLK.1R, CLK 1L, CLK 2R, CLK 2L, ..., CLK NR. CLK NL.
  • the clock signal CLK 1R is used to control the shift output of the GOA (1) unit
  • the clock signal CLK 2R is used to control the shift output of the GOA (3) unit, ...
  • the clock signal CLK.NR is used to control the GOA.
  • inch clock signal CLK 1L is used to control the shift output of the GOA (2) unit
  • the opening time interval of the adjacent odd-numbered gate lines is the same, and in the second H-inch interval t2, the opening time of the adjacent even-numbered gate lines is made.
  • the interval is the same.
  • the first time t1 and the second time t2 are independent of each other, the interval between the adjacent odd-numbered row gate lines and the adjacent even-numbered row-gate lines may not be the same. .
  • Those skilled in the art can further set different odd-line lines and even-numbered gate lines according to the design and needs of the display device, thereby overcoming the problem of poor display of the display device, for example, the problem of poor horizontal stripes existing in the display of the display device .
  • the first gate line and the second gate line are turned on/off as an example.
  • the opening/closing of the first gate line depends on the GATE 1 signal provided by the GOA (1) connected to the first gate line, and the GATE 1 signal is the trigger signal STV 1R and the clock signal CLK after the trigger signal STV 1R is eroded. 1R control generation.
  • the STV1R signal and the clock signal CLK 1R generate a GATE signal, specifically: when the GATE i signal is high, the first gate line is turned on; When the GATE 1 signal is low, the first gate line is turned off.
  • the turn-on Z of the second gate line is turned off depending on the GATE 2 signal provided by the GOA (2) connected to the second gate line, and the GATE 2 signal is after the trigger signal STV1L is triggered by the etched signal STV 1L and The inch clock signal CLK IL controls the generation.
  • the 81 ⁇ 11 signal and the clock signal 011:11 ⁇ generate a 0 £ 2 signal, specifically: When the GATE 2 signal is high, the second gate line is turned on; when the GATE 2 signal is low, the second The grid line is closed.
  • the GATE signal of the control gate line can be determined to be turned on/off. After the first gate line and the second gate line are turned on, the Gate signal is sequentially outputted, specifically The timing of each GATE signal is shown in Figure 2.
  • FIG. 1 is a timing control diagram of a gate line driving method provided by the prior art
  • FIG. 2 is a timing control diagram of a gate line driving method provided by the present invention. It can be found from the observation that the gate line driving method provided by the prior art controls the interval between the GATE signals of the adjacent gate lines to be turned on/off during the driving process to be relatively small, and there may even be temporal overlap. In this way, the grid line is controlled, and the timing of each gate line GATE signal is as shown in FIG. Therefore, for the gate line driving method provided by the prior art, the flicker and data crosstalk generated by the display device are relatively serious.
  • the GATE signals for controlling the opening/closing of adjacent gate lines are separated from each other, for example, wherein the GATEI signal corresponding to the first gate line is turned on/off within the first time t1, The GATE2 signal corresponding to the on/off of the second gate line is within the second time t2. Therefore, there is no overlap between the GATE1 signal and the GATE2 signal. Further, when the gate lines are controlled in this manner, the gate lines of the GATE signals are as shown in FIG.
  • the flashing phenomenon test result of the display device using the gate line driving method provided by the prior art is 9%, and the average flicker phenomenon test result of the gate line driving method provided by the present invention is 5%, which is reduced by about 50% compared with the gate line driving method provided by the prior art; display by the grid line driving method provided by the prior art
  • the test result of the device data is 1.8%, and the test result of the cross-talk of the gate line driving method provided by the present invention is about 0.9%, which is about 50% lower than that of the prior art. . Therefore, the gate line driving method provided by the present invention can effectively reduce the possibility of the display device generating flicker and data crosstalk.
  • the timing diagram of the gate line driving method provided by the embodiment of the present invention may also be as shown in FIG. Show.
  • the timing chart shown in FIG. 3 is different from the timing chart shown in FIG. 2 in that the operating time of the clock signal CLK is shortened in FIG.
  • an arbitrary gate line is taken as an example for introduction.
  • take the first gate line as an example. Since the effective trigger time of the trigger signal STV 1R is within the first time t1, the portion of the corresponding clock signal CLK 1R that operates during the first time is actually valid (due to the second time t2, the trigger does not occur) The signal STV 1R, therefore, the clock signal CLK 1R in the second day between t2 does not produce an eclipse effect).
  • the timing diagram of the gate line driving method shown in FIG. 3 is a more preferable option, which can ensure the normal driving operation of the gate line driving method provided by the embodiment of the present invention, and can partially reduce the driving signal of the day clock. length of work.
  • the gate line driving method utilizes four etched signal STVs to complete the driving process of the gate lines.
  • those skilled in the art can adjust the gate line driving method by using the common knowledge in the art, so that the gate line driving method provided by the embodiment of the present invention uses other numbers of etched signals to control, and completes the driving process of the gate lines; Or the driving process of the gate line is completed in other forms.
  • the display device can be driven by the bilateral GOA control unit circuit to drive the gate line, or can be driven by the single-sided GOA control unit circuit to drive the gate line. Work, don't repeat them here.
  • the display device including the pixel unit having 2N rows of pixel units is described as an example (where N is an arbitrary natural number).
  • FIG. 4 is a schematic diagram of driving a pixel unit of a display device to perform row inversion by using a gate line driving method provided by the prior art (a timing diagram of a gate line driving method provided by the prior art may refer to FIG. 1). Specifically, as shown in FIG. 1,
  • the display device pixel unit displays the image at a certain time S10i′ as: odd line display such as first line, first line: ⁇ line, ..., Nth line, ..., 2N-1 line
  • odd line display such as first line, first line: ⁇ line, ..., Nth line, ..., 2N-1 line
  • the next frame time S102' after a certain frame time S10i' The display image is: the first line, the third line, ..., the Nth line, ..., the 2N-1 line, and the like, the odd lines display the negative polarity data, and the second line, the fourth line, ..., the Nth line, ..., the even-numbered lines such as the 2Nth line show the positive polarity data.
  • the image display process can be described as: Taking S101' as an example, the display device inputs positive polarity data when the first row gate line is open, input negative polarity when the second row gate line is open, input positive polarity data when the third row gate line is open, ... and so on. . That is to say, the display device using the gate line driving method provided by the prior art needs to control the polarity of the input data to be inverted between frames and frames, and also needs to continuously control the input data in the same frame time. Polarity reversal, this control input data polarity reversal action will cause a relatively large power loss of the display device. Therefore, when the gate line driving method provided by the prior art is used to drive the display device to perform line inversion display, a large power consumption is generated.
  • FIG. 5 is a schematic diagram of driving a pixel row of a display device by using a gate line driving method provided by the present invention (the gate line driving method provided by the present invention)
  • the timing diagram can be referred to Figure 2).
  • the display device pixel unit displays the image at a certain frame time S101 as: the first row, the third row, the ..., the Nth row, ..., the 2N row, and the like, the odd-numbered rows display the positive polarity data.
  • the even rows of the second row, the fourth row, the ..., the N+1th row, ..., the 2Nth row display negative polarity data;
  • the display image of the next time S102 after a certain frame time S101 is:
  • the odd line such as one line, the third line, ..., the Nth line, ..., the 2N-1 line, and the like, the negative line data, and the second line, the fourth line, ..., the third line, the line, ..., the second line
  • Even lines such as lines show positive polarity data.
  • the image display process can be described by using the gate line driving method provided by the embodiment of the present invention.
  • the image display process can be described as follows: Taking S101 as an example, the display device needs to sequentially open the first row gate line and the third row gate line at the first time U. When the odd-numbered gate lines are input, the positive polarity data is input, and when the second H-inch gate 2 sequentially turns on the even-numbered row gate lines such as the second-row gate line and the fourth-row gate line, negative polarity data, ..., and so on are input. That is to say, the display device of the gate line driving method provided by the embodiment of the present invention needs to invert the polarity of the input data between frames and frames, and only needs to invert the input data once in one frame time. The polarity of the line can complete the line inversion drive mode.
  • the gate line driving method provided by the embodiment of the present invention undoubtedly greatly reduces the power consumption caused by the polarity inversion action, compared to the gate line driving method provided by the prior art.
  • the display device is driven by the gate line driving method provided by the embodiment of the present invention.
  • the gate line driving method For example, for the same normally black mode display mode display device, when the same screen is displayed, the gate line provided by the embodiment of the present invention is utilized.
  • the driving method accomplishes pixel cell row inversion, which reduces power consumption by about 40% compared to the gate line driving method provided by the prior art.
  • the gate line driving method provided by the embodiment of the present invention is applied to a pixel unit.
  • the line inversion time factor also reduces the power consumption when applied to the pixel unit dot inversion.
  • the gate line driving method provided by the embodiment of the present invention changes only with respect to the gate line driving method provided by the prior art.
  • the order of the gate lines is turned on, and the driving frequency of the gate lines is not lowered (that is, the gate line driving method provided by the embodiment of the present invention completes the opening operation of all the gate lines in the same frame time). Therefore, the gate line driving method provided by the embodiment of the present invention does not have a problem that the quality of the display image is degraded due to a decrease in the scanning speed of the gate line.
  • a gate line driving method and a display device using the same by sequentially driving odd-numbered gate lines in a first time, sequentially driving even numbers in a second time after the end of the first time a gate line, thereby separating the driving process of the odd row gate lines from the driving process of the even row gate lines, reducing the possibility of signal crosstalk of adjacent gate lines, and improving the image display effect of the display device;
  • the driving sequence of adjusting the gate lines Through the above-mentioned driving sequence of adjusting the gate lines, the number of times of driving voltage electrode inversion during the gate line driving process is reduced, thereby making the display device more power-saving.
  • an embodiment of the present invention further provides a gate driving circuit including a bilateral driving circuit.
  • the first side driving circuit in the bilateral driving circuit is connected to the odd row gate lines for sequentially driving the odd row gate lines in the first time; the second side driving circuit and the even row gate lines in the bilateral driving circuit Connecting, ⁇ in the second time after the end of the first time, sequentially driving the even-numbered row gate lines, thereby completing the gate line driving process in one frame H inch.
  • an embodiment of the present invention further provides a display device including the gate drive circuit in the above embodiment.
  • the display device When applied to a dot inversion or line inversion display image, the display device reverses only the polarity of the display image once in a single time (refer to Fig. 5).
  • the display device may be: a product or a component having any display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • a display device includes the above-described gate driving circuit, which has better image display quality and less power consumption.

Abstract

提供了一种栅线驱动方法、栅极驱动电路以及显示装置。该方法涉及液晶显示领域，减少了显示装置显示图像过程中的闪烁或数据串扰现象，且能够有效的降低行反转或点反转时的电力耗损。该栅线驱动方法，在第一时间内，依次驱动奇数行栅线，在第一时间结束后的第二时间内，依次驱动偶数行栅线，从而完成一帧时间内的栅线驱动过程。

Description

栅线驱动方法、 栅极驱动电路以及显示装置
本申请主张在 2013 年 08 月 20 日在中国提交的中国专利申请号 No. 201310365075.5的优先权， 其全部内容通过引用包含于此。
本发明涉及液晶显示领
Figure imgf000003_0001
以及显示装置。
随着光电显示技术的日益成熟， 用户对显示装置的品质提出了越来越高 的要求。 液晶显示装置因其寿命长、 光效高、 低辐射、 低功耗的特点， 逐渐 取代了传统射线管显示装置而成为了近年来显示装置产品主流的研究方向。
作为一种驱动液晶显示装置栅线的方式， 现有技术提供的栅线驱动方法 通常使用逐行扫描的驱动方式。所谓逐行扫描驱动方法， 是指在一 ^间内， 遥过一次垂直扫描从第一栅线开始， 依次扫描各行栅线从而完成液晶显示装 置的图像显示过程。
然而， 在将上述逐行扫描驱动方法运用给液晶显示装置进行图像显示的 过程中， 发明人发现现有技术中至少存在如下问题： 由于逐行扫描驱动方法 遥过依次扫描各行栅线来完成图像显示， 因此驱动相邻栅线的驱动信号通常 间隔很小， 甚至在时间上可能存在重叠的情况出现， 导致驱动相邻栅线的驱 动信号之间容易发生耦合， 最终造成显示图像的闪烁或数据串扰的现象。 另 一方面， 当利 ^现有技术的逐行扫描驱动方法驱动液晶显示装置像素进行行 反转或者点反转时， 由于相连栅线驱动信号的极性通常是相互反转的， 导致 利用现有技术的逐行扫描驱动方法驱动液晶显示装置时电力耗损情况比较严 本发明的实施例提供一种栅线驱动方法、 栅极驱动电路以及显示装置， 减少了显示装置显示图像过程中的闪烁或数据串扰现象， 且能够有效的降低 行反转或点反转 0寸的电力耗损。
为解决上述技术问题， 本发明的实施例采用如下技术方案：
一种栅线驱动方法， 在第一时间内， 依次驱动奇数行栅线， 在第一时间 结束后的第二时间内， 加载第二驱动电压依次驱动偶数行栅线， 从而完成一 帧时间内的栅线驱动过程。
优选的， 在所述第一时间内， 相邻奇数行栅线的开启时间间隔相同， 在 所述第二时间内， 相邻偶数行栅线的开启时间间隔相同。
优选的， 所述一帧时间包括： 所述第一日寸间和所述第二日寸间。
优选的， 所述栅线驱动方法还包括： 在完成所述一帧时间内的栅线驱动 过程之后， 按照重复所述一帧时间内的栅线驱动过程的方式， 继续完成下一 帧时间内的栅线驱动过程， 直到完成所有帧时间内的栅线驱动过程。
另一方面， 本发明的实施例还提供了一种栅极驱动电路， 包括双边驱动 电路， 所述双边驱动电路中的第一边驱动电路与奇数行栅线连接， 用于在第 一时间内， 依次驱动所述奇数行栅线； 所述双边驱动电路中的第二边驱动电 路与偶数行栅线连接， 用于在第一 ^间结束后的第二时间内， 依次驱动偶数 行栅线， 从而完成一帧时间内的栅线驱动过程。
优选的， 在所述第一时间内， 相邻奇数行栅线的开启时间间隔相同， 在 所述第二时间内， 相邻偶数行栅线的开启时间间隔相同。
优选的， 所述一帧时间包括： 所述第一时间和所述第二时间。
优选的， 在完成所述一帧时间内的栅线驱动过程之后， 按照重复所述一 帧时间内的栅线驱动过程的方式， 继续完成下一帧时间内的栅线驱动过程， 直到完成所有顿时间内的栅线驱动过程。
再一方面， 本发明的实施例还提供了一种显示装置， 包括上述栅极驱动 电路， 在点反转或行反转显示图像的过程中， 所述显示装置在一帧时间内仅 反转一次显示图形的极性。
本发明实施例提供的一种栅线驱动方法、 栅极驱动电路以及显示装置， 遥过在第一时间内依次驱动奇数行栅线、 在第一 H寸间结束后的第二时间内依 次驱动偶数行栅线， 从而将奇数行栅线的驱动过程与偶数行栅线的驱动过程 分隔开来， 减少了相邻栅线发生信号串扰的可能性， 提高了显示装置的图像 显示效果； 同日寸通过上述调整栅线的驱动顺序， 减少了栅线驱动过程中驱动 电压电极反转的次数， 从而使得显示装置更加省电。
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的^图作简单地介绍， 显而易见地， 下面 描述中的^图仅仅是本发明的一些实施例， 对于本领域技术人员来讲， 在不 付出创造性劳动的前提下， 还可以根据这些 ^图获得其他的^图。
图 1为现有技术提供的栅线驱动方法的控制^序图；
图 2为本发明实施例提供的栅线驱动方法的控制时序图；
图 3为本发明实施例提供的栅线驱动方法的另一控制时序图；
图 4 为应用现有技术提供的栅线驱动方法进行行反转图像显示的示意 图；
图 5为应用本发明实施例提供的栅线驱动方法进行行反转图像显示的示 意图。 具体实施方式
本发明的实施例提供一种栅线驱动方法、 栅极驱动电路以及显示装置， 减少了显示装置显示图像过程中的闪烁或数据串扰现象， 且能够有效的降低 行反转或点反转时的电力耗损。
以下描述中， 为了说明而不是为了限定， 提出了诸如特定系统结构、 接 口、 技术之类的具体细节， 以便透切理解本发明。 然而， 本领域技术人员应 当清楚， 在没有这些具体细节的其它实施例中也可以实现本发明。 在其它情 况中， 省略对众所周知的装置、 电路以及方法的详细说明， 以免不必要的细 节妨碍本发明的描述。
下面对本发明实施例做进一步详细的描述。
本发明实施例提供一种栅线驱动方法，该栅线驱动方法在第一时间 tl内， 加载第一驱动电压 VI依次驱动奇数行栅线， 在第一时间 tl结束后的第二时 间 t2内， 加载第二驱动电压 V2依次驱动偶数行栅线， 从而完成一 ^时间内 的栅线驱动过程。 在一帧周期内的栅线驱动完成后， 重复上述驱动过程， 即 可完成对显示装置的栅线驱动过程。 其中， 第一驱动电压 VI 和第二驱动电 压 V2可以相同也可以不同， 只要能保证所在行的栅线开启即可。
需要说明的是， 对于本发明实施例提供的栅线驱动方法而言， 其一帧时 间内实际进行了两次垂直扫描， 即第一时间 tl时刻驱动扫描奇数行栅线， 第 二时间 ί2时刻驱动扫描偶数行栅线。 因此， 第一时间 t!与第二时间 t2的时 间之和等于一个图像显示帧的时间。
作为本发明实施例提供的栅线驱动方法的一种具体实施方式， 在该具体 实施方式中以 STV信号作为与对应栅线连接的移位寄存器（GOA)单元工作 的触发信号，以 CLK信号作为控制 GOA单元移位输出的时钟信号,通过 STV 信号以及 CLK信号完成栅线开启 /关闭的控制过程。
为方便本领域技术人员理解本发明， 下面结合^图对本发明提供的栅线 驱动方法的具体实施方式做进一歩解释。
首先， 以包括有 2N行栅线的显示装置为例迸行介绍。 （其中， N为任意 一自然数）。栅线的开启 /关闭由与该栅线连接的移位寄存器 GOA单元提供的 GATE信号决定。 进一步的， GATE信号是在触发信号 STV触发后， 由蝕发 信号 STV与时钟信号 CLK控制生成。 具体的， 触发信号 STV作为 GOA单 元工作的开启信号， 时钟信号 CLK控制 GOA单元的移位输出。 以包括双边 驱动电路的显示装置的栅线的控制过程为例， 双边驱动电路中第一边驱动电 路， 其中包含的 GOA单元分别对应与奇数行栅线连接， 例如 GOAI 与第一 栅线连接、 GOA3 与第三栅线连接…， 以此类推； 双边驱动电路中第二边驱 动电路， 其中包含的 GOA单元分别与偶数行栅线连接， 例如 GOA2与第二 栅线连接、 GOA4 与第四栅线连接…， 以此类推。 进一步的， 触发信号可包 括 STV 1R、 STV 1L、 STV 2R, STV 2L。 其中， STV 1R用作触发奇数行栅 线中与第一栅线连接的 GOA ( 1 ) 工作的开启信号， 然后移位传输到与第五 栅线、第九栅线等等连接的 GOA (5 )、 GOA (9), GOA ( 13 ), .... GOA (4n+l ), 其中 n::::0、 1、 2、、、； STV 2R用作触发奇数行栅线中与第三栅线连接的 GOA (3)工作的开启信号， 然后移位传输到与第七栅线、 第十一栅线等等连接的 GOA (7)、 GOA (11)、 GO A (15)、 …、 GOA (4n+3)， 其中 n=0、 1、 2、、、； STV !L用作蝕发偶数行栅线中与第二栅线连接的 GOA(2)工作的开启信号， 然后移位传输到与第六栅线、 第十栅线等等连接的 GOA (6)、 GOA (10)、 GOA (14); STV2L用作蝕发偶数行栅线中与第四栅线连接的 GOA (4)， 然 后移位传输到与第八栅线、第十二栅线等等连接的 GOA (8)、 GOA ( 12),…、 GOA (4n +4)， 其中 η ！、 2、、、。而时钟信号包括 CLK.1R、 CLK 1L、 CLK 2R、 CLK 2L、 …、 CLK NR. CLK NL。 其中， 时钟信号 CLK 1R用于控制 GOA (1)单元的移位输出， 日寸钟信号 CLK 2R用于控制 GOA (3)单元的移 位输出，、 …、 时钟信号 CLK.NR用于控制 GOA (2N-1) 单元的移位输出； 寸钟信号 CLK 1L用于控制 GOA (2) 单元的移位输出， 时钟信号 CLK 2L ^于控制 GOA (4)单元的移位输出，、 …、 时钟信号 CLKNL用于控制 GOA
(2N) 单元的移位输出， …， 以此类推。
为简化驱动过程， 进一步的做如下设定， 第一时间 tl内， 令相邻奇数行 栅线的开启时间间隔相同， 在第二 H寸间 t2内， 令相邻偶数行栅线的开启时间 间隔相同。 需要说明的是， 由于第一时间 tl与第二时间 t2是相互独立的， 因 此， 相邻奇数行栅线的开启 ^间间隔与相邻偶数行栅线的开启 ^间间隔有可 能并不相同。 本领域技术人员可以根据显示装置的设计 ·需要， 进一步对奇数 行栅线以及偶数行栅线进行不同设置， 从而克服显示装置显示不良的问题， 例如： 显示装置显示中存在的橫纹不良的问题。
具体的， 以第一栅线以及第二栅线的开启 /关闭举例说明。 第一栅线的开 启 /关闭取决于与第一栅线连接的 GOA (1)提供的 GATE 1信号， 而 GATE 1 信号为在触发信号 STV 1R蝕发后， 由触发信号 STV 1R与时钟信号 CLK 1R 控制生成。 如图 2所示， 在第一 H寸间 U内， 在 STV1R信号触发后， STV1R 信号与时钟信号 CLK 1R生成 GATE 信号， 具体的： 当 GATE i信号为高电 平时， 第一栅线开启； 当 GATE 1信号为低电平^, 第一栅线关闭。 另一方 面， 第二栅线的开启 Z关闭取决于与第二栅线连接的 GOA (2)提供的 GATE 2 信号， 而 GATE 2信号为在触发信号 STV1L触发后， 由蝕发信号 STV 1L与 寸钟信号 CLK IL控制生成。 如图 2所示， 在第二时间 t2内， 在 STV 1L信 号触发后， 81^ 11信号与时钟信号011：11^生成0 £ 2信号， 具体的： 当 GATE 2信号为高电平时， 第二栅线开启； 当 GATE 2信号为低电平时， 第二 栅线关闭。 同样道理， 根据对应的 STV蝕发信号以及 CLK日寸钟信号可以确 定控制栅线开启 /关闭的 GATE信号， 第一栅线和第二栅线开启后依序进行 Gate信号的移位输出， 具体的各 GATE信号的时序如图 2所示。
相比于如图 1所示的 GATE信号时序， 其中图 1为现有技术提供的栅线 驱动方法的时序控制图， 图 2为本发明提供的栅线驱动方法的时序控制图。 观察后可以发现， 现有技术提供的栅线驱动方法在驱动过程中控制相邻栅线 开启 /关闭的 GATE信号之间的间隔是比较小的，甚至可能存在时间上的重叠。 以此种方式控制栅线日寸， 其各栅线 GATE信号时序如图 1 中所示。 因此， 对 于现有技术提供的栅线驱动方法而言， 显示装置产生的闪烁以及数据串扰现 象比较严重。
而对于本发明提供的栅线驱动方法而言， 控制相邻栅线开启 /关闭的 GATE信号是相互分开的， 例如：其中对应开启 /关闭第一栅线的 GATEI信号 处于第一时间 tl内， 而对应开启 /关闭第二栅线的 GATE2信号处于第二时间 t2内。 因此， GATE1信号与 GATE2信号不存在 H寸间上的重叠。 进而以此种 方式控制栅线时， 其各栅线 GATE信号^序如图 2中所示。可以观察到的是， 相邻行的栅线打开的时间间隔较远； 而相邻的奇数行栅线、 相邻的偶数行栅 线打开的时机虽然较近， 但由于相邻的奇数行栅线、 相邻的偶数行栅线其位 置上并不紧靠， 因此发生信号耦合的可能性大大的降低了。 进一步利 ^模拟 软件迸行模拟后， 以对相同结构的显示装置进行不同栅线驱动方法测试， 比 较后可以发现， 利用现有技术提供的栅线驱动方法的显示装置存在的闪烁现 象测试结果为 9%,而本发明提供的栅线驱动方法的平均闪烁现象测试结果为 5%, 相对现有技术提供的栅线驱动方法降低了约 50%; 利用现有技术提供的 栅线驱动方法的显示装置数据发生串扰的情况其测试结果为 1.8%, 而本发明 提供的栅线驱动方法数据发生串扰的情况其测试结果约为 0.9%， 相对现有技 术提供的栅线驱动方法降低了约 50%。 因此， 本发明提供的栅线驱动方法可 以有效的降低显示装置产生闪烁以及数据串扰现象的可能性。
更进一步的， 本发明实施例提供的栅线驱动方法的时序图还可如图 3所 示。 需要说明的是， 图 3所示的时序图与图 2所示的时序图不同之处在于： 在图 3中时钟信号 CLK的工作时间缩短了。具体的， 以任意一栅线为例进行 介绍。 例如， 以第一栅线为例。 由于触发信号 STV 1R的有效触发时间处于 第一时间 tl 内， 因此对于对应的时钟信号 CLK 1R而言， 其工作于第一时间 内的部分是实际有效的 （由于第二时间 t2不会出现触发信号 STV 1R, 因此 第二日寸间 t2内的时钟信号 CLK 1R不会产生蝕发效果）。同样道理，对任意一 条栅线而言， 日寸钟信号只有在该栅线对应的蝕发信号触发工作日寸段内才会有 效。 因此， 如图 3所示的栅线驱动方法时序图为一种更为优选的选择， 既可 保证本发明实施例提供的栅线驱动方法正常驱动工作， 又可部分减少日寸钟驱 动信号的工作时长。
在此， 需要补充一点， 在上述实施例提供的栅线驱动方法分析过程中， 栅线驱动方法均利用了四个蝕发信号 STV完成对栅线的驱动过程。 事实上， 利用本领域公知常识， 本领域技术人员可调整栅线驱动方法， 从而令本发明 实施例提供的栅线驱动方法利用其它数量的蝕发信号进行控制， 完成对栅线 的驱动过程； 或者以其他形式完成栅线的驱动过程， 举例来说， 以显示装置 为例，显示装置既可以通过双边 GOA控制单元电路驱动栅线进行工作，也可 遥过单边 GOA控制单元电路驱动栅线进行工作， 在此不做赘述。
另一方面， 从像素单元驱动角度进行分析， 进一步描述本发明实施例提 供的栅线驱动方法带来的有益效果。 以包括有 2N行像素单元的显示装置迸 行行反转像素单元驱动为例进行介绍 （其中， N为任意一自然数）。
如图 4所示， 图 4为利用现有技术提供的栅线驱动方法驱动显示装置像 素单元进行行反转的示意图 （现有技术提供的栅线驱动方法的时序图可参考 图 1 )。 具体的， 如图 4所示， 显示装置像素单元在某一顿时刻 SlOi'显示图 像为： 第一行、 第:≡行、 …、 第 N行、 …、 第 2N- 1行等奇数行显示正极性 的数据， 而第二行、 第四行、 …、 第 N+i行、 …、 第 2N行等偶数行显示负 极性的数据； 在某一帧时刻 SlOi'后下一帧时刻 S102'的显示图像为： 第一行、 第三行、 …、 第 N行、 …、 第 2N-1行等奇数行显示负极性的数据， 而第二 行、 第四行、 …、 第 N行、 …、 第 2N行等偶数行显示正极性的数据。 依据 现有技术提供的栅线驱动方法进行图像显示时， 该图像显示过程可描述为： 以 S101'为例， 显示装置在第一行栅线打开时输入正极性数据、第二行栅线打 开时输入负极性、 第三行栅线 ίί开时输入正极性数据， …， 以此类推。 也就 是说， 采用现有技术提供的栅线驱动方法的显示装置除了需要在帧与帧之间 控制输入数据的极性进行反转， 另外在同一帧时间内也需要不停地控制输入 数据的极性迸行反转， 这种控制输入数据极性反转动作会造成显示装置比较 大的电力耗损。 因此， 采用现有技术提供的栅线驱动方法驱动显示装置进行 行反转显示时会产生较大的电力耗损。
进一步相比于图 4所示的示意图， 如图 5所示， 图 5为利用本发明提供 的栅线驱动方法驱动显示装置像素单元迸行行反转的示意图 （本发明提供的 栅线驱动方法的时序图可参考图 2)。 具体的， 如图 5所示， 显示装置像素单 元在某一帧时刻 S101显示图像为： 第一行、 第≡行、 …、 第 N行、 …、 第 2N行等奇数行显示正极性的数据， 而第二行、 第四行、 …、 第 N+1行、 …、 第 2N行等偶数行显示负极性的数据；在某一帧时刻 S101后下一顿时刻 S102 的显示图像为： 第一行、 第≡行、 …、 第 N行、 …、 第 2N- 1行等奇数行显 示负极性的数据， 而第二行、 第四行、 …、 第 Ν·Η行、 …、 第 2Ν行等偶数 行显示正极性的数据。 结合本发明实施例提供的栅线驱动方法进行图像显示 寸， 该图像显示过程可描述为： 以 S101 为例， 显示装置需要在第一时刻 U 依次打开第一行栅线、 第三行栅线等奇数行栅线时输入正极性数据、 在第二 H寸刻 ΐ2 依次打开第二行栅线、 第四行栅线等偶数行栅线时输入负极性数 据， …， 以此类推。 也就是说， 采 ^本发明实施例提供的栅线驱动方法的显 示装置除了需要在帧与幀之间控制输入数据的极性进行反转， 其在一帧时间 内只需要反转一次输入数据的极性即可完成行反转驱动方式。 因此， 在利用 相同的显示装置显示相同图像时， 相比于现有技术提供的栅线驱动方法， 本 发明实施例提供的栅线驱动方法无疑会大大地降低极性反转动作造成的电力 耗损。 遥过相关模拟测算， 利用本发明实施例提供的栅线驱动方法驱动显示 装置^, 例如对于相同的常黑模式显示模式显示装置来说， 显示相同画面时， 利用本发明实施例提供的栅线驱动方法完成像素单元行反转， 比利用现有技 术提供的栅线驱动方法降低了约 40%的电力耗损。
需要说明的是， 本发明实施例提供的栅线驱动方法除了应用于像素单元 行反转日寸会产生上述有益效果之外， 应用于像素单元点反转时同样也会降低 电力耗损。
另外， 需要特别说明的是， 相对比于图 1 的时序图， 通过图 2或图 3可 以发现： 本发明实施例提供的栅线驱动方法相对于现有技术提供的栅线驱动 方法，仅改变了栅线打开的前后顺序，而并没有降低打开栅线的驱动频率（即 本发明实施例提供的栅线驱动方法在相同的一帧时间内， 同样完成全部栅线 的开启工作）。 因此， 本发明实施例提供的栅线驱动方法不会存在因栅线扫描 速度下降而产生显示图像质量下降的问题。
本发明实施例提供的一种栅线驱动方法以及应用该栅线驱动方法的显示 装置， 通过在第一时间内依次驱动奇数行栅线、 在第一时间结束后的第二时 间内依次驱动偶数行栅线， 从而将奇数行栅线的驱动过程与偶数行栅线的驱 动过程分隔开来， 减少了相邻栅线发生信号串扰的可能性， 提高了显示装置 的图像显示效果； 同 H寸通过上述调整栅线的驱动顺序， 减少了栅线驱动过程 中驱动电压电极反转的次数， 从而使得显示装置更加省电。
另一方面， 本发明实施例还提供了一种栅极驱动电路， 栅极驱动电路中 包括有双边驱动电路。 具体的， 双边驱动电路中的第一边驱动电路与奇数行 栅线连接， 用于在第一时间内， 依次驱动奇数行栅线； 双边驱动电路中的第 二边驱动电路与偶数行栅线连接， ^于在第一时间结束后的第二时间内， 依 次驱动偶数行栅线， 从而完成一帧 H寸间内的栅线驱动过程。 其中， 栅极驱动 电路的具体驱动过程可参照上述实施例中栅极驱动方法的介绍， 在此不做赘 述。
另一方面， 本发明实施例还提供了一种显示装置， 该显示装置包括上述 实施例中的栅极驱动电路。 当应用于点反转或行反转显示图像的过程中， 该 显示装置在一顿时间内仅反转一次显示图像的极性 （参照图 5 )。 其中， 所述 显示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等具有任何显示功能的产品或部件。
本发明实施例提供的一种显示装置， 包括上述栅极驱动电路， 其图像显 示质量更佳且电力耗损更少。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何本技术领域的技术人员在本发明揭露的技术范围内， 可轻易想到 的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护范 围应以所述权利要求的保护范围为准。

Claims

一种栅线驱动方法， 其特征在于， 在第一日寸间内， 依次驱动奇数行栅 线， 在第一时间结束后的第二时间内， 依次驱动偶数行栅线， 认而完成一 ^ ø寸间内的栅线驱动过程。
2、 根据权利要求 1所述的栅线驱动方法， 其特征在于， 在所述第一时间 内， 相邻奇数行栅线的开启 0寸间间隔相同， 在所述第二 0寸间内， 相邻偶数行 栅线的开启时间间隔相同。
3、 根据权利要求 1所述的栅线驱动方法， 其特征在于， 所述一帧时间包 括： 所述第一时间和所述第二时间。
4、 根据权利要求 1所述的栅线驱动方法， 其特征在于， 所述栅线驱动方 法还包括：
在完成所述一帧 H寸间内的栅线驱动过程之后， 按照重复所述一 时间内 的栅线驱动过程的方式， 继续完成下一帧时间内的栅线驱动过程， 直到完成
5、 一种栅极驱动电路， 其特征在于， 包括双边驱动电路， 所述双边驱动 电路中的第一边驱动电路与奇数行栅线连接， 用于在第一时间内， 依次驱动 所述奇数行栅线；
所述双边驱动电路中的第二边驱动电路与偶数行栅线连接， 用于在第一 时间结束后的第二时间内， 依次驱动偶数行栅线， 从而完成一帧时间内的栅 线驱动过程。
6、 根据权利要求 5所述的栅极驱动电路， 其特征在于， 在所述第一时间 内， 相邻奇数行栅线的开启 H寸间间隔相同， 在所述第二 H寸间内， 相邻偶数行 栅线的开启时间间隔相同。
7、 根据权利要求 5所述的栅极驱动电路， 其特征在于， 所述一帧时间包 括： 所述第 - ·时间和所述第二时间。
8、 根据权利要求 5所述的栅极驱动电路， 其特征在于，
在完成所述一帧时间内的栅线驱动过程之后， 按照重复所述一顿时间内 的栅线驱动过程的方式， 继续完成下一帧^间内的栅线驱动过程， 直到完成 所有帧时间内的栅线驱动过程。
9、 一种显示装置， 其特征在于， 包括如权利要求 5-8中任一项所述栅极 驱动电路。
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