WO2015014114A1 - 抗工艺涨落的自修调片上振荡器 - Google Patents

抗工艺涨落的自修调片上振荡器 Download PDF

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Publication number
WO2015014114A1
WO2015014114A1 PCT/CN2014/071614 CN2014071614W WO2015014114A1 WO 2015014114 A1 WO2015014114 A1 WO 2015014114A1 CN 2014071614 W CN2014071614 W CN 2014071614W WO 2015014114 A1 WO2015014114 A1 WO 2015014114A1
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chip
oscillator
self
trimming
output pulse
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French (fr)
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韩雁
孙俊
刘晓鹏
钱雨霁
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Zhejiang University ZJU
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Zhejiang University ZJU
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Priority to JP2016530312A priority Critical patent/JP6229057B2/ja
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Priority to US14/832,155 priority patent/US9413370B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

Definitions

  • the present invention relates to the field of integrated circuits, and more particularly to an on-chip oscillator that resists process fluctuations. Background technique
  • CMOS integrated circuits In order to meet the needs of energy saving and small size of portable electronic products, wireless sensor network nodes and biochips, low power consumption and high integration have become the mainstream of future development of CMOS integrated circuits. As an important part of digital circuits and even some analog circuits, clock generators are attracting more and more attention to their power consumption, accuracy and integration.
  • the crystal oscillator is a high-precision and high-stability oscillator, but it cannot be integrated inside the chip, increasing application cost and space consumption.
  • on-chip integration of accurate clock sources under standard CMOS processes has received widespread attention in industry and academia.
  • on-chip integration of commonly used clock sources can be divided into three categories, on-chip integration of LC oscillators, on-chip integration of RC oscillators, and on-chip integration of ring oscillators.
  • LC oscillators provide comparable accuracy and phase noise performance to crystal oscillators.
  • large inductors cannot be implemented in standard CMOS processes, additional high-speed dividers are required to achieve lower oscillation frequencies. Make it difficult to achieve power consumption below lOOuW.
  • the RC oscillator has low power consumption and is suitable for low frequency applications.
  • the main problem is that the on-chip integrated resistors and capacitors provided by the CMOS process have large process dispersion, which causes the output frequency of the RC oscillator to be greatly affected by the process fluctuation. In a typical CMOS process, the frequency variation caused by process dispersion can reach 50%.
  • the ring oscillator is suitable for high frequency applications and has been specially designed to provide a significant increase in the accuracy of the ring oscillator.
  • the simulation data shows that in the standard CMOS process, the frequency of the ring oscillator with special structure is less affected by the process fluctuation.
  • the output frequency of the ring oscillator follows the process. Changes can be made within ⁇ 2%.
  • the Chinese patent publication No. CN1669221A discloses a current controlled ring oscillator which has an output frequency variation of less than 10% under different process, voltage and temperature (PVT) conditions, but this oscillator frequency Higher, higher power consumption.
  • the Chinese patent publication No. CN1 1351 18A discloses a ring oscillator having a frequency control loop for setting the bias current of the on-chip ring oscillator until the frequency of the ring oscillator coincides with the target frequency.
  • This method of trimming through the off-chip can obtain accurate oscillation frequency, but due to electricity
  • the current setting method in the flow compensation method is complicated, and adopts off-chip trimming. Each chip needs to perform an additional trimming process after the manufacturing is completed, resulting in an increase in the overall cost of the chip. Summary of the invention
  • the invention provides a self-repairing on-chip oscillator which is resistant to process fluctuations, so as to solve the problem that the output frequency of the on-chip oscillator has a great influence on the process fluctuation.
  • a reference oscillating unit configured to generate a reference pulse
  • the self-tuning logic control unit is configured to receive the reference pulse and the output pulse, and send a corresponding trimming signal to the to-be-tuned oscillation unit according to the received reference pulse and the output pulse, and control the frequency of the output pulse to be repaired by the to-be-tuned oscillation unit. Tune.
  • a reference oscillating unit is disposed in the chip, and the output of the reference oscillating unit is used as a reference pulse, and the trimming of the output pulse generated by the oscillator unit to be trimmed is controlled by the self-tuning logic control unit.
  • the frequency trimming of the output pulse is realized, so that the oscillation frequency of the output pulse of the oscillator is equal to the required oscillation frequency.
  • the self-tuning logic control unit is further configured to: turn off or turn on the reference oscillator unit by transmitting a corresponding control signal to the to-be-tuned oscillation unit according to the received reference pulse and the output pulse. Turning off the reference oscillator unit after trimming is completed reduces power consumption.
  • the reference oscillating unit includes:
  • a ring oscillator for generating a reference pulse
  • a current generator for providing a bias current to the ring oscillator
  • a sleep transistor for receiving the control signal and turning the ring oscillator and current generator off or on.
  • the current value provided by the current generator is proportional to the absolute temperature, that is, the PTAT (proportional to absolute temperature) current, and the ring oscillator is temperature-compensated to overcome the temperature drift, so that the ring oscillator outputs the pulse.
  • the frequency is stable, and the on-chip integration of the reference oscillating unit can be realized, and the off-chip oscillator is used to provide the reference pulse, thereby realizing the on-chip self-tuning of the oscillating unit to be trimmed.
  • the to-be-tuned oscillation unit includes:
  • a relaxation oscillator for generating an output pulse
  • a basic bias current stage for providing a basic bias current to the relaxation oscillator
  • a bias current array for receiving a trim signal, comprising N controllable bias current levels
  • the controllable bias current stage is provided with a control switch for turning off or turning on the corresponding controllable bias current level according to the received trimming signal, and frequency trimming the output pulse.
  • Low-frequency output is achieved by using a relaxation oscillator-based oscillator output unit based on a relaxation oscillator, suitable for low Frequency application, and low power consumption.
  • the basic bias current is applied to the relaxation oscillator through the basic bias current to ensure that the relaxation oscillator has a basic oscillation frequency.
  • the frequency of the relaxation oscillator is adjusted by the bias current array to make the frequency coincide with the target frequency.
  • the self-tuning logic control unit includes:
  • a counter for counting the number of reference pulses in one or more cycles of the output pulse; an output module for latching the counting result, and assigning a delay module to the trimming signal and the control signal according to the counting result, The time at which the delayed output pulse enters the counter;
  • the power-on reset module is used to initialize the chip when the chip is powered on.
  • the power-on reset module clears the counter and the delay module, and the output module assigns values to the trimming signal and the control signal, so that the bias current array in the unit to be trimmed, the reference oscillator unit Open, to ensure that the self-repair adjustment starts smoothly.
  • the output pulse is delayed by the delay module for a certain time to ensure the stability on the chip during counting, and the accuracy of the adjustment is guaranteed.
  • the counter is an addition counter composed of an N-bit D flip-flop.
  • the circuit structure is simple, easy to implement, and low in cost.
  • the trimming signal is an N-bit binary digital signal.
  • the on and off of the N controllable bias current levels in the oscillating unit to be trimmed are respectively controlled by the N-bit binary digital signals.
  • said N controllable bias current levels provide a step change in bias current.
  • the gradient of the step change is set according to the magnitude of the output frequency of the relaxation oscillator in the on-chip oscillator which is affected by the process deviation and the reference frequency, and the conduction current of each controllable bias current level is made by the step change of the bias current.
  • the corresponding frequency increase amount is stepwise, which ensures the precision of the trimming.
  • the self-repairing process of the self-repairing on-chip oscillator against the process fluctuation of the present invention is as follows:
  • Chip initialization After the chip is powered on, the power-on reset circuit completes the chip initialization, clears the counter and delay module, sets "1" to the trim signal, and closes the bias current array in the unit to be trimmed. " 0" , the reference oscillating unit is turned on to prepare for the trimming process.
  • the output pulse After the chip is powered on, the output pulse enters the counter after delay of the delay module, starts counting, and counts one or more oscillation cycles of the output pulse with the reference pulse. After one or more output pulse cycles, the counting ends. .
  • the output unit assigns a value to the trimming signal according to the latched counting result, and the frequency of the output pulse is trimmed by the bias current array, and the output unit sets the control signal to "1", and is closed by the sleep transistor. Reference oscillating unit.
  • the self-repairing on-chip oscillator that is resistant to process fluctuations provided by the present invention reduces the effect of process fluctuations on the output pulse frequency.
  • the reference pulse required for frequency adjustment is provided by an on-chip integrated reference oscillating unit, and After the trimming is completed, the reference oscillating unit is turned off, and the on-chip self-tuning of the output frequency is realized.
  • the simulation data shows that the dispersion frequency of the oscillator to be trimmed before and after trimming is reduced from 30% to 6% at different process angles. It is beneficial to reduce the cost of chip preparation, and the hardware structure is simple and easy to implement. After the trimming is completed, the reference oscillating unit is turned off, which is beneficial to reducing the power consumption of the chip.
  • FIG. 1 is a block diagram of a self-repairing on-chip oscillator of the present invention resistant to process fluctuations;
  • FIG. 2 is a circuit schematic diagram of a reference oscillating unit in the embodiment
  • FIG. 3 is a schematic circuit diagram of the oscillation unit to be trimmed in the embodiment. detailed description
  • a self-repairing on-chip oscillator resistant to process fluctuations includes a reference oscillating unit integrated on the same chip for generating a reference pulse, including:
  • a ring oscillator for generating a reference pulse
  • a sleep transistor for turning off or turning on the ring oscillator and the current generator
  • the oscillation unit to be modified is used to generate an output pulse, including:
  • a relaxation oscillator for generating an output pulse
  • Basic bias current stage for providing the base bias current for the relaxation oscillator
  • the bias current array is configured to receive the trimming signal, and includes four controllable bias current levels, and each of the controllable bias current levels has a control switch at the signal receiving end, and the corresponding control signal is controlled according to the received trimming signal.
  • the current level is turned off or on, and the output pulse is frequency-tuned.
  • the output current values of the four controllable bias current stages are stepwise;
  • a self-tuning logic control unit configured to receive the reference pulse and the output pulse, and respectively send a corresponding trimming signal to the bias current array in the oscillating unit to be trimmed according to the received reference pulse and the output pulse, and oscillate to the reference
  • the sleep transistor in the unit sends a control signal, including:
  • Counter A modulo sixteen addition counter used to count the number of reference pulses in a pulse period for one or more output pairs.
  • An output module configured to latch the counting result, and assign a value to the trimming signal and the control signal according to the counting result
  • a power-on reset module configured to initialize the chip when the chip is powered on
  • Delay module used to delay the time when the output pulse enters the counter, and ensure that the counter counts the core The film has been powered on and stable.
  • the target frequency of the oscillator chip output pulse is assumed to be 64
  • the reference pulse CLK re ⁇ frequency is 64
  • the relaxation oscillator is trimmed before the output pulse CLK
  • the frequency variation of the output of the relaxation oscillator is less than 20% with respect to the process fluctuation, and is smaller than the target frequency.
  • the control signal is Finish
  • the frequency increase of the output pulse before the trimming is in accordance with Equation 2 64.
  • the output pulse After the chip is powered on, the output pulse enters the counter after delaying the delay module for 5ms, starts counting, counts one oscillation period of the output pulse with the reference pulse, and ends counting after one output pulse period.
  • the counter counts as 001 1, and the counter overflows 4 times.
  • the corresponding controllable bias current level completes the frequency trimming of the output pulse, increasing the frequency of the output pulse to reach the target frequency.
  • the operating state of the bias current array in the on-chip oscillator remains unchanged, thereby keeping the frequency of the output pulse constant until the chip is reinitialized the next time power is applied.

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  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

本发明公开了一种抗工艺涨落的自修调片上振荡器，包括集成于同一芯片的用于产生基准脉冲的基准振荡单元，用于产生输出脉冲的待修调振荡单元，以及用于接收基准脉冲和输出脉冲，并根据接收到的基准脉冲和输出脉冲向待修调振荡单元发出相应的修调信号，控制待修调振荡单元对输出脉冲进行频率修调的自修调逻辑控制单元。由可片内集成的基准振荡单元提供频率调修所需的基准脉冲，并在修调完成后关闭基准振荡单元，实现了输出频率的片内自修调，避免片外修调，有利于降低芯片制备成本。且硬件结构简单，容易实现，并在不修调时，关闭基准振荡单元，降低芯片的功耗。

Description

抗工艺涨落的自修调片上振荡器 技术领域
本发明涉及集成电路领域， 尤其涉及抗工艺涨落的片上振荡器。 背景技术
为了满足便携式电子产品、 无线传感网络节点以及生物芯片等对节能以及 小尺寸的需要， 低功耗以及高集成度已经成为未来 CMOS集成电路发展的主流方 向。 时钟发生器作为数字电路甚至某些模拟电路的一个重要组成部分， 其功耗、 准确度和集成度也越来越受到人们的关注。
晶体振荡器是一种高精度和高稳定度的振荡器，但它不能集成在芯片内部， 增加了应用成本和空间消耗。 近年来， 随着半导体工艺的发展， 标准 CMOS工艺 下精确时钟源的片上集成受到了工业界和学术界的广泛关注。 目前， 常用的时 钟源的片上集成可以分为三类， 分别是 LC振荡器的片上集成、 RC振荡器的片上 集成和环形振荡器的片上集成。
LC振荡器可以提供与晶体振荡器相媲美的准确度和相位噪声性能， 然而由 于大的电感无法在标准 CMOS工艺下实现， 为了获得较低的振荡频率， 就需要额 外的高速分频器， 这使得它的功耗很难做到 lOOuW以下。
RC振荡器的功耗较低， 适用于低频应用， 但它存在主要问题是 CMOS工艺提 供的片上集成电阻和电容的工艺离散都较大， 导致 RC振荡器输出频率受工艺涨 落的影响较大， 在典型的 CMOS工艺中工艺离散引起的频率变化可以达到 50%。
环形振荡器适用于高频应用， 经过特殊设计， 环形振荡器的准确度可以得 到显著提升。 仿真数据表明， 在标准 CMOS工艺中， 特殊结构的环形振荡器的频 率受工艺涨落的影响较小， 当产生偏置电流的偏置电阻置于片外时， 环形振荡 器的输出频率随工艺变化可以做到 ± 2%以内。 公开号为 CN1669221A的中国专利 文献公开了一种电流控制环形振荡器， 其在不同的工艺、 电压和温度 （Process Voltage Temperature , PVT ) 条件下的输出频率变化小于 10%， 但这种振荡器频 率较高， 功耗较大。
公开号为 CN1 1351 18A的中国专利文献公开了一种具有频率控制环的环形 振荡器， 对片内环形振荡器偏置电流进行设定， 直到环形振荡器的频率与目标 频率一致。 这种通过片外修调的方法虽然可以获得精确的振荡频率， 但由于电 流补偿法中电流设定的方法较为复杂， 且采用片外修调， 每一块芯片都需要在 制造完成之后进行一次额外的修调过程， 导致芯片的总体成本增加。 发明内容
本发明提供了一种抗工艺涨落的自修调片上振荡器，以解决片上振荡器输出 频率随工艺涨落影响较大的问题。
一种抗工艺涨落的自修调片上振荡器， 包括集成于同一芯片的：
基准振荡单元， 用于产生基准脉冲；
待修调振荡单元， 用于产生输出脉冲；
自修调逻辑控制单元，用于接收基准脉冲和输出脉冲， 并根据接收到的基准 脉冲和输出脉冲向待修调振荡单元发出相应的修调信号，控制待修调振荡单元对 输出脉冲进行频率修调。
本发明自修调片上振荡器中，在片内设置基准振荡单元， 以该基准振荡单元 的输出为基准脉冲，通过自修调逻辑控制单元控制完成对待修调振荡器单元产生 的输出脉冲的修调， 从而实现对输出脉冲的频率修调， 使振荡器的输出脉冲的振 荡频率与所需的振荡频率相等。
所述的自修调逻辑控制单元还用于根据接收到的基准脉冲和输出脉冲向待 修调振荡单元发送相应的控制信号， 关闭或开启基准振荡器单元。在修调完成后 关闭基准振荡器单元， 可以降低功耗。 所述的基准振荡单元包括：
环形振荡器， 用于产生基准脉冲；
电流发生器， 用于为环形振荡器提供偏置电流；
睡眠晶体管，用于接收所述的控制信号并关闭或开启环形振荡器和电流发生 器。
在所述基准振荡单元中， 通过电流发生器提供的电流值与绝对温度成正比， 即 PTAT (proportional to absolute temperature ) 电流， 对环形振荡器进行温度补 偿， 克服温漂， 使环形振荡器输出脉冲频率稳定， 且能够实现基准振荡单元的片 内集成， 避免采用片外振荡器提供基准脉冲， 实现了对待修调振荡单元的片内自 修调。
所述的待修调振荡单元包括：
用于产生输出脉冲的张弛振荡器；
基本偏置电流级， 用于为张弛振荡器提供基本偏置电流；
偏置电流阵列， 用于接收修调信号， 包括 N个可控偏置电流级；
所述的可控偏置电流级设有控制开关，根据接收到的修调信号关闭或打开对 应的可控偏置电流级， 对输出脉冲进行频率修调。
采用基于张弛振荡器的待修调振荡器输出单元， 能够实现低频输出，适合低 频应用， 且功耗低。 通过基本偏置电流对张弛振荡器提供基本偏置电流， 保证张 弛振荡器有一个基本的振荡频率，通过偏置电流阵列对张弛振荡器进行频率修调 使频率与目标频率一致。
所述的自修调逻辑控制单元包括：
计数器， 用于对输出脉冲的一个或多个周期内的基准脉冲个数进行计数； 输出模块，用于锁存计数结果， 并根据计数结果对修调信号和控制信号赋值 延时模块， 用于延时输出脉冲进入计数器的时间；
上电复位模块， 用于在芯片上电时使芯片初始化。
芯片 （片上振荡器）上电后， 上电复位模块使计数器和延时模块清零， 同时 输出模块对修调信号和控制信号赋值， 使待修调单元中的偏置电流阵列， 基准振 荡单元开启， 保证自修调顺利启动。 同时输出脉冲通过延时模块进行一定时间延 时， 确保计数时芯片上稳定， 保证修调的准确性。
作为优选， 所述的计数器是由 N位 D触发器构成的加法计数器。 电路结构简 单， 易于实现， 且成本低。
作为优选， 所述的修调信号为 N位二进制数字信号。 通过 N位二进制数字信 号分别控制待修调振荡单元中 N个可控偏置电流级的通断。
作为优选， 所述的 N个可控偏置电流级提供的偏置电流呈阶梯变化。 该阶梯 变化的梯度根据片上振荡器中的张弛振荡器的输出频率受工艺偏差影响的大小 以及基准频率进行设定，通过偏置电流的阶梯变化使每个可控偏置电流级的导通 时对应的频率增加量呈阶梯变化， 保证修调的精度。
以上的 N 取值相同。
本发明的抗工艺涨落的自修调片上振荡器的自修调过程如下：
芯片初始化： 芯片上电后， 上电复位电路完成芯片初始化， 使计数器和延时 模块清零， 对修调信号置 " 1 " ， 关闭待修调单元中的偏置电流阵列， 对控制信 号置 " 0" ， 开启基准振荡单元， 为修调过程作准备。
计数： 芯片上电初始化后， 输出脉冲经延时模块延时后进入计数器， 开始计 数， 用基准脉冲对输出脉冲的一个或多个振荡周期进行计数， 一个或多个输出脉 冲周期后， 计数结束。
锁存： 计数完成后， 输出单元锁存计数结果， 直到芯片重新上电。
信号赋值： 计数完成后， 输出单元根据锁存的计数结果赋值给修调信号， 通 过偏置电流阵列完成对输出脉冲的频率修调， 同时输出单元对控制信号置 " 1 "， 通过睡眠晶体管关闭基准振荡单元。
本发明提供的抗工艺涨落的自修调片上振荡器降低了工艺涨落对输出脉冲 频率的影响。 由可片内集成的基准振荡单元提供频率调修所需的基准脉冲， 并 在修调完成后关闭基准振荡单元， 实现了输出频率的片内自修调， 仿真数据表 明，修调前后待修调振荡器的输出频率在不同工艺角的离散由 30%降低到了 6% 。 有利于降低芯片制备成本， 且硬件结构简单， 容易实现。 且在修调完毕后， 关闭基准振荡单元， 有利于降低芯片的功耗。 附图说明
图 1是本发明的抗工艺涨落的自修调片上振荡器结构框图；
图 2为本实施例中基准振荡单元的电路原理图；
图 3为本实施例中待修调振荡单元的电路原理图。 具体实施方式
下面结合具体实施例对本发明抗工艺涨落的自修调片上振荡器电作进一步 详细描述。
如图 1所示，一种抗工艺涨落的自修调片上振荡器，包括集成于同一芯片的: 基准振荡单元， 用于产生基准脉冲， 包括：
环形振荡器， 用于产生基准脉冲，
电流发生器， 用于为环形振荡器提供偏置电流，
睡眠晶体管， 用于关闭或开启环形振荡器和电流发生器；
待修调振荡单元， 用于产生输出脉冲， 包括：
张弛振荡器， 用于产生输出脉冲，
基本偏置电流级， 用于为张弛振荡器提供基本偏置电流，
偏置电流阵列， 用于接收修调信号， 包括 4个可控偏置电流级， 每个可 控偏置电流级的信号接收端均设有控制开关，根据接收到的修调信号控制相应 可控电流级的关闭或开启， 对输出脉冲进行频率修调。 4个可控偏置电流级的 输出电流值呈阶梯变化；
自修调逻辑控制单元，用于接收所述基准脉冲和输出脉冲， 并根据接收到的 基准脉冲和输出脉冲分别向待修调振荡单元中的偏置电流阵列发出相应的修调 信号， 向基准振荡单元中的睡眠晶体管发送控制信号， 包括：
计数器：用于对一个或多个输出对脉冲周期内的基准脉冲个数计数， 为 4位 D触发器构成的模十六加法计数器。
输出模块，用于锁存计数结果， 并根据计数结果对修调信号和控制信号 赋值；
上电复位模块， 用于在芯片上电时使芯片初始化；
延时模块，用于延时输出脉冲进入计数器的时间，保证计数器计数时芯 片已上电稳定。
其中，基准振荡单元和待修调振荡单元的电路原理分别如图 2和图 3所示，其 中图 3中 VH和 VL为高电平和低电平， 一定程度上可以决定张弛振荡器的输出频 率， 实际应用中可以需求灵活配置， 本实施例中分别为 VH=3V和 VL= 1V。
下面将详细说明本实施例的自修调片上振荡器的自修调过程，其中：假设振 荡器芯片输出脉冲的目标频率为 ，基准脉冲 CLKre^ 频率为 64 ， 张弛振荡器修 调前输出脉冲 CLK的频率为 f=64/67fQ， 张弛振荡器输出的频率变化相对工艺涨落 的频率偏差小于 20%， 且小于目标频率。 假设控制信号为 Finish, 修调信号为 Cal[0:3]， Cal[n]=0(n=0..3)时， 对应的可控电流级导通时， 振荡器的输出脉冲的 频率相对修调前输出脉冲的频率提高符合公式 2 64。
芯片初始化： 芯片上电后， 上电复位电路产生复位信号对芯片初始化， 计数 器和延时电路清零，对修调信号置 " 1 "，对控制信号置 " 0 "， BP : Cal[0:3]=l l l l , Finish=0, 关闭待修调单元中的偏置电流阵列， 开启基准振荡单元。
计数： 芯片上电初始化后， 输出脉冲经延时模块延时 5ms后进入计数器， 开 始计数，用基准脉冲对输出脉冲的一个振荡周期进行计数，一个输出脉冲周期后， 计数结束。 本实施例中计数器计数结果为 001 1， 计数器溢出 4次。
锁存： 计数完成后， 输出单元锁存计数结果 001 1。
信号赋值：输出单元根据输出单元锁存的计数结果对修调信号 Cal[0:3]赋值， 使 Cal[0:3]=001 1， 开启偏置电流阵列中 Cal[0]和 Cal[l]对应的可控偏置电流级， 完 成对输出脉冲的频率修调， 使输出脉冲的频率增加， 达到目标频率 。 同时输出 单元对控制信号置 " 1 "， 即 Finish=l， 睡眠晶体管截止， 环形振荡器和电流发生 器断电关闭。
若不重新上电，则片上振荡器中的偏置电流阵列的工作状态维持不变，从而 使输出脉冲的频率保持不变， 直到下次上电时芯片重新初始化。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限于 此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易想到 的变化或替换， 都应涵盖在本发明的保护范围之内。

Claims

权 利 要 求
1. 一种抗工艺涨落的自修调片上振荡器， 其特征在于， 包括集成于同一芯 片的：
基准振荡单元， 用于产生基准脉冲；
待修调振荡单元， 用于产生输出脉冲；
自修调逻辑控制单元，用于接收基准脉冲和输出脉冲， 并根据接收到的基准 脉冲和输出脉冲向待修调振荡单元发出相应的修调信号，控制待修调振荡单元对 输出脉冲进行频率修调。
2. 如权利要求 1所述的抗工艺涨落的自修调片上振荡器， 其特征在于， 所述 的自修调逻辑控制单元还用于根据接收到的基准脉冲和输出脉冲向待修调振荡 单元发送相应的控制信号， 关闭或开启基准振荡器单元。
3. 如权利要求 2所述的抗工艺涨落的自修调片上振荡器， 其特征在于， 所述 的基准振荡单元包括：
环形振荡器， 用于产生基准脉冲；
电流发生器， 用于为环形振荡器提供偏置电流；
睡眠晶体管，用于接收所述的控制信号并关闭或开启环形振荡器和电流发生
4. 如权利要求 3所述的抗工艺涨落的自修调片上振荡器， 其特征在于， 所述 的待修调振荡单元包括：
用于产生输出脉冲的张弛振荡器；
基本偏置电流级， 用于为张弛振荡器提供基本偏置电流；
偏置电流阵列， 用于接收修调信号， 包括 N个可控偏置电流级；
所述的可控偏置电流级设有控制开关，根据接收到的修调信号关闭或打开对 应的可控偏置电流级， 对输出脉冲进行频率修调。
5. 如权利要求 4所述的抗工艺涨落的自修调片上振荡器， 其特征在于， 所述 的自修调逻辑控制单元包括：
计数器， 用于对输出脉冲的一个或多个周期内的基准脉冲个数进行计数； 输出模块，用于锁存计数结果， 并根据计数结果对修调信号和控制信号赋值 延时模块， 用于延时输出脉冲进入计数器的时间； 上电复位模块， 用于在芯片上电时使芯片初始化。
6. 如权利要求 5所述的抗工艺涨落的自修调片上振荡器， 其特征在于， 所述 的计数器是由 N位 D触发器构成的加法计数器。
7. 如权利要求 4所述的抗工艺涨落的自修调片上振荡器， 其特征在于， 所述 的修调信号为 N位二进制数字信号， 分别控制待修调振荡单元中 N个可控偏置电 流级的通断。
8. 如权利要求 7所述的抗工艺涨落的自修调振荡器， 其特征在于， 所述的 N 个可控偏置电流级提供的偏置电流值呈阶梯变化。
PCT/CN2014/071614 2013-07-30 2014-01-28 抗工艺涨落的自修调片上振荡器 Ceased WO2015014114A1 (zh)

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