WO2015014070A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2015014070A1
WO2015014070A1 PCT/CN2013/089152 CN2013089152W WO2015014070A1 WO 2015014070 A1 WO2015014070 A1 WO 2015014070A1 CN 2013089152 W CN2013089152 W CN 2013089152W WO 2015014070 A1 WO2015014070 A1 WO 2015014070A1
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Prior art keywords
array substrate
metal layer
gate metal
layer
exposure
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French (fr)
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沈奇雨
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/388,122 priority Critical patent/US9496294B2/en
Publication of WO2015014070A1 publication Critical patent/WO2015014070A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • an amorphous silicon structure is prepared by using an excimer laser as a heat source and projected on a glass substrate, and the amorphous silicon structure is absorbed. After the energy of the excimer laser, it will be transformed into a polysilicon structure. Since the entire crystallization process is completed below 600 ° C, it is called a low temperature process and is applicable to general glass substrates.
  • LTPS low temperature poly-silicon
  • TFT-LCD thin film transistor liquid crystal display
  • LTPS-TFT LCD is widely used due to its high resolution, fast response speed, high brightness, high aperture ratio, etc., but the TFT of the conventional array substrate needs to pass through two masks for photolithography.
  • the gate and the low doped region are formed, so the lithographic apparatus needs to replace the mask after fabrication of the gate to make a low doped region.
  • There is a high probability of alignment error between the two masks which may result in inconsistent lengths of the two lowly doped regions that should be symmetrically located on either side of the gate.
  • This inconsistent low-doped region reduces the ability of the TFT to reject leakage currents, resulting in excessive leakage current, thereby increasing the power consumption of the LTPS-TFT LCD. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device, which are capable of making the lengths of two low-doped regions of the LTPS-TFT uniform, thereby ensuring the ability of the LTPS-TFT to suppress leakage current.
  • a first aspect of the present invention provides a method for fabricating an array substrate, comprising: forming a gate metal layer on the array substrate by using a mask; and controlling exposure energy by using the mask to obtain greater than A second exposed feature size of the size of the gate metal layer to form a low doped region on both sides of the gate metal layer and of the same length.
  • the low doped region has a length of 1 to 2 ⁇ m.
  • the method for example, before forming the gate metal layer on the array substrate, further includes: Forming a first insulating layer on the substrate; forming an amorphous silicon layer on the first insulating layer, and performing a laser annealing process to form a polysilicon layer; forming a silicon island of the polysilicon layer by the first patterning process.
  • the method further includes: performing a laser annealing process on the silicon island.
  • forming a low doped region on both sides of the gate metal layer and having the same length includes: controlling the exposure energy by using the mask to obtain a second larger than the size of the gate metal layer Exposing the feature size to form a region to be doped on both sides of the gate metal layer and having the same length; performing an ion doping process on the region to be doped to form a low doped region.
  • a second aspect of the invention provides an array substrate comprising a gate metal layer and a low doped region having the same length on both sides of the gate metal layer.
  • the low doped region has a length of 1 to 2 microns.
  • a third aspect of the invention provides a display device comprising the above array substrate.
  • FIG. 1 is a schematic structural view 1 of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a second schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view 3 of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view 4 of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram 5 of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view 6 of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view 7 of an array substrate according to an embodiment of the present invention.
  • FIGS 8A-8C are schematic views for explaining the operation of the embodiment of the present invention.
  • 1 a substrate; 2 - a first insulating layer; 3 - a silicon island;
  • Embodiments of the present invention provide a method for fabricating an array substrate, including the following processes.
  • Step S101 Using a mask, controlling exposure energy to obtain a first exposure feature size to form a gate metal layer on the array substrate.
  • Step S102 using the mask again to control the exposure energy to obtain a second exposure feature size larger than the size of the gate metal layer to form a low-doped region having the same length on both sides of the gate metal layer.
  • the "exposure feature size” is the size of a region formed by an exposure process.
  • the gate metal layer includes a gate of the thin film transistor, a gate line connected to the gate, and the like. Therefore, in step S101, the obtained first exposure feature size corresponds to the size of the gate and the gate line.
  • the first exposure feature size, the second exposure feature size, and the size of the gate metal layer all refer to the size in the width direction of the gate or gate line corresponding to a specific position.
  • the amount of exposure energy can determine the illumination intensity at the edge of the beam.
  • FIG. 8A shows a case where the photoresist layer 120 on the substrate substrate 100 is exposed and developed using the reticle 140 in a case where the exposure energy is moderate.
  • the light source used for exposure is, for example, UV Light, a positive photoresist is used.
  • the photoresist layer 120 is, for example, coated over the structural layer 110 that needs to be patterned.
  • the exposed photoresist layer 110 is developed to obtain a photoresist pattern 121 having a desired normal feature size.
  • Fig. 8B shows a case where the photoresist layer 120 on the substrate substrate 100 is exposed and developed using the reticle 140 with a small exposure energy.
  • the photoreactive incomplete region 130 is obtained in the region which should be completely exposed; after development Due to the presence of the photoreactive incomplete region 130, the feature size of the photoresist pattern 122 obtained after development is made larger than that of the normal photoresist pattern 121 in the case shown in FIG. 8A.
  • Fig. 8C shows a case where the photoresist layer 120 on the substrate substrate 100 is exposed and developed using the reticle 140 in the case where the exposure energy is excessive.
  • the photoreaction region 131 is obtained in a region which should not be exposed; after development, Due to the presence of the photoreactive region 131, the feature size of the photoresist pattern 123 obtained after development is made smaller than that of the normal photoresist pattern 121 in the case shown in Fig. 8A.
  • the process parameters may remain the same except for the amount of exposure energy used for the exposure.
  • the embodiment of the present invention mainly utilizes the situation shown in Fig. 8C.
  • the case of using a negative photoresist is contrary to the case described above, that is, a part of the photoresist irradiated with light remains after development, and a part of the photoresist which is not irradiated with light is removed after development, and will not be described again.
  • another embodiment of the present invention provides a method of fabricating an array substrate, which includes the following processes.
  • the scope of the invention is not limited to the specific illustrated cases.
  • Step S201 forming a first insulating layer on the substrate.
  • a first insulating layer 2 is formed on the substrate 1.
  • the first insulating layer 2 may have a multi-layer structure.
  • the first insulating layer 2 includes two layers, from bottom to top, a silicon nitride (SiNx) layer and a silicon dioxide (Si0 2 ) layer, respectively.
  • the SiNx layer has high breakdown voltage characteristics and self-hydrogenation repair capability. However, due to excessive defects and traps at the interface with the polysilicon layer, it is easy to cause carrier trapping defects and threshold voltage drift. Therefore, it is necessary to deposit a layer of Si0 2 on the SiNx layer, and the Si0 2 layer can form a good matching relationship with the interface of the polysilicon layer, thereby enhancing the mobility of the polysilicon material and ensuring the mobility.
  • the high response rate of LTPS-TFT may have a thickness of 30 to 50 nm, and the Si0 2 layer may have a thickness of 100 to 120 nm.
  • Step S202 forming an amorphous silicon layer on the first insulating layer, and performing a laser annealing process to form a polysilicon layer.
  • the amorphous silicon layer may be formed by deposition, for example, the deposited amorphous silicon layer may have any thickness within a range of 180 to 220 nm.
  • the amorphous silicon layer may be dehydrogenated prior to the laser annealing process to reduce the hydrogen content in the amorphous silicon layer to about 2% to prevent hydrogen explosion.
  • the laser annealing process can be carried out in various ways, such as excimer laser crystallization (ELA), metal lateral induction (MILC), and the like.
  • Step S203 forming a silicon island of a polysilicon layer by the first patterning process.
  • silicon islands 3 separated from each other may be formed, and each silicon island 3 corresponds to one LTPS-TFT.
  • Step S204 Perform ion doping on the silicon island.
  • the silicon island is doped with boron ions.
  • the dose of the doped boron ions can be controlled only when the silicon island is ion doped, thereby forming a P-type LTPS-TFT channel.
  • the conductive channel of the LTPS-TFT is an N-type channel, only a portion of the silicon island region should be doped with boron ions, and then the silicon island region not doped with boron ions is doped with phosphorus ions to form an N-type LTPS. - TFT channel.
  • Step S205 forming a second insulating layer and a first metal layer on the silicon island.
  • the second insulating layer may also be a multi-layered structure including, for example, a Si0 2 layer having a thickness of 30 to 50 nm and a SiNx layer having a thickness of 100 to 120 nm from bottom to top.
  • the lowermost layer of Si0 2 is used to form a good interface match with the silicon island 3; the SiNx layer serves to prevent the LTPS-TFT from being electrically broken down.
  • the first metal layer may have a thickness of 200 to 300 nm and may be made of a metal such as aluminum, phase, or copper, or an alloy thereof.
  • the embodiment of the present invention further includes:
  • Step S101 Using a mask, controlling exposure energy to obtain a first exposure feature size to form a gate metal layer on the array substrate.
  • an example of the step S101 includes: forming a photoresist on the array substrate by coating or the like, and selecting a positive photoresist or a negative photoresist, using the mask 4, After the second patterning process, the second insulating layer and the first metal layer are respectively etched to form the gate insulating layer 5 and the gate metal layer 6.
  • the gate metal layer 6 shown in FIG. 1 corresponds to the gate of the thin film transistor.
  • the second insulating layer and the excess portion of the first metal layer are removed by using the mask 4 through a second patterning process including a photolithography process and an etching process, and the second insulating layer and the remaining portions of the first metal layer are respectively formed.
  • the exposure energy is controlled to obtain a first exposure feature size, thereby obtaining a corresponding photoresist pattern, and after etching, a gate metal corresponding to the photoresist pattern is obtained.
  • the first exposure feature size is, for example, equal to the width D of the gate metal layer 6 (i.e., the width D of the gate).
  • the first metal layer is also used to form the gate lines on the array substrate.
  • Step S206 forming a photoresist on the substrate.
  • the photoresist 7 may be formed on the substrate by coating or the like, and the photoresist 7 may be a negative photoresist or a positive photoresist. If the gate metal layer 6 is selected to be a positive photoresist, the photoresist here should be a negative photoresist; otherwise, if the gate metal layer 6 is formed, a negative photoresist is selected. , the photoresist here should be a positive photoresist. The reason why the photoresist is selected in this way is to utilize the mask 4 used in forming the gate metal layer 6. Hereinafter, a negative photoresist will be described as an example. The structure of the array substrate at this time is as shown in FIG. 2.
  • Step S102 Control the exposure energy by using the mask to obtain a second exposure feature size larger than the size of the gate metal layer to form a low-doped region on both sides of the gate metal layer and having the same length.
  • the second exposure feature size is also shown to be larger than the first exposure feature size of the corresponding location.
  • the mask used when performing exposure, will form a symmetrical shaded area on the photoresist, which is the area covered by the so-called mask, is not Will be exposed; because the exposed light will scatter in the air, together with the shielding effect of the mask, a certain transition zone will be formed between the shaded area and the exposed area where the exposed light is sufficiently illuminated.
  • the area receives less exposure energy.
  • the size of the shaded area can be adjusted by adjusting the distance of the exposure device to the mask or by adjusting the exposure intensity.
  • the exposure energy can be reduced by appropriately reducing the exposure energy, so that the exposure energy received by the excessive region is small, which is insufficient.
  • the negative photoresist of the transition region is sufficiently reacted so that the negative photoresist of the transition region can still be developed by the developer, and a pattern region slightly larger than the mask is formed on the negative photoresist.
  • the exposure energy can be slightly lowered to make the exposure
  • the feature size D2 is larger than the size D of the gate metal layer 6, and after development, the photoresist pattern obtained by the remaining photoresist will expose a partial region on both sides of the gate metal layer 6, and then correspondingly
  • the regions to be doped are located on both sides of the gate metal layer 6 and of the same length, and the regions to be doped are simultaneously defined by the gate metal layer 6 and the remaining photoresist 7.
  • a negative photoresist is preferably used in forming the region to be doped to utilize the mask forming the gate metal layer 6.
  • the plate 4 forms a region to be doped. Accordingly, a positive photoresist is preferred when the gate metal layer 6 is formed.
  • the region to be doped is subjected to an ion doping process to form a low doped region.
  • step S206 since the photoresist 7 used is a negative photoresist, when the exposure process is performed, the photoresist 7 in the exposed feature size can be removed by being dissolved in the developer because it is not exposed.
  • the photoresist 7 which is not exposed exposes the gate metal layer 6 and the region to be doped as shown in FIG.
  • the photoresist 7 and the gate metal layer 6 which are not removed by exposure are used as a mask, and the region to be doped is ion-doped with N+ ions (for example, phosphorus ions) to form a low-doped region 8 .
  • N+ ions for example, phosphorus ions
  • the length of the low doped region 8 is too long and too short, which affects the on-state current and the state current of the LTPS-TFT. Specifically, an excessively long low doped region 8 reduces the on-state current of the LTPS-TFT, thereby lowering the response rate of the LTPS-TFT; and an excessively lowly doped region 8 causes an increase in leakage current. Therefore, the length of the low doped region 8 must be controlled within a suitable range. In the embodiment of the invention, the length of the low doped region 8 is limited to 1 to 2 micrometers.
  • the photoresist which has not been exposed to the developing solution after exposure is removed by a photoresist stripping process.
  • Step S207 forming a third insulating layer, and performing a third patterning process on the third insulating layer to form a pattern including first via holes and second via holes symmetrically located on both sides of the gate metal layer.
  • the first via 10 and the second via 11 can be as shown in FIG.
  • the third insulating layer 9 may have a multi-layer structure including a Si0 2 layer having a thickness of 30 to 50 nm and a SiNx layer having a thickness of 100 to 120 nm from bottom to top.
  • Step S208 forming a second metal layer, and forming a pattern including a source and a drain through a fourth patterning process.
  • the second metal layer can be formed by sputtering, deposition, or the like.
  • the data lines on the array substrate can also be formed while forming the source 12 and the drain 13 as shown in FIG. 4 by the fourth patterning process.
  • the second metal layer may be made of a metal such as molybdenum, aluminum, tantalum, copper or the like and an alloy thereof.
  • Step S209 depositing a resin layer, and forming a pattern including a third via hole located in the drain region by a fifth patterning process.
  • the material of the resin layer 14 may be a photosensitive resin and a non-photosensitive resin.
  • Step S210 forming a first transparent conductive film, and forming a pixel electrode connected to the drain through the third via hole through a sixth patterning process.
  • the first transparent conductive film can be formed by sputtering or the like.
  • the structure of the array substrate shown in Fig. 5 is formed. As shown in FIG. 5, the pixel electrode 16 is electrically connected to the drain electrode 13 through the third via hole 15 on the resin layer 14.
  • Step S211 forming a protective layer.
  • the structure of the array substrate shown in Fig. 6 is formed.
  • the material of the protective layer 17 may be a resin, specifically a photosensitive resin or a non-photosensitive resin. Step S212, forming a second transparent conductive film, and forming a pattern including a common electrode by a seventh patterning process.
  • a pixel region on the array substrate has a common electrode 18 which is a slit electrode, and each of the common electrodes 18 has a certain interval therebetween.
  • the array substrate as shown in FIG. 7 can be obtained. It should be noted that, after the step S202, the uniformity of the crystal nucleus of the formed polysilicon layer does not meet the expected requirements, the formed polysilicon layer may be subjected to laser annealing treatment again.
  • the laser annealing treatment may be performed after the step S102.
  • the number of laser annealing treatments is preferably limited to two or less, because even after the dehydrogenation treatment, when the number of laser annealing treatments is more than two, the probability of occurrence of hydrogen explosion is greatly increased, and at the same time It also increases the manufacturing cost of the LTPS-TFT.
  • an embodiment of the present invention further provides an array substrate prepared by the method for fabricating the array substrate, wherein the array substrate includes a gate metal layer 6 and two of the gate metal layers 6 A low doped region 8 of the same side and of the same length, wherein the low doped region 8 has a length of 1 to 2 micrometers.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element.
  • the thin film transistor of each pixel unit is obtained by the above method to obtain LTPS-TFT 0
  • the embodiment of the present invention further provides a display device, which may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator Any product or part that has a display function.
  • a display device which may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator Any product or part that has a display function.
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color film substrate.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • OLED organic light emitting diode

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Abstract

阵列基板的制作方法，包括：利用掩膜板（4），控制曝光能量以得到第一曝光特征尺寸，以在阵列基板上形成栅极金属层；再次利用该掩膜板，控制曝光能量，得到大于栅极金属层的尺寸的第二曝光特征尺寸，以形成位于栅极金属层的两侧且长度相同的低掺杂区（8）。该方法能够使得LTPS-TFT的两个低掺杂区的长度一致，保证了LTPS-TFT抑制漏电流的能力。

Description

阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、 显示装置。 背景技术
在制备低温多晶硅 (Low Temperature Poly-silicon, LTPS)薄膜晶体管液晶 显示器 (TFT-LCD)的过程中， 利用准分子激光作为热源， 投射于玻璃基板上 制备的非晶硅结构， 非晶硅结构吸收准分子激光的能量后， 会转变成为多晶 硅结构。 因为整个晶化处理过程都是在 600°C以下完成， 故被称为低温工艺， 对于一般玻璃基板皆可适用。
LTPS-TFT LCD因其具有高分辨率、 反应速度快、 高亮度、 高开口率等 优点而得到广泛的应用，但传统的阵列基板的 TFT需分别通过两个掩膜板以 进行光刻工艺以形成栅极和低掺杂区， 因此光刻设备在制作完成栅极之后， 需要更换掩膜板来制作低掺杂区。 这两个掩膜板之间很可能存在对位误差， 可能导致本应对称位于栅极两侧的两个低掺杂区的长度不一致。 这种不一致 的低掺杂区降低了 TFT抑制漏电流的能力， 导致漏电流过大， 由此增大了 LTPS-TFT LCD的功耗。 发明内容
本发明的实施例提供了一种阵列基板及其制作方法、 显示装置， 能够使 得 LTPS-TFT的两个低掺杂区的长度一致， 保证了 LTPS-TFT抑制漏电流的 能力。
本发明的第一方面提供了一种阵列基板的制作方法， 包括： 利用掩膜板， 在所述阵列基板上形成栅极金属层； 利用所述掩膜板， 控制曝光能量， 得到 大于所述栅极金属层的尺寸的第二曝光特征尺寸， 以形成位于栅极金属层的 两侧且长度相同的低掺杂区。
在该方法中， 例如， 所述低掺杂区的长度为 1~2微米。
该方法， 例如， 在所述阵列基板上形成栅极金属层之前， 还包括： 在所 述基板上形成第一绝缘层； 在所述第一绝缘层上形成非晶硅层， 并进行激光 退火工艺， 形成多晶硅层； 通过第一次构图工艺， 形成多晶硅层的硅岛。
在该方法中， 例如， 在所述阵列基板上形成栅极金属层之后， 还包括： 对所述硅岛进行激光退火工艺。
在该方法中， 例如， 形成位于栅极金属层的两侧且长度相同的低掺杂区 包括： 利用所述掩膜板， 控制曝光能量， 得到大于所述栅极金属层的尺寸的 第二曝光特征尺寸， 以形成位于栅极金属层的两侧且长度相同的待掺杂区； 对所述待掺杂区进行离子掺杂工艺， 形成低掺杂区。
本发明的第二方面提供了一种阵列基板， 包括栅极金属层和位于所述栅 极金属层两侧且长度相同的低掺杂区。
例如， 所述低掺杂区的长度为 1~2微米。
本发明的第三方面提供了一种显示装置， 包括上述的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例中的阵列基板的结构示意图一；
图 2为本发明实施例中的阵列基板的结构示意图二；
图 3为本发明实施例中的阵列基板的结构示意图三；
图 4为本发明实施例中的阵列基板的结构示意图四；
图 5为本发明实施例中的阵列基板的结构示意图五；
图 6为本发明实施例中的阵列基板的结构示意图六；
图 7为本发明实施例中的阵列基板的结构示意图七；
图 8A-8C为解释本发明实施例的工作原理的示意图。
附图标记：
1一基板； 2—第一绝缘层； 3—硅岛；
4—掩膜板； 5—栅极绝缘层； 6—栅极金属层；
7—光刻胶； 8—低掺杂区； 9一第三绝缘层； 10—第一过孔； 11一第二过孔； 12—源极； 13—漏极； 14一树脂层; 15—第三过孔;
16—像素电极; 17—保护层; 18—公共电极。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供一种阵列基板的制作方法， 包括如下工艺。
步骤 S101、 利用掩膜板， 控制曝光能量以得到第一曝光特征尺寸， 以在 所述阵列基板上形成栅极金属层。
步骤 S102、 再次利用所述掩膜板， 控制曝光能量， 得到大于所述栅极金 属层的尺寸的第二曝光特征尺寸， 以形成位于栅极金属层的两侧且长度相同 的低掺杂区。
本公开之中， "曝光特征尺寸"为利用曝光工艺形成的区域的尺寸。 栅金 属层包括薄膜晶体管的栅极以及与栅极连接的栅线等。 因此， 在步骤 S101 中， 所得到的第一曝光特征尺寸对应于栅极、 栅线的尺寸。 为了方便比较， 第一曝光特征尺寸、 第二曝光特征尺寸以及栅金属层的尺寸均指对应特定位 置的栅极或栅线的宽度方向上的尺寸。
在本实施例的技术方案中， 在形成栅极金属层后， 利用形成栅极金属层 的掩膜板， 并通过控制曝光能量， 得到大于所述栅极金属层的尺寸的第二曝 光特征尺寸， 形成位于栅极金属层的两侧且长度相同的低掺杂区。 防止了由 于更换掩膜板导致的对位误差的出现， 保证了低掺杂区的长度相同， 保证了 由此制备的 LTPS-TFT 抑制漏电流的能力， 进而减小了漏电流， 降低了 LTPS-TFT LCD的功耗。
这里参考图 8A-图 8B对本发明实施例的工作原理进行说明。在使用掩模 版曝光的过程中， 曝光能量的大小可以决定光束边缘部分光照强度。
图 8A示出了在曝光能量适中的情况下对村底基板 100上的光刻胶层 120 使用掩模版 140进行曝光、显影的情形。例如，曝光所使用的光源例如为 UV 光， 所使用的是正性光刻胶。 该光刻胶层 120例如涂覆在需要被构图的结构 层 110之上。 对曝光后的光刻胶层 110显影得到具有所希望的正常特征尺寸 的光刻胶图案 121。
图 8B示出了在曝光能量较小的情况下对村底基板 100上的光刻胶层 120 使用掩模版 140进行曝光、 显影的情形。 相对于图 8A所示的情形， 由于在 掩模版 140的边缘部分所对应位置的光刻胶吸收的光能量小， 从而在本来应 当被完全曝光的区域中得到光反应不完全区域 130; 显影之后， 由于光反应 不完全区域 130的存在，而使得显影后得到光刻胶图案 122的特征尺寸偏大， 大于图 8A所示情形中的正常的光刻胶图案 121的尺寸。
图 8C示出了在曝光能量偏大的情况下对村底基板 100上的光刻胶层 120 使用掩模版 140进行曝光、 显影的情形。 相对于图 8A所示的情形， 由于在 掩模版 140的边缘部分所对应位置的光刻胶吸收的光能量大， 从而在本来应 当不应被曝光的区域中得到光反应区域 131;显影之后， 由于光反应区域 131 的存在， 而使得显影后得到光刻胶图案 123的特征尺寸偏小， 小于图 8A所 示情形中的正常的光刻胶图案 121的尺寸。
这里请注意， 对于图 8A-8C所示出的三种情况， 除了曝光所使用的曝光 能量大小不一样之外， 其他的工艺参数可以保持不变。 本发明的实施例主要 利用了图 8C所示的情形。 使用负性光刻胶的情形与上述描述的情形相反， 即被光照射的部分光刻胶在显影后留下来， 而未被光照射的部分光刻胶在显 影后去除， 这里不再赘述。
在上述实施例的基础上， 本发明的再一个实施例提供一种阵列基板的制 作方法， 包括如下工艺。 但是， 本发明的范围不限于具体示出的情形。
步骤 S201、 在所述基板上形成第一绝缘层。
如图 1所示， 在所述基板 1上形成第一绝缘层 2。 在本发明实施例中， 第一绝缘层 2可以为多层结构。 例如， 第一绝缘层 2包括两层， 由下至上分 别为氮化硅 (SiNx)层和二氧化硅 (Si02)层。
SiNx层具有高的击穿电压特性， 具备自氢化修补能力，但因其与多晶硅 层的界面存在过多的缺陷和陷阱， 易产生载流子捕获缺陷和阈值电压漂移等 不良现象。 因此， 还需在 SiNx层上沉积形成一层 Si02层， Si02层能够与多 晶硅层的界面形成良好的匹配关系， 进而增强了多晶硅材料的迁移率， 保证 了 LTPS-TFT的高响应速率。 例如， SiNx层的厚度可以为 30~50纳米， Si02 层的厚度可以为 100~120纳米。
步骤 S202、 在所述第一绝缘层上形成非晶硅层， 并进行激光退火工艺， 形成多晶硅层。
在本发明实施例中， 非晶硅层可通过沉积的方式形成， 例如沉积的非晶 硅层的厚度可以为 180~220纳米内的任意数值。
在进行激光退火工艺之前， 可以对该非晶硅层进行去氢处理， 使得非晶 硅层内的氢含量降至 2%左右， 以此防止氢爆现象的产生。 该激光退火工艺 可以采用多种方式， 例如准分子激光晶化 (ELA)、金属横向诱导法 (MILC)等。
步骤 S203、 通过第一次构图工艺， 形成多晶硅层的硅岛。
在形成多晶硅层后， 经过包括光刻工艺和刻蚀工艺的第一次构图工艺， 可形成一个个相互隔离开来的硅岛 3, 每一个硅岛 3对应一个 LTPS-TFT。
步骤 S204、 对所述硅岛进行离子掺杂。 例如， 应用硼离子对所述硅岛进 行掺杂。
若该 LTPS-TFT的导电沟道为 P型沟道， 则只需对所述硅岛进行离子掺 杂时控制所掺杂的硼离子的剂量， 即可形成 P型 LTPS-TFT沟道。
若该 LTPS-TFT的导电沟道为 N型沟道， 则应仅对部分的硅岛区域掺杂 硼离子，之后对未掺杂硼离子的硅岛区域掺杂磷离子，以形成 N型 LTPS-TFT 沟道。
步骤 S205、 在所述硅岛上形成第二绝缘层和第一金属层。
与第一绝缘层类似的， 第二绝缘层也可以为多层结构， 其由下至上例如 包括厚度为 30~50nm的 Si02层和厚度为 100 ~ 120nm的 SiNx层。 位于最下 层的 Si02层是为了与硅岛 3 形成良好的界面匹配； SiNx 层可起到防止 LTPS-TFT被电击穿的作用。 例如， 第一金属层的厚度可以为 200~300纳米， 可以由铝、 相、 铜等金属及其合金制成。
进一步的， 本发明实施例还包括：
步骤 S101、 利用掩膜板， 控制曝光能量以得到第一曝光特征尺寸， 以在 所述阵列基板上形成栅极金属层。
在本发明实施例中， 步骤 S101 的一个示例包括： 在阵列基板上通过涂 覆等方式形成光刻胶， 可选用正性光刻胶或负性光刻胶， 利用掩膜板 4, 通 过第二次构图工艺， 将所述第二绝缘层和第一金属层分别刻蚀形成栅极绝缘 层 5和栅极金属层 6。 这里图 1中所示出的栅极金属层 6对应于薄膜晶体管 的栅极。
利用掩膜板 4经过包括光刻工艺和刻蚀工艺的第二次构图工艺， 去除第 二绝缘层和第一金属层多余的部分， 第二绝缘层和第一金属层剩余的部分分 别形成了栅极绝缘层 5和栅极金属层 6。 在该光刻工艺中对光刻胶进行曝光 时， 控制曝光能量以得到第一曝光特征尺寸， 从而得到相应的光刻胶图形， 在刻蚀之后， 得到对应于光刻胶图案的栅极金属层。 此时， 该第一曝光特征 尺寸例如等于栅极金属层 6的宽度 D (也即栅极的宽度 D)。
在通过第二次构图工艺形成栅极金属层 6的同时， 还利用第一金属层形 成了阵列基板上的栅线。
综上， 经过步骤 S201~S101后， 制得如图 1所示的阵列基板。
步骤 S206、 在所述基板上形成光刻胶。
在本发明实施例中， 可通过涂覆等方式在基板上形成光刻胶 7, 所述光 刻胶 7可选负性光刻胶或正性光刻胶。 若形成栅极金属层 6所选用的为正性 光刻胶， 则此处的光刻胶应为负性光刻胶； 反之， 若形成栅极金属层 6所选 用的为负性光刻胶， 则此处的光刻胶应为正性光刻胶。 这样选择光刻胶的原 因是要利用在形成栅极金属层 6时使用的掩膜板 4。 以下， 以负性光刻胶为 例进行说明。 此时的阵列基板的结构如图 2所示。
步骤 S102、 利用所述掩膜板， 控制曝光能量， 得到大于所述栅极金属层 的尺寸的第二曝光特征尺寸， 以形成位于栅极金属层的两侧且长度相同的低 掺杂区。
在第一曝光特征尺寸对应于栅极金属层 6的尺寸的情况下， 所示第二曝 光特征尺寸也大于相应位置的第一曝光特征尺寸。
如上参照图 8A-8C所描述的， 在进行曝光时， 所采用的掩膜板会在光刻 胶上形成对称的阴影区域， 这阴影区域就是通常所说的掩膜板遮挡的区域， 是不会被曝光的； 由于曝光的光线在空气中会发生散射， 同时加上掩膜板的 遮挡效果， 在阴影区域和曝光的光线充分照射的曝光区域之间会形成一定的 过渡区域， 这部分过渡区域接收到的曝光能量较小。 该阴影区域的大小可以 通过调整曝光设备到掩膜板的距离或者调节曝光强度来进行调节。 同时由于负性光刻胶只有在吸收足够的能量后才能发生化学反应， 形成 不溶于显影液的部分； 而则可以通过适当减小曝光能量来使得该过度区域接 收的曝光能量较小， 不足以使得过渡区域的负性光刻胶发生充分的反应， 使 得过渡区域的负性光刻胶仍然可被显影液显影， 在负性光刻胶上形成略微大 于掩膜板的图形区域。
如图 3所示， 利用形成所述栅极金属层的图案的掩膜板 4, 在保证该负 性光刻胶层在厚度上能充分反应的前提下， 可以稍微降低曝光能量， 使曝光 的特征尺寸 D2大于栅极金属层 6的尺寸 D, 那么显影之后， 由剩余的光刻 胶所得到的光刻胶图案将暴露出栅极金属层 6两侧的部分区域， 那么相应地 即可形成位于栅极金属层 6的两侧且长度相同的待掺杂区， 该待掺杂区由栅 极金属层 6以及剩余的光刻胶 7同时限定。
进一步的， 由于负性光刻胶的刻蚀误差大于正性光刻胶的刻蚀误差， 因 而在形成待掺杂区时优选负性光刻胶， 以利用形成栅极金属层 6的掩膜板 4 形成待掺杂区。 相应的， 形成栅极金属层 6时优选正性光刻胶。
然后， 对所述待掺杂区进行离子掺杂工艺， 形成低掺杂区。
由步骤 S206可知， 由于采用的光刻胶 7为负性光刻胶， 在进行曝光工 艺时， 曝光特征尺寸内的光刻胶 7由于没有受到曝光， 可以通过使其在显影 液中溶解而去除未受到曝光的光刻胶 7, 使得栅极金属层 6和待掺杂区暴露 在外， 如图 3所示。
则以因被曝光而未去除的光刻胶 7和栅极金属层 6作为掩膜， 利用 N+ 离子 (例如磷离子)对所述待掺杂区进行离子掺杂， 以形成低掺杂区 8。
由于低掺杂区 8 的阻值较大， 那么低掺杂区 8 的长度过长、 过短， 对 LTPS-TFT的开态电流和状态电流都有影响。 具体的， 过长的低掺杂区 8会 降低 LTPS-TFT的开态电流， 进而降低 LTPS-TFT的响应速率； 而过低的低 掺杂区 8则会使得漏电流增大。 因而， 必须把低掺杂区 8的长度控制在一个 合适的范围内。则本发明实施例中，所述低掺杂区 8的长度限制为 1~2微米。
离子掺杂工艺结束后， 通过光刻胶剥离工艺除去经过曝光不溶解于显影 液的光刻胶。
步骤 S207、 形成第三绝缘层， 对所述第三绝缘层进行第三次构图工艺， 形成包括对称位于栅极金属层两侧的第一过孔和第二过孔的图形。 第一过孔 10和第二过孔 11可如图 4所示。
优选的， 所述第三绝缘层 9 可以为多层结构， 由下至上包括厚度为 30~50nm的 Si02层、 厚度为 100~120nm的 SiNx层。
步骤 S208、形成第二金属层， 通过第四次构图工艺形成包括源极和漏极 的图形。
第二金属层可通过溅射、 沉积等方式形成。 通过第四次构图工艺形成如 图 4所示的源极 12和漏极 13的同时， 还可形成阵列基板上的数据线。
在本发明实施例中， 第二金属层可以由钼、 铝、 钕、 铜等金属及其合金 制成。
步骤 S209、沉积树脂层， 并通过第五次构图工艺形成包括位于漏极区域 的第三过孔的图形。
树脂层 14的材料可为感光树脂和非感光树脂。
步骤 S210、形成第一透明导电薄膜， 并通过第六次构图工艺形成通过所 述第三过孔与所述漏极连接的像素电极。
例如， 该第一透明导电薄膜可通过溅射等方式形成。
步骤 S210结束后， 形成如图 5所示的阵列基板的结构。 如图 5所示， 像素电极 16通过树脂层 14上的第三过孔 15实现与漏极 13的电连接。
步骤 S211、 形成保护层。
步骤 S211结束后， 形成如图 6所示的阵列基板的结构。
所述保护层 17的材料可为树脂， 具体可为感光树脂或非感光树脂。 步骤 S212、形成第二透明导电薄膜， 并通过第七次构图工艺形成包括公 共电极的图形。
如图 7所示， 阵列基板上的一个像素区域内具有为狭缝电极的公共电极 18, 各个公共电极 18相互之间具有一定间隔。
综上， 在经过如图 2所示的步骤后， 可制得如图 7所示的阵列基板。 需要说明的是， 若经过步骤 S202之后， 所形成的多晶硅层的晶核的均 匀程度未达到预期要求时， 可以对形成的多晶硅层进行再次激光退火处理。
另外， 再次激光退火处理还可以在步骤 S102之后进行。
激光退火处理的次数最好限制在两次以内， 因为即使经过了去氢处理， 当激光退火处理的次数大于两次时， 发生氢爆现象的几率会大大增加， 同时 还增大了 LTPS-TFT的制作成本。
进一步的， 如图 7所示， 本发明实施例还提供了一种由上述阵列基板的 制作方法制得的阵列基板， 该阵列基板包括栅极金属层 6和位于所述栅极金 属层 6两侧且长度相同的低掺杂区 8, 其中所述低掺杂区 8的长度为 1~2微 米。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为开关 元件的薄膜晶体管。 例如， 每个像素单元的薄膜晶体管为采用上述方式得到 LTPS-TFT0
更进一步的， 本发明实施例还提供了一种显示装置， 所述显示装置可以 为： 液晶面板、 电子纸、 OLED面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
该显示装置的一个示例为液晶显示装置， 其中， 阵列基板与对置基板彼 此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为彩膜 基板。在一些示例中，该液晶显示装置还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机发光二极管 (OLED)显示装置， 其中， 阵 列基板上形成有有机发光材料叠层， 每个像素单元的像素电极作为阳极或阴 极用于驱动有机发光材料发光以进行显示操作。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板的制作方法， 包括：
利用掩膜板， 控制曝光能量以得到第一曝光特征尺寸， 以在所述阵列基 板上形成栅极金属层；
再次利用所述掩膜板， 控制曝光能量， 得到大于所述栅极金属层的尺寸 的第二曝光特征尺寸，以形成位于栅极金属层的两侧且长度相同的低掺杂区。
2、根据权利要求 1所述的阵列基板的制作方法， 其中， 所述低掺杂区的 长度为 1~2微米。
3、根据权利要求 1所述的阵列基板的制作方法，在所述阵列基板上形成 栅极金属层之前， 还包括：
在所述基板上形成第一绝缘层；
在所述第一绝缘层上形成非晶硅层， 并进行激光退火工艺， 形成多晶硅 层；
通过第一次构图工艺， 形成多晶硅层的硅岛。
4、根据权利要求 3所述的阵列基板的制作方法，在所述阵列基板上形成 栅极金属层之后， 还包括：
对所述硅岛进行激光退火工艺。
5、根据权利要求 3或 4所述的阵列基板的制作方法， 其中， 形成位于栅 极金属层的两侧且长度相同的低掺杂区包括：
再次利用所述掩膜板， 控制曝光能量， 得到大于所述栅极金属层的尺寸 的第二曝光特征尺寸形成位于栅极金属层的两侧且长度相同的待掺杂区； 对 所述待掺杂区进行离子掺杂工艺， 形成低掺杂区。
6、一种阵列基板， 包括栅极金属层和位于所述栅极金属层两侧且长度相 同的低掺杂区。
7、 根据权利要求 6所述的阵列基板， 其中， 所述低掺杂区的长度为 1~2 微米。
8、 一种显示装置， 包括如权利要求 6-7任一所述的阵列基板。
PCT/CN2013/089152 2013-07-31 2013-12-12 阵列基板及其制作方法、显示装置 Ceased WO2015014070A1 (zh)

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