WO2015014064A1 - 像素驱动电路、显示装置和像素驱动方法 - Google Patents

像素驱动电路、显示装置和像素驱动方法 Download PDF

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Publication number
WO2015014064A1
WO2015014064A1 PCT/CN2013/088746 CN2013088746W WO2015014064A1 WO 2015014064 A1 WO2015014064 A1 WO 2015014064A1 CN 2013088746 W CN2013088746 W CN 2013088746W WO 2015014064 A1 WO2015014064 A1 WO 2015014064A1
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Prior art keywords
tube
line
voltage
control
charging unit
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Ceased
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PCT/CN2013/088746
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English (en)
French (fr)
Inventor
谭文
祁小敬
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US14/362,114 priority Critical patent/US9230479B2/en
Publication of WO2015014064A1 publication Critical patent/WO2015014064A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel driving circuit, a display device, and a pixel driving method. Background technique
  • Active Matrix Organic Light Emitting Diode Panel Active Matrix Organic Light
  • Emitting Diode referred to as: AMOLED
  • the pixel display device of the AMOLED is an Organic Light-Emitting Diode (OLED), and the AMOLED can emit light by driving a thin film transistor to generate a driving current in a saturated state, and the driving current drives the 0 LED to emit light.
  • OLED Organic Light-Emitting Diode
  • 1 is a schematic structural diagram of a basic pixel driving circuit in the prior art.
  • the existing basic pixel driving circuit uses a 2T1C circuit, and the 2T1C circuit includes two thin film transistors and one storage capacitor. The specific structure can be seen in FIG. Show.
  • the threshold voltage Vth of the driving transistor DTFT is poor in uniformity in the existing low-temperature polysilicon process, and drift occurs during use, when the same data voltage Vdata is input to the driving transistor DTFT, the driving transistor Different threshold voltages of the DTFT generate different driving currents, resulting in poor uniformity of brightness of the AMOLED.
  • FIG. 2 is a schematic structural view of a pixel driving circuit having a threshold voltage compensation function in the prior art
  • FIG. 3 is a structural schematic diagram of an equivalent circuit of a discharging phase of the circuit shown in FIG. 2, as shown in FIG. 2 and FIG.
  • the circuit is a 6T1C circuit.
  • the connection of the driving transistor DTFT to the high level VDD and the low level VSS is cut off by the control switch, and one end of the storage capacitor C is connected to the voltage input terminal, and the other end of the storage capacitor C is Data line connection.
  • the voltage input terminal provides an initial voltage Vini
  • the data line provides a data voltage Vdata.
  • the voltage input terminal and the data line collectively charge the storage capacitor C such that the voltage across the storage capacitor has a voltage Vini-Vdata.
  • Vdata is the data signal voltage
  • Vth is the threshold voltage of the drive transistor DTFT.
  • the above circuit can realize the threshold compensation function only when the drive transistor DTFT is an enhancement transistor.
  • the driving transistor DTFT is a depletion transistor
  • the threshold voltage Vth of the depletion transistor is a negative value
  • the driving tube stops discharging because the driver is driven at this time.
  • the drive circuit has lost the threshold compensation function. Summary of the invention
  • the present invention provides a pixel driving circuit, a display device, and a pixel driving method, which can implement a threshold compensation function when the driving tube is of any type.
  • the present invention provides a pixel driving circuit, including: a light emitting device, a driving tube, a control unit, a first charging unit, a second charging unit, a first power terminal, and a second power terminal, wherein the control unit is a data line, a first control line, a second control line, a first gate line and a second gate line, wherein the first charging unit and the second charging unit are both connected to the control unit, the driving tube a gate is connected to the first charging unit, a drain of the driving tube is connected to the first power terminal, a source of the driving tube is connected to the control unit, and a first pole of the light emitting device is The control unit is connected to the second charging unit, and the second pole of the light emitting device is connected to the second power terminal; The control unit is configured to sequentially charge the first charging unit and the second charging unit according to signals of the first control line, the second control line, the first gate line, and the second gate line, respectively The voltage across the first charging unit is equal to a
  • the drive tube is configured to drive the light emitting device to emit light.
  • control unit includes: a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube;
  • the control pole of the first switch tube is connected to the first control line, the first pole of the first switch tube and the second end of the first charging unit and the first end of the second charging unit Connecting, the second pole of the first switch tube is connected to the source of the drive tube and the first pole of the fourth switch tube;
  • a control pole of the second switch tube is connected to the first gate line, a first pole of the second switch tube is connected to the data line, and a second pole of the second switch tube is connected to the first charging unit a first end and a gate connection of the drive tube;
  • a control pole of the third switch tube is connected to the second gate line, a first pole of the third switch tube is connected to the data line, a second pole of the third switch tube is connected to the first charging unit a second end, a first end of the second charging unit, and a first pole of the first switch tube;
  • a control pole of the fourth switch tube is connected to the second control line, a first pole of the fourth switch tube is connected to a source of the drive tube, and a second pole of the fourth switch tube is The second end of the second charging unit and the first pole of the light emitting device are connected.
  • the pixel driving circuit further includes: a fifth switch tube, a control pole of the fifth switch tube is connected to the first control line, and the first pole and the fourth pole of the fifth switch tube The second pole of the switch tube and the first pole of the light emitting device are connected, and the second pole of the fifth switch tube is connected to the second pole of the light emitting device and the second power terminal.
  • the voltage provided by the first power terminal is an operating voltage
  • the voltage provided by the second power terminal is a reference voltage
  • the first positive pole of the light emitting device, the light emitting The second extreme of the device is the negative pole.
  • the driving tube, the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, and the fifth switching tube are N-type thin film transistors.
  • the voltage provided by the first power terminal is a reference voltage
  • the voltage provided by the second power terminal is an operating voltage
  • the first terminal of the light emitting device is extremely negative
  • the second electrode of the light emitting device is extremely positive.
  • the driving tube, the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, and the fifth switching tube are P-type thin film transistors.
  • the first gate line and the second gate line are two gate lines adjacent to a gate timing, and the first gate line is gated before the second gate line.
  • the first control line starts to be gated simultaneously with the first gate line, and the first control line remains strobed until the gate is ended simultaneously with the second gate line;
  • the control line ends the gating during the period in which the first gate line is gated, and the second control line begins to gate at the time when the first control line ends the gating.
  • the present invention provides a display device including: a control unit, a data line driving unit, a gate line driving unit, a data line, a plurality of gate lines, a first control line, a second control line, and a plurality of pixel driving a control unit for regulating the first control line and the second control line, the data line driving unit is configured to drive the data line, and the gate line driving unit is configured to sequentially drive the multiple Bar grid line
  • the pixel driving circuit adopts any of the pixel driving circuits described above, and each of the pixel driving circuits is connected to two gate lines of the plurality of gate lines.
  • the present invention provides a pixel driving method, the pixel driving method is based on the pixel driving circuit, and the pixel driving circuit includes: a light emitting device, a driving tube, a control unit, a first charging unit, and a second a charging unit, a first power terminal and a second power terminal, wherein the control unit is connected to the data line, the first control line, the second control line, the first gate line and the second gate line, the first charging unit and the The second charging unit is connected to the control unit, the gate of the driving tube is connected to the first charging unit, and the drain of the driving tube is connected to the first power terminal, and the driving tube is a source is connected to the control unit, a first pole of the light emitting device is connected to the control unit and the second charging unit, and a second pole of the light emitting device is connected to the second power terminal, Pixel drive The method includes the following steps:
  • the control unit charges the first charging unit according to the signals of the first control line, the second control line, the first gate line and the second gate line, such that the voltage across the first charging unit is equal to the threshold voltage of the driving tube ;
  • the control unit charges the second charging unit according to the signals of the first control line, the second control line, the first gate line and the second gate line, such that the voltage across the second charging unit is equal to that provided by the data line Data voltage
  • the first charging unit and the second charging unit provide a driving voltage to the driving tube for a predetermined period of time according to the control of the control unit, the driving voltage being equal to a sum of a threshold voltage of the driving tube and the data voltage;
  • the drive tube drives the light emitting device to emit light.
  • the invention improves the pre-charging mode by setting two storage capacitors, so that the gate of the driving tube is fixedly set to a data voltage between the working voltage (high level) and the reference voltage (low level), and the driving tube is utilized.
  • the drive tube enters the sub-threshold off state before the source-drain voltage of the drive tube is zero, and the threshold voltage is stored in the storage capacitor, finally achieving the threshold voltage compensation function, and the drive tube in the circuit Can be of any type.
  • FIG. 1 is a schematic structural diagram of a basic pixel driving circuit in the prior art
  • FIG. 2 is a schematic structural view of a pixel driving circuit having a threshold voltage compensation function in the prior art
  • FIG. 3 is a schematic structural diagram of an equivalent circuit of a discharge phase of the circuit shown in FIG. 2.
  • FIG. 4 is a schematic structural diagram of a pixel driving circuit according to Embodiment 1 of the present invention;
  • FIG. 5 is a pixel driving circuit according to Embodiment 2 of the present invention;
  • Figure 6 is a schematic diagram of the operation of the circuit shown in Figure 5;
  • Figure 7 is an equivalent circuit diagram of the initial stage of the circuit shown in Figure 5;
  • Figure 8 is an equivalent circuit diagram of the reading phase of the circuit shown in Figure 5;
  • Figure 9 is an equivalent circuit diagram of the writing phase of the circuit shown in Figure 5
  • Figure 10 is an equivalent circuit diagram of the display phase of the circuit shown in Figure 5;
  • FIG. 11 is a schematic structural diagram of a pixel driving circuit according to Embodiment 3 of the present invention
  • FIG. 12 is a flowchart of a pixel driving method according to Embodiment 5 of the present invention. detailed description
  • the pixel driving circuit includes: a light emitting device, a driving tube, a control unit, a first charging unit, a second charging unit, and a first a power terminal and a second power terminal, the control unit is connected to the data line, the first control line, the second control line, the first gate line and the second gate line, and the first charging unit and the second charging unit are both connected to the control unit,
  • the gate of the driving tube is connected to the first charging unit
  • the drain of the driving tube is connected to the first power end
  • the source of the driving tube is connected to the control unit
  • the first pole of the light emitting device is connected with the control unit and the second charging unit.
  • a second pole of the light emitting device is connected to the second power terminal;
  • the control unit is configured to sequentially charge the first charging unit and the second charging unit according to signals of the first control line, the second control line, the first gate line and the second gate line, respectively, so that voltages across the first charging unit Equal to the threshold voltage of the driving tube and the voltage across the second charging unit is equal to the data voltage provided by the data line;
  • the first charging unit and the second charging unit are configured to supply a driving voltage to the driving tube according to the control of the control unit, the driving voltage being equal to a sum of a threshold voltage of the driving tube and a data voltage;
  • the drive tube is used to drive the light emitting device to emit light.
  • the data line provides the data voltage Vdata
  • one of the first power terminal and the second power terminal provides the operating voltage VDD
  • the other provides the reference voltage VSS.
  • the voltage provided by the first power terminal is the reference voltage VSS
  • the voltage supplied by the second power terminal is the operating voltage VDD higher than the reference voltage VSS
  • the voltage supplied by the second power terminal is the reference voltage At VSS
  • the voltage supplied by the first power supply terminal is higher than the reference.
  • the operating voltage VDD of the voltage VSS can be at a high level, and accordingly, VSS as a reference voltage can be a low level.
  • the data voltage Vdata, the operating voltage VDD, and the reference voltage VSS satisfy VSS ⁇ Vdata ⁇ VDD.
  • the working principle of the first embodiment of the present invention is as follows: the first charging unit and the second charging unit are respectively charged by the control unit, so that the voltage at both ends of the first charging unit is Vth, and the voltage at both ends of the second charging unit is Vdata, The sum of the voltages across the charging unit and the second charging unit is Vdata+Vth, where Vth is the threshold voltage of the driving tube.
  • Vgs Vdata+Vth 0 due to the driving tube
  • the consistency of the current I makes the AM0LED brightness uniform.
  • the first gate line and the second gate line are two gate lines adjacent to the gate timing, and the first gate line is gated before the second gate line.
  • the first control line starts to be gated simultaneously with the first gate line, and the first control line remains strobed until the gate is ended simultaneously with the second gate line; the second control line is in the period of the first gate line strobe The end of the strobe is completed, and the second control line starts strobing at the time when the first control line ends the strobe.
  • the drive tube of the present invention may be an enhanced drive tube or a depletion type drive tube. Because the drain of the driving tube is connected to the first power terminal, and the first power terminal can provide the operating voltage VDD or the reference voltage VSS, so that the source-drain voltage Vsd of the driving tube is not 0 during the discharging process of the first charging unit. Further, regardless of whether the threshold voltage Vth of the driving tube is positive or negative, the first charging unit can be discharged through the driving tube until the driving tube enters the sub-threshold off state from the conducting state, so that the voltage across the first charging unit is Vth o
  • the drive transistor is a depletion transistor. More preferably, the driving transistor is an oxide thin film transistor having an oxide semiconductor layer as an active layer.
  • the driving transistor is an oxide thin film transistor having an oxide semiconductor layer as an active layer.
  • the gate of the driving tube is fixedly set to a data voltage lower than the working voltage.
  • the source and the drain are in the source. Before the voltage is zero, the driving tube enters the sub-threshold off state from the on state, and the threshold voltage is stored in the storage capacitor, and finally the threshold voltage compensation function is realized. Meanwhile, the driving tube in the pixel driving circuit is provided in the first embodiment of the present invention. For any type. Embodiment 2
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit according to Embodiment 2 of the present invention.
  • a control electrode of a first switching transistor T1 is connected to a first control line, and a first pole and a first pole of the first switching transistor T1 are a control line is connected, the first pole of the first switch tube T1 is connected to the second end of the first charging unit and the first end of the second charging unit, the second pole of the first switch tube T1 and the source of the drive tube DTFT and The first pole of the fourth switching transistor T4 is connected.
  • the control pole of the second switch T2 is connected to the first gate line, the first pole of the second switch T2 is connected to the data line, the second pole of the second switch T2 and the first end of the first charging unit and the drive tube
  • the gate of the DTFT is connected.
  • the control pole of the third switch T3 is connected to the second gate line, the first pole of the third switch T3 is connected to the data line, the second pole of the third switch T3 is connected to the second end of the first charging unit, and the second The first end of the charging unit and the first pole of the first switching tube T1 are connected.
  • the control pole of the fourth switch tube T4 is connected to the second control line, the first pole of the fourth switch tube T4 is connected to the source of the drive tube DTFT, the second pole of the fourth switch tube T4 and the second pole of the second switch unit Terminal and 0LED connection.
  • the circuit of the second embodiment of the present invention is a 6T2C type circuit
  • the light emitting device is 0LED
  • the first charging unit is the first capacitor C1
  • the second charging unit is the second capacitor C2
  • the control unit is The method includes: a first switch tube T1, a second switch tube ⁇ 2, a third switch tube ⁇ 3, and a fourth switch tube ⁇ 4.
  • the data line provides a data voltage Vdata
  • the first control line provides a first control signal CR1
  • the second control line provides a second control signal CR2
  • the first gate line and the second gate line can be loaded with a scan signal, wherein the first gate line finger
  • the N-1th gate line Gn-1, the second gate line refers to the Nth gate line Gn
  • the gate line Gn_l and the gate line Gn are two adjacent gate lines, that is, the gate line Gn-1
  • the gate line Gn starts to load the scan signal and scans the signal, where N is greater than or equal to two.
  • the pixel driving circuit further includes: a fifth switch tube T5, the control pole of the fifth switch tube ⁇ 5 is connected to the first control line, and the first pole of the fifth switch tube ⁇ 5 and the second pole of the fourth switch tube ⁇ 4 And a first pole connection of the 0LED, and a second pole of the fifth switch T5 is connected to the second pole of the OLED and the second power terminal.
  • the first pole and the second pole of the fifth transistor T5 are connected at both ends of the OLED for short-circuiting the OLED when the driving transistor DTFT generates an incorrect driving current, so as to prevent the OLED from emitting light under the action of the incorrect driving current, thereby generating The incorrect luminous intensity causes a display error, and the 0LED is connected to the driving transistor DTFT when the driving transistor DTFT generates the correct driving current, so that the 0LED emits light under the correct driving current to ensure the display is normal.
  • the voltage supplied from the first power terminal is the operating voltage VDD
  • the voltage supplied from the second power terminal is the reference voltage VSS
  • the first positive terminal of the light emitting device is the first positive terminal of the light emitting device
  • the second extreme negative electrode of the light emitting device is the first positive terminal of the light emitting device.
  • the driving transistor DTFT, the first switching transistor T1, the second switching transistor 2, the third switching transistor 3, the fourth switching transistor 4, and the fifth switching transistor 5 are ⁇ -type thin film transistors, and the ⁇ -type thin film transistor can be high-voltage
  • the flat signal is turned on and turned off at the low level signal.
  • the first switch tube T1, the second switch tube ⁇ 2, the third switch tube ⁇ 3, the fourth switch tube ⁇ 4, and the fifth switch tube ⁇ 5 each include a control pole, a first pole and a second pole, a first pole and a second pole
  • the structure is the same.
  • the switching transistor is a thin film transistor (TFT)
  • the control is extremely gated, and in the first pole and the second pole, one pole of the transmitting carrier is used as a source, and one pole of the receiving carrier is taken as Drain.
  • the source can be used as the first pole of the switch tube, and accordingly, the drain is used as the switch tube.
  • the second pole; or, the drain may be the first pole of the switching transistor, and the source is the second pole of the switching transistor.
  • the working process of the pixel circuit provided by the second embodiment of the present invention can be divided into: an initial stage, a reading stage, a writing stage, and a display stage.
  • Figure 6 is an operational timing diagram of Figure 5;
  • Figure 7 is an equivalent circuit diagram of the initial stage of the circuit shown in Figure 5;
  • Figure 8 is an equivalent circuit diagram of the read phase of the circuit shown in Figure 5;
  • Figure 9 is Figure 5
  • Fig. 10 is an equivalent circuit diagram of the display phase of the circuit shown in Fig. 5,
  • FIG. 6 to FIG. 9 illustrate the operation of the pixel driving circuit provided by Embodiment 2 of the present invention.
  • the gate line Gn-1 is at a high level
  • the gate line Gn is at a low level
  • the first control signal CR1 is at a high level
  • the second control signal CR2 is at a high level.
  • the first switch tube T1, the second switch tube ⁇ 2, the fourth switch tube ⁇ 4, and the fifth switch tube ⁇ 5 are turned on, and the third switch tube ⁇ 3 is turned off.
  • the gate line Gn-1 is at a high level
  • the gate line Gn is at a low level
  • the first control signal CR1 is at a high level
  • the second control signal CR2 is at a low level.
  • the first switching transistor T1, the second switching transistor ⁇ 2, and the fifth switching transistor ⁇ 5 are turned on, and the third switching transistor ⁇ 3 and the fourth switching transistor ⁇ 4 are turned off.
  • the voltage across the first capacitor C1 is Vth.
  • the reading phase completes charging of the first capacitor C1 such that the voltage across the first capacitor C1 is Vth.
  • the gate line Gn-1 is at a low level
  • the gate line Gn is at a high level
  • the first control signal CR1 is at a high level
  • the second control signal CR2 is at a low level.
  • the first switching transistor T1, the third switching transistor ⁇ 3, and the fifth switching transistor ⁇ 5 are turned on, and the second switching transistor ⁇ 2 and the fourth switching transistor ⁇ 4 are turned off.
  • the data voltage Vdata is written to the second capacitor C2 through the third switching transistor T3, and the voltage across the second capacitor C2 is Vdata.
  • the gate line Gn-1 is at a low level
  • the gate line Gn is at a low level
  • the first control signal CR1 is at a low level
  • the second control signal CR2 is at a high level.
  • the fourth switch tube T4 is turned on, and the first switch tube T1, the second switch tube ⁇ 2, the third switch tube ⁇ 3, and the fifth switch tube ⁇ 5 are turned off, and the voltage across the first capacitor C1 is Vth, the voltage across the second capacitor C2 is Vdata, and the first capacitor C1 and the second capacitor C2 supply a voltage to the driving transistor DTFT, and the series voltage of the first capacitor C1 and the second capacitor C2 is the gate-source voltage of the driving transistor DTFT. , that is, the gate-source voltage of the driving transistor DTFT
  • the driving transistor DTFT in the present invention may be an enhanced driving transistor or a depletion driving transistor, because the drain of the driving transistor DTFT is connected to the first power terminal, and the first power terminal provides the working voltage VDD. Therefore, the source-drain voltage Vsd of the driving transistor DTFT is not 0 during the discharge of the first capacitor C1, so that the first capacitor C1 can be discharged through the driving tube DTFT regardless of whether the threshold voltage Vth of the driving transistor DTFT is positive or negative.
  • the driving transistor DTFT is in a subthreshold conduction state, and the voltage across the first capacitor C1 is Vth.
  • the pixel driving circuit provided by the embodiment of the present invention is applicable not only to a polysilicon thin film transistor but also to other transistors in practical applications.
  • the pre-charging mode is improved, and the gate of the driving tube is fixedly set to a data voltage lower than the working voltage, and during the discharging process by using the driving tube, Before the source-drain voltage is zero, the driving tube enters the sub-threshold off state from the on state, and the threshold voltage is stored in the first capacitor, thereby finally implementing the threshold voltage compensation function.
  • the pixel driving circuit is provided in the second embodiment of the present invention.
  • the middle drive tube can be of any type.
  • FIG. 11 is a schematic structural diagram of a pixel driving circuit according to Embodiment 3 of the present invention.
  • the pixel driving circuit provided in this embodiment is different from the second embodiment in that: the voltage supplied from the first power terminal is a reference voltage. , the negative electrode of the light emitting device and the fourth switch The second pole of the tube is connected, and the anode of the light emitting device is connected to the second power terminal.
  • the control pole of the fifth switch tube T5 is connected to the first control line, the first pole of the fifth switch tube T5 is connected to the second pole of the fourth switch tube T4, and the first pole of the fifth switch tube T5 is connected to the light emitting device.
  • the second pole of the fifth switch tube T5 is connected to the anode of the light-emitting device, and the second pole of the fifth switch tube T5 is connected to the second power source, and the drive tube, the first switch tube T1, and the second switch tube ⁇ 2 are simultaneously connected.
  • the third switch transistor ⁇ 3, the fourth switch transistor ⁇ 4, and the fifth switch transistor ⁇ 5 are ⁇ -type thin film transistors, and the ⁇ -type thin film transistor can be turned on at a low level and turned off at a high level signal.
  • the pre-charging mode is improved, and the gate of the driving tube is fixedly set to a data voltage lower than the working voltage, and during the discharging process by using the driving tube, Before the source-drain voltage is zero, the driving tube enters the sub-threshold off state from the on state, and the threshold voltage is stored in the first capacitor, thereby finally implementing the threshold voltage compensation function, and is provided in the pixel driving circuit in the third embodiment of the present invention.
  • the drive tube can be of any type.
  • Embodiment 4 of the present invention provides a display device, including: a control unit, a data line driving unit, a gate line driving unit, a data line, a plurality of gate lines, a first regulation line, a second regulation line, and a pixel driving circuit.
  • the control unit is configured to control the first control line and the second control line
  • the data line driving unit is used to drive the data line
  • the gate line driving unit is used to sequentially drive the plurality of gate lines
  • the pixel driving circuit adopts the above implementation embodiment 1 and the second embodiment Or the pixel driving circuit provided in the third embodiment, as described in the first embodiment, the second embodiment, or the third embodiment, and the details are not described herein.
  • Each of the pixel driving circuit and the two of the plurality of gate lines The grid lines are connected.
  • the display device provided in Embodiment 4 of the present invention includes a pixel driving circuit.
  • the pixel driving circuit by setting two storage capacitors, the pre-charging mode is improved, and the gate of the driving tube is fixedly set to a data voltage lower than the working voltage.
  • the driving tube enters the sub-threshold off state before the source-drain voltage is zero, and the threshold voltage is stored in the first capacitor, thereby finally realizing the threshold voltage compensation function.
  • the driving tube may be of any type.
  • the pixel driving method is based on a pixel driving circuit
  • the pixel driving circuit includes: a light emitting device, a driving tube, a control unit, a first charging unit, and a first a charging unit, a first power terminal and a second power terminal, wherein the control unit is connected to the data line, the first control line, the second control line, the first gate line and the second gate line, the first charging unit and The second charging unit is connected to the control unit, the gate of the driving tube is connected to the first charging unit, and the drain of the driving tube is connected to the first power terminal, the driving tube a source is connected to the control unit, a first pole of the light emitting device is connected to the control unit and the second charging unit, and a second pole of the light emitting device is connected to the second power terminal, such as shown in FIG. 12, the pixel driving method includes:
  • Step 101 The control unit charges the first charging unit according to the signals of the first control line, the second control line, the first gate line, and the second gate line, so that the voltage across the first charging unit is equal to the driving tube. Threshold voltage.
  • Step 102 The control unit charges the second charging unit according to the signals of the first control line, the second control line, the first gate line, and the second gate line, so that the voltage across the second charging unit is equal to the data.
  • the data voltage provided by the line is equal to the data.
  • Step 103 The first charging unit and the second charging unit provide a driving voltage for the driving tube for a predetermined period of time according to control of the control unit, the driving voltage being equal to a threshold voltage of the driving tube and the data voltage Sum.
  • Step 104 The driving tube drives the light emitting device to emit light.
  • the pixel driving method provided in the fifth embodiment of the present invention improves the pre-charging mode by setting two storage capacitors, and the gate of the driving tube is fixedly set to a data voltage lower than the working voltage, and is driven when discharging by the driving tube.
  • the driving tube enters the sub-threshold off state from the on state, and the threshold voltage is stored in the storage capacitor, thereby finally implementing the threshold voltage compensation function, and driving in the pixel driving method in the fifth embodiment of the present invention.
  • the tube can be of any type. It is to be understood that the above embodiments are merely exemplary embodiments employed to explain the principles of the invention, but the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and improvements are also considered to be within the scope of the invention.

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Abstract

一种像素驱动电路、显示装置和像素驱动方法，在像素驱动电路中，控制单元与数据线、第一控制线、第二控制线、第一栅线（Gn-1）和第二栅线（Gn）连接，第一充电单元（C1）和第二充电单元（C2）均与控制单元连接，驱动管（DTFT）的栅极与第一充电单元（C1）连接，驱动管（DTFT）的漏极与第一电源端连接，驱动管（DTFT）的源极与控制单元连接，发光器件（OLED）的第一极与控制单元和第二充电单元（C2）连接，发光器件（OLED）的第二极与第二电源端连接。通过设置两个存储电容，改进预充电方式，使驱动管（DTFT）的栅极固定设置为低于工作电压的数据电压（Vdata）,在利用驱动管（DTFT）进行放电过程中，在源漏电压为零之前使得驱动管（DTFT）进入亚阈值导通状态，将阈值电压存入第一电容（C1）中，实现阈值电压补偿功能。

Description

像素驱动电路、 显示装置和像素驱动方法 技术领域
本发明涉及显示技术领域， 特别涉及一种像素驱动电路、 显示 装置和像素驱动方法。 背景技术
有源矩阵有机发光二极体面板 （Active Matrix Organic Light
Emitting Diode，简称： AMOLED) 的应用越来越广泛。 AMOLED的像素 显示器件为有机发光二极管 （Organic Light-Emitting Diode，简称 OLED) ， AMOLED 能够发光是通过驱动薄膜晶体管在饱和状态下产生 驱动电流， 该驱动电流驱动 0LED发光。 图 1为现有技术中基本的像 素驱动电路的结构示意图， 现有的基本的像素驱动电路采用 2T1C电 路， 该 2T1C电路包括两个薄膜晶体管和 1个存储电容， 具体的结构 可参见图 1所示。
但是， 由于在现有的低温多晶硅工艺制程中驱动管 DTFT的阈值 电压 Vth 均匀性较差， 而且在使用过程中还会发生漂移， 这样当向 驱动管 DTFT输入相同数据电压 Vdata时，由于驱动管 DTFT的阈值电 压不同产生不同的驱动电流， 从而导致 AMOLED 亮度的均匀性较差。
为解决上述问题， 本领域中的技术人员设计出具有阈值电压补 偿功能的 AMOLED像素驱动电路。 图 2为现有技术中的具有阈值电压 补偿功能的像素驱动电路的结构示意图，图 3为图 2中所示电路的放 电阶段的等效电路的结构示意图，如图 2和图 3所示，该电路为 6T1C 电路， 在充电阶段， 通过控制开关管切断驱动管 DTFT与高电平 VDD 和低电平 VSS的连接， 同时存储电容 C的一端与电压输入端子连接， 存储电容 C的另一端与数据线连接。电压输入端子提供了一个初始电 压 Vini，数据线提供数据电压 Vdata， 电压输入端子与数据线共同对 存储电容 C进行充电， 使得存储电容两端有电压 Vini-Vdata。 在放 电阶段， 参见图 3， 通过开关控制管切断驱动管 DTFT与高电平 VDD、 低电平 VSS、数据电压以及初始电压 Vini的连接，而连接驱动管 DTFT 的栅极和驱动管 DTFT的漏极的开关管 S1继续保持导通，存储电容 C 与驱动管 DTFT两端连接通过驱动管 DTFT来进行放电，当驱动管的栅 极电压 Vg=Vdata+Vth时，驱动管 DTFT处于亚阈值导通状态，则放电 结束， 此时存储电容两端电压为 Vth。 其中 Vdata为数据信号电压， Vth为驱动管 DTFT的阈值电压。 在发光显示阶段时， 驱动管 DTFT的 栅极电压 Vg=Vdata+Vth，驱动晶体管的源极电压 Vs=VSS，驱动管 DTFT 的栅源电压 Vgs=Vdata+Vth， 又因为驱动回路中的驱动电流为 I = K*(Vgs-Vth)2 , 因此驱动电流 I = K*Vdata2， 使得驱动电流与阈值电压 无关， 最终实现了阈值补偿功能。
但是，上述电路仅仅在驱动管 DTFT为增强型晶体管时才能实现阈 值补偿功能。 当驱动管 DTFT为耗尽型晶体管时， 耗尽型晶体管的阈值 电压 Vth为负值，在放电阶段时，当驱动管 DTFT的栅极电压 Vg=Vdata 时驱动管便停止放电， 因为此时驱动管 DTFT栅极、 源极和漏极的电 压均为 Vdata, 即源漏电压 Vsd=0， 而使得放电结束， 此时电容的两 端电压为 0， 而不会为 Vth， 因此， 该 AM0LED像素驱动电路失去了阈 值补偿功能。 发明内容
本发明提供一种像素驱动电路、 显示装置和像素驱动方法， 其 可以在驱动管为任意类型时都能实现阈值补偿功能。
为实现上述目的， 本发明提供一种像素驱动电路， 包括： 发光 器件、 驱动管、 控制单元、 第一充电单元、 第二充电单元、 第一电源 端和第二电源端，所述控制单元与数据线、第一控制线、第二控制线、 第一栅线和第二栅线连接，所述第一充电单元和所述第二充电单元均 与所述控制单元连接， 所述驱动管的栅极与所述第一充电单元连接， 所述驱动管的漏极与所述第一电源端连接，所述驱动管的源极与所述 控制单元连接，所述发光器件的第一极与所述控制单元和所述第二充 电单元连接， 所述发光器件的第二极与所述第二电源端连接； 其中， 所述控制单元用于根据所述第一控制线、 第二控制线、 第一栅 线和第二栅线的信号而依次对所述第一充电单元和所述第二充电单 元进行充电，分别使得所述第一充电单元两端的电压等于驱动管的阈 值电压且所述第二充电单元两端的电压等于数据线提供的数据电压； 所述第一充电单元和第二充电单元用于根据所述控制单元的控 制而为所述驱动管提供驱动电压，该驱动电压等于所述驱动管的阈值 电压与所述数据电压之和；
所述驱动管用于驱动所述发光器件发光。
可选地， 所述控制单元包括： 第一开关管、 第二开关管、 第三 开关管和第四开关管；
所述第一开关管的控制极与所述第一控制线连接， 所述第一开 关管的第一极与所述第一充电单元的第二端以及所述第二充电单元 的第一端连接，所述第一开关管的第二极与所述驱动管的源极以及所 述第四开关管的第一极连接；
所述第二开关管的控制极与第一栅线连接， 所述第二开关管的 第一极与所述数据线连接，所述第二开关管的第二极与所述第一充电 单元的第一端以及所述驱动管的栅极连接；
所述第三开关管的控制极与第二栅线连接， 所述第三开关管的 第一极与所述数据线连接，所述第三开关管的第二极与所述第一充电 单元的第二端、所述第二充电单元的第一端以及所述第一开关管的第 一极连接；
所述第四开关管的控制极与所述第二控制线连接， 所述第四开 关管的第一极与所述驱动管的源极连接，所述第四开关管的第二极与 所述第二充电单元的第二端以及所述发光器件的第一极连接。
可选地， 所述像素驱动电路还包括： 第五开关管， 所述第五开关 管的控制极与所述第一控制线连接， 所述第五开关管的第一极与所述 第四开关管的第二极以及所述发光器件的第一极连接， 所述第五开关 管的第二极与所述发光器件的第二极以及所述第二电源端连接。
可选地， 所述第一电源端提供的电压为工作电压， 所述第二电源 端提供的电压为参考电压， 所述发光器件的第一极为正极， 所述发光 器件的第二极为负极。
可选地， 所述驱动管、 所述第一开关管、 所述第二开关管、 所述 第三开关管、 所述第四开关管和所述第五开关管为 N型薄膜晶体管。
可选地， 所述第一电源端提供的电压为参考电压， 所述第二电源 端提供的电压为工作电压， 所述发光器件的第一极为负极， 所述发光 器件的第二极为正极。
可选地， 所述驱动管、 所述第一开关管、 所述第二开关管、 所述 第三开关管、 所述第四开关管、 所述第五开关管为 P型薄膜晶体管。
可选地， 所述第一栅线与所述第二栅线为选通时序相邻的两条 栅线， 且所述第一栅线先于所述第二栅线选通。
可选地， 所述第一控制线与所述第一栅线同时开始选通， 且所述 第一控制线一直保持选通直到与所述第二栅线同时结束选通； 所述第 二控制线在所述第一栅线选通的期间内结束选通， 且所述第二控制线 在所述第一控制线结束选通的时刻开始选通。
为实现上述目的， 本发明提供一种显示装置， 包括： 调控单元、 数据线驱动单元、 栅线驱动单元、 数据线、 多条栅线、 第一控制线、 第二控制线和多个像素驱动电路， 所述调控单元用于调控所述第一控 制线和所述第二控制线， 所述数据线驱动单元用于驱动所述数据线， 所述栅线驱动单元用于依次驱动所述多条栅线；
所述像素驱动电路采用上述任一所述的像素驱动电路， 每个所述 像素驱动电路与所述多条栅线中的两条栅线相连。
为实现上述目的， 本发明提供一种像素驱动方法， 所述像素驱动 方法是基于所述像素驱动电路， 所述像素驱动电路包括： 发光器件、 驱动管、 控制单元、 第一充电单元、 第二充电单元、 第一电源端和第 二电源端， 所述控制单元与数据线、 第一控制线、 第二控制线、 第一 栅线和第二栅线连接，所述第一充电单元和所述第二充电单元均与所 述控制单元连接，所述驱动管的栅极与所述第一充电单元连接，所述 驱动管的漏极与所述第一电源端连接，所述驱动管的源极与所述控制 单元连接，所述发光器件的第一极与所述控制单元和所述第二充电单 元连接， 所述发光器件的第二极与所述第二电源端连接，所述像素驱 动方法包括下述步骤：
控制单元根据所述第一控制线、 第二控制线、 第一栅线和第二 栅线的信号而对第一充电单元充电，使得所述第一充电单元两端的电 压等于驱动管的阈值电压；
控制单元根据所述第一控制线、 第二控制线、 第一栅线和第二 栅线的信号而对第二充电单元进行充电，使得所述第二充电单元两端 的电压等于数据线提供的数据电压；
第一充电单元和第二充电单元根据所述控制单元的控制而在预 定的时段内为所述驱动管提供驱动电压，该驱动电压等于所述驱动管 的阈值电压与所述数据电压之和；
驱动管驱动发光器件发光。
本发明具有以下有益效果：
本发明通过设置两个存储电容， 改进预充电方式， 使驱动管的 栅极固定设置为介于工作电压（高电平）与参考电压（低电平）之间 的数据电压，在利用驱动管放电的过程中，在驱动管的源漏电压为零 之前使得驱动管由导通状态进入亚阈值截止状态，将阈值电压存入存 储电容，最终实现了阈值电压补偿功能， 同时该电路中驱动管可为任 意类型。 附图说明
图 1为现有技术中基本的像素驱动电路的结构示意图； 图 2 为现有技术中的具有阈值电压补偿功能的像素驱动电路的 结构示意图；
图 3为图 2中所示电路的放电阶段的等效电路的结构示意图； 图 4为本发明实施例一提供的像素驱动电路的结构示意图； 图 5为本发明实施例二提供的像素驱动电路的结构示意图； 图 6为图 5中所示电路的工作时序图；
图 7为图 5中所示电路的初始阶段的等效电路图；
图 8为图 5中所示电路的读取阶段的等效电路图；
图 9为图 5中所示电路的写入阶段的等效电路图； 图 10为图 5中所示电路的显示阶段的等效电路图；
图 1 1为本发明实施例三提供的像素驱动电路的结构示意图； 图 12为本发明实施例五提供的像素驱动方法的流程图。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案， 下面结 合附图对本发明提供的像素驱动电路、显示装置和像素驱动方法进行 详细描述。
实施例一
图 4为本发明实施例一提供的像素驱动电路的结构示意图， 如 图 4所示， 该像素驱动电路包括： 发光器件、 驱动管、 控制单元、 第 一充电单元、第二充电单元、第一电源端和第二电源端， 控制单元与 数据线、 第一控制线、 第二控制线、 第一栅线和第二栅线连接， 第一 充电单元和第二充电单元均与控制单元连接，驱动管的栅极与第一充 电单元连接，驱动管的漏极与第一电源端连接，驱动管的源极与控制 单元连接，发光器件的第一极与控制单元和第二充电单元连接，发光 器件的第二极与第二电源端连接； 其中，
控制单元用于根据第一控制线、 第二控制线、 第一栅线和第二 栅线的信号而依次对第一充电单元和第二充电单元进行充电，分别使 得第一充电单元两端的电压等于驱动管的阈值电压且第二充电单元 两端的电压等于数据线提供的数据电压；
第一充电单元和第二充电单元用于根据控制单元的控制而为驱 动管提供驱动电压，该驱动电压等于驱动管的阈值电压与数据电压之 和；
驱动管用于驱动发光器件发光。
其中，数据线提供数据电压 Vdata，第一电源端和第二电源端中 的一个提供工作电压 VDD, 另一个提供参考电压 VSS。 具体地， 若第 一电源端提供的电压为参考电压 VSS时，则相应地，第二电源端提供 的电压为高于参考电压 VSS的工作电压 VDD;若第二电源端提供的电 压为参考电压 VSS时，则相应地，第一电源端提供的电压为高于参考 电压 VSS的工作电压 VDD。 其中， VDD可以为高电平， 则相应地， 作 为参考电压的 VSS可以为低电平。且数据电压 Vdata、工作电压 VDD、 参考电压 VSS满足 VSS〈Vdata〈VDD。
本发明实施例一的工作原理如下， 通过控制单元为第一充电单 元和第二充电单元分别充电， 使得第一充电单元的两端电压为 Vth， 第二充电单元的两端电压为 Vdata，第一充电单元和第二充电单元的 两端电压之和为 Vdata+Vth， 其中 Vth为驱动管的阈值电压。 在第一 充电单元和第二充电单元为驱动管提供电压时，由于驱动管的栅源电 压 Vgs 为第一充电单元和第二充电单元的电压之和， 则 Vgs=Vdata+Vth0 由于驱动管能够提供正比于该驱动管的栅源电压同 其阈值电压之差的平方的驱动电流， ΒΡ， 驱动回路中的驱动电流 I = K*(Vgs-Vth)2 , Ά Vgs=Vdata+Vth, 贝 lj I = K*Vdata2， 使得驱动管在饱 和状态下的驱动电流 I 与其阈值电压 Vth无关， 因此驱动管的阈值 电压 Vth 不会对流经发光器件的电流产生影响， 从而更好地保证了 驱动电流 I 的一致性， 使 AM0LED 亮度的均匀性较好。
可选地， 在利用实施例一提供的像素驱动电路中， 第一栅线与第 二栅线为选通时序相邻的两条栅线， 且第一栅线先于第二栅线选通。
进一步地， 第一控制线与第一栅线同时开始选通， 且第一控制线 一直保持选通直到与第二栅线同时结束选通； 第二控制线在第一栅线 选通的期间内结束选通， 且第二控制线在第一控制线结束选通的时刻 开始选通。
需要注意的是， 本发明中的驱动管可以为增强型驱动管或是耗 尽型驱动管。因为驱动管的漏极连接有第一电源端，而且第一电源端 可以提供工作电压 VDD或者是参考电压 VSS， 从而使得在第一充电单 元放电过程中驱动管的源漏电压 Vsd不为 0，进而使得无论驱动管的阈 值电压 Vth为正或为负， 第一充电单元都可通过驱动管放电直至驱动 管由导通状态进入亚阈值截止状态， 从而使得第一充电单元两端电压 为 Vth o
优选地， 驱动管为耗尽型晶体管。 更优选地， 驱动管为以氧化物 半导体层作为有源层的氧化物薄膜晶体管。 本发明实施例一提供的像素驱动电路中， 通过设置两个存储电 容，改进预充电方式，使驱动管的栅极固定设置为低于工作电压的数 据电压， 在读取阶段中， 在源漏电压为零之前其使得驱动管由导通状 态进入亚阈值截止状态， 将阈值电压存入存储电容， 最终实现了阈值 电压补偿功能， 同时，在本发明实施例一提供像素驱动电路中驱动管 可为任意类型。 实施例二
图 5 为本发明实施例二提供的像素驱动电路的结构示意图， 如 图 5所示， 第一开关管 T1的控制极与第一控制线连接， 第一开关管 T1的第一极与第一控制线连接，第一开关管 T1的第一极与第一充电 单元的第二端以及第二充电单元的第一端连接， 第一开关管 T1的第 二极与驱动管 DTFT的源极以及第四开关管 T4的第一极连接。
第二开关管 T2的控制极与第一栅线连接， 第二开关管 T2的第 一极与数据线连接， 第二开关管 T2的第二极与第一充电单元的第一 端以及驱动管 DTFT的栅极连接。
第三开关管 T3的控制极与第二栅线连接， 第三开关管 T3的第 一极与数据线连接， 第三开关管 T3的第二极与第一充电单元的第二 端、 第二充电单元的第一端以及第一开关管 T1的第一极连接。
第四开关管 T4的控制极与第二控制线连接， 第四开关管 T4的 第一极与驱动管 DTFT的源极连接，第四开关管 T4的第二极与第二充 电单元的第二端以及 0LED连接。
本实施例与实施例一的区别在于， 本发明实施例二的电路为 6T2C型电路， 发光器件为 0LED, 第一充电单元为第一电容 Cl， 第二 充电单元为第二电容 C2， 控制单元包括： 第一开关管 Tl、 第二开关 管 Τ2、第三开关管 Τ3和第四开关管 Τ4。数据线提供数据电压 Vdata, 第一控制线提供第一控制信号 CR1， 第二控制线提供第二控制信号 CR2, 第一栅线和第二栅线中可以加载扫描信号， 其中第一栅线指的 是第 N-1条栅线 Gn-1， 第二栅线指的是第 N条栅线 Gn， 栅线 Gn_l 与栅线 Gn为两条相邻的栅线，即栅线 Gn-1上完成信号扫描后，栅线 Gn开始加载扫描信号， 进行信号扫描， 其中 N大于等于 2。
可选地， 像素驱动电路还包括： 第五开关管 T5， 第五开关管 Τ5 的控制极与第一控制线连接，第五开关管 Τ5的第一极与第四开关管 Τ4 的第二极以及 0LED的第一极连接， 第五开关管 T5的第二极与 0LED的 第二极以及第二电源端连接。第五晶体管 T5的第一极和第二极连接在 0LED的两端， 用于在驱动管 DTFT产生不正确的驱动电流时将 0LED短 路， 以免 0LED在不正确的驱动电流作用下发光， 从而产生不正确的发 光强度以造成显示错误， 并在驱动管 DTFT 产生正确的驱动电流时使 0LED 与驱动管 DTFT连通， 使 0LED 在正确的驱动电流作用下发光， 保证显示正常。
本实施例中， 第一电源端提供的电压为工作电压 VDD， 第二电源 端提供的电压为参考电压 VSS，发光器件的第一极为正极，发光器件的 第二极为负极。
进一步地， 驱动管 DTFT、 第一开关管 Tl、 第二开关管 Τ2、 第三 开关管 Τ3、 第四开关管 Τ4、 第五开关管 Τ5为 Ν型薄膜晶体管， Ν型薄 膜晶体管可在高电平信号下导通， 并在低电平信号下截止。
上述第一开关管 Tl、第二开关管 Τ2、第三开关管 Τ3、第四开关 管 Τ4、 第五开关管 Τ5均包含控制极、 第一极和第二极， 第一极和第 二极的结构是相同的。 在开关管为薄膜晶体管 （TFT) 的情况下， 所述 控制极为栅极， 并且在第一极和第二极中， 发送载流子的一极作为源 极， 接收载流子的一极作为漏极。 实际应用时， 对于一个开关管， 根 据该开关管在电路中的位置和作用以及开关管的沟道类型， 可以以源 极作为开关管的第一极， 相应地， 以漏极作为开关管的第二极； 或者， 可以以漏极作为开关管的第一极， 相应地， 以源极作为开关管的第二 极。
本发明实施例二提供的像素电路的工作过程可分为： 初始阶段、 读取阶段、 写入阶段和显示阶段。 图 6为图 5 的工作时序图； 图 7 为图 5中所示电路的初始阶段的等效电路图；图 8为图 5中所示电路 的读取阶段的等效电路图；图 9为图 5中所示电路的写入阶段的等效 电路图； 图 10为图 5中所示电路的显示阶段的等效电路图， 下面结 合图 6至图 9描述本发明实施例二提供的像素驱动电路的工作过程。 在初始阶段， 栅线 Gn-1为高电平， 栅线 Gn为低电平， 第一控 制信号 CR1为高电平， 第二控制信号 CR2为高电平。
如图 7所示， 第一开关管 Tl、 第二开关管 Τ2、 第四开关管 Τ4 和第五开关管 Τ5导通， 第三开关管 Τ3截止。 此时数据电压 Vdata 通过第二开关管 T2写到第一电容 Cl， 使得节点 A的电压 Va=Vdata， 节点 B的电压为 Vb=VSS，驱动管 DTFT的栅极电压 Vg=Vdata，驱动管 DTFT的源极电压 Vs=VSS。
在读取阶段， 栅线 Gn-1为高电平， 栅线 Gn为低电平， 第一控 制信号 CR1为高电平， 第二控制信号 CR2为低电平。
如图 8所示， 第一开关管 Tl、 第二开关管 Τ2和第五开关管 Τ5 导通， 第三开关管 Τ3和第四开关管 Τ4截止。 第一电容 C1可以通过 驱动管 DTFT进行放电至亚阈值饱和截止状态，即驱动管 DTFT的栅源 电压 Vgs=Vth， 又因为驱动管 DTFT的栅极一直与数据线连接， 所以 Vg=Vdata, 则 Vs=Vdata_Vth。 此时节点 A的电压 Va=Vdata， 节点 B 的电压为 Vb= Vdata-Vth, 第一电容 C1的两端电压为 Vth。
读取阶段完成了对第一电容 C1的充电， 使第一电容 C1的两端 电压为 Vth。
在写入阶段， 栅线 Gn-1为低电平， 栅线 Gn为高电平， 第一控 制信号 CR1为高电平， 第二控制信号 CR2为低电平。
如图 9所示， 第一开关管 Tl、 第三开关管 Τ3和第五开关管 Τ5 导通， 第二开关管 Τ2和第四开关管 Τ4截止。 第一电容 C1的两端电 压保持为 Vth， 节点 B与数据线连接， 则使得节点 B的电压突变为 Vb=Vdata,节点 A的电压突变为 Va=Vdata+Vth，所以 Vg= Vdata+Vth, Vs=Vdata。 同时， 数据电压 Vdata通过第三开关管 T3写入到第二电 容 C2, 第二电容 C2的两端电压为 Vdata。
写入阶段完成了对第二电容 C2的充电， 使第二电容 C2的两端 电压为 Vdata0
在显示阶段， 栅线 Gn-1为低电平， 栅线 Gn为低电平， 第一控 制信号 CR1为低电平， 第二控制信号 CR2为高电平。 如图 10所示， 第四开关管 T4导通， 第一开关管 Tl、 第二开关 管 Τ2、 第三开关管 Τ3和第五开关管 Τ5截止， 此时第一电容 C1的两 端电压为 Vth， 第二电容 C2的两端电压为 Vdata， 第一电容 C1和第 二电容 C2为驱动管 DTFT提供电压， 则第一电容 C1与第二电容 C2 的串联电压为驱动管 DTFT的栅源电压， 即驱动管 DTFT的栅源电压
Vgs=Vdata+Vth0 驱动管 DTFT驱动 OLED进行发光， 又由于驱动电流 I = K*(Vgs-Vth)2，且 Vgs=Vdata+Vth,贝 !j I = K*(Vdata+Vth-Vth )2 =K*Vdata2， 本发明实施二提供的像素驱动电路使得驱动管 DTFT在饱和状态下的 驱动电流 I与其阈值电压 Vth无关，因此驱动管 DTFT的阈值电压 Vth 不会对流经发光器件的电流产生影响，从而更好地保证了驱动电流 I 的一致性， 使 AM0LED 亮度的均匀性较好。
需要注意的是， 本发明中的驱动管 DTFT可以为增强型驱动管或 是耗尽型驱动管， 因为驱动管 DTFT的漏极连接有第一电源端， 而且 第一电源端提供工作电压 VDD，从而使得在第一电容 C1放电过程中驱 动管 DTFT的源漏电压 Vsd不为 0，进而使得无论驱动管 DTFT的阈值电 压 Vth为正或为负， 第一电容 C1都可通过驱动管 DTFT放电直至驱动 管 DTFT处于亚阈值导通状态， 此时第一电容 C1的两端电压为 Vth。
同时， 本发明实施例所提供的像素驱动电路， 在实际应用中， 不 仅适用于多晶硅薄膜晶体管， 对其他晶体管也适用。
本发明实施例二提供的像素驱动电路中， 通过设置两个存储电 容，改进预充电方式，使驱动管的栅极固定设置为低于工作电压的数 据电压，在利用驱动管进行放电过程中，在源漏电压为零之前使得驱 动管由导通状态进入亚阈值截止状态， 将阈值电压存入第一电容中， 最终实现了阈值电压补偿功能， 同时，在本发明实施例二提供像素驱 动电路中驱动管可为任意类型。 实施例三
图 11为本发明实施例三提供的像素驱动电路的结构示意图， 如 图 11所示， 本实施例提供的像素驱动电路与上述实施例二的区别在 于： 第一电源端提供的电压为参考电压， 发光器件的负极与第四开关 管的第二极连接， 发光器件的正极与第二电源端连接。 而且第五开关 管 T5的控制极与第一控制线连接， 第五开关管 T5的第一极与第四开 关管 T4的第二极连接， 第五开关管 T5的第一极与发光器件的负极连 接， 第五开关管 T5 的第二极与发光器件的正极连接， 第五开关管 T5 的第二极与第二电源端连接， 同时驱动管、 第一开关管 Tl、 第二开关 管 Τ2、 第三开关管 Τ3、 第四开关管 Τ4、 第五开关管 Τ5为 Ρ型薄膜晶 体管， 而 Ρ型薄膜晶体管可在低电平下导通， 并在高电平信号下截止。
本发明实施例三提供的像素电路的各个开关管的开关顺序和整个 电路的工作过程具体类似于上述实施例二， 此处不再赘述。
本发明实施例三提供的像素驱动电路中， 通过设置两个存储电 容，改进预充电方式，使驱动管的栅极固定设置为低于工作电压的数 据电压，在利用驱动管进行放电过程中，在源漏电压为零之前使得驱 动管由导通状态进入亚阈值截止状态， 将阈值电压存入第一电容中， 最终实现了阈值电压补偿功能，同时在本发明实施例三提供像素驱动 电路中驱动管可为任意类型。 实施例四
本发明实施例四提供一种显示装置，该显示装置包括：调控单元、 数据线驱动单元、 栅线驱动单元、 数据线、 多条栅线、 第一调控线、 第二调控线和像素驱动电路， 调控单元用于调控第一控制线和第二控 制线， 数据线驱动单元用于驱动数据线， 栅线驱动单元用于依次驱动 多条栅线， 像素驱动电路采用上述实施一、 实施例二或实施例三提供 的像素驱动电路， 具体可参见上述实施例一、 实施例二或实施例三中 所述， 此处不再赘述， 每个像素驱动电路与所述多条栅线中的两条栅 线相连。
本发明实施例四提供的显示装置包括像素驱动电路， 在该像素 驱动电路中， 通过设置两个存储电容， 改进预充电方式， 使驱动管的 栅极固定设置为低于工作电压的数据电压，在利用驱动管进行放电过 程中，在源漏电压为零之前使得驱动管由导通状态进入亚阈值截止状 态， 将阈值电压存入第一电容中， 最终实现了阈值电压补偿功能， 同 时在本发明实施例四提供的显示装置中驱动管可为任意类型。 实施例五
图 12为本发明实施例五提供的像素驱动方法的流程图，其中，该 像素驱动方法是基于像素驱动电路，该像素驱动电路包括：发光器件、 驱动管、 控制单元、 第一充电单元、 第二充电单元、 第一电源端和第 二电源端， 所述控制单元与数据线、 第一控制线、 第二控制线、 第一 栅线和第二栅线连接，所述第一充电单元和所述第二充电单元均与所 述控制单元连接，所述驱动管的栅极与所述第一充电单元连接，所述 驱动管的漏极与所述第一电源端连接，所述驱动管的源极与所述控制 单元连接，所述发光器件的第一极与所述控制单元和所述第二充电单 元连接， 所述发光器件的第二极与所述第二电源端连接， 如图 12所 示， 该像素驱动方法包括：
步骤 101 : 控制单元根据所述第一控制线、第二控制线、第一栅 线和第二栅线的信号而对第一充电单元充电，使得所述第一充电单元 两端的电压等于驱动管的阈值电压。
步骤 102: 控制单元根据所述第一控制线、第二控制线、第一栅 线和第二栅线的信号而对第二充电单元进行充电，使得所述第二充电 单元两端的电压等于数据线提供的数据电压。
步骤 103:第一充电单元和第二充电单元根据所述控制单元的控 制而在预定的时段内为所述驱动管提供驱动电压，该驱动电压等于所 述驱动管的阈值电压与所述数据电压之和。
步骤 104: 驱动管驱动发光器件发光。
本发明实施例五提供的像素驱动方法， 通过设置两个存储电容， 改进预充电方式，且使驱动管的栅极固定设置为低于工作电压的数据 电压，在利用驱动管放电时，在驱动管的源漏电压为零之前使得驱动 管从导通状态进入亚阈值截止状态，将阈值电压存入存储电容，最终 实现了阈值电压补偿功能，同时在本发明实施例五提供像素驱动方法 中驱动管可为任意类型。 可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而 采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的 普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做 出各种变型和改进， 这些变型和改进也视为本发明的保护范围。

Claims

权 利 要 求 书
1.一种像素驱动电路， 其特征在于， 包括： 发光器件、 驱动管、 控制单元、第一充电单元、第二充电单元、第一电源端和第二电源端， 所述控制单元与数据线、 第一控制线、 第二控制线、 第一栅线和第二 栅线连接，所述第一充电单元和所述第二充电单元均与所述控制单元 连接， 所述驱动管的栅极与所述第一充电单元连接， 所述驱动管的漏 极与所述第一电源端连接， 所述驱动管的源极与所述控制单元连接， 所述发光器件的第一极与所述控制单元和所述第二充电单元连接，所 述发光器件的第二极与所述第二电源端连接； 其中，
所述控制单元用于根据所述第一控制线、 第二控制线、 第一栅 线和第二栅线的信号而依次对所述第一充电单元和所述第二充电单 元进行充电，分别使得所述第一充电单元两端的电压等于驱动管的阚 值电压且所述第二充电单元两端的电压等于数据线提供的数据电压； 所述第一充电单元和第二充电单元用于根据所述控制单元的控 制而为所述驱动管提供驱动电压，该驱动电压等于所述驱动管的阈值 电压与所述数据电压之和；
所述驱动管用于驱动所述发光器件发光。
2.根据权利要求 1 所述的像素驱动电路， 其特征在于， 所述控 制单元包括： 第一开关管、 第二开关管、 第三开关管和第四开关管； 所述第一开关管的控制极与所述第一控制线连接， 所述第一幵 关管的第一极与所述第一充电单元的第二端以及所述第二充电单元 的第一端连接，所述第一开关管的第二极与所述驱动管的源极以及所 述第四开关管的第一极连接；
所述第二开关管的控制极与第一栅线连接， 所述第二开关管的 第一极与所述数据线连接，所述第二幵关管的第二极与所述第一充电 单元的第一端以及所述驱动管的栅极连接；
所述第三开关管的控制极与第二栅线连接， 所述第三开关管的 第一极与所述数据线连接，所述第三幵关管的第二极与所述第一充电 单元的第二端、所述第二充电单元的第一端以及所述第一开关管的第 一极连接；
所述第四开关管的控制极与所述第二控制线连接， 所述第四开 关管的第一极与所述驱动管的源极连接，所述第四开关管的第二极与 所述第二充电单元的第二端以及所述发光器件的第一极连接。
3.根据权利要求 2所述的像素驱动电路， 其特征在于， 还包括： 第五幵关管， 所述第五开关管的控制极与所述第一控制线连接， 所述 第五幵关管的第一极与所述第四幵关管的第二极以及所述发光器件的 第一极连接， 所述第五开关管的第二极与所述发光器件的第二极以及 所述第二电源端连接。
4.根据权利要求 3所述的像素驱动电路， 其特征在于， 所述第一 电源端提供的电压为工作电压， 所述第二电源端提供的电压为参考电 压， 所述发光器件的第一极为正极， 所述发光器件的第二极为负极。
5.根据权利要求 4所述的像素驱动电路， 其特征在于， 所述驱动 管、 所述第一开关管、 所述第二开关管、 所述第三开关管、 所述第四 开关管和所述第五开关管为 N型薄膜晶体管。
6.根据权利要求 3所述的像素驱动电路， 其特征在于， 所述第一 电源端提供的电压为参考电压， 所述第二电源端提供的电压为工作电 压， 所述发光器件的第一极为负极， 所述发光器件的第二极为正极。
7.根据权利要求 6所述的像素驱动电路， 其特征在于， 所述驱动 管、 所述第一开关管、 所述第二开关管、 所述第三开关管、 所述第四 幵关管、 所述第五开关管为 P型薄膜晶体管。
8.根据权利要求 2所述的像素驱动电路， 其特征在于， 所述第一 栅线与所述第二栅线为选通时序相邻的两条栅线，且所述第一栅线先 于所述第二栅线选通。
9.根据权利要求 8所述的像素驱动电路， 其特征在于， 所述第一 控制线与所述第一栅线同时开始选通， 且所述第一控制线一直保持选 通直到与所述第二栅线同时结束选通； 所述第二控制线在所述第一栅 线选通的期间内结束选通， 且所述第二控制线在所述第一控制线结束 选通的时刻开始选通。
10.—种显示装置， 其特征在于， 包括： 调控单元、 数据线驱动单 元、 栅线驱动单元、 数据线、 多条栅线、 第一控制线、 第二控制线和 多个像素驱动电路， 所述调控单元用于调控所述第一控制线和所述第 二控制线， 所述数据线驱动单元用于驱动所述数据线， 所述栅线驱动 单元用于依次驱动所述多条栅线；
所述像素驱动电路采用权利要求 1至 9中任一所述的像素驱动电 路， 每个所述像素驱动电路与所述多条栅线中的两条相邻的栅线相连。
11.一种像素驱动方法， 其特征在于， 所述像素驱动方法是基于所 述像素驱动电路， 所述像素驱动电路包括： 发光器件、 驱动管、 控制 单元、 第一充电单元、 第二充电单元、 第一电源端和第二电源端， 所 述控制单元与数据线、 第一控制线、 第二控制线、 第一栅线和第二栅 线连接，所述第一充电单元和所述第二充电单元均与所述控制单元连 接， 所述驱动管的栅极与所述第一充电单元连接， 所述驱动管的漏极 与所述第一电源端连接， 所述驱动管的源极与所述控制单元连接， 所 述发光器件的第一极与所述控制单元和所述第二充电单元连接，所述 发光器件的第二极与所述第二电源端连接， 所述像素驱动方法包括下 述步骤：
控制单元根据所述第一控制线、 第二控制线、 第一栅线和第二 栅线的信号而对第一充电单元充电以使得所述第一充电单元两端的 电压等于驱动管的阈值电压；
控制单元根据所述第一控制线、 第二控制线、 第一栅线和第二 栅线的信号而对第二充电单元进行充电以使得所述第二充电单元两 端的电压等于数据线提供的数据电压；
第一充电单元和第二充电单元根据所述控制单元的控制而在预 定的时段内为所述驱动管提供驱动电压，该驱动电压等于所述驱动管 的阈值电压与所述数据电压之和；
驱动管驱动发光器件发光。
12.根据权利要求 10所述的像素驱动方法， 其中所述对第一充电 单元充电的步骤包括初始阶段和读取阶段， 其中
在所述初始阶段， 所述第一栅线为高电平， 所述第二栅线为 低电平， 所述第一控制线为髙电平， 所述第二控制线为髙电平； 在所述读取阶段， 所述第一栅线为高电平， 所述第二栅线为 低电平， 所述第一控制线为高电平， 所述第二控制线为低电平； 并且 所述对第一充电单元充电的步骤包括写入阶段， 在所述写入阶 段， 所述第一栅线为低电平， 所述第二栅线为髙电平， 所述第一控制 线为髙电平， 所述第二控制线为低电平；
所述驱动发光器件发光的步骤包括显示阶段， 在所述显示阶段， 所述第一栅线为低电平， 所述第二栅线为低电平， 所述第一控制线为 低电平， 所述第二控制线为高电平。
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