WO2015003453A1 - 显示面板及其制作方法和显示装置 - Google Patents

显示面板及其制作方法和显示装置 Download PDF

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Publication number
WO2015003453A1
WO2015003453A1 PCT/CN2013/087972 CN2013087972W WO2015003453A1 WO 2015003453 A1 WO2015003453 A1 WO 2015003453A1 CN 2013087972 W CN2013087972 W CN 2013087972W WO 2015003453 A1 WO2015003453 A1 WO 2015003453A1
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WO
WIPO (PCT)
Prior art keywords
gate
via hole
substrate
line
display panel
Prior art date
Application number
PCT/CN2013/087972
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English (en)
French (fr)
Inventor
李凡
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/366,908 priority Critical patent/US9240421B2/en
Publication of WO2015003453A1 publication Critical patent/WO2015003453A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B5/00—Optical elements other than lenses
    • G02B5/20—Filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B5/00—Optical elements other than lenses
    • G02B5/20—Filters
    • G02B5/201—Filters in the form of arrays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/816—Multilayers, e.g. transparent multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Display panel manufacturing method thereof and display device
  • Embodiments of the present invention relate to the field of display, and in particular, to a display panel, a manufacturing method thereof, and a display device. Background technique
  • the connection end of the gate line and the gate line driving circuit is disposed at the periphery of the effective display area, the display has a wider border, thereby reducing the visual effect of the entire display, when the area of the border is larger, The worse the visual effect.
  • the prior art discloses an array substrate, wherein the gate connection lines are L-shaped, part of the gate connection lines and the data lines are arranged in parallel, and the gate connection lines are separated from the data lines by gate insulation. Floor. Similar to the arrangement of the connection ends of the data line and the data line driving circuit, the connection end of the gate connection line and the gate line driving circuit is located in an area corresponding to the black matrix in the effective display area, thereby avoiding reservation for the gate connection line. A wider border reduces the width of the display's border.
  • the embodiment of the invention provides a display panel, a manufacturing method thereof and a display device, which can improve the display effect of the display panel and the display device while reducing the width of the frame.
  • a display panel includes an array substrate and a color filter substrate; a gate line and a gate connection line of the array substrate are disposed orthogonally;
  • a passivation layer is formed on a side of the source or the drain of the array substrate adjacent to the color filter substrate, and the passivation layer is provided with a first via hole in a region corresponding to the source or the drain;
  • the color filter substrate includes a first substrate, and a data line parallel to the gate connection line is formed on a side of the first substrate adjacent to the array substrate, and the data line is adjacent to the side of the array substrate
  • a protective layer, a black matrix, and a common electrode wherein the protective layer, the black matrix, and the common electrode are provided with a second via hole in a region corresponding to the data line, and a conductive spacer is disposed in the second via hole, a first end of the conductive spacer is connected to the source or the drain through the first via, and a second end of the conductive spacer is connected to the data line through the second via, and
  • the conductive spacer is insulated from the common electrode.
  • a display device comprising the display panel.
  • a method of fabricating a display panel comprising: forming a pattern including a data line on a first substrate;
  • a pattern including a conductive spacer in the second via, a second end of the conductive spacer connecting the data line through the second via, and the conductive spacer and the The common electrode is insulated, thereby forming a color filter substrate;
  • An array substrate is formed, a gate line and a gate connection line of the array substrate are orthogonally disposed, and a passivation layer of the array substrate is formed with a first via hole corresponding to a source or a drain;
  • the first end of the conductive spacer connecting the source or the drain through the first via, the gate connection line and the data Lines are set in parallel.
  • FIG. 1 is a cross-sectional view of a display panel according to Embodiment 1 of the present invention.
  • FIG. 2 is a plan view of a color filter substrate of a display panel according to Embodiment 1 of the present invention
  • FIG. 3 is a plan view showing an array substrate of the display panel according to Embodiment 1 of the present invention; a cross-sectional view of the panel;
  • 5a to 5h are process flow diagrams of a method for fabricating a display panel according to Embodiment 3 of the present invention
  • 6a-6d are process flow diagrams of a method for fabricating an array substrate according to Embodiment 4 of the present invention.
  • FIG. 1 is a cross-sectional view of a display panel according to Embodiment 1 of the present invention, the display panel including a color filter substrate and an array substrate.
  • 2 is a plan view showing a color filter substrate of a display panel according to Embodiment 1 of the present invention
  • FIG. 3 is a plan view showing an array substrate of the display panel according to Embodiment 1 of the present invention.
  • the color filter substrate includes: a first substrate 111, a data line 112 formed on a side of the first substrate 111 adjacent to the array substrate, and the data line is formed adjacent to the array substrate a protective layer 113 on one side, a black matrix 114 and a filter 115 formed on a side of the protective layer 113 near the array substrate, and the black matrix 114 and the filter 115 are formed on a side of the array substrate
  • the common electrode 116 is
  • the protective layer 113, the black matrix 114, and the common electrode 116 are formed with a second via 117b corresponding to a region of the data line 112. a second end of the conductive spacer 117 is connected to the data line 112 through the second via 117b, and an opening of the second via 117b on the common electrode 116 is larger than the protective layer 113 and An opening in the black matrix 114 is such that the conductive spacer 117 and the common electrode 116 are insulated from each other.
  • the data line 112 is provided with a protrusion 112a (see FIG. 2) corresponding to the position of the drain 126 on the array substrate, and has the same shape as the drain 126.
  • the second end of the conductive spacer 117 is connected to the protruding portion 112a, so that the connection area of the conductive spacer 117 and the data line 112 can be increased to enhance the conductive stability.
  • the data line 112 is formed in the projection area of the black matrix 114 in the first substrate 111, so that the data line 112 and the conductive spacer 117 can be prevented from affecting the display panel.
  • the normal display in practical applications, the data line 112 may be partially disposed outside the projection area of the color matrix substrate, that is, the projection of the filter 115 on the first substrate 111. In this case, the second via hole 117b may partially pass through the filter 115 at this time. This situation may have a certain influence on the display effect of the display panel, but generally has little effect, and can ensure normal operation. display effect.
  • the array substrate includes: a second substrate 121, a gate line 122 formed on a side of the second substrate 121 adjacent to the color filter substrate, and the gate line 122 is formed near the color a gate insulating layer 123 on one side of the film substrate, an active layer 124 and a gate connection line 127 formed on a side of the gate insulating layer 123 adjacent to the color filter substrate, and the active layer 124 is formed adjacent to the color
  • a source electrode 125 and a drain electrode 126 on one side of the film substrate are formed on the side of the gate connection line 127, the source electrode 125, and the drain electrode 126 near the side of the color filter substrate, and are formed in the passivation layer.
  • the layer 128 is adjacent to the pixel electrode 129 on the side of the color filter substrate.
  • the gate insulating layer 123 is formed with a third via hole 127a corresponding to the gate line, and the gate connection line 127 is connected to the gate line 122 through the third via hole 127a, and each of the gate connections line 127 corresponds to one of the gate lines 122.
  • the gate connection line 127 is made of the same metal material as the source electrode 125 and the drain electrode 126, and the same metal material as the gate connection line 127 fills the third via hole 127a to connect the gate.
  • the gate connection line 127 and the gate line 122 are orthogonally disposed, and the gate connection line 127 and the data line 112 are disposed in parallel.
  • the gate connection line is directly disposed on the side of the second substrate near the color filter substrate, and then the second insulation layer, the gate line, and the gate insulation layer are sequentially disposed on the side of the gate connection line adjacent to the color filter substrate. And a scheme of connecting the via lines of the gate connection lines and the gate lines in the second insulating layer.
  • the embodiment by disposing the gate connection line 127 on the side of the gate insulating layer 123 close to the color filter substrate, the one-step patterning process and the reduction of the insulating layer can be reduced. , reducing production costs and increasing production efficiency.
  • the passivation layer 128 is formed with a first via 117a corresponding to the region of the drain 126, and the first end of the conductive spacer 117 is connected to the drain 126 through the first via 117a, thereby A data signal on the data line 112 is transmitted to the drain 126 via the conductive spacer 117; a fourth via 129a is formed in a region of the passivation layer 128 corresponding to the source 125, and the pixel electrode 129 The source 125 is connected through the fourth via 129a.
  • the positions of the source 125 and the drain 126 are not limited to the positions shown in the drawings, and may be replaced, for example, with each other.
  • the gate connection line 127 is disposed in the display area to reduce the width of the frame, and at the same time, the data line 112 is disposed on the color film substrate and the data line 112 is connected through the conductive spacer 117.
  • the drain electrodes 126 of the array substrate are connected, increasing the distance between the data lines 112 and the gate connection lines 127, reducing crosstalk between the data lines 112 and the gate connection lines 127, thereby reducing the width of the frame while reducing the width of the frame. , improving the display effect of the display panel and the display device.
  • Example 2 Example 2
  • FIG. 4 is a cross-sectional view of the display panel according to the second embodiment of the present invention.
  • the display panel of the embodiment is substantially the same as the display panel of the first embodiment, and the difference is that the third via hole 127a is further penetrated.
  • the passivation layer 128 is described, and the same metal material as the pixel electrode 129 fills the third via hole 127a to connect the gate line 122 and the gate connection line 127.
  • the third via hole penetrating the passivation layer 128 and the gate insulating layer 123 can be formed while forming the fourth via hole 129a on the passivation layer 128. 127a', thereby omitting the step of separately forming the third via hole on the gate insulating layer 123, reducing the one-step patterning process.
  • FIG. 5a-5h are process flowcharts of a method for fabricating a display panel according to Embodiment 3 of the present invention, as shown in FIG.
  • the method includes the steps:
  • a pattern including the data line 112 is formed on the first substrate 111.
  • a metal film of a data line is formed on the first substrate 111, and a pattern including the data line 112 is formed by a patterning process.
  • a pattern of protrusions (not shown) is formed simultaneously in a region of the data line metal film corresponding to the drain of the array substrate by a patterning process, the protrusion having the same shape as the drain.
  • the patterning process generally includes a process of photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • a protective layer film is formed on the data line 112, and a pattern including the second sub via 117c is formed in a region of the protective layer film corresponding to the data line 112 by a patterning process.
  • the second sub-via 117c is provided, for example, in a region corresponding to the protrusion.
  • a pattern including a filter 115 may be formed on the protective layer 113 in this step, and the filter 115 may include a red filter, a green filter, and a blue filter. Red filter, green filter, blue filter and white filter. This scheme is described only in the case of including a red filter, a green filter, and a blue filter, but the method is also applicable to include a red filter, a green filter, a blue filter, and a white filter. The four-color display of the light sheet will not be described here.
  • the process of forming the black matrix 114, the red color filter, the green color filter, and the blue color filter may employ an existing patterning process, for example, including a 4-step (third step to sixth step) patterning process.
  • the black matrix 114, the red color filter, the green color filter, and the blue color filter After forming the black matrix 114, the red color filter, the green color filter, and the blue color filter, forming the common electrode 116 on the black matrix 114, the red color filter, the green color filter, and the blue color filter.
  • the pattern, and the pattern including the second via 117b is formed by the seventh step patterning process. In one example, this step The second via in the middle may also partially pass through the filter 115.
  • 540 forming a pattern including a conductive spacer 117 in the second via hole 117b, the second end of the conductive spacer 117 is connected to the data line 112 through the second via hole 117b, and the conductive spacer
  • the pad 117 and the common electrode 116 are insulated from each other, thereby forming a color filter substrate.
  • a conductive spacer metal material is formed on the common electrode 116, a pattern including a conductive spacer 117 is formed by an eighth patterning process, and the second pass is performed by an eighth patterning process.
  • the opening of the hole 117b on the common electrode 116 is enlarged so that the common electrode 116 does not contact the conductive spacer 117, thereby ensuring that the conductive spacer 117 and the common electrode 116 are insulated from each other, thereby forming a color filter substrate.
  • a pattern including a gate line 122 and a gate insulating layer 123 is sequentially formed on the second substrate 121, and a pattern including the third via hole 127a is formed in a region of the gate insulating layer 123 corresponding to the gate line 122.
  • a process step of sequentially forming a pattern including the gate line 122 and the gate insulating layer 123 on the second substrate 121 may be performed by a conventional technique, for example, by forming a pattern of the gate line 122 by a first patterning process, and then A pattern including the third via hole 127a may be formed in a region of the gate insulating layer 123 corresponding to the gate line 122 by a second patterning process.
  • connection line 127 is connected to the gate line 122 through the third via hole 127a, and the gate connection line 127 and the gate line 122 are orthogonal.
  • a pattern including the active layer 124 is formed by a third patterning process, and then formed by the fourth patterning process.
  • a pattern of source 125, drain 126, and gate connection line 127 is formed by the same metal material, and the same metal material as the gate connection line 127 fills the third via. 127a, to connect the gate line 122 and the gate connection line 127.
  • 570 forming a passivation layer 128 on the source electrode 125, the drain electrode 126, and the gate connection line 127, and forming a pattern including the first via hole 117a in a region of the passivation layer 128 corresponding to the drain electrode 126.
  • the passivation layer 128 may correspond to the drain 126 through a fifth patterning process.
  • the area forms a pattern including the first via 117a.
  • a pattern including the fourth via hole 129a is further formed in a region of the passivation layer 128 corresponding to the source electrode 125 by the fifth patterning process, and a pixel including the pixel is formed on the passivation layer 128 by a sixth patterning process.
  • the pattern of the electrode 129 the specific process will not be described here. After this step is completed, an array substrate is obtained.
  • the conductive spacer As shown in FIG. 5h, after the color film substrate and the array substrate are paired with the box, the conductive spacer
  • the electrical connection of the data line 112 and the drain 126 is effected to transfer data signals from the color filter substrate to the drain 126 on the array substrate.
  • the positions of the source 125 and the drain 126 can be switched according to actual applications.
  • the array substrate requires 8 patterning processes, and the color film substrate requires 6 patterning processes.
  • the display panel described in Embodiment 1 can be prepared by a total of 14 patterning processes, and the process cartridge is prepared and prepared. The obtained display panel improves the display effect while reducing the width of the frame.
  • the method for fabricating the display panel of the embodiment is substantially the same as that of the embodiment 3, except that, as shown in FIGS. 6a to 6d, in the embodiment, the process of fabricating the array substrate is as follows:
  • the steps of the gate line 122 and the active layer 124 are respectively formed by using a conventional technique, for example, by two patterning processes, and the specific process will not be described herein.
  • 620 forming a pattern including a source electrode 125 and a drain electrode 126 on the active layer 124, forming a pattern including a gate connection line 127 on a region of the gate insulating layer 123 corresponding to the gate line 122, and The gate connection line 127 and the gate line 122 are orthogonal.
  • a pattern including the gate connection line 127 is further formed on the gate insulating layer 123 while forming a pattern including the source electrode 125 and the drain electrode 126 by one patterning process.
  • a pattern including the third via hole 127a is formed in a region of the passivation layer 128 and the gate insulating layer 123 corresponding to the gate line 122.
  • the first via 117a and the third via 127a, and the pattern of the fourth via 129a are simultaneously formed by one patterning process.
  • the fourth via 129a is formed in a region of the passivation layer 128 corresponding to the source 125.
  • the process of forming the pattern of the pixel electrode 129 in this step is substantially the same as the conventional technique, for example, using a patterning process, except that the same metal material as the pixel electrode 129 also fills the third via hole 127a. .
  • the preparation of the array substrate involves only five patterning processes. Therefore, in the embodiment, the preparation of the display panel involves 13 patterning processes in total, and the number of patterning processes is further reduced compared with the embodiment 3. The process flow reduces the cost of preparation.
  • Example 5
  • the present invention also provides a display device, which includes the display panel of any of the above embodiments, and the display device may be a liquid crystal panel, an electronic paper, an OLED panel, a plasma panel, a liquid crystal television, a liquid crystal display, Any product or component that has a display function, such as a digital photo frame, mobile phone, or tablet.
  • the gate connection line is disposed in the display area, the width of the frame is reduced, and the data line is disposed on the color film substrate and passes through the conductive spacer.
  • Connecting the data line to the drain of the array substrate increases the distance between the data line and the gate connection line, and reduces mutual crosstalk between the data line and the gate connection line, thereby reducing the width of the frame while reducing the width of the frame , improving the display effect of the display panel and the display device.

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Abstract

一种显示面板，阵列基板的栅线（122）和栅极连接线（127）正交设置；阵列基板的源极（125）或漏极（126）的靠近彩膜基板一侧形成有钝化层（128），钝化层（128）上设置有第一过孔（117a）；彩膜基板包括第一基板（111），第一基板（111）靠近阵列基板一侧形成有与栅极连接线（127）平行的数据线（112），数据线（112）靠近阵列基板一侧依次形成有保护层（113）、黑矩阵（114）和公共电极（116），保护层（113）、黑矩阵（114）和公共电极（116）在对应数据线（112）的区域设置有第二过孔（117b），导电隔垫物（117）的第一端通过第一过孔（117a）连接源极（125）或漏极（126），导电隔垫物（117）的第二端通过第二过孔（117b）连接数据线（112）。还提供了一种显示面板的制作方法及显示装置。

Description

显示面板及其制作方法和显示装置 技术领域
本发明实施例涉及显示领域， 特别涉及一种显示面板及其制作方法和显 示装置。 背景技术
传统的显示器， 由于栅线与栅线驱动电路的连接端设置在有效显示区域 的周边， 这就导致了显示器具有较宽的边框， 从而降低整个显示器的视觉效 果， 当边框的区域越大时， 视觉效果就越差。 为了解决上述问题， 现有技术 公开了一种阵列基板， 其中， 栅极连接线呈 L型， 部分栅极连接线和数据线 平行重叠设置， 并且栅极连接线与数据线之间隔着栅绝缘层。 类似于数据线 与数据线驱动电路的连接端的设置方式， 栅极连接线与栅线驱动电路的连接 端位于有效显示区域内与黑矩阵相对应的区域， 从而避免了为栅极连接线预 留较宽的边框， 减小了显示器的边框宽度。
然而该技术方案却带来了另一个问题， 该技术方案中设置在阵列基板上 的栅极连接线和数据线存在相互平行设置的部分， 虽然隔着绝缘层， 但是由 于距离较近， 栅极连接线和数据线之间的串扰现象非常严重， 从而导致显示 器的显示画面品质不佳。 发明内容
本发明实施例提供一种显示面板及其制作方法和显示装置， 在减小边框 宽度的同时， 提高显示面板及显示装置的显示效果。
根据本发明的第一方面，提供一种显示面板， 包括阵列基板和彩膜基板； 所述阵列基板的栅线和栅极连接线正交设置；
所述阵列基板的源极或漏极的靠近所述彩膜基板一侧形成有钝化层， 所 述钝化层在对应所述源极或漏极的区域设置有第一过孔；
所述彩膜基板包括第一基板， 所述第一基板靠近所述阵列基板一侧形成 有与所述栅极连接线平行的数据线， 所述数据线靠近所述阵列基板一侧依次 形成有保护层、 黑矩阵和公共电极， 所述保护层、 黑矩阵和公共电极在对应 所述数据线的区域设置有第二过孔， 所述第二过孔中设置有导电隔垫物， 所 述导电隔垫物的第一端通过所述第一过孔连接所述源极或漏极， 所述导电隔 垫物的第二端通过所述第二过孔连接所述数据线， 并且所述导电隔垫物与所 述公共电极绝缘设置。
根据本发明的第二方面， 还提供一种显示装置， 所述显示装置包括所述 的显示面板。
根据本发明的第三方面， 还提供一种显示面板制作方法， 该方法包括： 在第一基板上形成包括数据线的图形；
在所述数据线上形成保护层， 在所述保护层对应所述数据线的区域形成 包括第二子过孔的图形；
在所述保护层上依次形成包括黑矩阵和公共电极的图形， 在所述黑矩阵 和公共电极对应所述第二子过孔处形成包括第二过孔的图形；
在所述第二过孔中形成包括导电隔垫物的图形， 所述导电隔垫物的第二 端通过所述第二过孔连接所述数据线， 并且所述导电隔垫物和所述公共电极 绝缘设置， 由此形成彩膜基板；
形成阵列基板， 所述阵列基板的栅线和栅极连接线正交设置， 所述阵列 基板的钝化层对应源极或漏极的区域形成有第一过孔；
将所述彩膜基板和所述阵列基板对盒， 所述导电隔垫物的第一端通过所 述第一过孔连接所述源极或漏极， 所述栅极连接线和所述数据线平行设置。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1是本发明实施例 1所述的显示面板的剖视图；
图 2是本发明实施例 1所述显示面板的彩膜基板的平面示意图； 图 3是本发明实施例 1所述显示面板的阵列基板的平面示意图； 图 4是本发明实施例 2所述显示面板的剖视图；
图 5a~5h是本发明实施例 3所述显示面板制作方法工艺流程图； 图 6a~6d是本发明实施例 4所述阵列基板制作方法工艺流程图。
附图标记列表：
111-第一基板， 112-数据线， 112a-突出部， 113-保护层， 114-黑矩阵， 115- 滤光片， 116-公共电极， 117-导电隔垫物， 117a-第一过孔， 117b-第二过孔， 117c-第二子过孔， 121-第二基板， 122-栅线， 123-栅绝缘层， 124-有源层， 125-源极， 126-漏极， 127-栅极连接线， 127a、 127a' -第三过孔， 128-钝化 层， 129-像素电极， 129a-第四过孔。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 或者 "一" 等类似词语也不表示数量限制，而是表示存在至少一个。 "包括"或者 "包含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵盖出 现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排除其 他元件或者物件。 "连接"或者 "相连"等类似的词语并非限定于物理的或者 机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置 改变后， 则该相对位置关系也可能相应地改变。 实施例 1
图 1是本发明实施例 1提供的显示面板的剖视图， 所述显示面板包括彩 膜基板和阵列基板。 图 2是本发明实施例 1所述显示面板的彩膜基板的平面 示意图， 图 3是本发明实施例 1所述显示面板的阵列基板的平面示意图。 参见图 1和图 2, 所述彩膜基板包括： 第一基板 111 , 形成在所述第一基 板 111靠近所述阵列基板一侧的数据线 112, 形成在所述数据线靠近所述阵 列基板一侧的保护层 113 , 形成在所述保护层 113靠近所述阵列基板一侧的 黑矩阵 114和滤光片 115, 形成在所述黑矩阵 114和滤光片 115靠近所述阵 列基板一侧的公共电极 116。
所述保护层 113、 黑矩阵 114和公共电极 116对应所述数据线 112的区 域形成有第二过孔 117b。 导电隔垫物 117的第二端穿过所述第二过孔 117b 连接所述数据线 112, 并且所述第二过孔 117b在所述公共电极 116上的开口 大于在所述保护层 113和黑矩阵 114上的开口， 从而使所述导电隔垫物 117 与所述公共电极 116之间相互绝缘。
在一个示例中， 所述数据线 112上设置有突出部 112a (见图 2 ), 所述突 出部 112a对应于所述阵列基板上漏极 126的位置，形状与所述漏极 126相同。 所述导电隔垫物 117的第二端连接所述突出部 112a, 从而可以增大所述导电 隔垫物 117和所述数据线 112的连接面积， 增强导电稳定性。
本实施例中，所述数据线 112形成在所述黑矩阵 114在所述第一基板 111 的投影区域内， 从而可以避免所述数据线 112和所述导电隔垫物 117影响所 述显示面板的正常显示。 另外， 实际应用中， 所述数据线 112也可以部分设 置于所述黑矩阵 114在所述彩膜基板的投影区域外，即设置在所述滤光片 115 在所述第一基板 111的投影区域内，此时所述第二过孔 117b还可能会部分穿 过所述滤光片 115 , 这种情况虽然会对显示面板的显示效果有一定影响， 但 是一般影响不大， 能够保证正常的显示效果。
参见图 1和图 3 , 所述阵列基板包括： 第二基板 121 , 形成在所述第二基 板 121靠近所述彩膜基板一侧的栅线 122, 形成在所述栅线 122靠近所述彩 膜基板一侧的栅绝缘层 123 , 形成在所述栅绝缘层 123靠近所述彩膜基板一 侧的有源层 124和栅极连接线 127, 形成在所述有源层 124靠近所述彩膜基 板一侧的源极 125和漏极 126,形成在所述栅极连接线 127、源极 125和漏极 126靠近所述彩膜基板一侧的钝化层 128,形成在所述钝化层 128靠近所述彩 膜基板一侧的像素电极 129。
所述栅绝缘层 123对应所述栅线的区域形成有第三过孔 127a,所述栅极 连接线 127通过所述第三过孔 127a连接所述栅线 122,每个所述栅极连接线 127对应一个所述栅线 122。所述栅极连接线 127采用与所述源极 125和漏极 126相同的金属材料， 并且与所述栅极连接线 127相同的金属材料填充所述 第三过孔 127a, 以连接所述栅极连接线 127和所述栅线 122。 所述栅极连接 线 127和所述栅线 122正交设置，并且所述栅极连接线 127和所述数据线 112 平行设置。
另外， 现有技术中也有将栅极连接线直接设置在第二基板靠近彩膜基板 一侧， 然后在栅极连接线靠近彩膜基板一侧依次设置第二绝缘层、 栅线和栅 绝缘层， 并在第二绝缘层设置连接栅极连接线和栅线的过孔的方案。 相比于 该现有方案，本实施例中通过将所述栅极连接线 127设置于所述栅绝缘层 123 靠近所述彩膜基板一侧， 可以减少一步构图工艺以及减少设置一层绝缘层， 降低了生产成本， 提高了生产效率。
所述钝化层 128对应所述漏极 126的区域形成有第一过孔 117a, 所述导 电隔垫物 117的第一端通过所述第一过孔 117a连接所述漏极 126, 从而将数 据线 112上的数据信号经所述导电隔垫物 117传输至所述漏极 126; 所述钝 化层 128对应所述源极 125的区域形成有第四过孔 129a, 所述像素电极 129 通过所述第四过孔 129a连接所述源极 125。所述源极 125和漏极 126的位置 不限于图中所示的位置， 例如可以互相替换。
本实施例所述显示面板， 将栅极连接线 127设置在显示区域内， 减小了 边框宽度， 同时， 将数据线 112设置在彩膜基板上并通过导电隔垫物 117将 数据线 112和阵列基板的漏极 126连接，增加了数据线 112与栅极连接线 127 之间的距离， 减小了数据线 112与栅极连接线 127之间的相互串扰， 从而在 减小边框宽度的同时， 提高了显示面板及显示装置的显示效果。 实施例 2
图 4是本发明实施例 2所述显示面板的剖视图， 本实施例所述显示面板 与实施例 1所述显示面板基本相同， 其不同之处在于， 所述第三过孔 127a， 还贯穿所述钝化层 128, 并且与所述像素电极 129相同的金属材料填充所述 第三过孔 127a， 以连接所述栅线 122和所述栅极连接线 127。
通过采用本实施例 2的结构， 可以在所述钝化层 128上形成所述第四过 孔 129a 的同时形成贯穿所述钝化层 128 和所述栅绝缘层 123 的第三过孔 127a' ,从而省略了单独在所述栅绝缘层 123上形成第三过孔的步骤，减少了 一步构图工艺。 实施例 3
图 5a~5h是本发明实施例 3 所述显示面板制作方法工艺流程图， 如图
5a~5h所示， 该方法包括步骤：
510: 在第一基板 111上形成包括数据线 112的图形。
如图 5a所示，在所述第一基板 111上形成数据线金属薄膜，通过构图工 艺形成包括数据线 112的图形。 在一个示例中， 在所述数据线金属薄膜对应 阵列基板漏极的区域通过构图工艺同时形成突出部（未示出） 的图形， 所述 突出部的形状与漏极相同。 其中， 所述构图工艺通常包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺。
520: 在所述数据线 112上形成保护层 113, 在所述保护层 113对应所述 数据线 112的区域形成包括第二子过孔 117c的图形。
如图 5b所示，在所述数据线 112上形成保护层薄膜，通过构图工艺在所 述保护层薄膜对应所述数据线 112的区域形成包括第二子过孔 117c的图形。 所述第二子过孔 117c例如设置在所述突出部对应的区域。
530:在所述保护层 113上依次形成包括黑矩阵 114和公共电极 116的图 形，在所述黑矩阵 114和公共电极 116对应所述第二子过孔 117c处形成包括 第二过孔 117b的图形。
如图 5c所示，本步骤中在所述保护层 113上还形成包括滤光片 115的图 形， 所述滤光片 115可以包括红色滤光片、 绿色滤光片和蓝色滤光片或红色 滤光片、 绿色滤光片、 蓝色滤光片和白色滤光片。 本方案仅以包括红色滤光 片、 绿色滤光片和蓝色滤光片的情形进行说明， 但该方法同样适用于包括红 色滤光片、 绿色滤光片、 蓝色滤光片和白色滤光片的四色显示， 在此不再赘 述。 形成所述黑矩阵 114、 红色滤光片、 绿色滤光片、 蓝色滤光片的工艺过 程可采用现有的构图工艺， 例如包括 4步（第三步至第六步）构图工艺。 形 成黑矩阵 114、红色滤光片、绿色滤光片、蓝色滤光片后，在所述黑矩阵 114、 红色滤光片、 绿色滤光片、 蓝色滤光片上形成包括公共电极 116的图形， 并 通过第七步构图工艺形成包括第二过孔 117b的图形。在一个示例中，本步骤 中的所述第二过孔还可以部分穿过所述滤光片 115。
540: 在所述第二过孔 117b中形成包括导电隔垫物 117的图形， 所述导 电隔垫物 117的第二端通过所述第二过孔 117b连接所述数据线 112, 并且导 电隔垫物 117和所述公共电极 116绝缘设置， 至此形成彩膜基板。
如图 5d所示，在所述公共电极 116上形成导电隔垫物金属材料，通过第 八次构图工艺形成包括导电隔垫物 117的图形， 并且通过第八次构图工艺将 所述第二过孔 117b在所述公共电极 116上的开口扩大， 以使公共电极 116 不接触导电隔垫物 117, 从而保证导电隔垫物 117和所述公共电极 116绝缘 设置， 至此形成彩膜基板。
550: 在第二基板 121上依次形成包括栅线 122和栅绝缘层 123的图形， 在所述栅绝缘层 123对应所述栅线 122的区域中形成包括第三过孔 127a的图 形。
如图 5e所示，在所述第二基板 121上依次形成包括栅线 122和栅绝缘层 123 的图形的工艺步骤可采用常规技术， 例如通过第一次构图工艺形成栅线 122的图形， 然后， 通过第二次构图工艺可以在所述栅绝缘层 123对应所述 栅线 122的区域中形成包括第三过孔 127a的图形。
560: 在所述栅绝缘层 123上依次形成包括有源层 124、 源极 125和漏极 126的图形， 在所述栅绝缘层 123上形成包括栅极连接线 127的图形， 所述 栅极连接线 127通过所述第三过孔 127a连接所述栅线 122, 并且所述栅极连 接线 127和所述栅线 122正交。
如图 5f所示， 在所述栅绝缘层 123上对应所述栅线 122的栅极的区域， 通过第三次构图工艺形成包括有源层 124的图形， 然后通过第四次构图工艺 形成包括源极 125、 漏极 126和栅极连接线 127的图形。 也就是说， 所述栅 极连接线 127和所述源极 125、 漏极 126采用相同的金属材料刻蚀得到， 并 且与所述栅极连接线 127相同的金属材料填充所述第三过孔 127a, 以连接所 述栅线 122和所述栅极连接线 127。
570: 在所述源极 125、 漏极 126和栅极连接线 127上形成钝化层 128, 在所述钝化层 128对应所述漏极 126的区域中形成包括第一过孔 117a的图 形。
如图 5g所示，通过第五次构图工艺可以在钝化层 128对应所述漏极 126 的区域形成包括第一过孔 117a的图形。 另外，通过第五次构图工艺还在钝化 层 128对应所述源极 125的区域形成包括第四过孔 129a的图形，以及通过第 六次构图工艺在所述钝化层 128上形成包括像素电极 129的图形， 具体工艺 过程在此不再赘述。 本步骤完成后， 得到阵列基板。
580: 将所述彩膜基板和所述阵列基板对盒，所述导电隔垫物 117的第一 端通过所述第一过孔 117a连接所述漏极 126, 所述栅极连接线 127和所述数 据线 112平行设置。
如图 5h所示， 所述彩膜基板和所述阵列基板对盒后， 所述导电隔垫物
117实现所述数据线 112和所述漏极 126的电连接， 从而将数据信号从彩膜 基板传输至阵列基板上的漏极 126。 本实施例中， 所述源极 125和漏极 126 的位置可以根据实际应用进行调换。
本实施例所述方法， 阵列基板需要 8次构图工艺， 彩膜基板需要 6次构 图工艺，通过共计 14次构图工艺即可制备得到实施例 1所述的显示面板，工 艺过程筒单， 并且制备得到的显示面板在减小边框宽度的同时， 提高了显示 效果。 实施例 4
本实施例的显示面板制作方法与实施例 3所述方法基本相同， 其不同之 处仅在于， 如图 6a~6d所示， 本实施例中， 阵列基板的制作过程如下：
610: 在第二基板 121上依次形成包括栅线 122、栅绝缘层 123和有源层
124的图形。
如图 6a所示，本步骤可采用常规技术，例如通过两次构图工艺分别形成 栅线 122和有源层 124的图形， 具体工艺过程在此不再赘述。
620:在所述有源层 124上形成包括源极 125和漏极 126的图形，在所述 栅绝缘层 123上对应所述栅线 122的区域形成包括栅极连接线 127的图形， 并且所述栅极连接线 127和所述栅线 122正交。
如图 6b所示，本步骤中，通过一次构图工艺在形成包括源极 125和漏极 126的图形同时，在所述栅绝缘层 123上还形成包括栅极连接线 127的图形。
630: 在所述源极 125、 漏极 126和栅极连接线 127上形成钝化层 128, 在所述钝化层 128和所述栅绝缘层 123对应所述栅线 122的区域形成包括第 三过孔 127a， 的图形。
如图 6c所示， 本步骤中利用一次构图工艺同时形成第一过孔 117a和第 三过孔 127a，， 以及第四过孔 129a的图形。 所述第四过孔 129a形成在所述 钝化层 128对应所述源极 125的区域。
640:在所述钝化层 128上形成包括像素电极 129的图形，与所述像素电 极 129相同的金属材料填充所述第三过孔 127a， 以连接所述栅线 122和栅极 连接线 127。
本步骤中形成所述像素电极 129的图形的过程与常规技术基本相同， 例 如采用一次构图工艺， 不同之处在于， 与所述像素电极 129相同的金属材料 还填充所述第三过孔 127a，。
本实施例中， 阵列基板的制备仅涉及 5次构图工艺， 因此， 本实施例中， 显示面板的制备共涉及 13次构图工艺， 相比实施例 3, 进一步减少了构图工 艺的次数， 筒化了工艺流程， 降低了制备成本。 实施例 5
本发明还提供一种显示装置， 所述显示装置包括上述任一实施例所述的 显示面板， 所述显示装置可以是液晶面板、 电子纸、 OLED面板、 等离子体 面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等任何具有显示 功能的产品或部件。 本发明以上实施例所述显示面板及其制作方法和显示装置， 将栅极连接 线设置在显示区域内， 减小了边框宽度， 同时， 将数据线设置在彩膜基板上 并通过导电隔垫物将数据线和阵列基板的漏极连接， 增加了数据线与栅极连 接线之间的距离， 减小了数据线与栅极连接线之间的相互串扰， 从而在减小 边框宽度的同时， 提高了显示面板及显示装置的显示效果。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种显示面板， 包括阵列基板和彩膜基板；
所述阵列基板的栅线和栅极连接线正交设置；
所述阵列基板的源极或漏极的靠近所述彩膜基板一侧形成有钝化层， 所 述钝化层在对应所述源极或漏极的区域设置有第一过孔；
所述彩膜基板包括第一基板， 所述第一基板靠近所述阵列基板一侧形成 有与所述栅极连接线平行的数据线， 所述数据线靠近所述阵列基板一侧依次 形成有保护层、 黑矩阵和公共电极， 所述保护层、 黑矩阵和公共电极在对应 所述数据线的区域设置有第二过孔， 所述第二过孔中设置有导电隔垫物， 所 述导电隔垫物的第一端通过所述第一过孔连接所述源极或漏极， 所述导电隔 垫物的第二端通过所述第二过孔连接所述数据线， 并且所述导电隔垫物与所 述公共电极绝缘设置。
2、如权利要求 1所述的显示面板，其中所述栅线形成在所述阵列基板的 第二基板靠近所述彩膜基板一侧， 所述栅线靠近所述彩膜基板一侧形成有栅 绝缘层， 所述栅绝缘层靠近所述彩膜基板一侧形成有所述栅极连接线、 源极 和漏极；
所述栅绝缘层上形成有第三过孔， 所述栅极连接线通过所述第三过孔连 接所述栅线。
3、如权利要求 1或 2所述的显示面板，其中所述栅极连接线形成在所述 黑矩阵在所述第二基板的投影区域内， 所述数据线形成在所述黑矩阵在所述 第一基板的投影区域内。
4、如权利要求 1至 3任意一项所述的显示面板，其中所述彩膜基板的滤 光片与所述黑矩阵同层设置， 所述第二过孔还穿过所述滤光片。
5、如权利要求 1至 4任意一项所述的显示面板，其中所述数据线上形成 有突出部， 所述突出部的位置与所述源极或漏极的位置相对应， 并且所述突 出部连接所述导电隔垫物的第二端。
6、如权利要求 1至 5任意一项所述的显示面板，其中所述栅极连接线与 所述源极或漏极的材料相同。
7、如权利要求 1至 6任意一项所述的显示面板，其中所述第二过孔在所 述公共电极上的开口被扩大以使第二过孔中的导电隔垫物不接触公共电极。
8、 一种显示装置， 包括如权利要求 1-7任意一项所述的显示面板。
9、 一种显示面板制作方法， 包括：
在第一基板上形成包括数据线的图形；
在所述数据线上形成保护层， 在所述保护层对应所述数据线的区域形成 包括第二子过孔的图形；
在所述保护层上依次形成包括黑矩阵和公共电极的图形， 在所述黑矩阵 和公共电极对应所述第二子过孔处形成包括第二过孔的图形；
在所述第二过孔中形成包括导电隔垫物的图形， 所述导电隔垫物的第二 端通过所述第二过孔连接所述数据线， 并且所述导电隔垫物和所述公共电极 绝缘设置， 由此形成彩膜基板；
形成阵列基板， 所述阵列基板的栅线和栅极连接线正交设置， 所述阵列 基板的钝化层对应源极或漏极的区域形成有第一过孔；
将所述彩膜基板和所述阵列基板对盒， 所述导电隔垫物的第一端通过所 述第一过孔连接所述源极或漏极， 所述栅极连接线和所述数据线平行设置。
10、 如权利要求 9所述的显示面板制作方法， 其中所述形成阵列基板包 括：
在第二基板上依次形成包括栅线和栅绝缘层的图形， 在所述栅绝缘层对 应所述栅线的区域中形成包括第三过孔的图形；
在所述栅绝缘层上依次形成包括有源层、 源极和漏极的图形， 在所述栅 绝缘层上形成包括栅极连接线的图形， 所述栅极连接线通过所述第三过孔连 接所述栅线， 并且所述栅极连接线和所述栅线正交；
在所述源极、 漏极和栅极连接线上形成钝化层， 在所述钝化层对应所述 源极或漏极的区域中形成包括第一过孔的图形。
11、 如权利要求 9所述的显示面板制作方法， 其中所述形成阵列基板包 括：
在第二基板上依次形成包括栅线、 栅绝缘层和有源层的图形； 在所述有源层上形成包括源极和漏极的图形， 在所述栅绝缘层上对应所 述栅线的区域形成包括栅极连接线的图形， 并且所述栅极连接线和所述栅线 正交； 在所述源极、 漏极和栅极连接线上形成钝化层， 在所述钝化层对应所述 源极或漏极的区域形成包括第一过孔的图形， 在所述钝化层和所述栅绝缘层 对应所述栅线的区域形成包括第三过孔的图形；
在所述钝化层上形成包括像素电极的图形， 与所述像素电极相同的金属 材料填充所述第三过孔以连接所述栅线和栅极连接线。
12、如权利要求 9至 11任意一项所述的显示面板制作方法，其中在形成 所述彩膜基板时， 在所述保护层上还形成与所述黑矩阵同层设置的滤光片的 图形， 所述第二过孔还穿过所述滤光片。
13、如权利要求 9至 12任意一项所述的显示面板制作方法，其中所述数 据线上形成有突出部， 所述突出部的位置与所述源极或漏极的位置相对应， 并且所述突出部连接所述导电隔垫物的第二端。
14、如权利要求 9至 13任意一项所述的显示面板制作方法，其中所述栅 极连接线与所述源极或漏极的材料相同。
15、如权利要求 9至 14任意一项所述的显示面板制作方法，其中所述第 二过孔在所述公共电极上的开口被扩大以使第二过孔中的导电隔垫物不接触 公共电极。
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