WO2015001603A1 - Circuit d'excitation d'élément de commutation à semi-conducteurs, et dispositif de conversion de puissance utilisant ledit circuit - Google Patents

Circuit d'excitation d'élément de commutation à semi-conducteurs, et dispositif de conversion de puissance utilisant ledit circuit Download PDF

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Publication number
WO2015001603A1
WO2015001603A1 PCT/JP2013/068039 JP2013068039W WO2015001603A1 WO 2015001603 A1 WO2015001603 A1 WO 2015001603A1 JP 2013068039 W JP2013068039 W JP 2013068039W WO 2015001603 A1 WO2015001603 A1 WO 2015001603A1
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WIPO (PCT)
Prior art keywords
gate
switching element
semiconductor switching
source voltage
drive circuit
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PCT/JP2013/068039
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English (en)
Japanese (ja)
Inventor
かおる 加藤
石川　勝美
歩 畑中
秋山　悟
貴史 小川
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株式会社日立製作所
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Priority to JP2015524923A priority Critical patent/JPWO2015001603A1/ja
Priority to PCT/JP2013/068039 priority patent/WO2015001603A1/fr
Priority to TW103121353A priority patent/TWI538365B/zh
Publication of WO2015001603A1 publication Critical patent/WO2015001603A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches

Definitions

  • the present invention is suitable for a driving circuit of a semiconductor switching element, particularly for a junction field effect transistor (Junction Field Effect Transistor: hereinafter abbreviated as JFET) or an electrostatic induction transistor (Static Induction Transistor: hereinafter abbreviated as SIT).
  • JFET Junction Field Effect Transistor
  • SIT Static Induction Transistor
  • SiC-JFET unipolar SiC junction field effect transistor
  • Patent Document 1 As a technique related to a drive circuit for switching and driving such a SiC-JFET, a technique described in Patent Document 1 is known.
  • a gate drive voltage for turning on is applied between the gate and the source of the SiC-JFET through two resistors connected in series.
  • a MOSFET is connected in parallel to one of the two resistors.
  • the MOSFET is turned off at room temperature (25 ° C.) and turned on at a high temperature (250 ° C.).
  • the SiC-JFET can be operated in a bipolar manner to reduce the on-resistance.
  • Equation (1) When the switching element is conducting, the conduction loss P Rds generated from the on-resistance R ds is generally expressed by the equation shown in Equation (1).
  • a and I d are a constant and a drain current, respectively.
  • the gate layer and the source layer form a pn junction, and the current / voltage characteristics between the gate and the source show forward diode characteristics when conducting. Accordingly, as shown in FIG. 2 (b), the gate current I G in proportion to the gate-source voltage V GS increases.
  • the gate loss P Ig of formula (2) is a JFET In case it cannot be ignored.
  • V G is a gate drive voltage generated by the drive circuit.
  • Equation (3) the conduction loss P loss_on is expressed by Equation (3).
  • P Loss_on unlike P Rds made smaller as increasing the gate voltage V GS, the loss becomes minimum at a certain gate voltage. Therefore, P Ig is small but compared with P Rds, it can not be ignored in P loss_on. Furthermore, minimum point P Loss_on, since there is a temperature dependence P Rds and P Ig constituting the P Loss_on, varies depending on the temperature.
  • Patent Document 1 has a problem that it is difficult to reliably reduce the conduction loss of the SiC-JFET.
  • the present invention provides a drive circuit capable of reliably reducing loss during conduction of a unipolar semiconductor switching element having a pn junction between a gate and a source such as a SiC-JFET, and an inverter device using the drive circuit. .
  • the semiconductor switching element drive circuit of the present invention is a semiconductor switching element drive circuit that is connected to the gate of a unipolar semiconductor switching element having a pn junction between the gate and the source and drives the semiconductor switching element on and off.
  • An on-drive circuit section for applying a gate-source voltage between the gate and source of the semiconductor switching element when the semiconductor switching element is conductive, and a current detection means for detecting a main circuit current flowing through the semiconductor switching element
  • gate-source voltage control means for changing the gate-source voltage according to the value of the main circuit current detected by the current detection means when the semiconductor switching element is conductive.
  • the power converter of the present invention includes a series connection circuit in which unipolar first and second semiconductor switching elements each having a pn junction between a gate and a source are connected in series, for the number of AC phases, and the series connection First and second DC terminals connected to respective terminals of the circuit, AC terminals consisting of interconnection points of the first and second semiconductor switching elements, and gates of the first and second semiconductor switching circuits, respectively.
  • a power conversion device comprising two drive circuits, wherein the first drive circuit has a gate-source connection between the gate and source of the first semiconductor switching element when the first semiconductor switching element is conductive.
  • the first on-driving circuit section for applying a voltage and the second driving circuit are configured such that the second semiconductor switching element is turned on when the second semiconductor switching element is conductive.
  • a second ON driving circuit for applying a gate-source voltage between the gate and source of the switching element, current detection means for detecting a main circuit current flowing through the semiconductor switching element, and the first semiconductor switching When the element is turned on, the gate-source voltage of the first semiconductor switching element is changed according to the value of the main circuit current detected by the current detection means, and the second semiconductor switching element is turned on.
  • a gate-source voltage control means for changing a gate-source voltage of the second semiconductor switching element according to a value of the main circuit current detected by the current detection means.
  • the present invention it is possible to reduce power loss including gate loss, which occurs when a unipolar semiconductor switching element having a pn junction between the gate and the source is conductive. Furthermore, the power loss which a power converter device generate
  • FIG. 1 shows a driving circuit for a semiconductor switching element according to a first embodiment.
  • An example of the relationship between on-resistance and gate voltage is shown.
  • An example of the relationship between gate current and gate voltage is shown.
  • An example of the relationship between conduction loss and gate loss and gate voltage is shown.
  • An example of the relationship between loss during conduction and gate voltage is shown.
  • movement waveform in a 1st Example is shown.
  • the drive circuit of the semiconductor switching element which is a 2nd Example is shown.
  • movement waveform in a 2nd Example is shown.
  • movement waveform in a 2nd Example is shown.
  • movement waveform in a 2nd Example is shown.
  • movement waveform in a 2nd Example is shown.
  • the power converter device which is a 3rd Example is shown.
  • the power converter device which is a 4th Example is shown.
  • a driving circuit is a driving circuit for a semiconductor switching element that drives an on / off of a unipolar semiconductor switching element having a pn junction between a gate and a source.
  • the gate-source voltage is changed according to the value. As a result, loss during conduction including loss due to on-resistance and gate loss can be reduced.
  • One embodiment of the present invention is a drive circuit for a semiconductor switching element that is connected to the gate of a unipolar semiconductor switching element having a pn junction between the gate and the source and drives the semiconductor switching element on and off.
  • This drive circuit includes an on-drive circuit section that applies a gate-source voltage between the gate and source of the semiconductor switching element and a current that detects a main circuit current flowing through the semiconductor switching element when the semiconductor switching element is conductive. Detection means; and gate-source voltage control means for changing the gate-source voltage in accordance with the value of the main circuit current detected by the current detection means when the semiconductor switching element is conductive.
  • the gate-source voltage is preferably changed so that the sum of the power loss caused by the on-resistance of the semiconductor switching element and the power loss caused by the gate current is within a minimum range with respect to the main circuit current. . Thereby, the loss at the time of conduction
  • the semiconductor switching element is a unipolar semiconductor switching element having a pn junction between the gate and the source, such as the above-described JFET or SIT.
  • constituent material of the semiconductor switching element may be not only a wide gap semiconductor such as SiC but also silicon.
  • FIG. 1 shows a driving circuit for a semiconductor switching element according to a first embodiment of the present invention.
  • the main circuit element in this embodiment and other embodiments described later is an SiC-JFET, but is simply referred to as JFET.
  • the main circuit 100 includes a gate resistor 105a connected between the gates of JFET101 and JFET101, which are switching elements, and an output of a gate drive circuit 110 described later, a speed-up capacitor 105b connected in parallel to the gate resistor 105a, and the JFET101.
  • a current transformer 108a that detects the flowing main circuit current and a temperature detection circuit 108b that detects the temperature of the JFET 101 are configured.
  • a driving circuit 110 that drives the JFET 101 on and off is connected to the gate of the JFET 101 via a gate resistor 105a and a speed-up capacitor 105b.
  • the drive circuit 110 has an npn transistor 114 that outputs a gate drive voltage for turning on to an emitter, with a collector connected to the gate power supply 117 for turn-on via a gate power supply 117 for turn-on and a gate resistor 113a.
  • a gate resistance switching pMOS 112a is connected in parallel to the gate resistance 113a. When the pMOS 112a is turned on, both ends of the gate resistance 113a are short-circuited.
  • the drive circuit 110 has a collector connected to the off-gate power source 118 via the off-gate power source 118 and the gate resistor 116 as an off-drive circuit unit, and outputs a gate drive voltage for off to the emitter. 115.
  • the drive circuit 110 When the npn transistor 114 and the pnp transistor 115 are complementarily driven by the drive logic circuit 111, the drive circuit 110 outputs gate drive voltages for on and off. Further, the gate-source voltage control circuit 109 provides a gate resistance switching signal to the pMOS 112a based on the main circuit current detected by the current transformer 108a and the temperature of the JFET 101 detected by the temperature detection circuit 108b. The total resistance value of the gate resistance connected between the JFET 101 and the on-gate power supply 117, that is, the effective gate resistance value in the on-drive circuit unit of the drive circuit 110 is controlled. In this embodiment, the gate resistance value is controlled to be either a resistance value corresponding to the on-resistance of the pMOS 112a or a resistance value of the gate resistance 113a, which is sufficiently smaller than the gate resistance 113a.
  • the gate resistance value for turning on is switched based on the main circuit current and the temperature of the JFET 101. Accordingly, have the property of gate current I G is proportional to the voltage V GS between the gate and the source, and the on-resistance R ds by conduction losses P Rds is JFET101 is generated having a characteristic which is proportional to the square of the main circuit current The loss during conduction including the gate loss can be reduced to a minimum value or a value close thereto.
  • the main circuit current detected by the current transformer 108a is smaller than a preset current reference value I 0 (see FIG. 5), and the temperature of the JFET 101 detected by the temperature detection circuit 108b is preset.
  • the gate-source voltage control circuit 109 transmits an off control signal to the pMOS 112a.
  • the gate resistor 113a is not short-circuited. Therefore, the effective gate resistance value between the gate of the JFET 101 and the on-gate power supply 117 is the sum of the resistance values of the gate resistance 105a and the gate resistance 113a.
  • the gate-source voltage control circuit 109 When the detected main circuit current is larger than the current reference value (approximately 1 ⁇ 2 or more of the rated value) and the detected temperature is lower than the temperature reference value, the gate-source voltage control circuit 109 is turned off to the pMOS 112a. A control signal for transferring from ON to ON is transmitted. At this time, since the pMOS 112a is turned on, the gate resistor 113a is short-circuited. For this reason, the effective gate resistance value becomes substantially equal to the resistance value of the gate resistance 105a and becomes smaller. Therefore, the voltage value shared by the gate resistance in the gate drive voltage is reduced, and the voltage value applied between the gate and source of the JFET 101 can be increased accordingly.
  • a shunt resistor or a JFET with a current sensing function may be used to detect the main circuit current. Further, the location where the main circuit current is detected may be on the drain side of the JFET 101 in addition to the source side of the JFET 101 as in this embodiment. Further, as the main circuit current detection means, the main circuit current value may be calculated from the load factor monitored by the control system during power supply operation, such as a server power supply. On the other hand, as the temperature detection circuit 108b, for example, a circuit using a temperature detection element such as a thermistor can be used.
  • FIG. 5 shows operation waveforms in this embodiment.
  • the drain current of the JFET 101 that is, the main circuit current, the ON / OFF state of the gate resistance switching pMOS 112a, the ON resistance of the JFET 101, the gate current, and the loss during conduction are shown from the top.
  • the conduction loss shown here is the sum of the conduction loss caused by the on-resistance of the JFET 101 and the gate loss caused by the gate current (the same applies to FIGS. 7 and 8 described later).
  • the on-resistance can be reduced, Also, the increase in gate current can be suppressed to a constant value. Thereby, the loss at the time of conduction
  • FIG. 5 shows, as a reference example, the operation waveform in a case where a larger gate current than that of the present embodiment is passed by a one-dot chain line.
  • the gate current is increased, the on-resistance is reduced, but the gate loss is increased, so that the conduction loss is larger than that of the present example and the conventional example.
  • the speed-up capacitor 105b by providing the speed-up capacitor 105b, the influence of the change in the gate resistance value on the JFET switching characteristics such as the turn-on characteristic and the turn-off characteristic can be reduced. For this reason, even if the value of the gate resistance changes, it is possible to drive at high speed without changing the switching speed and to suppress an increase in switching loss.
  • FIG. 6 shows a driving circuit for a semiconductor switching element according to the second embodiment of the present invention.
  • the same components as those in the first embodiment are denoted by the same symbols.
  • the gate resistance is switched in three stages. For this reason, in the ON drive circuit section of the drive circuit 110 that drives the JFET 101, a series connection circuit of the gate resistance switching pMOS 112b and the gate resistance 113b is further connected in parallel to the gate resistance 113a.
  • the gate resistance is switched in three stages. However, by increasing the number of gate resistance switching pMOS and gate resistance series-connected circuits connected in parallel to the gate resistance 113a, the gate resistance can be changed in four or more stages. You can also switch.
  • FIG. 7 shows operation waveforms of the second embodiment.
  • the drain current of the JFET 101 that is, the main circuit current
  • the on / off state of the gate resistance switching pMOS 112a the on / off state of the gate resistance switching pMOS 112b
  • the on resistance of the JFET 101 the gate current, and the conduction loss are shown. .
  • the gate-source voltage control circuit 109 transmits the respective off control signal to pMOS112a and PMOS112b.
  • the effective gate resistance value is the sum of the resistance values of the gate resistance 105a and the gate resistance 113a, and is the largest resistance value in the three stages. For this reason, the voltage applied between the gate and the source of the JFET 101 is the smallest.
  • the gate-source voltage control circuit 109 keeps the pMOS 112a in the off state and the pMOS 112b A control signal for transferring the signal from OFF to ON is transmitted.
  • the effective gate resistance value is the sum of the parallel resistance value of the gate resistance 113a and the gate resistance 113b and the resistance value of the gate resistance 105a. It becomes the second largest resistance value in three stages. Therefore, the voltage applied between the gate and source of JFET 101 is slightly increased. As a result, the on-resistance is reduced and the gate current is also suppressed, so that loss during conduction can be reduced.
  • the gate-source connection transmits control signals for shifting the pMOS 112a from off to on and the pMOS 112b from on to off.
  • the effective gate resistance value becomes the resistance value of the gate resistance 105a, which is the smallest among the three stages.
  • the voltage applied between the gate and the source of JFET 101 is maximized, and the gate-source voltage value that suppresses the sum of the conduction loss caused by the on-resistance and the gate loss caused by the gate current to a minimum or close to the minimum is obtained. Reduced.
  • FIG. 8 shows another operation waveform in the second embodiment. From the top, the drain current of the JFET 101, that is, the main circuit current, the detection temperature of the JFET, the on / off state of the gate resistance switching pMOS 112a, the on / off state of the gate resistance switching pMOS 112b, the on resistance of the JFET 101, the gate current, Indicates loss during conduction.
  • the source voltage control circuit 109 transmits an off control signal to each of the pMOS 112a and the pMOS 112b.
  • the effective gate resistance value is the sum of the resistance values of the gate resistance 105a and the gate resistance 113a, which is the largest resistance value among the three stages. For this reason, the voltage applied between the gate and the source of the JFET 101 is the smallest.
  • the gate-source voltage control circuit 109 keeps the pMOS 112a off and the pMOS 112b is turned off. Transmits a control signal for turning on.
  • the effective gate resistance value is the sum of the parallel resistance value of the gate resistance 113a and the gate resistance 113b and the resistance value of the gate resistance 105a. It becomes the second largest resistance value in three stages. Therefore, the voltage applied between the gate and source of JFET 101 is slightly increased. As a result, the on-resistance is reduced and the gate current is also suppressed, so that loss during conduction can be reduced.
  • the gate-source voltage control circuit 109 turns the pMOS 112a from off to on and turns on the pMOS 112b. A control signal for transferring from OFF to OFF is transmitted. At this time, since the pMOS 112a is turned on, the effective gate resistance value becomes the resistance value of the gate resistance 105a, which is the smallest among the three stages.
  • the voltage applied between the gate and the source of JFET 101 is maximized, and the gate-source voltage value that suppresses the sum of the conduction loss caused by the on-resistance and the gate loss caused by the gate current to a minimum or close to the minimum is obtained. Reduced.
  • FIG. 9 shows a power conversion apparatus according to a third embodiment of the present invention.
  • a main circuit 100 in the figure is one phase of an inverter device, and has a series connection circuit of JFET 101 and JFET 102. Although not shown, this series connection circuit is provided for the number of AC phases, for example, three for a three-phase AC.
  • Both ends of the series connection circuit of JFET 101 and JFET 102 are connected to DC power supply 107 via main circuit wiring inductances 127 and 128.
  • the AC power is output from an interconnection point between JFET 101 and JFET 102, that is, an AC terminal.
  • JFETs 101 and 102 are connected in parallel to unipolar diodes 103 and 104 such as Schottky barrier diodes, respectively. These diodes function as freewheeling diodes.
  • the drive circuit 110 shown in FIG. 1 is connected to the gate of the JFET 101 via a gate resistor 105a and a speed-up capacitor 105b. Similar to JFET 101, drive circuit 120 having the same configuration as drive circuit 110 shown in FIG. 1 is connected to the gate of JFET 102 via gate resistor 106a and speed-up capacitor 106b. However, the gate-source voltage control circuit 109 in the drive circuit 110 also transmits a control signal for switching the gate resistance to the drive circuit 120.
  • Each drive logic circuit in the drive circuits 110 and 120 drives the npn and pnp transistors in each drive circuit on and off in response to a command signal from the control circuit 121.
  • the current transformer 108a for detecting the main circuit current is inserted into the AC output wiring taken out from the connection point between the JFET 101 and the JFET 102.
  • the temperature detection circuit 108b detects the temperature of the JFET 102 on behalf of the JFETs 101 and 102, but may detect the temperature of the JFET 101. Further, each temperature of JFET 101 and JFET 102 may be detected.
  • the drive circuits 110 and 120 drive the JFETs 101 and 102 while switching the gate resistance when conducting.
  • the conduction loss including the gate loss in JFETs 101 and 102 can be reduced to a minimum value or a value close to the minimum value. Therefore, the power loss generated by the inverter device can be reduced.
  • FIG. 10 shows a power conversion apparatus according to a fourth embodiment of the present invention.
  • the drive circuit of the second embodiment shown in FIG. 6 is used as the drive circuits 110 and 120.
  • the drive circuits 110 and 120 drive the JFETs 101 and 102 while switching the gate resistance when conducting.
  • the conduction loss including gate loss in the JFETs 101 and 102 can be reduced to a minimum value or a value close to the minimum value. Therefore, the power loss generated by the inverter device can be reduced.
  • the above-described embodiments can be applied not only to JFETs but also to SITs.
  • These semiconductor switching elements may be either a normally-on type or a normally-off type.
  • a wide gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN), or silicon (Si) that has been conventionally used can be applied.
  • SiC silicon carbide
  • GaN gallium nitride
  • Si silicon
  • npn transistor 114 and the pnp transistor 115 in the drive circuit can be replaced with other switching elements such as pMOS and nMOS.
  • the gate-source voltage of the semiconductor switching element may be changed by switching the voltage value of the on-gate power supply.
  • a forward conversion device may be used in addition to the inverter device, that is, the reverse conversion device.
  • the free wheel diode used in the main circuit in these power converters may be a bipolar pn diode.
  • SYMBOLS 100 ... Main circuit, 101, 102 ... JFET, 103, 104 ... Diode, 105a, 106a, 113a, 113b, 116 ... Gate resistance, 105b, 106b ... Speed-up capacitor, 107 ... DC power supply, 108a ... Rent transformer, 108b ... Temperature detection circuit 109 ... Gate-source voltage control circuit 110, 120 ... Drive circuit, 111 ... Drive logic circuit, 112a, 112b ... pMOS, 114 ... npn transistor, 115 ... pnp transistor, 117, 118 ... Gate power supply, 121 ... Control circuit, 127,128 ... Main circuit wiring inductance

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Abstract

L'invention concerne un circuit d'excitation d'élément de commutation à semi-conducteurs servant à exciter un élément de commutation à semi-conducteurs du type unipolaire pourvu d'une jonction p-n entre la grille et la source, tel qu'un transistor à effet de champ à jonction (JFET) ou un transistor statique à induction (SIT), afin de le mettre sur marche et sur arrêt, le circuit d'excitation d'élément de commutation à semi-conducteurs étant connecté à une grille de l'élément de commutation à semi-conducteurs. Le circuit d'excitation d'élément de commutation à semi-conducteurs comprend : une unité de circuit de mise en route d'excitation servant à appliquer une tension grille-source entre la grille et la source de l'élément de commutation à semi-conducteurs lors de la conduction d'un courant ; un moyen de détection de courant servant à détecter un courant de circuit principal ; et un moyen de commande de tension grille-source servant à changer la tension grille-source en fonction du courant de circuit principal lors de la conduction d'un courant. De ce fait, les pertes durant la conduction, incluant les pertes de puissance produites par le courant de grille, sont réduites.
PCT/JP2013/068039 2013-07-01 2013-07-01 Circuit d'excitation d'élément de commutation à semi-conducteurs, et dispositif de conversion de puissance utilisant ledit circuit WO2015001603A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015524923A JPWO2015001603A1 (ja) 2013-07-01 2013-07-01 半導体スイッチング素子の駆動回路およびそれを用いた電力変換装置
PCT/JP2013/068039 WO2015001603A1 (fr) 2013-07-01 2013-07-01 Circuit d'excitation d'élément de commutation à semi-conducteurs, et dispositif de conversion de puissance utilisant ledit circuit
TW103121353A TWI538365B (zh) 2013-07-01 2014-06-20 半導體切換元件之驅動電路及使用其之電力轉換裝置

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PCT/JP2013/068039 WO2015001603A1 (fr) 2013-07-01 2013-07-01 Circuit d'excitation d'élément de commutation à semi-conducteurs, et dispositif de conversion de puissance utilisant ledit circuit

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JP2017163352A (ja) * 2016-03-09 2017-09-14 トヨタ自動車株式会社 駆動装置
CN112003458A (zh) * 2020-08-24 2020-11-27 珠海智融科技有限公司 通路管控制电路、电源管理芯片以及电源装置
JP2021035142A (ja) * 2019-08-22 2021-03-01 富士電機株式会社 ゲート駆動回路、駆動装置、半導体装置及びゲート駆動方法
JP2021078166A (ja) * 2019-11-05 2021-05-20 株式会社日立製作所 半導体装置の駆動装置および駆動方法、並びに電力変換装置

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CN113938007B (zh) * 2021-10-27 2022-11-04 西安华芯微半导体有限公司 一种电平转换高压高速大功率驱动方法及系统结构

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US20030179035A1 (en) * 2002-03-22 2003-09-25 Siemens Aktiengesellschaft Drive control circuit for a junction field-effect transistor
JP2007259576A (ja) * 2006-03-23 2007-10-04 Hitachi Ltd スイッチング素子の駆動回路
JP2009239214A (ja) * 2008-03-28 2009-10-15 Denso Corp スイッチング回路

Cited By (6)

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Publication number Priority date Publication date Assignee Title
JP2017163352A (ja) * 2016-03-09 2017-09-14 トヨタ自動車株式会社 駆動装置
JP2021035142A (ja) * 2019-08-22 2021-03-01 富士電機株式会社 ゲート駆動回路、駆動装置、半導体装置及びゲート駆動方法
JP7371393B2 (ja) 2019-08-22 2023-10-31 富士電機株式会社 駆動装置、半導体装置及びゲート駆動方法
JP2021078166A (ja) * 2019-11-05 2021-05-20 株式会社日立製作所 半導体装置の駆動装置および駆動方法、並びに電力変換装置
JP7300370B2 (ja) 2019-11-05 2023-06-29 株式会社日立製作所 半導体装置の駆動装置および駆動方法、並びに電力変換装置
CN112003458A (zh) * 2020-08-24 2020-11-27 珠海智融科技有限公司 通路管控制电路、电源管理芯片以及电源装置

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