WO2015000197A1 - 一种基于3d打印的封装基板及其制造方法 - Google Patents

一种基于3d打印的封装基板及其制造方法 Download PDF

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Publication number
WO2015000197A1
WO2015000197A1 PCT/CN2013/079460 CN2013079460W WO2015000197A1 WO 2015000197 A1 WO2015000197 A1 WO 2015000197A1 CN 2013079460 W CN2013079460 W CN 2013079460W WO 2015000197 A1 WO2015000197 A1 WO 2015000197A1
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WO
WIPO (PCT)
Prior art keywords
layer
electronic
printing
electronic device
substrate based
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PCT/CN2013/079460
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English (en)
French (fr)
Inventor
江俊逢
吴柏江
周丽
Original Assignee
Jiang Junfeng
Wu Bojiang
Zhou Li
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Application filed by Jiang Junfeng, Wu Bojiang, Zhou Li filed Critical Jiang Junfeng
Publication of WO2015000197A1 publication Critical patent/WO2015000197A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
    • B33Y80/00—Products made by additive manufacturing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • TECHNICAL FIELD This application is in the field of package substrate and printed circuit board (PCB) manufacturing, and specifically relates to manufacturing a multilayer circuit board, particularly a package substrate, using 3D printing technology.
  • PCB printed circuit board
  • 3D printing technology 3D printing technology.
  • Printed circuit boards or printed circuit boards also known as printed circuit boards or printed circuit boards, are referred to as circuit boards.
  • the circuit board serves as a mounting substrate for the electronic device and is used for electrical connection and support of the electronic device.
  • a wiring layer is used to implement electrical interconnection of electronic devices, referred to as interconnections.
  • a wiring layer generally includes an insulating substrate (referred to as a substrate) and a wiring thereof.
  • a substrate insulating substrate
  • the present application distinguishes an insulating substrate in a wiring layer from a conductor thereon.
  • the insulating substrate is referred to as an insulating layer, and the sum of wires and pads on the insulating layer is referred to as a wiring layer.
  • the power layer and the ground layer are actually a kind of wiring layer, but the material of the substrate is different from the specification of the wire.
  • the present application considers the power layer and the ground layer as wiring layers.
  • the bottom layer, the top layer, and the auxiliary layer are conventional technologies. Therefore, it can be simply said that the multilayer circuit board is a superposition of different wiring layers, and the manufacturing technology of the multilayer circuit board is the manufacturing technology of the wiring layer.
  • the manufacturing method of the existing multilayer circuit board is generally made of a wiring layer, which is formed into a single panel or a double panel by chemical etching, and an insulating layer is placed between each layer to complete the vertical interconnection and then press together. .
  • the wires between the different wiring layers are vertically interconnected by vias.
  • the via hole is a small hole filled with metal or filled with conductive paste in the substrate, wherein the buried via is used for vertical interconnection between the internal wiring layers, and the bl ind via is used for the internal wiring layer and the top layer/ Vertical interconnection between the bottom layers.
  • the main manufacturing processes of the existing multilayer circuit board manufacturing technology include film production, pattern transfer, drilling, hole metallization, and vacuum lamination.
  • the basic technical features are:
  • a copper clad laminate (Copper Clad Laminate) is used as a substrate of the wiring layer; the copper wire on the substrate is chemically etched to manufacture wires and pads on the wiring layer;
  • Drilling holes on the substrate using a CNC drilling machine or laser including buried holes and blind holes;
  • Packaging technology such as Ball Grid Array Package (BGA), Chip Scale Package (CSP), Multi Chip Package (MCP), System in a Package (SiP) Lead to the integration of circuit board manufacturing technology and electronic packaging technology.
  • BGA Ball Grid Array Package
  • CSP Chip Scale Package
  • MCP Multi Chip Package
  • SiP System in a Package
  • the package substrate has become the mainstream of multi-layer circuit boards, guiding the development trend of circuit board manufacturing technology and driving the entire industry to carry out technological innovation. Therefore, the Japan Circuit Board Industry Association (JPCA) renamed the "printed circuit board” called for decades, and the original double-sided circuit board, multilayer circuit board, and BGA, CSP, MCM, SiP, etc. are collectively referred to as electronic substrates. (Electric substrate), Europe and the United States and academia are called package substrates. This application uses the term package substrate.
  • JPCA Japan Circuit Board Industry Association
  • the package substrate industry is the most active industry in the modern electronic device manufacturing industry, accounting for more than a quarter of the total output value of electronic devices, and is the largest industry in the electronic device segmentation industry.
  • a passive/active electronic device is embedded inside the package substrate.
  • passive/active electronics are only mounted on the surface of the multilayer board, not embedded inside the board. This is the only difference between a multilayer board and a package substrate. Therefore, the present application no longer distinguishes between a multilayer wiring board and a package substrate, but treats the multilayer wiring board as a package substrate in which the passive/active electronic components are not embedded.
  • Package substrates are generally classified into three types: rigid organic package substrates, flexible package substrates, and ceramic package substrates.
  • high-density interconnect package substrates with fine apertures, thin wires, fine pitch, and high precision are called a new technological revolution. Since the line width/line spacing of the high-density interconnect is less than 30 ⁇ /30 ⁇ ⁇ , the diameter of the micro-via is less than 0. 25-0. 30mm, which produces various micro-hole manufacturing techniques (including micro-hole punching). Hole technology and microporous metallization technology).
  • a key technical issue for existing package substrates is what technical solution is used to achieve vertical interconnection between different wiring layers, the so-called vertical interconnection technique.
  • the wires in the different wiring layers are vertically interconnected by metallized vias.
  • the pattern transfer and chemical etching are performed first, and then the holes are drilled by the CNC drilling machine (buried holes and blind holes) or laser punched, and then the holes are metallized by electroplating.
  • This is the basic technical solution for the existing package substrate to solve the vertical interconnection.
  • the vertical interconnect technology especially the microvia manufacturing technology required for high-density interconnects, is the core manufacturing technology for existing package substrates.
  • the manufacturing cost of microvias is about 30% to 40% of the total cost.
  • Another key technical issue for existing package substrates is what technical solution is used to detect the interconnection state of the wiring layers, that is, the on/off state of the vertical interconnection and the horizontal interconnection.
  • the interconnection state of the wiring layer, especially the metallized via hole cannot be detected in real time during the manufacturing process, and only offline detection can be performed, and the detection technology is complicated; With the development of multi-chip packages, offline detection of existing package substrates is more difficult.
  • the inside of the package substrate has a complicated three-dimensional structure, for example, the wiring layers have different structures and are insulated from each other; buried holes and blind holes penetrating the wiring layer and metallization thereof; buried/active electrons are buried in the wiring layer Devices, etc.
  • the internal rigid product with complex three-dimensional structure is not manufacturable, and can only be split into some parts with 0" manufacturability, t3 ⁇ 4
  • the reduced material manufacturing uses Computer Numerical Control (CNC) to generate 3D solids by layering and layer-by-layer cutting to remove excess material.
  • CNC Computer Numerical Control
  • 3D printing technology also uses computer numerical control, but it is a layered and layer-by-layer addition to solidify the added materials to generate 3D entities, so it is called additive manufacturing.
  • the molding technology of molding materials and molding materials is the core technology of 3D printing, and is also the essential difference between additive manufacturing and material reduction manufacturing.
  • 3D printing technology generally includes:
  • 3DP's printing process lay a layer of powder; under the control of the CNC equipment, spray the adhesive on the area to be molded, and bond the material powder to form the cross section of the part; so repeatedly, layer by layer to obtain the 3D solid.
  • powder materials such as ceramic powder, metal powder, plastic powder, etc.
  • FDM Fused Deposition Modeling
  • FDM printing process heating and melting filamentous hot-melt material; spraying hot-melt fluid material on the area to be molded under the control of CNC equipment; rapid cooling and solidification; so repeated spraying, rapid cooling and solidification, layer Layer stacking to get 3D entities.
  • Filamentous polymer materials such as ABS (engineering plastics), PC (amorphous engineering plastics), and PLA (biodegradable plastics) are used.
  • SLA's printing process spraying a layer of liquid photosensitive resin, under the control of CNC equipment, laser scanning liquid photosensitive resin, photopolymerization and curing, so repeated spraying, laser scanning and curing, layer stacking, to obtain 3D solids.
  • a photosensitive resin is used.
  • SLS's printing process spraying a layer of powder material (metal powder or non-metal powder), preheating the material to near the melting point, under the control of the CNC equipment, laser scanning and sintering, so repeating the repeating of the powder, laser scanning and sintering, Get a 3D entity.
  • powder materials metal powder or non-metal powder.
  • DLP's print molding process A high-resolution digital light processor (DLP) projector is used to cure the liquid photopolymer and photo-curing layer by layer to obtain a 3D solid. A photosensitive resin is used.
  • DLP digital light processor
  • UV molding technology Ultraviolet Light, UV
  • UV printing process Similar to the SLA printing process, instead of using a laser, the liquid photosensitive resin is irradiated with ultraviolet light (Ultraviolet Light) and stacked from bottom to top to obtain a 3D solid. A photosensitive resin is used.
  • 3D printing fork BJ meter molding material must be powdered wood or liquid material, in the control of CNC equipment, coated by powder spray or droplet spray into a layer of solid, and then laser sintered curing or UV Scanning and curing is carried out, and thus solidification molding is added layer by layer.
  • an insulating layer is formed of a photosensitive resin, a wiring layer is formed using a photosensitive conductive ink, and an ultraviolet forming technique is employed; an insulating layer is formed from a ceramic powder, and a wiring layer is formed using a metal powder, and a selective laser sintering technique is employed.
  • the wiring layer produced by powder spraying or droplet spraying has low precision and is far from the requirement of high-density interconnection;
  • the material for fabricating the wiring layer (conductive particles in the photosensitive conductive ink, metal powder for laser sintering) must be nano-scale, and the manufacturing cost of the nano material is high;
  • Conductive ink is used for wiring and filling.
  • the stress caused by uneven growth and contraction of different materials is likely to cause cracking of the wire, and the hole is likely to be concave; the edge of the wire may cause void defects, which affect the electrical properties and connection reliability of the wiring layer.
  • 3D printing technology In contrast to the subtractive material manufacturing technology, a significant advantage of 3D printing technology is that products that are manufacturable due to complex internal solid structures, or products that must be disassembled to be manufacturable, can be directly manufactured using 3D printing technology.
  • the package substrate should be an additive manufacturing technology.
  • the existing package substrate manufacturing technology uses reduced material manufacturing technology, which has formed a large and complex technical system and industrial chain.
  • SUMMARY OF THE INVENTION The present application is based on a 3D printing technology, and re-examines the internal structure of a conventional package substrate and a method of manufacturing the wiring layer, and proposes a package substrate based on 3D printing and a method of manufacturing the same.
  • a single-sided wiring board or a multilayer wiring board is regarded as a special example of a package substrate.
  • the present application re-examines the internal structure of the existing package substrate, and regards the body of the package substrate as an insulating layer and an encapsulation layer having a complicated three-dimensional structure, and the electronic device and the electronic connection device embedded in the package layer constitute a functional layer.
  • the present application revisits the existing manufacturing method of the wiring layer, and treats the wires, the pillars, the pads, and their different structural components as electronic connecting devices, which are treated and standardized as passive/active electronic devices.
  • the present application proposes a direct interconnection technology, which uses a sitting pillar (seat pillar array) to realize vertical interconnection between electronic devices in different functional layers; using wires (wire bars) to realize electrons in the same functional layer Horizontal interconnection between devices. This is the forehead of the forehead.
  • a package substrate based on 3D printing comprising an insulating layer, a functional layer, and an encapsulation layer;
  • the insulating layer is formed by printing a 3D printer with an insulating material;
  • the encapsulation layer is located above the insulating layer, and the functional layer is embedded In the encapsulation layer;
  • the functional layer is composed of interconnected electronic devices;
  • the electronic device includes an electronic connection device;
  • the electronic connection device includes a horizontal type electronic connection device; and the horizontal type electronic connection device includes a wire.
  • the wires are connected to two or more other electronic devices in the same functional layer; the space between the electronic devices is printed and filled with an insulating material by a 3D printer to constitute the encapsulation layer.
  • the package substrate includes a plurality of insulating layers, a functional layer, and an encapsulation layer;
  • the electronic connection device includes a vertical type electronic connection device, and the vertical type electronic connection device includes a seated guide post, and the lower end of the seated guide post is attached Mounted on the upper surface of the current insulating layer, the upper end passes through the via of at least one other insulating layer to the other functional layer and is connected to the electronic device in the other functional layer.
  • the horizontal type electronic connecting device further includes a wire row integrated by a plurality of wires.
  • the vertical type electronic connection device further includes a seated column array integrated by a plurality of seated guide columns.
  • the electronic device also includes active electronics; the active electronic device includes a transistor, an integrated circuit, a chip and a chip module.
  • the electronic device further includes a passive electronic device; the passive electronic device includes a resistor, a capacitor, and an inductor.
  • the insulating layer and the insulating material of the encapsulating layer are ABS, PC, PLA or photosensitive resin.
  • a detection point is disposed on a pin of the electronic device.
  • a method for manufacturing a package substrate based on 3D printing comprises the following steps: Step (1), writing a layered printing program: determining a three-dimensional structure of an insulating layer, a functional layer, and an encapsulating layer according to functions and structures of electronic devices in a functional layer Writing a layered printing process for the insulating layer and the encapsulation layer; step (2), printing an insulating layer: printing the insulating layer using a 3D printer; and (3), mounting a functional layer: in the insulating The upper surface of the layer is mounted with electronic components; the electronic device comprises an electronic connection device; the electronic connection device comprises a horizontal type electronic connection device, the horizontal type electronic connection device comprises a wire; step (4), horizontal interconnection: a horizontal interconnection technique, using the wires to horizontally connect other electronic devices in the same functional layer; Step (5), printing an encapsulation layer: printing the encapsulation layer formed by printing a space between the electronic connection devices using a 3D printer Step (6), pressing the insulating layer and the
  • the package substrate includes a plurality of insulating layers, a functional layer, and an encapsulation layer;
  • the electronic connection device includes a vertical type electronic connection device, and the vertical type electronic connection
  • the device includes a seated guide post; the step (4) further uses the wire to connect other electronic devices in the same functional layer with the seated guide posts in the other layers; repeating the step (2) to the Step (6) is to obtain the number of layers determined in the step (1).
  • the vertical type electronic connecting device in the step (3) employs a sitting pillar array integrated by a plurality of sitting pillars, and the horizontal type electronic connecting device employs a wire row integrated by a plurality of wires.
  • a detection point is disposed on a pin of the electronic device in the step (3); in the step (4), a connection between the wire and other electronic devices in the same functional layer is performed by soldering, and after soldering, two tests are performed. Probe and solder joint The w inspection points of Lishou are connected to detect the connection status of the blank welding points; if the welding defects are found, the welding points of the blanks are repaired in real time.
  • the vertical interconnection between the wiring layers is realized by metallized via holes; the wiring layer is formed by chemical etching on the copper clad plate, and the I/ of the passive/active electronic device is realized by the wire bonding technology.
  • the horizontal interconnection between the O pin and the pad on the wiring layer is the basic technical means for the existing package substrate to solve the interconnection.
  • the manufacturing of wiring layers involves many complicated technologies such as photo imaging, pattern transfer, chemical etching, numerical control drilling/laser drilling, browning, hole metallization, electroplating, cleaning, drying, pressing, continuity testing, etc.
  • many processes include a dozen sub-processes.
  • a large number of complex devices are configured as pipelines to perform these operations in a serial operation.
  • Such a large number of processes require many expensive high-precision CNC equipment, such as laser photoplotters, CNC drilling machines/milling machines, fully automatic plating lines, fully automatic optical inspection systems, multi-layer positioning systems, various special test instruments, etc. .
  • the technical system of the existing package substrate is "five" (multiple disciplines, multiple technologies, multiple processes, multiple equipments, and various materials), and its industrial chain is costly and seriously pollutes the environment.
  • the existing enterprises that package substrates have become large capitalists, large technology giants, large laborers, and are also major polluters, large energy consumers, and large water users.
  • 3D printing technology has created a new concept of design and manufacturing.
  • An outstanding advantage of 3D printing technology is the ability to create parts made of functionally graded materials that can be directly fabricated into parts of any complex structure.
  • products that have a manufacturability due to a complex three-dimensional structure inside, or products that must be disassembled to be manufacturable can be directly manufactured by 3D printing technology.
  • a package substrate multilayer circuit board is such a product.
  • the present application is based on 3D printing technology, and re-examines the internal structure of the existing package substrate and the manufacturing method of the wiring layer from two aspects.
  • the second is to re-examine the manufacturing method of the existing wiring layer, and consider the wires, the guide posts, the pads and their different structural components as electronic connecting devices, and standardize them, and manufacture them by a plurality of methods by a third party.
  • the present application changes the existing production mode of the package substrate (multilayer circuit board)
  • the wiring layer is manufactured by all, the wiring layer design, photo imaging, pattern transfer, chemical etching, punching, hole metallization, plating, cleaning , drying, etc., are scattered in various enterprises, and each enterprise uses a non-standardized pipeline for serial operations. From a macro perspective, the production methods of the entire industry are still essentially workshop-style. This workshop-style serial production method carries out all its development history.
  • the present application defines a combination of wires, posts, pads, and their different structures as standardized electronic connectors.
  • These electronic connection devices can be manufactured by a third party in a variety of ways, thereby transforming the existing serial production mode of the package substrate (multi-layer circuit board) into a specialized, standardized parallel production mode, which reduces investment and improves efficiency. Significant benefits are achieved in terms of reducing pollution and saving resources.
  • the package substrate (multi-layer circuit board) can be regarded as an electronic functional component in which the insulating layer, the functional layer and the encapsulation layer are sequentially layer-by-layer stacked, and the core of the manufacturing technology is two interconnection technologies.
  • One is the vertical interconnection between the electronic devices in different functional layers, and the other is the horizontal interconnection between the electronic devices in the same functional layer.
  • the present application uses the 3D printing technology to manufacture the insulating layer and the encapsulation layer, and does not require a copper clad laminate manufacturing technique.
  • the present application proposes a direct interconnection technique that uses a standardized electronic connection device sitting pillar (seat pillar array) to achieve vertical interconnection between electronic devices in different functional layers, using standardized electronic connection device wires ( Wire bars) enable horizontal interconnections between electronic devices in the same functional layer.
  • the present application eliminates almost all the processes in the prior art for manufacturing a wiring layer, does not require a copper clad laminate manufacturing technique, and does not require micropore manufacturing technology, and completely changes the existing manufacturing technology of the package substrate (multilayer wiring board). And its industrial chain.
  • 3D printing technology is only used to fabricate the insulating layer and the encapsulation layer.
  • the present application simplifies the existing wiring layer manufacturing technology to horizontal interconnection between electronic devices in the same functional layer, thereby avoiding the problems of manufacturing thin wires, fine pitch, and high precision wiring layers by using 3D printing technology. Very good industrial applicability.
  • the present application proposes a direct interconnection technology, and the micropore manufacturing technology is no longer a technical bottleneck restricting the miniaturization of a package substrate (multilayer circuit board), and increasing the number of layers becomes a basic technical means for miniaturization of a package substrate (multilayer circuit board). , can significantly reduce the manufacturing cost of the package substrate (multilayer circuit board).
  • the electronic connecting device in this application adopts professional and standardized industrial production. Through the aging, vibration, detection and other technological measures, its reliability is high, far from the existing wiring layer. Compared with the existing wiring layers such as the chemically etched wiring on the overclad steel and the metallized guiding of the electric cymbal, the electronic connecting device in the armor can adopt various materials having good electrical properties and manufacturability, thereby reducing the circuit. Loss and signal transmission delay.
  • the existing manufacturing technology of the package substrate cannot detect the on-off state of the electrical interconnection in real time, and can only perform offline detection, and the detection technology is complicated and the cost is high.
  • This application solves the real-time detection problem of electrical interconnection with extremely simple technical means, reduces cost and improves reliability.
  • This application uses 3D printing technology to fabricate insulating layers and encapsulation layers with complex three-dimensional structures to accommodate the development of three-dimensional packaging.
  • FIG. 1 is a structural view of a specific embodiment of the present invention
  • the present application is a flow chart of a method of manufacturing a specific embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION The present application has been described in the technical background, and the multi-layer wiring board and the package substrate are no longer distinguished.
  • the present application treats a multilayer circuit board as a package substrate in which passive/active electronic devices are not embedded.
  • the package substrate comprises a circuit board, in particular a multilayer circuit board.
  • Passive electronic devices include resistors, capacitors, inductors, etc.
  • Active electronic devices include transistors, integrated circuits, chips and chip modules.
  • 3D printing technology has created a new concept of design and manufacturing.
  • An outstanding advantage of 3D printing technology is the ability to create parts made of functionally graded materials that can be directly fabricated into parts of any complex structure.
  • products that have a manufacturability due to a complex three-dimensional structure inside, or products that must be disassembled to be manufacturable can be directly manufactured by 3D printing technology.
  • the package substrate is just such a product.
  • the main structure of the package substrate is a three-dimensional insulating layer and an encapsulation layer.
  • a functional layer composed of electronic devices is embedded in the encapsulation layer.
  • the use of 3D printing technology to fabricate the insulation layer does not require copper clad laminate manufacturing techniques.
  • the insulating layer is filled with metal or a conductive hole filled with a conductive paste. This application is called a conductive column, and is referred to as a conductive column.
  • the pillars are used for vertical interconnections between electronic devices in different functional layers.
  • Passive/active electronic devices in the same package layer achieve horizontal interconnection through wires and pads.
  • the armor ffi nicknames the combination of the wires, the guides, the pads and their minor structures to the connector ⁇ .
  • the intrusion/output lead is an electronic connection device that is interconnected with the outside.
  • an electronic connection device is an electronic device that implements interconnection.
  • electronically connected devices are on an equal footing with passive/active electronic devices such as resistors, capacitors, inductors, transistors, integrated circuits, chip and chip modules, but with different functions.
  • electronic connecting devices such as wires, guide posts, and pads can be standardized and manufactured in advance by specialized production.
  • the materials gold, copper, aluminum
  • the dimensions of the pillars and pads are also standardized.
  • Wires, posts, pads, etc. are defined as separate, standardized electronically connected devices that are completely separate from existing wiring layers and their fabrication techniques. Therefore, unlike other processes such as photolithography, chemical etching, punching, hole metallization, and electroplating to fabricate wires, pads, and metallized via holes on a copper clad laminate, other techniques can be used (for example, machining, laser processing). Etching) Manufacturing of electronic connecting devices such as wires, pillars, and pads by specialized production.
  • the electronic connecting device of the present application can adopt various materials having good electrical properties and manufacturability, thereby reducing circuit loss and signal, compared with existing wiring layers such as chemically etched wiring on a copper clad plate, electroplated metallized via holes, and the like. Transmission delay. These electronic connecting devices can also improve their reliability through process measures such as aging, vibration, and detection.
  • the wires, the guide posts, and the pads can be combined into an electronic connection device having a different structure.
  • the pillars and pads can be combined into a seated pillar.
  • the guide post is a small upper and lower cone with a pad at the bottom; the pad facilitates the positioning/mounting of the guide post and provides a soldering surface for the wire.
  • the size of the seat post for example, material, height, upper/lower diameter, pad diameter and thickness are normalized.
  • a plurality of seated guide posts can also form an array or a carrier tape package, and the array pattern and spacing are standardized.
  • the sitting pillar and the sitting pillar array are used for vertical interconnection between electronic devices in different functional layers, and may be referred to as vertical type electronic connecting devices.
  • the multi-strand wires can be combined into a wire row, wherein the wires can be provided with or without pads at both ends, and can be wound or taped.
  • the wire can be wire or plate, wire diameter or line width / line thickness, wire length, number of strands and spacing are standardized.
  • Wires and wire bars are used for horizontal interconnection between electronic devices in the same functional layer and can be referred to as horizontal electronic connecting devices.
  • the electronic device embedded in the encapsulation layer is referred to herein as a functional layer.
  • the functional layer, the encapsulation layer, and the insulating layer form the core of the package substrate.
  • the number of layers of the package substrate refers to the number of layers of the functional layer. Generally, the number of layers of the package substrate is two or more.
  • the present application defines the package substrate as follows:
  • the package substrate is an electronic functional component in which an insulating layer, a functional layer, and an encapsulation layer are sequentially stacked.
  • the encapsulation layer is on the insulating layer, and the functional layer is buried in the encapsulation layer and on the upper surface of the insulating layer.
  • the functional layer is composed of interconnected electronic devices; the electronic device includes passive electronic devices, active electronic devices, and electronic connecting devices. Passive electronic devices include resistors, capacitors, and inductors; active electronic connecting devices include transistors, integrated circuits, chip and chip modules; electronic connecting devices include horizontal electronic connecting devices, vertical electronic connecting devices;
  • the water type is connected to the connector by using a water connection of the electric device 1Z 1" in the functional layer, and the vertical type is connected to the device for vertical interconnection between the electronic devices in different functional layers. .
  • the encapsulation layer is composed of an insulating material filled in the functional layer for electrical insulation and support between the electronic devices.
  • the insulating layer is made of an insulating material for electrical insulation between the functional layers; a through hole is formed in the insulating layer, and a vertical type electronic connecting device is embedded in the through hole.
  • the package substrate has a bottom layer and a top layer.
  • the above definitions indicate that if the top layer of the package substrate is mounted with passive/active electronic devices and there are no passive/active electronic devices in the functional layer, only the electronic connection device is used, and the package substrate is degraded into a multilayer circuit board; If there is only one functional layer in the multilayer circuit board, the multilayer circuit board is degraded into a single-sided circuit board.
  • the top layer of the package substrate may or may not be equipped with passive/active electronics. If the top layer of the package substrate is mounted with passive/active electronics, when printing the top layer, the connection between the I/O pins of the passive/active electronic device and the electronic connection device cannot print the insulating material, but should be left Open the hole for the user to install the soldering electronics.
  • an icon layer, a layer of text and symbols, should be created on the top layer to indicate where the passive/active electronics are mounted on the top layer.
  • the reliable connection between the wiring layer and the insulating substrate mainly depends on the copper clad manufacturing technology.
  • the present application is based on 3D printing technology and does not require a copper clad laminate manufacturing technique, so that a reliable connection between the top-level electronic connection device and the insulating layer is provided by the encapsulation layer.
  • the bottom layer and the top layer are all conventional technologies.
  • the bottom layer, the top layer, and the insulating layer are generally flat structures.
  • the outstanding advantage of using 3D printing technology is that it can manufacture the bottom layer, the top layer, the insulating layer and the encapsulation layer with complex three-dimensional structure, and can also print gradient structures with different functions and different materials to adapt to the development of three-dimensional packaging.
  • the through hole in which the seated pillar is embedded in the insulating layer is a tapered hole that is small and large, and is formed layer by layer around the seated guide column during printing, and the precision and manufacturing complexity are much lower than the existing package.
  • Micropore manufacturing technology in the substrate; the upper surface of the insulating layer is a complex curved surface with grooves, bumps, steps, and the like.
  • the above definition reveals that the three-dimensional structure of the insulating layer and the encapsulation layer and the manufacturing method thereof are one of the key technologies for packaging the substrate.
  • This is the advantage of 3D printing technology. Therefore, for such a 3D printed package substrate, the basic task of manufacturing the insulating layer and the encapsulation layer is to determine the three-dimensional structure of the insulating layer and the encapsulation layer according to the number of layers of the package substrate and the function and structure of the electronic device in the functional layer.
  • the vertical interconnection between the wiring layers is realized by metallized via holes; the wiring layer is formed by chemical etching on the copper clad plate, and the I/O tube of the passive/active electronic device is realized by the wire bonding technology.
  • the horizontal interconnection between the foot and the pad on the wiring layer is the basic technical means for the existing package substrate to solve the interconnection.
  • the horizontal interconnection technique between the I/O pin of the NMOS/active device and the pad on the wiring layer embedded in the wiring layer is generally referred to as a lead connection. technology.
  • Commonly used wire bonding technology has wire bonding
  • FCB Flip Chip Bonding
  • WB Wire Bonding, WB
  • TAB Tape Automated Bonding
  • BLB Beam Lead Bonding
  • FCB Flip Chip Bonding
  • FCB uses a bump interconnection for the vertical interconnection of hundreds of I/O pins to the substrate in a flip chip.
  • copper pillar (Cu-pilar lar Bump) interconnect has become the mainstream of bump interconnect technology.
  • the so-called copper pillar interconnection refers to replacing the tin-lead bump with a copper pillar with an aspect ratio greater than 1:1 to achieve vertical interconnection between the chip and the substrate.
  • bump interconnection is generalized, and a sitting pillar (sit-on pillar array) is used for vertical interconnection between electronic devices in different functional layers, especially in adjacent functional layers. Vertical interconnection between devices.
  • a seated guide post (seat guide post array) is defined as an independent standardized electronic connection device, thereby providing a new perspective for 3D printing technology to examine the manufacturing technology of the package substrate.
  • the interconnection problem in the package substrate is simplified to the horizontal interconnection problem between the electronic devices in the same functional layer.
  • This application extends the wire bonding technique, not by chemically etched wiring, but by the standardized electronically connected device wires (wire bars) to achieve the two horizontal interconnect modes described above.
  • This application refers to the above interconnection method as a direct interconnection technique.
  • Increasing the number of layers is the most suitable way to miniaturize the package substrate.
  • the number of layers is increased, the yield is significantly reduced, and the cost is greatly increased, forcing the fine pitch, the thin wire, the fine pitch, the high-precision high-density interconnection to be packaged.
  • the mainstream development direction of the substrate, line width and aperture are the representatives of the technical level, and micro-hole manufacturing technology has become a key technology.
  • the direct interconnect technology proposed by the present application does not require microvia fabrication techniques. Therefore, the micropore manufacturing technology is no longer a technical bottleneck for miniaturizing the package substrate, and increasing the number of layers becomes the basic technical means for miniaturization of the package substrate.
  • the seated guide post of the present embodiment has a structure similar to that of a copper post in flip chip technology.
  • the sitting guide column (sitting column array) can be made of copper or copper alloy.
  • copper alloy seated posts (seat-type column arrays) are easier to manufacture and have better overall performance than copper posts in flip-chip technology, reducing circuit losses and signal propagation delays.
  • the seated guide post (sitting guide post array) and the wire (wire bar) can be manufactured by a third party in a variety of ways.
  • Laser Micro Welder is a revolutionary new welding process that is fast and precise, flexible and simple, does not require a vacuum environment, is non-radioactive, and is non-polluting. It is a non-contact electrical connection technology.
  • the commonly used industrial laser has a wavelength of 1064 nm, and its reflectance to copper is as high as 90%, making it difficult to achieve copper connection.
  • the 532 nm laser green laser can continuously penetrate into the copper to stably connect the copper.
  • the material of the insulating layer is different, and the 3D printing technology is also different.
  • the material of the insulating layer is ABS,
  • 3D printing technology can choose fuse deposition technology or lithography technology, digital light Fork shaping, UV forming fork.
  • the material of the insulating layer is Taohua powder, and the 3D printing technology can use three-dimensional printing technology and selective laser sintering technology.
  • the present application uses an industrial grade 3D printer; ABS, PC, PLA as the material of the insulating layer and the encapsulation layer, fuse deposition molding technology as a 3D printing molding technique, or a photosensitive resin as an insulating layer and
  • the material of the encapsulation layer is UV-forming technology as a 3D printing molding technology; the copper or copper alloy sitting pillar (seat-type column array) is used as a vertically interconnected electronic connecting device, with wires (wire bars) as horizontal interconnection Electronic connection devices; horizontal interconnection technology uses green laser welding technology.
  • FIG. 1 is a schematic cross-sectional view showing the internal structure of a package substrate based on 3D printing.
  • a package substrate as shown in FIG. 1 includes three insulating layers 1, two encapsulating layers 2, and two functional layers; the functional layer of the first layer includes a first layer of active/passive electronic components 3 as The first layer of wires 61 of the horizontal type electronic connecting device serves as a sitting pillar (or a sitting pillar array) of the vertical type electronic connecting device; the second layer of the functional layer includes the second layer of active/passive electronic components 4 , the second layer of wire 62.
  • the lower end of the seat post 5 is mounted on the lower surface of the insulating layer of the first layer, and the upper end passes through the through hole of the second insulating layer.
  • the I/O pin 31 of the active/passive electronic device 3 is soldered to the lower end of the seat post 5 through the first wire 61; in the second functional layer, the active/passive electronic device 4
  • the I/O pin 41 is soldered to the upper end of the seat post 5 via the second wire 62.
  • the insulating layer of the lowermost layer serves as the bottom layer of the package substrate.
  • the insulating layer of the uppermost layer serves as the top layer of the package substrate. Referring to FIG. 2, the method for manufacturing the package substrate includes the following steps:
  • Step (1) writing a layered printing program: determining the three-dimensional structure of each insulating layer, each functional layer, and each encapsulating layer according to the number of layers of the package substrate and the function and structure of the electronic device in the functional layer, and writing for each insulating layer, A layered printing program for the encapsulation layer.
  • Step (2) print the first insulation layer using a 3D printer.
  • Step (3) attaching the first functional layer: attaching the first active/passive electronic device 3, the sitting guide post 5, and the lead 61 to the upper surface of the first insulating layer.
  • Step (4) the first layer of functional layer horizontal interconnection: Using the horizontal interconnection technique, the active/passive electronic component 3 in the first functional layer is horizontally connected to the lower end of the sitting pillar 5 by a wire 61.
  • Step (5) printing the first encapsulation layer: printing the gap between each electronic connection device in the first functional layer by using a 3D printer to form a first encapsulation layer.
  • Step (6) pressing the first insulating layer, the first functional layer, and the first encapsulating layer.
  • Step (7) print a second insulating layer using a 3D printer.
  • Step (8) attaching the second functional layer: attaching a second active/passive electronic device 4 and a wire 62 to the upper surface of the second insulating layer.
  • Step (9) the second layer of functional layer horizontal interconnection: Using the horizontal interconnection technique, the active/passive electronic component 4 in the second functional layer is horizontally connected to the upper end of the sitting pillar 5 by a wire 62.
  • Step (10) printing the second encapsulation layer: printing a gap between each electronic connection device in the second functional layer by using a 3D printer to form a second encapsulation layer.
  • Step (11) using a 3D printer to print a three-layer insulating layer as a "shell" of the package substrate.
  • Step (12) pressing the second insulating layer, the second functional layer, and the second encapsulating layer.
  • the sitting guide column uses copper or copper alloy
  • the horizontal interconnection technology uses green laser welding technology.
  • the steps (2) to (6) are repeated a plurality of times until the required number of layers.
  • metallized vias are used to achieve vertical interconnection between the wiring layers.
  • the metallized via holes are fabricated by electroplating, and the manufacturing process is completely closed, and real-time on/off detection cannot be performed during the manufacturing process.
  • the electronic device is first mounted on the insulating layer, and then the green laser is used to realize the sitting pillar (seat pillar array) and the passive/active electronic device.
  • the horizontal interconnection between the I/O pins is completely open. This creates conditions for real-time detection of the interconnect state of the package substrate.
  • the manufacturing method proposed by the present application can realize real-time detection of the on/off state by using extremely simple technical means, and the technical solution thereof is as follows.
  • One detection point is set on the pin of each electronic device; real-time on/off detection is performed when the electronic device is soldered horizontally.
  • the real-time detection of the on/off state is like the usual multimeter detection on and off.
  • Two test probes are respectively connected to two detection points before and after the welding point, and the resistance value of the welding between the two detection points is detected, thereby judging the pass. / off, and judge the connection status according to the magnitude of the resistance value. If the connection point is broken or the resistance value is too large, the connection point can be repaired in real time by the green laser to improve the yield.
  • the two test probes are controlled by a 3D printer, when the layered printing program is written, and the control program of the test probe is simultaneously written, the above real-time detection process is automatically performed.
  • the seated pillar/sitting pillar array is used as a vertically interconnected electronic connecting device, and the wire/wire row is used as a horizontally interconnected electronic connecting device, with ABS, PC, PLA or photosensitive resin as the material of the insulating layer and the encapsulation layer, fuse deposition molding technology or ultraviolet molding technology as the 3D printing molding technology, green laser welding as the horizontal interconnection technology to explain the technical solution of the present application in detail, can not be determined
  • the specific implementation of the application is limited to these descriptions.
  • the insulating layer and the encapsulating layer of different materials and their corresponding 3D printing forming techniques for electronic connecting devices of different structures without departing from the concept of the present application. It is also possible to make a number of simple deductions or substitutions, which should be considered as belonging to the scope of protection of this application.

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Abstract

一种基于3D打印的封装基板及其制造方法。封装基板包括具有复杂立体结构的绝缘层（1）和封装层（2），封装层（2）内部埋置无源/有源电子器件（3、4）和电子连接器件；电子连接器件包括导线（61、62）、导柱（5）、焊盘及其组合件。基于3D打印的封装基板及其制造方法，改进了现有封装基板（多层线路板）及其布线层的制造方法，改变了封装基板（多层线路板）的生产方式与制造技术。

Description

一种基于 3D打印的封装基板及其制造方法
技术领域 本申请属封装基板 (Package Substrate )与线路板 (Printed Circuit Board, PCB) 制造领域， 具体涉及采用 3D打印技术制造多层线路板， 尤其是封装基板。 技术背景 印刷线路板或印制线路板， 又称印刷电路板或印制电路板， 本申请简称线路板。 线路板作为电子器件的安装基板， 用于电子器件的电气连接与支撑。
多层线路板具有层次结构， 由布线层（顶层、底层、中间布线层）、 电源层（Power)、 地线层 （Gr0Und)、 辅助层构成， 其辅助层包括顶层的阻焊层、 图标层 （legend)。
布线层用于实现电子器件的电气互连 （Electrical Interconnection), 简称互连。 在多层线路板中， 所谓布线层一般包括绝缘基板 (简称基板)及其导线。 为叙述方便 起见， 本申请将布线层中的绝缘基板与其上的导线予以区分， 绝缘基板称为绝缘层， 绝 缘层上的导线、 焊盘之总和称为布线层。
电源层、 地线层其实也是一种布线层， 只是基板的材质与导线的规范不同罢了。 为 叙述的方便起见， 本申请将电源层、 地线层也视为布线层。 底层、 顶层、 辅助层均属常 规技术， 因而， 可以简单地说， 多层线路板就是不同布线层的叠加， 多层线路板的制造 技术就是布线层的制造技术。
现有多层线路板的制造方法一般先做布线层， 以化学蚀刻法做成单面板或双面板， 并在每层板间放进一层绝缘层， 完成垂直互连， 再压合在一起。 不同布线层之间的导线 通过导孔 （via) 实现垂直互连。 导孔是基板中充满金属或填充导电胶的小洞， 其中， 埋孔 （buried via) 用于内部布线层之间的垂直互连， 盲孔 （bl ind via) 用于内部布 线层与顶层 /底层之间的垂直互连。
现有多层线路板制造技术的主要制造流程包括底片制作， 图形转移、 钻孔、 孔金属 化、 真空层压， 其基本技术特征是：
1、 在图形转移中采用印刷术在基板上印刷布线图；
2、 采用覆铜板 （Copper Clad Laminate ) 作为布线层的基板； 通过化学蚀刻基板 上的覆铜箔以制造布线层上的导线、 焊盘；
3、 采用 CNC钻床或激光在基板上钻孔， 包括埋孔和盲孔；
4、 采用电镀将埋孔和盲孔予以金属化或填充导电胶， 用于布线层的垂直互连；
5、 真空压合绝缘层、 单面板或双面板；
6、 制作辅助层；
7、 电路测试。 球栅阵列封装（Bal l Grid Array Package, BGA)、芯片尺寸封装（Chip Scale Package, CSP)、 多芯片封装（Multi Chip Package, MCP)、 系统级封装（ System in a Package, SiP)等封装技术导致线路板制造技术与电子封装技术的融合。 大规模 /超大规模集成电 路的广泛应用， 许多无源 /有源电子器件， 特别是多芯片与芯片模块 （MCM)直接埋置在 布线层中， 促使多层线路板从安装基板发展为封装基板。
封装基板已成为多层线路板的主流品种， 引导着线路板制造技术的发展潮流， 带动 整个产业进行技术创新。 因之， 日本线路板工业协会 （JPCA)将几十年称谓的 "印刷线 路板"改名， 将原有双面线路板、 多层线路板， 以及 BGA、 CSP 、 MCM、 SiP等统称为电 子基板 （Electric substrate ) , 欧美地区及学术界则称为封装基板， 本申请采用封装 基板这一术语。
据统计， 全球生产总值的 65%同集成电路有关。 封装基板产业为当代电子器件制造 业中最活跃的产业， 占电子器件总产值的四分之一以上， 是电子器件细分产业中比重最 大的产业。
封装基板的内部埋置无源 /有源电子器件。对于多层线路板， 无源 /有源电子器件只 安装在多层线路板的表面， 而不是埋置在多层线路板内部。 这是多层线路板与封装基板 的唯一区别。 因而， 本申请不再区分多层线路板与封装基板， 而是将多层线路板视为内 部未埋置无源 /有源电子器件的封装基板。
封装基板一般分为三类： 刚性有机封装基板、 柔性封装基板、 陶瓷封装基板。 伴随电子技术向高速度、 多功能、 大容量、 小体积方向发展， 细孔径、 细导线、 细 间距、 高精度的高密度互连 (High Density Interconnect)封装基板誉为一场新的技术 革命。 由于高密度互连的线宽 /线间距小于 30 μ πι/30 μ πι， 微孔 （micro-via) 的直径小 于 0. 25-0. 30mm， 产生了种种微孔制造技术 （包括微孔打孔技术与微孔金属化技术）。
对于现有封装基板， 一个关键的技术问题是， 采用什么技术方案实现不同布线层之 间的垂直互连， 即所谓垂直互连技术。
在现有封装基板中， 不同布线层中的导线通过金属化导孔实现垂直互连。
先进行图形转移与化学蚀刻， 再经 CNC钻床钻孔 （埋孔和盲孔） 或激光打孔， 然后 通过电镀完成孔金属化。 这是现有封装基板解决垂直互连的基本技术方案。 垂直互连技 术， 特别是高密度互连所要求的微孔制造技术成为现有封装基板的核心制造技术， 微孔 的制造成本约占总成本的 30%到 40%。
对于现有封装基板， 另一个关键的技术问题是， 采用什么技术方案检测布线层的互 连状态， 即垂直互连与水平互连的通 /断状态。
在现有封装基板中， 对于布线层的互连状态， 特别是金属化导孔不能在制造过程中 进行实时通 /断检测， 只能实施离线检测， 且检测技术复杂； 随着电子封装技术向多芯 片封装的发展， 现有封装基板的离线检测更为困难。
封装基板的内部具有复杂的立体结构，例如，布线层的结构各异，且相互之间绝缘; 贯穿布线层的埋孔与盲孔及其金属化； 布线层中埋置无源 /有源电子器件等。 在 3D打印 技术诞生之前， 对于减材制造 （subtractive manufacturing) 来说， 像封装基板这种 内部具有复杂立体结构的严品没有 0」制造性， 只能拆分为一些具有 0」制造性的部仵， t¾|J 单面线路板或双面线路板。这是导致现有封装基板制造技术采用减材制造技术的根本原 因， 由此形成了庞大而复杂的技术体系与产业链。 因而， 现有封装基板制造技术必须首 先分别制造单面线路板或双面线路板， 安装好无源 /有源电子器件， 在每层板间放进一 层绝缘层， 完成垂直互连， 经压合后构成封装基板。
减材制造采用计算机数字控制（Computer Numerical Control , CNC) , 通过分层与 逐层切削， 去除多余的材料来生成 3D实体。 3D打印技术也采用计算机数字控制， 却是 通过分层与逐层添加， 固化添加的材料来生成 3D 实体， 故称为增材制造 （additive manufacturing) o
就制造方法而言， 成型材料、 成型材料的喷射技术是 3D打印的核心技术， 也是增 材制造与减材制造的本质区别。
3D打印成型技术大致包括：
1、 三维印刷成型技术 (Three Dimensional Printing, 3DP)
3DP的打印成型过程： 铺一层粉末； 在 CNC设备的控制下， 对需要成型的区域喷涂 粘合剂， 使材料粉末粘接， 形成零件截面； 如此反复， 层层叠加， 获得 3D实体。 使用 粉末材料， 如陶瓷粉末、 金属粉末、 塑料粉末等。
2、 熔丝沉积成型技术 (Fused Deposition Modeling, FDM)
FDM的打印成型过程： 将丝状的热熔性材料加热融化； 在 CNC设备的控制下， 对需 要成型的区域喷涂热熔的流体材料；快速冷却固化；如此不断重复喷涂、快速冷却固化， 层层叠加， 获得 3D实体。 使用 ABS (工程塑料）、 PC (非晶体工程塑料）、 PLA (生物降 解塑料） 等丝状高分子材料。
3、 光亥 [J成型技术 (Stereolithigraphy Apparatus, SLA)
SLA的打印成型过程： 喷涂一层液态光敏树脂， 在 CNC设备的控制下， 激光扫描液 态光敏树脂， 产生光聚合反应而固化， 如此不断重复喷涂、 激光扫描固化， 层层叠加， 获得 3D实体。 使用光敏树脂。
4、 选区激光烧结技术 (Selecting Laser Sintering, SLS)
SLS的打印成型过程： 喷涂一层粉末材料（金属粉末或非金属粉末）， 将材料预热到 接近熔化点， 在 CNC设备的控制下， 激光扫描烧结， 如此不断重复铺粉、激光扫描烧结， 获得 3D实体。 使用粉末材料 （金属粉末或非金属粉末）。
5、 数字光处理成型技术 (Digital Light Procession, DLP)
DLP的打印成型过程:使用高分辨率的数字光处理器 (DLP)投影仪来固化液态光聚合 物， 逐层进行光固化， 获得 3D实体。 使用光敏树脂。
6、 紫外线成型技术 (Ultraviolet Light, UV)
UV 的打印成型过程： 与 SLA 的打印成型过程类似， 不是用激光， 而是用紫外线 (Ultraviolet Light ) 照射液态光敏树脂， 由下而上逐层叠加， 获得 3D实体。 使用光 敏树脂。 3D打印扠术 BJ米用的成型材科必须为粉禾材科或液体材科， 在 CNC设备的控制卜， 通过粉末喷射或液滴喷射涂覆成一层实体，再经激光烧结固化成型或紫外线扫描固化成 型， 如此逐层添加固化成型。
采用 3D打印技术来制造封装基板一直受到高度重视， 许多国家纷纷投入巨资来研 究和开发这项技术。 例如， 以光敏树脂制作绝缘层、 用光敏导电油墨制作布线层， 采用 紫外线成型技术； 以陶瓷粉末制作绝缘层、 用金属粉末制作布线层， 采用选区激光烧结 技术。
采用 3D打印技术制造封装基板的关键在于布线层。在 3D打印布线层方面， 目前尚 存在下述问题：
1、 布线层的精度问题
粉末喷射或液滴喷射所制造的布线层精度低， 与高密度互连的要求相差甚远；
2、 纳米材料成本高
制作布线层的材料（光敏导电油墨中的导电粒子、 用于激光烧结的金属粉末）必须 为纳米级， 纳米材料的制造成本较高；
3、 布线层的电性能和连接可靠性
印刷后， 纳米材料原有的电学性能有所下降；
采用导电油墨来布线与填孔， 不同材料涨縮不匀所产生的应力易产生导线开裂， 填 孔易产生凹陷； 导线的边缘可能会产生空洞缺陷， 影响布线层的电性能和连接可靠性。
4、 对环境洁净度的要求非常高。
与减材制造技术对比， 3D打印技术的一个突出优点是， 由于内部具有复杂的立体结 构导致丧失可制造性的产品， 或必须拆分才具有可制造性的产品， 可用 3D打印技术直 接制造。
在本质上， 封装基板应属于增材制造技术。 不幸的是， 由于历史的原因， 现有封装 基板制造技术采用减材制造技术， 由此形成了庞大而复杂的技术体系与产业链。 发明内容 本申请基于 3D打印技术，重新审视现有封装基板的内部结构及布线层的制造方法， 提出一种基于 3D打印的封装基板及其制造方法。
本申请将单面线路板、 多层线路板视为封装基板的特例。
本申请重新审视现有封装基板的内部结构，将封装基板的主体视为具有复杂立体结 构的绝缘层与封装层， 封装层内部埋置的电子器件与电子连接器件构成功能层。
本申请重新审视布线层的现有制造方法， 将导线、 导柱、 焊盘及其不同结构的组合 件视为电子连接器件， 与无源 /有源电子器件同等对待， 并予以标准化。
本申请提出一种直接互连技术， 采用坐式导柱 （坐式导柱阵列）实现不同功能层中 的电子器件之间的垂直互连； 采用导线 （导线排）实现同一功能层中的电子器件之间的 水平互连。 本甲谞的扠术万茱说明如 卜。
一种基于 3D打印的封装基板， 包括绝缘层、 功能层、 封装层； 所述绝缘层由 3D打 印机采用绝缘材料打印构成； 所述封装层位于所述绝缘层之上， 所述功能层埋置于所述 封装层中； 所述功能层由互连的电子器件构成； 所述电子器件包括电子连接器件； 所述 电子连接器件包括水平型电子连接器件； 所述水平型电子连接器件包括导线， 所述导线 连接同一功能层中的两个或多个其他电子器件； 所述电子器件之间的空间由 3D打印机 采用绝缘材料打印填充从而构成所述封装层。
所述封装基板包括多层绝缘层、 功能层、 封装层； 所述电子连接器件包括垂直型电 子连接器件， 所述垂直型电子连接器件包括坐式导柱， 所述坐式导柱的下端贴装在当前 绝缘层上表面，上端穿过至少另一个绝缘层的通孔到达另一个功能层并与另一个功能层 中的所述电子器件连接。
所述水平型电子连接器件还包括由多根导线集成的导线排。
所述垂直型电子连接器件还包括由多根坐式导柱集成的坐式导柱阵列。
所述电子器件还包括有源电子器件； 所述有源电子器件包括晶体管、 集成电路、 芯 片与芯片模块。
所述电子器件还包括无源电子器件； 所述无源电子器件包括电阻、 电容、 电感。 所述绝缘层、 所述封装层的绝缘材料为 ABS、 PC、 PLA或光敏树脂。
所述电子器件的引脚上设置有检测点。
一种基于 3D打印的封装基板的制造方法， 包括以下步骤： 步骤 （1 )、 编写分层打 印程序： 根据功能层中电子器件的功能与结构， 确定绝缘层、 功能层、 封装层的立体结 构， 编写针对所述绝缘层、 所述封装层的分层打印程序； 步骤 （2)、 打印绝缘层： 使用 3D打印机打印所述绝缘层； 步骤（3)、装贴功能层： 在所述绝缘层的上表面装贴电子器 件； 所述电子器件包括电子连接器件； 所述电子连接器件包括水平型电子连接器件， 所 述水平型电子连接器件包括导线； 步骤 （4)、 水平互连： 采用水平互连技术， 用所述导 线将同一功能层中的其他电子器件水平连接； 步骤 （5)、 打印封装层： 使用 3D打印机 打印所述电子连接器件之间的空间所构成的所述封装层； 步骤 （6)、 压合所述绝缘层、 所述封装层。
所述步骤（1 ) 中， 所述封装基板包括多层绝缘层、 功能层、 封装层； 所述步骤（3 ) 中， 所述电子连接器件包括垂直型电子连接器件， 所述垂直型电子连接器件包括坐式导 柱； 所述步骤 （4 ) 中还用所述导线将同一功能层中的其他电子器件与其他层中的坐式 导柱连接； 重复进行所述步骤 （2 ) 至所述步骤 （6 ) 以获得所述步骤 （1 ) 中确定的层 数。
所述步骤（3 ) 中的垂直型电子连接器件采用由多根坐式导柱集成的坐式导柱阵列， 所述水平型电子连接器件采用由多根导线集成的导线排。
在步骤 （3 ) 中的所述电子器件的引脚上设置有检测点； 所述步骤 （4) 中， 导线与 同一功能层中的其他电子器件的连接采用焊接， 焊接后， 用两支测试探针分别与焊接点 丽后的 w个检测点连接， 检测所坯焊接点的连接状况； 如果发现焊接缺陷， 对所坯焊接 点实时进行补焊。
本发明与现有技术对比所具有的有益效果是：
1、 在现有封装基板中， 通过金属化导孔实现布线层之间的垂直互连； 在覆铜板上 经化学蚀刻形成布线层， 采用引线连接技术实现无源 /有源电子器件的 I/O管脚与布线 层上的焊盘之间的水平互连， 这是现有封装基板解决互连的基本技术手段。
布线层的制造涉及光成像、 图形转移、 化学蚀刻、 数控钻孔 /激光打孔、 棕化、 孔 金属化、 电镀、 清洗、 干燥、 压合、 通断测试等许多复杂技术， 其制造过程有三四十道 工序， 不少工序又包括了一二十道子工序。 大量复杂的设备配置成流水线， 以串行作业 方式完成这些工序。
如此众多的工序需要许多贵重的高精度 CNC设备， 例如， 激光光绘机、 CNC钻床 / 铣床、 全自动电镀线、 全自动光学检测系统、 多层定位系统、 各种各样的专用测试仪器 等。
如此众多的工序还涉及众多辅助设备， 例如， 纯水、 污水处理站、 消防等多个辅助 设备系统。 这些辅助设施约占总投资的 30%。
如此众多的工序还需使用到数百种物料和辅料， 如干膜、 覆铜板、 各种化学药品、 化学添加剂、 钻头、 铣刀、 特种胶带等。
因而， 现有封装基板的技术体系为 "五多"（多个学科、 多种技术、 多道工序、 多 种设备、 多种物料）， 其产业链耗资巨大， 并对环境产生严重污染。 现有封装基板的企 业成为资金大户、 技术大户、 劳动力大户、 更是污染大户、 耗能大户、 用水大户。
由此可见， 在现有封装基板的制造技术中， 生产工序多， 串行作业且重复加工工作 量大、 材料消耗大、 废液排放高、 环保压力重， 使现有封装基板成为一个投资大、 效率 低、 污染重、 资源消耗高的产业。
2、 本申请改变了封装基板 (多层线路板）的现有生产方式与制造技术。
3D打印技术开创了设计、 制造的新观念。
3D打印技术的一个突出优点是，可实现由功能梯度材料构成的零部件，可直接制造 任意复杂结构的零部件。特别是， 由于内部具有复杂的立体结构导致丧失可制造性的产 品， 或必须拆分才具有可制造性的产品， 可用 3D打印技术直接制造。 封装基板 (多层线 路板）正是这样的产品。
本申请基于 3D打印技术， 从两方面重新审视现有封装基板的内部结构及布线层的 制造方法。
一是重新审视现有封装基板 (多层线路板）的内部结构，将封装基板 (多层线路板）的 主体视为具有复杂立体结构的绝缘层与封装层， 封装层内部埋置的电子器件构成功能 层； 二是重新审视现有布线层的制造方法， 将导线、 导柱、 焊盘及其不同结构的组合件 视为电子连接器件， 并予以标准化， 由第三方以多种方法制造。
这些新观念改变了封装基板 (多层线路板）的现有生产方式与制造技术。
1 )、 本申请改变了封装基板 (多层线路板）的现有生产方式 在现有封装基攸（多层线路攸）中， 制造布线层的儿于所有工)予， 包拈布线层设计、 光成像、 图形转移、 化学蚀刻、 打孔、 孔金属化、 电镀、 清洗、 干燥等， 都分散于各个 企业， 而每个企业又采用非标准化的流水线进行串行作业。 从宏观上看， 整个行业的生 产方式实质上仍然是作坊式的。 这种作坊式的串行生产方式贯彻其全部发展史。
本申请首次将导线、 导柱、 焊盘及其不同结构的组合件定义为标准化的电子连接器 件。
这些电子连接器件可由第三方以多种方法制造，从而将现有封装基板 (多层线路板) 的作坊式串行生产方式转变为专业化、标准化的并行生产方式，在降低投资、提高效率、 减少污染、 节约资源等方面产生显著效益。
2)、 本申请彻底改变了封装基板 (多层线路板）的现有制造技术及其产业链 互连与封装是构建电子产品的基础。 封装基板是互连与封装的融合。
从 3D打印技术来看， 封装基板 (多层线路板)可视为由绝缘层、 功能层、 封装层依 次逐层叠加而成的电子功能部件， 其制造技术的核心就是两种互连技术， 一是不同功能 层中的电子器件之间的垂直互连， 二是同一功能层中的电子器件之间的水平互连。
众所周知， 垂直互连技术， 特别是微孔制造技术是现有封装基板 (多层线路板）的核 心制造技术。
本申请采用 3D打印技术制造绝缘层与封装层， 不需要覆铜板制造技术。 本申请提 出一种直接互连技术， 采用标准化的电子连接器件坐式导柱 （坐式导柱阵列）实现不同 功能层中的电子器件之间的垂直互连， 采用标准化的电子连接器件导线 （导线排）实现 同一功能层中的电子器件之间的水平互连。
因而， 本申请取消了制造布线层的现有技术中的几乎所有工序， 不需要覆铜板制造 技术， 也不需要微孔制造技术， 彻底改变了封装基板 (多层线路板）的现有制造技术及其 产业链。
3、 在本申请中， 3D打印技术只用于制造绝缘层与封装层。 本申请将现有布线层制 造技术简化为同一功能层中的电子器件之间的水平互连， 从而避免了采用 3D打印技术 制造细导线、 细间距、 高精度的布线层所存在的问题， 具有很好的工业适用性。
4、增加层数是封装基板 (多层线路板)微型化的最适宜的办法。然而，在封装基板 (多 层线路板）的现有技术体系中， 由于分别制造布线层， 增加层数导致合格率显著降低与 成本大幅提升， 迫使细孔径、 细导线、 细间距、 高精度的高密度互连成为封装基板的主 流发展方向， 线宽、 孔径等成为技术水平的代表， 微孔制造技术成为关键技术。
本申请提出一种直接互连技术，微孔制造技术不再是制约封装基板 (多层线路板)微 型化的技术瓶颈， 增加层数成为封装基板 (多层线路板)微型化的基本技术手段， 可显著 降低封装基板 (多层线路板）的制造成本。
5、 本申请中的电子连接器件采用专业化、 标准化的工业生产， 通过老化、 振动、 检测等工艺措施， 其可靠性之高， 远非现有布线层所能比。 与覆钢攸上化学蚀刻的布线、 电镄的金属化导扎等现有布线层相比， 本甲谞中的电 子连接器件可采用种种具有良好电气性能与可制造性的材料，从而减少电路损耗和信号 传输延迟。
6、 封装基板 (多层线路板）的现有制造技术不能实时检测电气互连的通断状态， 只 能实施离线检测， 且检测技术复杂， 成本很高。
本申请以极其简单的技术手段解决了电气互连的实时检测问题， 降低了成本， 提高 了可靠性。
7、 本申请采用 3D打印技术， 可以制造具有复杂立体结构的绝缘层与封装层， 以适 应三维封装的发展。
8、 本申请采用 3D打印技术制造封装基板 (多层线路板）， 在单件、 小批量方面具有 突出的优势。 另一方面， 与封装基板 (多层线路板） 现有制造技术中许多贵重的高精度 设备相比， 工业级 3D打印机是极为便宜的， 因而可组成大规模的制造阵列， 对封装基 板 (多层线路板)进行大规模、 低成本的工业化生产。 附图说明 图 1为本发明一种具体实施方式的结构图；
图 2为本发明具体实施方式制造方法的流程图。 具体实施方式 本申请在技术背景中已说明， 不再区分多层线路板与封装基板。 本申请将多层线路 板视为内部未埋置无源 /有源电子器件的封装基板。 因而， 在本申请中， 封装基板包括 线路板， 特别是多层线路板。 无源电子器件包括电阻、 电容、 电感等， 有源电子器件包 括晶体管、 集成电路、 芯片与芯片模块等。
3D打印技术开创了设计、 制造的新观念。
3D打印技术的一个突出优点是，可实现由功能梯度材料构成的零部件，可直接制造 任意复杂结构的零部件。特别是， 由于内部具有复杂的立体结构导致丧失可制造性的产 品， 或必须拆分才具有可制造性的产品， 可用 3D打印技术直接制造。 封装基板正是这 样的产品。
从 3D打印技术的观点来看， 封装基板的主体结构为立体结构的绝缘层与封装层。 封装层中埋置由电子器件构成的功能层。 采用 3D打印技术制造绝缘层， 不需要覆铜板 制造技术。
绝缘层中充满金属或填充导电胶的导孔， 本申请称之为导电柱， 简称导柱。 导柱用 于不同功能层中的电子器件之间的垂直互连。
同一封装层中的无源 /有源电子器件， 通过导线、 焊盘实现水平互连。 本甲谞迸 ffi将导线、 导枉、 焊盘及其小问结构的组合仵称 Z为电于连接器仵。 湔入 /输出引线则是一种与外部互连的电子连接器件。
在这一定义中， 电子连接器件是一种实现互连的电子器件。 在本申请中， 电子连接 器件与电阻、 电容、 电感、 晶体管、 集成电路、 芯片与芯片模块等无源 /有源电子器件 处于同等地位， 只是功能不同罢了。
如同插头 /插座、 螺栓 /螺母等标准化机械连接零件， 以及电阻、 电容等标准化无源 电子器件一样， 导线、 导柱、 焊盘等电子连接器件可以标准化， 并采用专业化生产事先 制造出来。 例如， 电子连接器件的材质 （金、 铜、 铝）、 线径、 线长都标准化， 供设计 封装基板时选用。 同样， 导柱、 焊盘的尺寸也予以标准化。
导线、 导柱、 焊盘等定义为独立的标准化的电子连接器件， 从而与现有布线层及其 制造技术完全分离。 因而， 有别于在覆铜板上通过光刻、 化学蚀刻、 打孔、 孔金属化、 电镀来制造导线、 焊盘、 金属化导孔的流水作业， 可采用其他技术 （例如， 机械加工、 激光蚀刻） 通过专业化生产来制造导线、 导柱、 焊盘等电子连接器件。
与覆铜板上化学蚀刻的布线、 电镀的金属化导孔等现有布线层相比， 本申请中的电 子连接器件可采用种种具有良好电气性能与可制造性的材料，从而减少电路损耗和信号 传输延迟。这些电子连接器件还可通过老化、振动、检测等工艺措施， 提高其可靠性高。
导线、 导柱、 焊盘可组合成具有不同结构的电子连接器件。
例如，导柱与焊盘可组合为一种坐式导柱。导柱为上小下大的圆锥，底部带有焊盘； 焊盘既有利于导柱的定位 /装贴， 又为导线提供焊接面。 坐式导柱的尺寸， 例如， 材质、 高度、 上 /下直径、 焊盘的直径与厚度均标准化。
多个坐式导柱还可构成阵列或采用载带封装， 其阵列模式、 间距均标准化。
坐式导柱、 坐式导柱阵列用于不同功能层中的电子器件之间的垂直互连， 可称之为 垂直型电子连接器件。
相应于坐式导柱阵列， 多股导线可组合成导线排， 其中， 导线的两端可带焊盘或不 带焊盘， 可采用卷带或载带封装。 导线可以为丝材或板材， 线径或线宽 /线厚、 线长、 股数与间距都标准化。
导线、 导线排用于同一功能层中的电子器件之间的水平互连， 可称之为水平型电子 连接器件。
本申请将埋置于封装层中的电子器件称之为功能层。 功能层、 封装层、 绝缘层组成 封装基板的核心。 封装基板的层数指的是功能层的层数。 一般来说， 封装基板的层数为 2层或 2层以上。
因而， 基于 3D打印技术， 本申请将封装基板定义如下：
所谓封装基板是由绝缘层、 功能层、 封装层依次叠加而成的电子功能部件。
封装层位于绝缘层之上， 功能层埋置于封装层中并处于绝缘层的上表面。
功能层由互连的电子器件构成； 电子器件包括无源电子器件、 有源电子器件、 电子 连接器件。 无源电子器件包括电阻、 电容、 电感； 有源电子连接器件包括晶体管、 集成 电路、芯片与芯片模块； 电子连接器件包括水平型电子连接器件、垂直型电子连接器件; 水千型电于连接器仵用十问一功能层中的电于器仵 Z 1」的水千 连， ¾直型电于连接器 件用于不同功能层中的电子器件之间的垂直互连。
封装层由填充于功能层中的绝缘材料构成， 用于电子器件之间的电气绝缘与支撑。 绝缘层由绝缘材料构成， 用于功能层之间的电气绝缘； 绝缘层中设置通孔， 通孔中 埋置垂直型电子连接器件。
此外， 封装基板还有底层、 顶层。
上述定义说明， 如果封装基板的顶层安装无源 /有源电子器件， 且功能层中都没有 无源 /有源电子器件， 仅有电子连接器件， 封装基板则退化为多层线路板； 进而， 如果 多层线路板中只有一层功能层， 多层线路板则退化为单面线路板。
封装基板的顶层可安装也可不安装无源 /有源电子器件。 如果封装基板的顶层安装 无源 /有源电子器件， 打印顶层时， 对于无源 /有源电子器件的 I/O管脚与电子连接器件 之间的连接部位不能打印绝缘材料，而应留有开孔， 以便用户安装焊接电子器件。此外， 在顶层上还应制作一层图标层即一层文字与符号， 以标示无源 /有源电子器件在顶层上 的安装位置。
在常规线路板中， 空气扮演了封装层的角色， 布线层与绝缘基板之间的可靠连接主 要取决于覆铜板制造技术。 对于单面线路板与多层线路板， 本申请基于 3D打印技术， 不需要覆铜板制造技术， 因而， 顶层的电子连接器件与绝缘层之间的可靠连接由封装层 提供。
底层、 顶层均属于常规技术。
在现有封装基板中， 底层、 顶层、 绝缘层一般为平板结构。 采用 3D打印技术的突 出优点是， 可以制造具有复杂立体结构的底层、 顶层、 绝缘层与封装层， 还可打印功能 不同、 材料不同的梯度结构， 以适应三维封装的发展。 例如， 绝缘层中埋置坐式导柱的 通孔为上小下大的圆锥孔， 在打印过程中围绕坐式导柱逐层生成， 对精度的要求与制造 复杂性远低于现有封装基板中的微孔制造技术； 绝缘层的上表面为带有凹槽、 凸块、 台 阶的复杂曲面， 等等。 这些复杂立体结构有利于处理电磁兼容与散热问题， 还有利于电 子器件的定位 /装贴， 不必进行额外的底部填充。
上述定义揭示，绝缘层与封装层的立体结构及其制造方法是封装基板的关键技术之 一。 这正是 3D打印技术的优势。 因而， 对于这种基于 3D打印的封装基板， 制造绝缘层 与封装层的基本任务是， 根据封装基板的层数以及功能层中电子器件的功能与结构， 确 定绝缘层与封装层的立体结构， 编写绝缘层与封装层的分层打印程序。
众所周知， 绝缘层与封装层的 3D打印， 无源 /有源电子器件、 电子连接器件的拾取 /定位 /装贴 /连接等均为常规技术。 因而， 对于 3D打印技术来说， 封装基板制造技术的 核心就是两种互连技术， 一是不同功能层中的电子器件之间的垂直互连； 二是同一功能 层中的电子器件之间的水平互连。
在现有封装基板中， 通过金属化导孔实现布线层之间的垂直互连； 在覆铜板上经化 学蚀刻形成布线层， 采用引线连接技术实现无源 /有源电子器件的 I/O管脚与布线层上 的焊盘之间的水平互连， 这是现有封装基板解决互连的基本技术手段。 在现有封装基攸中， 布线层中埋置的尤源 /有源电于器仵的 I/O営脚与布线层上的 焊盘之间的水平互连技术， 一般称之为引线连接技术。 常用的引线连接技术有丝材键合
(Wire Bonding, WB)技术、 载带自动键合技术（Tape Automated Bonding, TAB)、 梁引 线技术 (Beam Lead Bonding, BLB)， 这些引线连接技术必须也只能用引线 （金线、 铜线、 铝线） 进行水平互连。 倒装芯片技术 (Fl ip Chip Bonding, FCB)则采用凸点互连 （bump interconnection) , 用于倒装芯片中数百个 I/O 管脚与基板的垂直互连。 其中， 铜柱 (Cu-pi l lar Bump) 互连已成为凸块互连技术的主流。 所谓铜柱互连指的是， 以高宽比 大于 1 ： 1的铜柱取代锡铅凸块 (Solder Bump) , 实现芯片与基板之间的垂直互连。
本实施方式中， 将凸点互连予以推广， 采用坐式导柱 （坐式导柱阵列）用于不同功 能层中的电子器件之间的垂直互连， 特别是相邻功能层中的电子器件之间的垂直互连。
本实施方式将坐式导柱（坐式导柱阵列）定义为独立的标准化的电子连接器件， 从 而为 3D打印技术提供了审视封装基板制造技术的新视野。
这样一来，封装基板中的互连问题便简化为同一功能层中的电子器件之间的水平互 连问题， 其模式只有两种： 一是无源 /有源电子器件的 I/O管脚与坐式导柱 （坐式导柱 阵列） 之间的水平互连， 二是无源 /有源电子器件的 I/O管脚之间的水平互连。
本申请将引线连接技术予以推广， 不是通过化学蚀刻的布线， 而是通过标准化的电 子连接器件导线 （导线排） 实现上述两种水平互连模式。
本申请将上述互连方法称之为直接互连技术。
增加层数是封装基板微型化的最适宜的办法。然而，在现有封装基板的技术体系中， 由于分别制造布线层， 增加层数导致合格率显著降低与成本大幅提升， 迫使细孔径、 细 导线、 细间距、 高精度的高密度互连成为封装基板的主流发展方向， 线宽、 孔径等成为 技术水平的代表， 微孔制造技术成为关键技术。
本申请所提出的直接互连技术不需要微孔制造技术。 因而， 微孔制造技术不再是制 约封装基板微型化的技术瓶颈， 增加层数成为封装基板微型化的基本技术手段。
本实施方式的坐式导柱， 其结构与倒装芯片技术中的铜柱类似。 坐式导柱（坐式导 柱阵列） 可采用铜或铜合金。 特别是， 与倒装芯片技术中的铜柱相比， 铜合金坐式导柱 (坐式导柱阵列）更容易制造， 综合性能更好， 从而减少电路损耗和信号传输延迟。 作 为独立的标准化的电子连接器件， 坐式导柱 （坐式导柱阵列）、 导线 （导线排） 可以由 第三方以多种方法制造。
焊接是实现水平互连最常见的技术手段。 激光微焊接 （Laser Micro Welder) 快速 和精确， 灵活简便， 不需要真空环境， 无放射性， 无污染， 是一种非接触式电气连接技 术， 属于革命性的焊接新工艺。常用的工业激光的波长为 1064nm， 其对铜的反射率高达 90%， 难以实现铜的连接。 而 532 nm波长的激光 （绿激光） 能够持续渗入铜内， 稳定地 实现铜的连接。
对于不同的封装基板 （刚性有机封装基板、 柔性封装基板、 陶瓷封装基板等）， 绝 缘层的材料不同， 3D打印技术也不同。例如， 对于柔性封装基板， 绝缘层的材料为 ABS、
PC、 PLA或光敏树脂， 3D打印技术可选用熔丝沉积成型技术或光刻成型技术、 数字光处 理成型扠术、 紫外线成型扠术。 对十陶瓮封装基攸， 絶缘层的材科为陶瓮粉禾， 3D打印 技术可选用三维印刷成型技术、 选区激光烧结技术。
在具体优选实施方式中， 本申请采用工业级 3D打印机； 以 ABS、 PC、 PLA作为绝缘 层与封装层的材料， 以熔丝沉积成型技术作为 3D打印成型技术， 或者以光敏树脂作为 绝缘层与封装层的材料， 以紫外线成型技术作为 3D打印成型技术； 以铜或铜合金坐式 导柱 （坐式导柱阵列） 作为垂直互连的电子连接器件， 以导线 （导线排） 作为水平互连 的电子连接器件； 水平互连技术采用绿激光焊接技术。 图 1为一种基于 3D打印的封装基板内部结构的剖面示意图。
如图 1所示的一种封装基板， 包括三层绝缘层 1、 两层封装层 2、 两层功能层； 第 一层的功能层包括有第一层有源 /无源电子器件 3，作为水平型电子连接器件的第一层导 线 61， 作为垂直型电子连接器件的坐式导柱 （或坐式导柱阵列） 5; 第二层功能层包括 第二层有源 /无源电子器件 4， 第二层导线 62。 坐式导柱 5下端贴装在第一层的绝缘层 的下表面， 上端穿过第二层绝缘层的通孔。 第一层功能层中， 有源 /无源电子器件 3 的 I/O管脚 31通过第一导线 61与坐式导柱 5下端焊接；第二功能层中，有源 /无源电子器 件 4 的 I/O管脚 41通过第二导线 62与坐式导柱 5的上端焊接。最下面一层的绝缘层可 作为封装基板的底层。 最上面一层的绝缘层可作为封装基板的顶层。 参看图 2所示， 上述封装基板的制造方法， 包括以下步骤：
步骤（1 )、 编写分层打印程序： 根据封装基板的层数以及功能层中电子器件的功能 与结构， 确定各绝缘层、 各功能层、 各封装层的立体结构， 编写针对各绝缘层、 封装层 的分层打印程序。
步骤 （2)、 使用 3D打印机打印第一层绝缘层。
步骤 （3)、 装贴第一层功能层： 在第一层绝缘层的上表面装贴第一层有源 /无源电 子器件 3、 坐式导柱 5、 导线 61。
步骤 （4)、 第一层功能层水平互连： 采用水平互连技术， 用导线 61将第一层功能 层中的有源 /无源电子器件 3与坐式导柱 5的下端水平连接。
步骤 （5)、 打印第一层封装层： 使用 3D打印机打印填充第一层功能层中各电子连 接器件之间的空隙， 构成第一层封装层。
步骤 （6)、 压合上述第一层绝缘层、 第一层功能层、 第一层封装层。
步骤 （7)、 使用 3D打印机打印第二层绝缘层。
步骤 （8)、 装贴第二层功能层： 在第二层绝缘层的上表面装贴第二层有源 /无源电 子器件 4、 导线 62。
步骤 （9)、 第二层功能层水平互连： 采用水平互连技术， 用导线 62将第二层功能 层中的有源 /无源电子器件 4与坐式导柱 5的上端水平连接。
步骤（10)、 打印第二层封装层： 使用 3D打印机打印填充第二层功能层中各电子连 接器件之间的空隙， 构成第二层封装层。 歩骤 （11 )、 使用 3D打印机打印弟三层絶缘层作为封装基攸的」贝层。
步骤 （12)、 压合第二绝缘层、 第二层功能层、 第二层封装层。
坐式导柱 （坐式导柱阵列） 采用铜或铜合金， 水平互连技术采用绿激光焊接技术。 其他实施中， 如果封装基板的层数在 2层以上， 则步骤（2 )至步骤（6 )重复多次， 直至所要求的层数。 在现有封装基板中， 采用金属化导孔实现布线层之间的垂直互连。 通过电镀制造金 属化导孔， 其制造过程是完全封闭的， 不能在制造过程中进行实时通 /断检测。
从上述步骤可知， 在本申请所提出的制造方法中， 先在绝缘层上装贴电子器件， 然 后采用绿激光焊接， 实现坐式导柱 （坐式导柱阵列） 与无源 /有源电子器件的 I/O管脚 之间的水平互连。 因而， 本申请的制造过程是完全开放的。 这就为封装基板的互连状态 进行实时检测创造了条件。
因而， 对于同一功能层中的电子器件之间的互连状态， 本申请所提出的制造方法可 以采用极为简单的技术手段实现通 /断状态的实时检测， 其技术方案如下。
在每个电子器件的引脚上设置 1个检测点； 在水平焊接连接电子器件时， 进行实时 通 /断检测。通 /断状态的实时检测如同通常的万用表检测通断那样， 将 2支测试探针分 别与焊接点前后 2个检测点连接， 检测 2个检测点之间的焊接的电阻值， 从而判断其通 /断， 并根据电阻值的大小判断连接状态。 如果连接点断路或电阻值过大， 可通过绿激 光对连接点实时进行补焊， 从而提高成品率。
显然， 如果两支测试探针由 3D打印机控制， 编写分层打印程序时， 同时编写测试 探针的控制程序， 则上述实时检测过程自动进行。 在本申请的上述具体优选实施方式中， 以坐式导柱 /坐式导柱阵列作为垂直互连的 电子连接器件， 以导线 /导线排作为水平互连的电子连接器件， 以 ABS、 PC、 PLA或光敏 树脂作为绝缘层与封装层的材料， 以熔丝沉积成型技术或紫外线成型技术作为 3D打印 成型技术， 以绿激光焊接作为水平互连技术详细地说明了本申请的技术方案， 不能认定 本申请的具体实施只局限于这些说明。特别是， 对于本申请所属技术领域的普通技术人 员来说， 在不脱离本申请构思的前提下， 对于不同结构的电子连接器件， 不同材料的绝 缘层与封装层及其相应的 3D打印成型技术， 还可以做出若干简单推演或替换， 都应当 视为属于本申请的保护范围。

Claims

权 利 要 求 书
1、 一种基于 3D打印的封装基板， 其特征在于： 包括绝缘层、 功能层、 封装层； 所述绝缘层由 3D打印机采用绝缘材料打印构成；
所述封装层位于所述绝缘层之上， 所述功能层埋置于所述封装层中；
所述功能层由互连的电子器件构成； 所述电子器件包括电子连接器件； 所述电子连 接器件包括水平型电子连接器件； 所述水平型电子连接器件包括导线， 所述导线连接同 一功能层中的两个或多个其他电子器件；
所述电子器件之间的空间由 3D打印机采用绝缘材料打印填充从而构成所述封装层。
2、 如权利要求 1所述的基于 3D打印的封装基板， 其特征在于： 所述封装基板包括 多层绝缘层、 功能层、 封装层； 所述电子连接器件包括垂直型电子连接器件， 所述垂直 型电子连接器件包括坐式导柱， 所述坐式导柱的下端贴装在当前绝缘层上表面， 上端穿 过至少另一个绝缘层的通孔到达另一个功能层并与另一个功能层中的所述电子器件连 接。
3、 如权利要求 2所述的基于 3D打印的封装基板， 其特征在于： 所述水平型电子连 接器件还包括由多根导线集成的导线排。
4、 如权利要求 2所述的基于 3D打印的封装基板， 其特征在于： 所述垂直型电子连 接器件还包括由多根坐式导柱集成的坐式导柱阵列。
5、 如权利要求 3所述的基于 3D打印的封装基板， 其特征在于： 所述垂直型电子连 接器件还包括由多根坐式导柱集成的坐式导柱阵列。
6、 如权利要求 2所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件还包 括有源电子器件； 所述有源电子器件包括晶体管、 集成电路、 芯片或芯片模块。
7、 如权利要求 2所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件还包 括无源电子器件； 所述无源电子器件包括电阻、 电容或电感。
8、 如权利要求 6所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件还包 括无源电子器件； 所述无源电子器件包括电阻、 电容或电感。
9、 如权利要求 5所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件还包 括有源电子器件； 所述有源电子器件包括晶体管、 集成电路、 芯片或芯片模块； 所述电 子器件还包括无源电子器件； 所述无源电子器件包括电阻、 电容或电感。
10、 如权利要求 1所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件的 引脚上设置有检测点。
11、 如权利要求 2所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件的 引脚上设置有检测点。
12、 如权利要求 5所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件的 引脚上设置有检测点。
13、 如权利要求 8所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件的 引脚上设置有检测点。
14、 如权利要求 9所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件的 引脚上设置有检测点。
15、 如权利要求 7所述的基于 3D打印的封装基板， 其特征在于： 所述电子器件的 引脚上设置有检测点。
16、 一种基于 3D打印的封装基板的制造方法， 其特征在于， 包括以下步骤： 步骤 （1 )、 编写分层打印程序： 确定绝缘层、 功能层、 封装层的立体结构， 编写针 对所述绝缘层、 所述封装层的分层打印程序；
步骤 （2)、 打印绝缘层： 使用 3D打印机打印所述绝缘层；
步骤（3)、 装贴功能层： 在所述绝缘层的上表面装贴电子器件； 所述电子器件包括 电子连接器件； 所述电子连接器件包括水平型电子连接器件， 所述水平型电子连接器件 包括导线；
步骤（4)、 水平互连： 采用水平互连技术， 用所述导线将同一功能层中的其他电子 器件水平连接；
步骤 （5)、 打印封装层： 使用 3D打印机打印填充所述电子连接器件之间的空间， 从而构成所述封装层；
步骤 （6)、 压合所述绝缘层、 所述封装层。
17、 如权利要求 16所述的基于 3D打印的封装基板的制造方法， 其特征在于： 所述步骤 （1 ) 中， 确定所述封装基板包括多层绝缘层、 功能层、 封装层； 所述步 骤 （3 ) 中， 所述电子连接器件包括垂直型电子连接器件， 所述垂直型电子连接器件包 括坐式导柱； 所述步骤 （4 ) 中还用所述导线将同一功能层中的其他电子器件与其他层 中的坐式导柱连接； 重复进行所述步骤 （2 ) 至所述步骤 （6 ) 以获得所述步骤 （1 ) 中 确定的层数。
18、 如权利要求 16所述的基于 3D打印的封装基板的制造方法， 其特征在于， 步骤 ( 3 ) 中的所述电子器件的引脚上设置有检测点； 所述步骤 （4) 中， 导线与同一功能层 中的其他电子器件的连接采用焊接， 焊接后， 用两支测试探针分别与焊接点前后的两个 检测点连接， 检测所述焊接点的连接状况； 如果发现焊接缺陷， 对所述焊接点实时进行 补焊。
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