WO2014205797A1 - 一种辨识方法、装置、系统及基站 - Google Patents

一种辨识方法、装置、系统及基站 Download PDF

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Publication number
WO2014205797A1
WO2014205797A1 PCT/CN2013/078410 CN2013078410W WO2014205797A1 WO 2014205797 A1 WO2014205797 A1 WO 2014205797A1 CN 2013078410 W CN2013078410 W CN 2013078410W WO 2014205797 A1 WO2014205797 A1 WO 2014205797A1
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Prior art keywords
signal
unit
base station
output
feedback
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PCT/CN2013/078410
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English (en)
French (fr)
Inventor
叶四清
肖宇翔
李珽
尤览
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201380000843.5A priority Critical patent/CN103650444B/zh
Priority to PCT/CN2013/078410 priority patent/WO2014205797A1/zh
Publication of WO2014205797A1 publication Critical patent/WO2014205797A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to an identification method, apparatus, system, and base station. Background technique
  • FIG. 1 is a schematic diagram of the composition of the identification system in the prior art.
  • the whole system includes a digital predistortion unit, a linear compensation unit, a linear identification unit, a transmitting unit, a feedback receiving unit, a fractional delay and amplitude relative unit, a subtraction unit and an integer delay unit.
  • the digital predistortion unit, the linear compensation unit and the transmitting unit form a transmitting channel.
  • the downlink signal of the base station is input into the integer delay unit, and the other part is input to the digital predistortion unit.
  • the downlink signal output of the base station is converted to a transmitting signal by the transmitting unit, a part of the transmitting signal is outputted to the wireless space by the transmitting unit, and a part is output to the feedback receiving unit, and converted into a first feedback signal by the feedback receiving unit and output to the decimal delay and
  • the amplitude is relatively homogeneous, the fractional delay and the amplitude relative unit receive the downlink signal of the base station from the delay of the integer delay unit, delay the delay of the first feedback signal outputted by the feedback receiving unit, and then delay with the integer delay unit
  • the downlink signal amplitude of the base station is synchronously outputted to the linear identification unit and the subtraction unit, and the linear identification unit receives the linearly compensated base station downlink signal, and calculates a linear compensation coefficient according to the linearly compensated base station downlink signal and the amplitude-aligned second feedback signal.
  • the coefficient is sent to the linear compensation unit, and the linear compensation unit linearly compensates the downlink signal of the base station after the predistortion processing, and the subtraction unit receives the downlink signal of the base station delayed by the integer delay unit, and the second delay and the amplitude are aligned.
  • the feedback signal is subtracted from the downlink signal of the integer delay and the error signal is obtained and output to the digital predistortion unit.
  • the digital predistortion unit calculates the predistortion coefficient according to the downlink signal and the error signal of the base station, and completes the digital predistortion processing of the downlink signal of the base station. , thereby reducing transmission distortion.
  • the loop used for pre-distortion processing the downlink signal of the base station is called a pre-distortion inner loop.
  • the digital pre-distortion unit, the linear compensation unit, the transmitting unit, the feedback receiving unit, the fractional delay and the amplitude are relative.
  • the loop formed by the unit and the subtraction unit is called a predistortion inner loop.
  • Linear compensation can include amplitude-phase equalization pre-compensation and Inphase and Quadrature (IQ) image distortion pre-compensation.
  • linear compensation effect is poor, there will be amplitude-phase equalization distortion or IQ image distortion, then the final calculation of the pre-distortion coefficient will result in Large errors or even algorithms do not converge, that is, the error increases or does not tend to zero. Therefore, the role of linear compensation is very important.
  • the effect of linear compensation mainly depends on the calculation of the linear compensation coefficient.
  • the linear compensation coefficient is calculated based on the linearly compensated base station downlink signal and the second feedback signal aligned with the integer delayed base station downlink signal.
  • the second feedback signal after the amplitudes includes linear distortion information of the predistortion inner loop. Since the linear identification accuracy of the pre-distorted inner loop signal is related to the bandwidth of the signal through the pre-distorted inner loop, the smaller the bandwidth of the signal passing through the pre-distorted inner loop, the lower the linear identification accuracy.
  • the downlink signal bandwidth of the base station varies with the service configuration. At the narrowest time, there may be only one Global System of Mobile communication (GSM) carrier.
  • GSM Global System of Mobile communication
  • the linear identification unit cannot effectively linearly recognize the digital predistortion inner loop, and then can not effectively linearly compensate the digital predistortion inner loop, thereby affecting the calculation of the predistortion coefficient, resulting in serious transmission distortion.
  • Embodiments of the present invention provide an identification method, device, system, and base station, which can perform good linear identification and compensation on signals of different bandwidths in a predistortion inner loop, improve system applicability, and reduce transmission distortion.
  • a first aspect of the embodiments of the present invention provides an identification method, which may include:
  • the second input signal includes linear distortion information of a predistortion inner loop for performing predistortion processing on the downlink signal of the base station, and a first input signal processed by the predistortion inner loop;
  • the second input signal is a second feedback signal generated after the first feedback signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the decimal delay.
  • the first feedback signal is a signal generated by the feedback receiving unit according to the received transmission signal of the received transmitting unit.
  • the second input signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the first feedback signal passes the fractional delay, and then the integer delay
  • the base station downlink signal is subjected to subtraction processing to remove the base station downlink signal information of the integer delay
  • the error signal generated after the first feedback signal is a signal generated by the feedback receiving unit according to the received transmission signal of the transmitting unit.
  • the transmitting signal is a signal that is converted and output by the transmitting unit according to the combining signal, where the The path signal is a signal that the adding unit adds the linearly compensated base station downlink signal output by the received linear compensation unit and the injection signal generated by the injection unit.
  • the bandwidth of the injection signal is greater than a bandwidth threshold K, and the bandwidth threshold is K is greater than zero.
  • a second aspect of the embodiments of the present invention provides an identification device, which may include:
  • a receiving module configured to receive an injection signal generated by the injection unit, use the injection signal as a first input signal for linear identification, and receive a second input signal, where the second input signal is used to perform downlink signal to the base station Linear distortion information of the predistortion processed inner ring of the predistortion and the first input signal processed by the predistortion inner loop;
  • a calculating module configured to calculate a linear compensation coefficient according to the first input signal and the second input signal received by the receiving module.
  • the second input signal is a second feedback signal generated after the first feedback signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the decimal delay.
  • the first feedback signal is a signal generated by the feedback receiving unit according to the received transmission signal of the received transmitting unit.
  • the second input signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the first feedback signal passes the fractional delay, and then the integer delay
  • the downlink signal of the base station is subjected to a subtraction process, and the error signal generated after the downlink signal information of the base station of the integer delay is removed, wherein the first feedback signal is a signal generated by the feedback receiving unit according to the received signal output by the received transmitting unit.
  • the transmitting signal is a signal that is converted and output by the transmitting unit according to the combining signal, where the The path signal is a signal that the adding unit adds the linearly compensated base station downlink signal output by the received linear compensation unit and the injection signal generated by the injection unit.
  • the bandwidth of the injection signal is greater than a bandwidth threshold K, and the bandwidth threshold K is greater than zero.
  • a third aspect of the embodiments of the present invention provides an identification system, which may include:
  • a linear identification unit configured to receive an injection signal, use the injection signal as a linearly recognized first input signal, and receive a second input signal, and calculate a linear compensation coefficient according to the first input signal and the second input signal
  • the second input signal includes linear distortion information of a predistortion inner loop for performing predistortion processing on the downlink signal of the base station, and a first input signal processed by the predistortion inner loop;
  • a first linear compensation unit configured to receive a downlink signal of the base station after the pre-distortion processing, and perform linear compensation on the downlink signal of the base station after the pre-distortion processing according to the linear compensation coefficient calculated by the linear identification unit;
  • An injection unit configured to output the injection signal
  • An adding unit configured to receive the injected signal and the downlink signal of the base station after linear compensation of the first linear compensation unit, add the injected signal and the downlink signal of the linearly compensated base station, and output the signal; Receiving the combined signal output by the adding unit, converting the combined signal into a transmitting signal and outputting;
  • a feedback receiving unit configured to receive a transmission signal output by the transmitting unit, convert the transmission signal into a first feedback signal, and output the signal;
  • a fractional delay and amplitude relative unit configured to receive an integer delay base station downlink signal and a first feedback signal output by the feedback receiving unit, delaying the first feedback signal by a fractional delay and the integer delay Aligning the amplitude and phase of the downlink signal of the base station to generate a second feedback signal and outputting;
  • An integer delay unit configured to receive the downlink signal of the base station, perform integer delay processing on the downlink signal of the base station, and output the result to the fractional delay and the amplitude relative unit;
  • a subtraction unit configured to receive the second feedback signal of the fractional delay and the amplitude of the unit output, and the base station downlink signal of the integer delay output by the integer delay unit, and the second feedback signal and the integer
  • the base station downlink signal of the integer delay output by the delay unit is subtracted, and the downlink signal information of the base station with the integer delay is removed to obtain an error signal and output;
  • a digital pre-distortion unit configured to receive an error signal output by the subtraction unit and a downlink signal of the base station, calculate a pre-distortion coefficient according to the error signal and the downlink signal of the base station, and use the pre-distortion coefficient to the base station
  • the downlink signal is predistorted and output to the first linear compensation Unit.
  • the second input signal is a second feedback signal of the fractional delay and the amplitude of the unit output, or an error signal output by the subtraction unit.
  • the integer delay unit is specifically configured to perform an integer number of clock cycles of the downlink signal of the base station. Delaying; the fractional delay and the amplitude matching unit are specifically configured to perform a fractional delay of a non-integer number of clock cycles on the first feedback signal output by the feedback receiving unit to enable the first feedback of the output of the feedback receiving unit The signal is aligned with the amplitude and phase of the base station downlink signal of the integer delay output by the integer delay unit.
  • system further includes:
  • a switch selection unit configured to receive an error signal output by the subtraction unit and the second feedback signal of the fractional delay and the amplitude of the unit output, and select the error signal or the second feedback signal to output to the Linear identification unit.
  • system further includes:
  • a second linear compensation unit configured to receive the second feedback signal of the fractional delay and the amplitude of the unit output, and the linear compensation coefficient calculated by the linear identification unit is output to the fractional delay and the amplitude of the unit
  • the second feedback signal is linearly compensated to generate a third feedback signal and output to the subtraction unit.
  • the first linear compensation unit and the digital pre-distortion Units are integrated or set separately.
  • a fourth aspect of the embodiments of the present invention provides an identification device, which may include:
  • the memory is configured to store a program executed by the processor
  • the processor is configured to receive an injection signal generated by the injection unit, use the injection signal as a first input signal for linear identification, and receive a second input signal, where the second input signal includes Linear distortion information of the predistortion processed inner pre-distortion ring and the first input signal processed by the predistortion inner loop; according to the received first input signal and the The second input signal calculates a linear compensation coefficient.
  • the second input signal is a second feedback signal generated after the first feedback signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the decimal delay.
  • the first feedback signal is a signal generated by the feedback receiving unit according to the received transmission signal of the received transmitting unit.
  • the second input signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the first feedback signal passes the fractional delay, and then the integer delay
  • the downlink signal of the base station is subjected to a subtraction process, and the error signal generated after the downlink signal information of the base station of the integer delay is removed, wherein the first feedback signal is a signal generated by the feedback receiving unit according to the received signal output by the received transmitting unit.
  • the transmitting signal is a signal that is converted and output by the transmitting unit according to the combining signal, where the The path signal is a signal that the adding unit adds the linearly compensated base station downlink signal output by the received linear compensation unit and the injection signal generated by the injection unit.
  • the bandwidth of the injection signal is greater than a bandwidth threshold K, and the bandwidth threshold is K is greater than zero.
  • a fifth aspect of the embodiments of the present invention provides a base station, which may include:
  • the first input signal that is, the injection signal, and the second input signal including the predistortion inner loop linear distortion information and the first input signal processed by the predistortion inner loop are received by receiving an input signal that can effectively linearly identify the system characteristic.
  • the calculation can obtain a more accurate linear compensation coefficient, so that the effect of linear identification and compensation is independent of the signal bandwidth of the digital predistortion unit output, which improves the applicability of the system; achieves good linear compensation for the output signal of the digital predistortion unit.
  • the error is calculated when the digital predistortion unit calculates the predistortion coefficient, and finally the transmission distortion is reduced.
  • Figure 1 is a schematic diagram of the composition of an existing identification system
  • FIG. 2 is a schematic flowchart of an identification method according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the composition of the first embodiment of the identification device of the present invention.
  • FIG. 4 is a schematic diagram of the composition of a first embodiment of the identification system of the present invention.
  • Figure 5 is a schematic diagram showing the composition of a second embodiment of the identification system of the present invention.
  • FIG. 6 is a schematic structural diagram of a third embodiment of the identification system of the present invention.
  • FIG. 7 is a schematic structural diagram of a fourth embodiment of the identification system of the present invention.
  • FIG. 8 is a schematic diagram of the composition of the second embodiment of the identification device of the present invention. detailed description
  • FIG. 2 is a schematic flowchart of an identification method according to an embodiment of the present invention.
  • the method may be applied to a linear identification unit of an identification system.
  • the method includes the following steps:
  • S201 Receive an injection signal generated by the injection unit, and use the injection signal as the first input signal for linear identification.
  • the digital predistortion unit has a bandwidth of less than one third of the maximum output bandwidth of the digital predistortion unit. If the predistortion inner loop is linearly compensated based on the base station downlink signal, since the input signal bandwidth varies with the base station service configuration, there may be only one GSM carrier at the narrowest time, that is, only 200 kHz, and the bandwidth of the digital predistortion unit output signal at this time. It can only be less than or equal to this bandwidth. Because the bandwidth is too narrow, the effective identification of the pre-distortion inner loop characteristics cannot be completed. In general, the larger the output bandwidth, the better the effective identification of the predistortion inner loop characteristics.
  • the bandwidth of the first input signal is greater than a bandwidth threshold K, where the bandwidth threshold K is greater than zero.
  • the value of the threshold K can be configured to be 0.8fs or more, where fs is the sampling rate of the digital predistortion unit through the signal, when the bandwidth value of the injected signal is greater than 0.8fs.
  • the injection signal can be called a broadband signal No., which facilitates linear identification and subsequent linear compensation.
  • the K is less than 0.8fs, the characteristics of the predistortion inner loop can be linearly recognized, but the identification efficiency and the identification accuracy are greatly reduced.
  • the amplitude of the injected signal is small, and the magnitude of the amplitude of the injected signal is close to the amplitude of the noise of the transmitting unit circuit, that is, the difference between the two is within a preset range, and even the amplitude of the injected signal is smaller than The magnitude of the noise of the transmit unit circuit.
  • the interference caused by the received injection signal to the downlink signal of the base station is basically negligible.
  • the second input signal includes linear distortion information of a pre-distorted inner loop for performing pre-distortion processing on the downlink signal of the base station, and a first input signal processed by the pre-distortion inner loop.
  • the second input signal includes linear distortion information of the predistortion inner loop and the first input signal processed by the predistortion inner loop.
  • the first input signal is not only used as a reference signal for linear identification, but also is added to the downlink signal of the base station after digital predistortion processing and linear compensation, and is output to the transmitting unit and processed by the predistortion inner loop. Therefore, linear distortion information including a predistortion inner loop and a first input signal subjected to the predistortion inner loop processing are included in the second input signal.
  • S203 Calculate a linear compensation coefficient according to the first input signal and the second input signal.
  • the injected signal that is, the first input signal is a wideband signal
  • the characteristic of the predistortion inner loop can be effectively linearly recognized, and a relatively accurate linear compensation coefficient is obtained, so that the digital predistortion unit output signal is well linearly compensated, so that When the digital predistortion unit calculates the predistortion coefficient, the error is small, and finally the transmission distortion is reduced. Because the injection signal is added, the effect of linear identification and compensation is independent of the signal bandwidth input by the digital predistortion unit, which improves the applicability of the system.
  • the second input signal may be a second feedback signal generated after the first feedback signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the decimal delay.
  • the first feedback signal is a signal generated by the feedback receiving unit according to the received transmission signal of the received transmitting unit.
  • the transmitting signal is a signal that the transmitting unit converts and outputs according to the combining signal.
  • the combining signal is a linearly compensated base station downlink signal output by the receiving unit and the injected signal generated by the injection unit, that is, the first input signal, and the output signal is added and outputted. signal of.
  • the second input signal signal is subjected to amplitude and phase alignment processing after the first feedback signal is subjected to a fractional delay, and is inversely processed with the integer delayed base station downlink signal, and then subtracted from the integer delayed base station downlink signal. And removing the error signal generated after the integer delayed base station downlink signal information.
  • the integer delay specifically indicates a delay of an integer number of clock cycles for the downlink signal of the base station; the decimal delay specifically indicates that the first feedback signal output by the feedback receiving unit is subjected to a fractional delay of a non-integer number of clock cycles.
  • the first feedback signal output by the feedback receiving unit is aligned with the amplitude and phase of the integer delayed base station downlink signal.
  • the second feedback signal is derived from the downlink signal of the base station
  • the second feedback signal includes information of a large number of downlink signals of the base station.
  • the amplitude of the injected signal is generally small, so the amplitude of the injected signal is also small in the second feedback signal, and the ratio of the downlink signal to the circuit noise is smaller than that of the base station, and the linear identification needs to be compared.
  • Long-term correlation accumulation increases the ratio of the injected signal relative to the base station downlink signal and circuit noise.
  • the amplitude of the downlink signal of the base station is much larger than the circuit noise.
  • the second feedback signal has a certain time difference from the downlink signal of the base station because it has undergone a series of processes. If the information of the downlink signal of the base station included in the received second feedback signal can be removed, the correlation accumulation time of the injected signal will be greatly shortened. The content of the downlink signal of the base station in the error signal obtained by the subtraction process has been removed, so that the correlation accumulation time of the ideal injected signal can be obtained.
  • the injection signal with a large amplitude can be received to obtain the linear compensation coefficient, and the correlation accumulation time can also be shortened.
  • the feedback signal of the downlink signal information of the base station can be directly used.
  • FIG. 3 is a schematic diagram of the composition of the first embodiment of the identification device of the present invention.
  • the device includes: a receiving module 100 and a computing module 200.
  • the receiving module 100 is configured to receive an injection signal generated by the injection unit, use the injection signal as a linearly recognized first input signal, and receive a second input signal, where the second input signal includes a linear distortion information of the predistortion inner loop of the signal subjected to predistortion processing and a first input signal processed by the predistortion inner loop;
  • the digital predistortion unit has an input signal, that is, the bandwidth of the downlink signal of the base station does not exceed one third of the maximum output bandwidth of the digital predistortion unit. If the predistortion inner loop is linearly compensated based on the base station downlink signal, since the input signal bandwidth varies with the base station service configuration, there may be only one at the narrowest time.
  • the GSM carrier that is, only 200 kHz, the bandwidth of the digital predistortion unit output signal can only be less than or equal to this bandwidth. Because the bandwidth is too narrow, the effective identification of the predistortion inner loop characteristic cannot be completed. In general, the larger the output bandwidth, the better the effective identification of the predistortion inner loop characteristics.
  • the bandwidth of the first input signal is greater than the bandwidth threshold K
  • the bandwidth threshold K is greater than 0.
  • the value of the threshold K is It can be configured to be 0.8fs or more, where fs is the sampling rate of the signal passing through the digital predistortion unit.
  • the bandwidth value of the injected signal is greater than 0.8fs
  • the injected signal can be called a wideband signal, which is beneficial for linear identification and subsequent Linear compensation.
  • the characteristics of the predistortion inner loop can be linearly recognized when K is less than 0.8 fs, but the identification efficiency and the identification accuracy are greatly reduced.
  • the amplitude of the injected signal is small, and the magnitude of the amplitude of the injected signal is close to the amplitude of the noise of the transmitting unit circuit, that is, the difference between the two is within a preset range, and even the amplitude of the injected signal is smaller than The magnitude of the noise of the transmit unit circuit.
  • the interference caused by the received injection signal to the downlink signal of the base station is basically negligible.
  • the second input signal includes linear distortion information of a pre-distorted inner loop for performing pre-distortion processing on the downlink signal of the base station, and a first input signal processed by the pre-distortion inner loop.
  • the second input signal includes linear distortion information of the predistortion inner loop and the first input signal processed by the predistortion inner loop.
  • the first input signal is not only used as a reference signal for linear identification, but also is added to the downlink signal of the base station after digital predistortion processing and linear compensation, and is output to the transmitting unit and processed by the predistortion inner loop. Therefore, linear distortion information including a predistortion inner loop and a first input signal subjected to the predistortion inner loop processing are included in the second input signal.
  • the calculation module 200 is configured to calculate a linear compensation coefficient according to the first input signal and the second input signal received by the receiving module.
  • the second input signal may be a second feedback signal generated after the first feedback signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the decimal delay.
  • the first feedback signal is a signal generated by the feedback receiving unit according to the transmitted signal output by the received transmitting unit.
  • the transmission signal is a signal that the transmitting unit converts and outputs according to the combining signal.
  • the combining signal is a linearly compensated base station downlink signal output by the receiving unit and the injected signal generated by the injection unit, that is, the first input signal, and the output signal is added and outputted. signal of.
  • the second input signal signal is subjected to amplitude and phase alignment processing after the first feedback signal is subjected to a fractional delay, and is inversely processed with the integer delayed base station downlink signal, and then subtracted from the integer delayed base station downlink signal. And removing the error signal generated after the integer delayed base station downlink signal information.
  • the integer delay specifically indicates a delay of an integer number of clock cycles for the downlink signal of the base station; the decimal delay specifically indicates that the first feedback signal output by the feedback receiving unit is subjected to a fractional delay of a non-integer number of clock cycles.
  • the first feedback signal output by the feedback receiving unit is aligned with the amplitude and phase of the integer delayed base station downlink signal.
  • the second feedback signal is derived from the downlink signal of the base station
  • the second feedback signal includes information of a large number of downlink signals of the base station.
  • the amplitude of the injected signal is generally small, so the amplitude of the injected signal is also small in the second feedback signal, and the ratio of the downlink signal to the circuit noise is smaller than that of the base station, and the linear identification needs to be compared.
  • Long-term correlation accumulation increases the ratio of the injected signal relative to the base station downlink signal and circuit noise.
  • the amplitude of the downlink signal of the base station is much larger than the circuit noise.
  • the second feedback signal has a certain time difference from the downlink signal of the base station because it has undergone a series of processes. If the information of the downlink signal of the base station included in the received second feedback signal can be removed, the correlation accumulation time of the injected signal will be greatly shortened. The content of the downlink signal of the base station in the error signal obtained by the subtraction process has been removed, so that the correlation accumulation time of the ideal injected signal can be obtained.
  • the transmission channel since there is no downlink signal input from the base station, it is possible to receive a large amplitude injection signal to obtain a linear compensation coefficient, which can also shorten the correlation accumulation time. At this time, the feedback signal without removing the downlink signal information of the base station can be directly used as the second input signal for linear identification.
  • FIG. 4 it is a schematic diagram of the composition of the first embodiment of the identification system of the present invention.
  • the system includes: a linear identification unit 1, a first linear compensation unit 2, an injection unit 3, and The unit 4, the transmitting unit 5, the feedback receiving unit 6, the fractional delay and amplitude matching unit 7, the integer delay unit 8, the subtracting unit 9, and the digital predistortion unit 10.
  • the linear identification unit 1 is configured to receive an injection signal, use the injection signal as a linearly recognized first input signal, and receive a second input signal, and calculate a linearity according to the first input signal and the second input signal. a compensation coefficient; wherein the second input signal includes linear distortion information of a predistortion inner loop for performing predistortion processing on a downlink signal of the base station, and a first input signal processed by the predistortion inner loop;
  • the first linear compensation unit 2 is configured to receive the downlink signal of the base station after the pre-distortion processing, and perform linear compensation on the downlink signal of the base station after the pre-distortion processing according to the linear compensation coefficient calculated by the linear identification unit 1;
  • the injection unit 3 is configured to output the injection signal
  • the adding unit 4 is configured to receive the injected signal and the base station downlink signal after the linear compensation of the first linear compensation unit, and add the injected signal and the linearly compensated base station downlink signal to output;
  • the transmitting unit 5 is configured to receive a combined signal output by the adding unit 4, convert the combined signal into a transmitting signal, and output the signal;
  • the feedback receiving unit 6 is configured to receive a transmission signal output by the transmitting unit 5, convert the transmission signal into a first feedback signal, and output the signal;
  • the fractional delay and amplitude align unit 7 is configured to receive the base station downlink signal of the integer delay and the first feedback signal output by the feedback receiving unit 6, and delay the first feedback signal with the integer and the integer Delaying the amplitude and phase alignment of the downlink signal of the base station to generate a second feedback signal and outputting;
  • the integer delay unit 8 is configured to receive the downlink signal of the base station, perform integer delay processing on the downlink signal of the base station, and output the result to the decimal delay and amplitude relative unit 7;
  • the subtracting unit 9 is configured to receive the second feedback signal output by the decimal delay and the amplitude matching unit 7 and the base station downlink signal of the integer delay output by the integer delay unit 8, and the second feedback signal Subtracting the base station downlink signal of the integer delay outputted by the integer delay unit 8, removing the base station downlink signal information of the integer delay to obtain an error signal, and outputting the error signal;
  • the digital pre-distortion unit 10 is configured to receive an error signal output by the subtraction unit 9 and a downlink signal of the base station, and calculate a pre-distortion coefficient according to the error signal and the downlink signal of the base station, according to the pre-distortion coefficient pair.
  • the base station downlink signal is pre-distorted and output to the first Linear compensation unit 2.
  • the integer delay unit 8 is specifically configured to perform an integer delay of an integer number of clock cycles on the downlink signal of the base station; the fractional delay and amplitude matching unit 7 is specifically configured to output the first output to the feedback receiving unit.
  • the feedback signal performs a fractional delay of a non-integer number of clock cycles to align the first feedback signal output by the feedback receiving unit 6 with the amplitude and phase of the integer delayed base station downlink signal output by the integer delay unit 8.
  • the digital predistortion unit has a bandwidth of less than one third of the maximum output bandwidth of the digital predistortion unit. If the predistortion inner loop is linearly compensated based on the base station downlink signal, since the input signal bandwidth varies with the base station service configuration, there may be only one GSM carrier at the narrowest time, that is, only 200 kHz, and the bandwidth of the digital predistortion unit output signal at this time. It can only be less than or equal to this bandwidth. Because the bandwidth is too narrow, the effective identification of the pre-distortion inner loop characteristics cannot be completed. In general, the larger the output bandwidth, the better the effective identification of the predistortion inner loop characteristics.
  • the bandwidth of the first input signal is greater than the bandwidth threshold K
  • the bandwidth threshold K is greater than 0.
  • the value of the threshold K is It can be configured to be 0.8fs or more, where fs is the sampling rate of the signal passing through the digital predistortion unit.
  • the bandwidth value of the injected signal is greater than 0.8fs
  • the injected signal can be called a wideband signal, which is beneficial for linear identification and subsequent Linear compensation.
  • the characteristics of the predistortion inner loop can be linearly recognized when K is less than 0.8 fs, but the identification efficiency and the identification accuracy are greatly reduced.
  • the amplitude of the injected signal is small, and the magnitude of the amplitude of the injected signal is close to the amplitude of the noise of the transmitting unit circuit, that is, the difference between the two is within a preset range, and even the amplitude of the injected signal is smaller than The magnitude of the noise of the transmit unit circuit.
  • the interference caused by the received injection signal to the downlink signal of the base station is basically negligible.
  • the second input signal includes linear distortion information of a pre-distorted inner loop for performing pre-distortion processing on the downlink signal of the base station, and a first input signal processed by the pre-distortion inner loop.
  • the second input signal includes linear distortion information of the predistortion inner loop and the first input signal processed by the predistortion inner loop.
  • the first input signal is not only used as a reference signal for linear identification, but also is added to the downlink signal of the base station after digital predistortion processing and linear compensation, and is output to the transmitting unit and processed by the predistortion inner loop. Therefore, in the second The input signal will include linear distortion information of the predistortion inner loop and the first input signal processed by the predistortion inner loop.
  • the characteristic of the predistortion inner loop can be effectively linearly recognized, and a relatively accurate linear compensation coefficient is obtained, so that the digital predistortion unit output signal is well linearly compensated, so that When the digital predistortion unit calculates the predistortion coefficient, the error is small, and finally the transmission distortion is reduced. Because the injection signal is added, the effect of linear identification and compensation is independent of the signal bandwidth input by the digital predistortion unit, which improves the applicability of the system.
  • the injection signal is used as the first input signal for linear identification
  • the second feedback signal is used as the second input signal for linear identification
  • the second feedback signal includes the first
  • the input signal is the linear distortion information of the injected signal and the predistortion inner loop, so that the accurate linear compensation coefficient is calculated, the effect of linear compensation is improved, the error in calculating the predistortion coefficient is reduced, and the transmission distortion is finally reduced.
  • the added signal in the adding unit 4 may also be the downlink signal of the base station before the linear compensation of the first linear compensation unit 3, that is, the injection signal is injected first, and then added.
  • the signal is linearly compensated.
  • the specific algorithm is slightly different, and the effect of linear recognition is similar.
  • FIG. 5 is a schematic diagram of the composition of the second embodiment of the identification system of the present invention.
  • the system includes: a linear identification unit 1, a first linear compensation unit 2, an injection unit 3, an addition unit 4, a transmission unit 5, a feedback receiving unit 6, a fractional delay and a amplitude-aligned unit 7, An integer delay unit 8, a subtraction unit 9, and a digital predistortion unit 10.
  • the linear identification unit 1 is configured to receive an injection signal, use the injection signal as a linearly recognized first input signal, and receive a second input signal, and calculate a linearity according to the first input signal and the second input signal. a compensation coefficient; wherein the second input signal includes linear distortion information of a predistortion inner loop for performing predistortion processing on a downlink signal of the base station, and a first input signal processed by the predistortion inner loop;
  • the first linear compensation unit 2 is configured to receive the downlink signal of the base station after the pre-distortion processing, and perform linear compensation on the downlink signal of the base station after the pre-distortion processing according to the linear compensation coefficient calculated by the linear identification unit 1;
  • the injection unit 3 is configured to output the injection signal
  • the adding unit 4 is configured to receive the injection signal and the base station downlink signal after the linear compensation of the first linear compensation unit, and add the injected signal and the linearly compensated base station downlink signal After output
  • the transmitting unit 5 is configured to receive a combined signal output by the adding unit 4, convert the combined signal into a transmitting signal, and output the signal;
  • the feedback receiving unit 6 is configured to receive a transmission signal output by the transmitting unit 5, convert the transmission signal into a first feedback signal, and output the signal;
  • the fractional delay and amplitude align unit 7 is configured to receive the base station downlink signal of the integer delay and the first feedback signal output by the feedback receiving unit 6, and delay the first feedback signal with the integer and the integer Delaying the amplitude and phase alignment of the downlink signal of the base station to generate a second feedback signal and outputting;
  • the integer delay unit 8 is configured to receive the downlink signal of the base station, perform integer delay processing on the downlink signal of the base station, and output the result to the decimal delay and amplitude relative unit 7;
  • the subtracting unit 9 is configured to receive the second feedback signal output by the decimal delay and the amplitude matching unit 7 and the base station downlink signal of the integer delay output by the integer delay unit 8, and the second feedback signal Subtracting the base station downlink signal of the integer delay outputted by the integer delay unit 8, removing the base station downlink signal information of the integer delay to obtain an error signal, and outputting the error signal;
  • the digital pre-distortion unit 10 is configured to receive an error signal output by the subtraction unit 9 and a downlink signal of the base station, and calculate a pre-distortion coefficient according to the error signal and the downlink signal of the base station, according to the pre-distortion coefficient pair.
  • the downlink signal of the base station is pre-distorted and output to the first linear compensation unit 2.
  • the integer delay unit 8 is specifically configured to perform an integer delay of an integer number of clock cycles on the downlink signal of the base station;
  • the fractional delay and amplitude matching unit 7 is specifically configured to perform a fractional delay of a non-integer number of clock cycles on the first feedback signal output by the feedback receiving unit to enable the first feedback signal output by the feedback receiving unit 6 Aligning with the amplitude and phase of the base station downlink signal of the integer delay output by the integer delay unit 8.
  • the digital predistortion unit has an input signal, that is, the bandwidth of the downlink signal of the base station does not exceed one third of the maximum output bandwidth of the digital predistortion unit. If the predistortion inner loop is linearly compensated based on the base station downlink signal, since the input signal bandwidth varies with the base station service configuration, there may be only one GSM carrier at the narrowest time, that is, only 200 kHz, and the bandwidth of the digital predistortion unit output signal at this time. It can only be less than or equal to this bandwidth. Because the bandwidth is too narrow, the effective identification of the pre-distortion inner loop characteristics cannot be completed. In general, the larger the output bandwidth, the better the effective identification of the predistortion inner loop characteristics.
  • the bandwidth of the first input signal is greater than the bandwidth threshold K
  • the bandwidth threshold K is greater than 0.
  • the value of the threshold K is It can be configured to be 0.8fs or more, where fs is the sampling rate of the signal passing through the digital predistortion unit.
  • the bandwidth value of the injected signal is greater than 0.8fs, the injected signal can be called a wideband signal, which is beneficial for linear identification and subsequent Linear compensation.
  • the K is less than 0.8fs, the characteristics of the predistortion inner loop can be linearly recognized, but the identification efficiency and the identification accuracy are greatly reduced.
  • the amplitude of the injected signal is small, and the magnitude of the amplitude of the injected signal is close to the amplitude of the noise of the transmitting unit circuit, that is, the difference between the two is within a preset range, and even the amplitude of the injected signal is smaller than The magnitude of the noise of the transmit unit circuit.
  • the interference caused by the received injection signal to the downlink signal of the base station is basically negligible.
  • the second input signal includes linear distortion information of a pre-distorted inner loop for performing pre-distortion processing on the downlink signal of the base station, and a first input signal processed by the pre-distortion inner loop.
  • the second input signal includes linear distortion information of the predistortion inner loop and the first input signal processed by the predistortion inner loop.
  • the first input signal is not only used as a reference signal for linear identification, but also is added to the downlink signal of the base station after digital predistortion processing and linear compensation, and is output to the transmitting unit and processed by the predistortion inner loop. Therefore, linear distortion information including a predistortion inner loop and a first input signal subjected to the predistortion inner loop processing are included in the second input signal.
  • the characteristic of the predistortion inner loop can be effectively linearly recognized, and a relatively accurate linear compensation coefficient is obtained, so that the digital predistortion unit output signal is well linearly compensated, so that When the digital predistortion unit calculates the predistortion coefficient, the error is small, and finally the transmission distortion is reduced. Because the injection signal is added, the effect of linear identification and compensation is independent of the signal bandwidth input by the digital predistortion unit, which improves the applicability of the system.
  • the second input signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal, and then subtracted with the integer delayed base station downlink signal to remove the The error signal generated after the base station downlink signal information of the integer delay is described.
  • the integer delay specifically indicates a delay of an integer number of clock cycles for the downlink signal of the base station; the decimal delay specifically indicates that the first feedback signal output by the feedback receiving unit is not a whole number of clock cycles.
  • the fractional delay is such that the first feedback signal output by the feedback receiving unit is aligned with the amplitude and phase of the integer delayed base station downlink signal.
  • the second feedback signal is derived from the downlink signal of the base station
  • the second feedback signal includes information of a large number of downlink signals of the base station.
  • the amplitude of the injected signal is generally small, so the amplitude of the injected signal is also small in the second feedback signal, and the ratio of the downlink signal to the circuit noise is smaller than that of the base station, and the linear identification needs to be compared.
  • Long-term correlation accumulation increases the ratio of the injected signal relative to the base station downlink signal and circuit noise.
  • the amplitude of the downlink signal of the base station is much larger than the circuit noise.
  • the second feedback signal has a certain time difference from the downlink signal of the base station because it has undergone a series of processes. If the information of the downlink signal of the base station included in the received second feedback signal can be removed, the correlation accumulation time of the injected signal will be greatly shortened. The content of the downlink signal of the base station in the error signal obtained by the subtraction process has been removed, so that the correlation accumulation time of the ideal injected signal can be obtained.
  • the injection signal with a large amplitude can be received to obtain the linear compensation coefficient, which can also shorten the correlation accumulation time without causing large interference to the downlink signal of the base station.
  • the feedback signal without removing the downlink signal information of the base station can be directly used as the second input signal for linear identification.
  • the added signal in the adding unit 4 may also be the downlink signal of the base station before the linear compensation of the first linear compensation unit 3, that is, the injected signal is injected first, and then the added signal is added. Perform linear compensation.
  • the specific algorithm is slightly different, and the effect of linear recognition is similar.
  • the injection signal is used as the first input signal for linear identification, and the error signal with the downlink signal information of the base station is removed as the second input signal for linear identification, and the error signal includes the first input signal, that is, the injected signal and the predistortion inner loop.
  • Linear distortion information which greatly reduces the accumulation time of the injected signal and improves the efficiency of the system.
  • FIG. 6 is a schematic diagram of the composition of the third embodiment of the identification system of the present invention.
  • the system includes: a linear identification unit 1, a first linear compensation unit 2, an injection unit 3, an addition unit 4, a transmission unit 5, a feedback receiving unit 6, a fractional delay and a amplitude-aligned unit 7, An integer delay unit 8, a subtraction unit 9, a digital predistortion unit 10, and a switch selection unit 11.
  • the linear identification unit 1 is configured to receive an injection signal, use the injection signal as a linearly recognized first input signal, and receive a second input signal according to the first input signal and the second input Inputting a signal, calculating a linear compensation coefficient; wherein the second input signal includes linear distortion information of a predistortion inner loop for performing predistortion processing on a downlink signal of the base station, and a first input processed by the predistortion inner loop signal;
  • the first linear compensation unit 2 is configured to receive the downlink signal of the base station after the pre-distortion processing, and perform linear compensation on the downlink signal of the base station after the pre-distortion processing according to the linear compensation coefficient calculated by the linear identification unit 1;
  • the injection unit 3 is configured to output the injection signal
  • the adding unit 4 is configured to receive the injected signal and the base station downlink signal after the linear compensation of the first linear compensation unit, and add the injected signal and the linearly compensated base station downlink signal to output;
  • the transmitting unit 5 is configured to receive a combined signal output by the adding unit 4, convert the combined signal into a transmitting signal, and output the signal;
  • the feedback receiving unit 6 is configured to receive a transmission signal output by the transmitting unit 5, convert the transmission signal into a first feedback signal, and output the signal;
  • the fractional delay and amplitude align unit 7 is configured to receive the base station downlink signal of the integer delay and the first feedback signal output by the feedback receiving unit 6, and delay the first feedback signal with the integer and the integer Delaying the amplitude and phase alignment of the downlink signal of the base station to generate a second feedback signal and outputting;
  • the integer delay unit 8 is configured to receive the downlink signal of the base station, perform integer delay processing on the downlink signal of the base station, and output the result to the decimal delay and amplitude relative unit 7;
  • the subtracting unit 9 is configured to receive the second feedback signal output by the decimal delay and the amplitude matching unit 7 and the base station downlink signal of the integer delay output by the integer delay unit 8, and the second feedback signal Subtracting the base station downlink signal of the integer delay outputted by the integer delay unit 8, removing the base station downlink signal information of the integer delay to obtain an error signal, and outputting the error signal;
  • the digital pre-distortion unit 10 is configured to receive an error signal output by the subtraction unit 9 and a downlink signal of the base station, and calculate a pre-distortion coefficient according to the error signal and the downlink signal of the base station, according to the pre-distortion coefficient pair.
  • the downlink signal of the base station is pre-distorted and output to the first linear compensation unit 2.
  • the integer delay unit 8 is specifically configured to perform an integer delay of an integer number of clock cycles on the downlink signal of the base station; the fractional delay and amplitude matching unit 7 is specifically configured to output the first output to the feedback receiving unit.
  • the feedback signal performs a fractional delay of a non-integer number of clock cycles to cause the feedback receiving unit
  • the first feedback signal outputted by 6 is aligned with the amplitude and phase of the integer delayed base station downlink signal output by the integer delay unit 8.
  • the switch selection unit 11 is configured to receive an error signal output by the subtraction unit 9 and a second feedback signal output by the fractional delay and amplitude relative unit 7, and select the error signal or the second feedback The signal is output to the linear identification unit 1.
  • a large amplitude injection signal can be received at the start of the transmission channel to obtain a linear compensation coefficient.
  • the feedback signal without removing the downlink signal information of the base station can be directly used as the linearly recognized comparison signal, and the path of the error signal can be selected by the switch selection unit 11.
  • the switch selection unit 11 can also be used to turn off the input signal of the linear identification unit 1 to reduce interference when the digital predistortion unit 10 performs training.
  • FIG. 7 is a schematic structural diagram of a fourth embodiment of the identification system of the present invention.
  • the system includes: a linear identification unit 1, a first linear compensation unit 2, an injection unit 3, an addition unit 4, a transmission unit 5, a feedback receiving unit 6, a fractional delay and a amplitude-aligned unit 7, An integer delay unit 8, a subtraction unit 9, a digital predistortion unit 10, a switch selection unit 11, and a second linear compensation unit 12.
  • the linear identification unit 1 is configured to receive an injection signal, use the injection signal as a linearly recognized first input signal, and receive a second input signal, and calculate a linearity according to the first input signal and the second input signal. a compensation coefficient; wherein the second input signal includes linear distortion information of a predistortion inner loop for performing predistortion processing on a downlink signal of the base station, and a first input signal processed by the predistortion inner loop;
  • the first linear compensation unit 2 is configured to receive the downlink signal of the base station after the pre-distortion processing, and perform linear compensation on the downlink signal of the base station after the pre-distortion processing according to the linear compensation coefficient calculated by the linear identification unit 1;
  • the injection unit 3 is configured to output the injection signal
  • the adding unit 4 is configured to receive the injected signal and the base station downlink signal after the linear compensation of the first linear compensation unit, and add the injected signal and the linearly compensated base station downlink signal to output;
  • the transmitting unit 5 is configured to receive a combined signal output by the adding unit 4, convert the combined signal into a transmitting signal, and output the signal;
  • the feedback receiving unit 6 is configured to receive a transmit signal output by the transmitting unit 5, and send the The signal is converted into a first feedback signal and output;
  • the fractional delay and amplitude align unit 7 is configured to receive the base station downlink signal of the integer delay and the first feedback signal output by the feedback receiving unit 6, and delay the first feedback signal with the integer and the integer Delaying the amplitude and phase alignment of the downlink signal of the base station to generate a second feedback signal and outputting;
  • the integer delay unit 8 is configured to receive the downlink signal of the base station, perform integer delay processing on the downlink signal of the base station, and output the result to the decimal delay and amplitude relative unit 7;
  • the subtracting unit 9 is configured to receive the second feedback signal output by the decimal delay and the amplitude matching unit 7 and the base station downlink signal of the integer delay output by the integer delay unit 8, and the second feedback signal Subtracting the base station downlink signal of the integer delay outputted by the integer delay unit 8, removing the base station downlink signal information of the integer delay to obtain an error signal, and outputting the error signal;
  • the digital pre-distortion unit 10 is configured to receive an error signal output by the subtraction unit 9 and a downlink signal of the base station, and calculate a pre-distortion coefficient according to the error signal and the downlink signal of the base station, according to the pre-distortion coefficient pair.
  • the downlink signal of the base station is pre-distorted and output to the first linear compensation unit 2.
  • the integer delay unit 8 is specifically configured to perform an integer delay of an integer number of clock cycles on the downlink signal of the base station; the fractional delay and amplitude matching unit 7 is specifically configured to output the first output to the feedback receiving unit.
  • the feedback signal performs a fractional delay of a non-integer number of clock cycles to align the first feedback signal output by the feedback receiving unit 6 with the amplitude and phase of the integer delayed base station downlink signal output by the integer delay unit 8.
  • the switch selection unit 11 is configured to receive an error signal output by the subtraction unit 9 and a second feedback signal output by the fractional delay and amplitude relative unit 7, and select the error signal or the second feedback The signal is output to the linear identification unit 1.
  • the second linear compensation unit 12 is configured to receive the second feedback signal output by the decimal delay and the amplitude matching unit 7, and the linear compensation coefficient calculated according to the linear identification unit 1 is opposite to the decimal delay and the amplitude
  • the second feedback signal output by the unit 7 is linearly compensated to generate a third feedback signal, and is output to the subtraction unit 9.
  • the first linear compensation unit 2 is integrated with the digital predistortion unit 10 or is separately provided.
  • the injection signal may be pseudo noise (Pseudo-Noise, PN), which is accumulated using time domain correlation. It can also be a periodic signal such as Orthogonal Frequency Division Multiplexing (Orthogonal) Frequency Division Multiplexing, called OFDM, uses time domain or frequency domain correlation accumulation within the usage period.
  • PN pseudo noise
  • OFDM Orthogonal Frequency Division Multiplexing
  • a part of the downlink signal of the base station is input to the integer delay unit 8 , and another part is input to the digital pre-distortion unit 10, and is output to the first linear compensation unit 2 after pre-distortion processing, and is linearly compensated and output to the
  • the adding unit 4 is added to the injection signal outputted by the injection unit 3, and then output to the transmitting unit 5, and after digital-to-analog conversion, up-conversion, power amplification, and converted into a transmission signal and output to the wireless space, a part of the output signal is output.
  • the feedback receiving unit 6 After the down-conversion and analog-to-digital conversion are performed, the feedback receiving unit 6 outputs the result to the fractional delay and amplitude matching unit 7, and the fractional delay and amplitude matching unit 7 is received from the integer delay unit 8. Delaying the base station downlink signal, delaying the first feedback signal outputted by the feedback receiving unit 6 and then outputting the same to the delayed base station downlink signal amplitude to the second linear compensation unit 12 for linear compensation And outputting to the switch selecting unit 11 and the subtracting unit 9, the subtracting unit 9 receiving the delay in the integer delay unit 8.
  • the downlink signal of the base station is subtracted from the third feedback signal output by the second linear compensation module 12 and the downlink signal of the integer delay base station to obtain an error signal and output to the switch selection unit 11 and the digital predistortion unit. 10.
  • the switch selection unit 11 further selects an appropriate signal output to the linear identification unit 1 according to the need, and the linear identification unit 1 receives the signal output by the switch selection unit 11 and the injection signal output by the injection unit 3.
  • the embodiment of the present invention further includes a base station, where the base station includes any one of the identification systems described above, and it should be noted that, in the implementation of the present invention, in the base station described in the example, each unit in any one of the above identification systems may be separately set in the form of hardware, or may be integrated in hardware form, or may be partially set in hardware and partially stored in memory in software.
  • the embodiment of the present invention does not impose any limitation.
  • FIG. 8 is a schematic diagram of the composition of the second embodiment of the identification device of the present invention.
  • the device includes:
  • processor 300 and a memory 400 cooperating with the processor 300;
  • the memory 400 is configured to store a program executed by the processor 300;
  • the processor 300 is configured to receive an injection signal generated by an injection unit, and use the injection signal as Linearly identifying the first input signal, and receiving the second input signal, wherein the second input signal includes linear distortion information of a predistortion inner loop for predistorting the base station downlink signal and passing through the predistortion a loop-processed first input signal; calculating a linear compensation coefficient based on the received first input signal and the second input signal.
  • the second input signal is a second feedback signal generated after the first feedback signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the decimal delay.
  • the second input signal is subjected to amplitude and phase alignment processing with the integer delayed base station downlink signal after the first feedback signal is subjected to the fractional delay, and then subtracted from the integer delayed base station downlink signal to remove The error signal generated by the integer delayed base station downlink signal information.
  • the first feedback signal is a signal generated by the feedback receiving unit according to the received transmission signal of the transmitting unit.
  • the transmitting signal is a signal that the transmitting unit converts and outputs according to the combined signal.
  • the combining signal is a signal that the adding unit outputs the linearly compensated base station downlink signal output by the received linear compensation unit and the injection signal generated by the injection unit.
  • the bandwidth of the injected signal is greater than the bandwidth threshold K, and the bandwidth threshold K is greater than zero.
  • the present invention has the following advantages:
  • the first input signal that is, the injection signal, and the second input signal including the predistortion inner loop linear distortion information and the first input signal processed by the predistortion inner loop are received by receiving an input signal that can effectively linearly identify the system characteristic.
  • the calculation can obtain a more accurate linear compensation coefficient, so that the effect of linear identification and compensation is independent of the signal bandwidth of the digital predistortion unit output, which improves the applicability of the system; achieves good linear compensation for the output signal of the digital predistortion unit.
  • the error is calculated when the digital predistortion unit calculates the predistortion coefficient, and finally the transmission distortion is reduced.
  • the linear compensation coefficient is calculated by using the error signal of the downlink signal information of the base station from which the delay is removed, thereby greatly shortening the time of linear identification and improving the system.
  • Working efficiency By adding a switch selection unit, a contrast signal for linear identification can be selected according to actual needs, and the degree of freedom is high, and the applicability is strong; and a linear compensation unit is provided in both the forward channel and the feedback loop, which can improve the effect of linear compensation. , reduce calculations
  • the error in the predistortion coefficient ultimately reduces the transmission distortion.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

本发明实施例公开了一种辨识方法，包括：接收注入单元产生的注入信号，将所述注入信号作为线性辨识的第一输入信号；接收第二输入信号，其中，所述第二输入信号包含用于对基站下行信号进行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处理后的第一输入信号；根据所述第一输入信号及所述第二输入信号，计算线性补偿系数。本发明实施例还公开了一种辨识装置、系统及基站。采用本发明，可以对预失真内环中各种不同带宽的信号进行良好的线性辨识与补偿，提高了系统的适用性，减少了发射失真。

Description

一种辨识方法、 装置、 系统及基站
技术领域
本发明涉及通信技术领域， 尤其涉及一种辨识方法、 装置、 系统及基站。 背景技术
在基站中，发射失真是影响通信质量的关键因素。所以需要对发射通道失 真进行校正。 请参照图 1 , 为现有技术中辨识系统的组成示意图。 整个系统包 括数字预失真单元、线性补偿单元、线性辨识单元、发射单元、反馈接收单元、 小数延时和幅相对齐单元、 减法单元及整数延时单元。 由数字预失真单元、 线 性补偿单元及发射单元组成发射通道，基站下行信号一部分输入整数延时单元, 另一部分输入数字预失真单元，经过预失真处理后输出至线性补偿单元进行线 性补偿， 线性补偿后的基站下行信号输出至发射单元转换为发射信号，发射信 号的一部分由发射单元输出至无线空间，一部分输出至反馈接收单元， 由反馈 接收单元转换为第一反馈信号并输出至小数延时和幅相对齐单元，小数延时和 幅相对齐单元接收来自整数延时单元延时的基站下行信号，将反馈接收单元输 出的第一反馈信号小数延时后，再与整数延时单元延时的基站下行信号幅相对 齐后输出至线性辨识单元及减法单元，线性辨识单元接收线性补偿后的基站下 行信号，根据线性补偿后的基站下行信号及幅相对齐后的第二反馈信号计算线 性补偿系数并将计算得到的线性补偿系数发送给线性补偿单元，由线性补偿单 元对预失真处理后的基站下行信号进行线性补偿，减法单元接收整数延时单元 延时的基站下行信号，将小数延时和幅相对齐后的第二反馈信号与整数延时的 基站下行信号相减后得到误差信号并输出至数字预失真单元，数字预失真单元 根据基站下行信号及误差信号计算预失真系数，完成对基站下行信号的数字预 失真处理， 从而减少发射失真。 其中， 用于对基站下行信号进行预失真处理的 环路称为预失真内环， 在图 1中， 由数字预失真单元、 线性补偿单元、 发射单 元、反馈接收单元、 小数延时和幅相对齐单元及减法单元组成的环路即可称为 预失真内环。 为了保证数字预失真单元算法的收敛性与性能，对预失真内环进 行线性补偿是十分必要的。线性补偿可以包括幅相均衡预补偿以及同相与正交 ( Inphase and Quadrature, 筒称 IQ )镜像失真预补偿。 如果线性补偿效果较差 将导致存在幅相均衡失真或 IQ镜像失真，那么最终计算预失真系数时将产生较 大的误差甚至算法不收敛即误差扩大或不趋于 0。 因此， 线性补偿的作用十分 重要。 而线性补偿的效果主要取决于线性补偿系数的计算。
在现有技术中， 线性补偿系数是根据线性补偿后的基站下行信号， 以及与 整数延时的基站下行信号进行幅相对齐后的第二反馈信号计算得到的。 其中， 幅相对齐后的第二反馈信号中包含预失真内环的线性失真信息。由于预失真内 环信号的线性辨识精度与通过预失真内环的信号的带宽有关，当通过预失真内 环的信号的带宽越小时， 线性辨识精度越低。 而基站下行信号带宽随业务配置 而变化，最窄的时候可能只有一个全球移动通讯系统（ Global System of Mobile communication, 筒称 GSM )载波。 此时， 线性辨识单元无法对数字预失真内 环进行有效的线性辨识， 继而无法对数字预失真内环进行有效的线性补偿， 由 此也将影响预失真系数的计算， 导致发射失真严重。 发明内容
本发明实施例提供了一种辨识方法、 装置、 系统及基站， 可以对预失真内 环中各种不同带宽的信号进行良好的线性辨识与补偿， 提高了系统的适用性， 减少了发射失真。
本发明实施例第一方面提供一种辨识方法， 可包括：
接收注入单元产生的注入信号，将所述注入信号作为线性辨识的第一输入 信号；
接收第二输入信号， 其中， 所述第二输入信号包含用于对基站下行信号进 行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处理后 的第一输入信号；
根据所述第一输入信号及所述第二输入信号， 计算线性补偿系数。
在第一种可能的实现方式中，所述第二输入信号为第一反馈信号经过小数 延时之后，与整数延时的基站下行信号进行幅度与相位对齐处理后生成的第二 反馈信号， 其中， 所述第一反馈信号为反馈接收单元根据接收到的发射单元输 出的发射信号所产生的信号。
在第二种可能的实现方式中，所述第二输入信号为第一反馈信号经过小数 延时之后， 与整数延时的基站下行信号进行幅度和相位对齐处理，再与所述整 数延时的基站下行信号进行减法处理，去除所述整数延时的基站下行信号信息 后生成的误差信号， 其中， 所述第一反馈信号为反馈接收单元根据接收到的发 射单元输出的发射信号所产生的信号。
结合第一方面的第一或第二种可能的实现方式，在第三种可能的实现方式 中， 所述发射信号为所述发射单元根据合路信号转换并输出的信号， 其中， 所 述合路信号为所述加法单元将接收到的线性补偿单元输出的经过线性补偿后 的基站下行信号及所述注入单元产生的所述注入信号相加后输出的信号。
结合第一方面或结合第一方面的第一或第二或第三种可能的实现方式，在 第四种可能的实现方式中， 所述注入信号的带宽大于带宽阈值 K, 且所述带宽 阈值 K大于 0。
本发明实施例第二方面提供一种辨识装置， 可包括：
接收模块， 用于接收注入单元产生的注入信号，将所述注入信号作为线性 辨识的第一输入信号， 以及接收第二输入信号， 其中， 所述第二输入信号包含 用于对基站下行信号进行预失真处理的预失真内环的线性失真信息以及经过 所述预失真内环处理后的第一输入信号；
计算模块，用于根据所述接收模块接收的所述第一输入信号及所述第二输 入信号， 计算线性补偿系数。
在第一种可能的实现方式中，所述第二输入信号为第一反馈信号经过小数 延时之后，与整数延时的基站下行信号进行幅度与相位对齐处理后生成的第二 反馈信号， 其中，所述第一反馈信号为反馈接收单元根据接收到的发射单元输 出的发射信号所产生的信号。
在第二种可能的实现方式中，所述第二输入信号为第一反馈信号经过小数 延时之后， 与整数延时的基站下行信号进行幅度和相位对齐处理，再与所述整 数延时的基站下行信号进行减法处理，去除所述整数延时的基站下行信号信息 后生成的误差信号， 其中， 所述第一反馈信号为反馈接收单元根据接收到的发 射单元输出的发射信号所产生的信号。
结合第二方面的第一或第二种可能的实现方式，在第三种可能的实现方式 中， 所述发射信号为所述发射单元根据合路信号转换并输出的信号， 其中， 所 述合路信号为所述加法单元将接收到的线性补偿单元输出的经过线性补偿后 的基站下行信号及所述注入单元产生的所述注入信号相加后输出的信号。
结合第二方面或结合第二方面的第一或第二或第三种可能的实现方式，在 第四种可能的实现方式中， 所述注入信号的带宽大于带宽阈值 K, 且所述带宽 阈值 K大于 0。
本发明实施例第三方面提供一种辨识系统， 可包括：
线性辨识单元， 用于接收注入信号，将所述注入信号作为线性辨识的第一 输入信号， 以及接收第二输入信号，根据所述第一输入信号及所述第二输入信 号， 计算线性补偿系数； 其中， 所述第二输入信号包含用于对基站下行信号进 行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处理后 的第一输入信号；
第一线性补偿单元， 用于接收预失真处理后的基站下行信号，根据所述线 性辨识单元计算的线性补偿系数对所述预失真处理后的基站下行信号进行线 性补偿后输出；
注入单元， 用于输出所述注入信号；
加法单元，用于接收所述注入信号及所述第一线性补偿单元线性补偿后的 基站下行信号，将所述注入信号及所述线性补偿后的基站下行信号相加后输出； 发射单元， 用于接收所述加法单元输出的合路信号，将所述合路信号转换 为发射信号并输出；
反馈接收单元， 用于接收所述发射单元输出的发射信号，将所述发射信号 转换为第一反馈信号并输出；
小数延时和幅相对齐单元，用于接收整数延时的基站下行信号及所述反馈 接收单元输出的第一反馈信号，将所述第一反馈信号小数延时后与所述整数延 时的基站下行信号的幅度和相位对齐生成第二反馈信号并输出；
整数延时单元， 用于接收所述基站下行信号，对所述基站下行信号进行整 数延时处理后输出至所述小数延时和幅相对齐单元；
减法单元，用于接收所述小数延时和幅相对齐单元输出的第二反馈信号及 所述整数延时单元输出的整数延时的基站下行信号，将所述第二反馈信号与所 述整数延时单元输出的整数延时的基站下行信号相减，去除所述整数延时的基 站下行信号信息得到误差信号并输出；
数字预失真单元，用于接收所述减法单元输出的误差信号及所述基站下行 信号，根据所述误差信号及所述基站下行信号计算得到预失真系数，根据所述 预失真系数对所述基站下行信号进行预失真处理并输出至所述第一线性补偿 单元。
在第一种可能的实现方式中，所述第二输入信号为所述小数延时和幅相对 齐单元输出的第二反馈信号， 或者为所述减法单元输出的误差信号。
结合第三方面或结合第三方面的第一种可能的实现方式，在第二种可能的 实现方式中，所述整数延时单元具体用于对所述基站下行信号进行整数个时钟 周期的整数延时；所述小数延时和幅相对齐单元具体用于对所述反馈接收单元 输出的第一反馈信号进行非整数个时钟周期的小数延时以使所述反馈接收单 元输出的第一反馈信号与所述整数延时单元输出的整数延时的基站下行信号 的幅度和相位对齐。
结合第三方面或结合第三方面的第一或第二种可能的实现方式，在第三种 可能的实现方式中， 所述系统还包括：
开关选择单元，用于接收所述减法单元输出的误差信号及所述小数延时和 幅相对齐单元输出的第二反馈信号，并选择所述误差信号或所述第二反馈信号 输出至所述线性辨识单元。
结合第三方面或结合第三方面的第一或第二或第三种可能的实现方式，在 第四种可能的实现方式中， 所述系统还包括：
第二线性补偿单元，用于接收所述小数延时和幅相对齐单元输出的第二反 馈信号，根据所述线性辨识单元计算的线性补偿系数对所述小数延时和幅相对 齐单元输出的第二反馈信号进行线性补偿后生成第三反馈信号，并输出至所述 减法单元。
结合第三方面或结合第三方面的第一或第二或第三或第四种可能的实现 方式，在第五种可能的实现方式中， 所述第一线性补偿单元与所述数字预失真 单元集成在一起或单独设置。
本发明实施例第四方面提供一种辨识装置， 可包括：
处理器及与所述处理器相配合的存储器；
所述存储器用于存储所述处理器执行的程序；
所述处理器用于接收注入单元产生的注入信号，将所述注入信号作为线性 辨识的第一输入信号， 以及接收第二输入信号， 其中， 所述第二输入信号包含 用于对基站下行信号进行预失真处理的预失真内环的线性失真信息以及经过 所述预失真内环处理后的第一输入信号；根据接收的所述第一输入信号及所述 第二输入信号， 计算线性补偿系数。
在第一种可能的实现方式中，所述第二输入信号为第一反馈信号经过小数 延时之后，与整数延时的基站下行信号进行幅度与相位对齐处理后生成的第二 反馈信号， 其中，所述第一反馈信号为反馈接收单元根据接收到的发射单元输 出的发射信号所产生的信号。
在第二种可能的实现方式中，所述第二输入信号为第一反馈信号经过小数 延时之后， 与整数延时的基站下行信号进行幅度和相位对齐处理，再与所述整 数延时的基站下行信号进行减法处理，去除所述整数延时的基站下行信号信息 后生成的误差信号， 其中， 所述第一反馈信号为反馈接收单元根据接收到的发 射单元输出的发射信号所产生的信号。
结合第四方面的第一或第二种可能的实现方式，在第三种可能的实现方式 中， 所述发射信号为所述发射单元根据合路信号转换并输出的信号， 其中， 所 述合路信号为所述加法单元将接收到的线性补偿单元输出的经过线性补偿后 的基站下行信号及所述注入单元产生的所述注入信号相加后输出的信号。
结合第四方面或结合第四方面的第一或第二或第三种可能的实现方式，在 第四种可能的实现方式中， 所述注入信号的带宽大于带宽阈值 K, 且所述带宽 阈值 K大于 0。
本发明实施例第五方面提供一种基站， 可包括：
如本发明实施例第三方面或第三方面中任一实现方式中所述的系统。
实施本发明实施例， 具有如下有益效果：
通过接收可以对系统特性进行有效线性辨识的第一输入信号即注入信号， 以及包含预失真内环线性失真信息以及经过所述预失真内环处理后的第一输 入信号的第二输入信号， 经过计算可以得到较为精确的线性补偿系数，使得线 性辨识及补偿的效果与数字预失真单元输出的信号带宽无关，提高了系统的适 用性； 实现了对数字预失真单元输出信号进行良好的线性补偿，使得数字预失 真单元计算预失真系数时误差较小， 最终降低发射失真。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例中所需要使用的附图作筒单地介绍，显而易见地， 下面描述中的附图仅仅是 本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的 前提下， 还可以根据这些附图获得其他的附图。
图 1 为现有的辨识系统的组成示意图；
图 2 为本发明实施例辨识方法的流程示意图；
图 3为本发明辨识装置第一实施例的组成示意图；
图 4为本发明辨识系统的第一实施例的组成示意图；
图 5为本发明辨识系统的第二实施例的组成示意图；
图 6为本发明辨识系统的第三实施例的组成示意图；
图 7为本发明辨识系统的第四实施例的组成示意图；
图 8为本发明辨识装置第二实施例的组成示意图。 具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清 楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是 全部的实施例。基于本发明中的实施例， 本领域普通技术人员在没有作出创造 性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
请参见图 2, 为本发明实施例辨识方法的流程示意图， 该方法可以应用于 辨识系统的线性辨识单元中， 在本实施例中， 所述方法包括以下步骤：
S201 ,接收注入单元产生的注入信号，将所述注入信号作为线性辨识的第 一输入信号。
一般地，数字预失真单元其输入信号即基站下行信号的带宽不超过数字预 失真单元最大输出带宽的三分之一。如果基于基站下行信号来对预失真内环做 线性补偿， 由于输入信号带宽随基站业务配置而变化， 最窄的时候可能只有一 个 GSM载波， 即只有 200kHz, 此时数字预失真单元输出信号的带宽只能小于 或等于这个带宽， 由于带宽过窄， 无法完成对预失真内环特性的有效辨识。 一 般来说， 输出带宽越大， 越有利于预失真内环特性的有效辨识。
具体地，在本实施例中， 所述第一输入信号即注入信号的带宽大于带宽阈 值 K, 其中， 所述带宽阈值 K大于 0。 根据大量的模拟仿真及实际操作经验， 此 处阈值 K的值可以在配置为 0.8fs或以上， 其中， fs为数字预失真单元通过信号 的采样率， 当注入信号的带宽数值大于 0.8fs时， 所述注入信号可以称为宽带信 号， 利于线性辨识及后续的线性补偿。 当然， 在 K小于 0.8fs的时候也能对预失 真内环的特性进行线性辨识， 但是无论是辨识效率及辨识精度均大幅度降低。
更具体地， 所述注入信号的幅度较小， 其幅度大小在发射单元输出端的表 现与发射单元电路噪声的幅度大小接近， 即两者差值在一预设范围内， 甚至注 入信号的幅度小于发射单元电路噪声的幅度大小。这样，接收的注入信号对基 站下行信号造成的干扰基本可以忽略。在没有基站下行信号经过数字预失真单 元的时候， 由于不存在对基站下行信号的干扰问题， 因此可以适当提高注入信 号输出的幅度。
5202, 接收第二输入信号。
其中，所述第二输入信号包含用于对基站下行信号进行预失真处理的预失 真内环的线性失真信息以及经过所述预失真内环处理后的第一输入信号。
在本实施例中 ,所述第二输入信号中包含预失真内环的线性失真信息以及 经过所述预失真内环处理后的第一输入信号。所述第一输入信号不仅用于作为 线性辨识的基准信号，同时还会与经过数字预失真处理及线性补偿后的基站下 行信号相加输出至所述发射单元并经过预失真内环的处理， 因此，在所述第二 输入信号中将包含预失真内环的线性失真信息以及经过所述预失真内环处理 后的第一输入信号。
5203 , 根据所述第一输入信号及所述第二输入信号， 计算线性补偿系数。 当所述注入信号即第一输入信号为宽带信号时，可以对预失真内环特性进 行有效的线性辨识，得到较为精确的线性补偿系数从而对数字预失真单元输出 信号进行良好的线性补偿， 使得数字预失真单元计算预失真系数时误差较小， 最终降低发射失真， 因为加入了注入信号， 所以线性辨识及补偿的效果与数字 预失真单元输入的信号带宽无关， 提高了系统的适用性。
其中， 所述第二输入信号可以为第一反馈信号经过小数延时之后， 与整数 延时的基站下行信号进行幅度与相位对齐处理后生成的第二反馈信号。
所述第一反馈信号为反馈接收单元根据接收到的发射单元输出的发射信 号所产生的信号。所述发射信号为所述发射单元根据合路信号转换并输出的信 号，。 所述合路信号为所述加法单元将接收到的线性补偿单元输出的经过线性 补偿后的基站下行信号及所述注入单元产生的所述注入信号，也即第一输入信 号， 相加后输出的信号。 优选地， 所述第二输入信号信号为第一反馈信号经过小数延时之后， 与整 数延时的基站下行信号进行幅度和相位对齐处理，再与所述整数延时的基站下 行信号进行减法处理，去除所述整数延时的基站下行信号信息后生成的误差信 号。所述整数延时具体表示对基站下行信号进行整数个时钟周期的延时； 所述 小数延时具体表示对所述反馈接收单元输出的第一反馈信号进行非整数个时 钟周期的小数延时以使所述反馈接收单元输出的第一反馈信号与整数延时的 基站下行信号的幅度和相位对齐。
因为所述第二反馈信号来源于基站下行信号，所以所述第二反馈信号中包 含大量基站下行信号的信息。 而所述注入信号的幅度一般较小， 因此在所述第 二反馈信号中所述注入信号的幅度同样较小，相对于基站下行信号与电路噪声 的比例也较小，进行线性辨识时需要较长时间的相关积累来提升所述注入信号 相对于基站下行信号与电路噪声的比例。通常基站下行信号的幅度远大于电路 噪声。
所述第二反馈信号因为经过了一系列处理，与所述基站下行信号具有一定 时差。如果能够去除接收的所述第二反馈信号中包含的所述基站下行信号的信 息， 那么所述注入信号的相关积累时间将大大缩短。 而采用减法处理得到的误 差信号中关于基站下行信号的内容已经去除，因此可以得到理想的注入信号的 相关积累时间。
当然， 在发射通道启动时， 由于没有基站下行信号输入， 因此可以接收幅 度大的注入信号来获取线性补偿系数， 同样可以缩短相关积累时间， 这时可以 直接用未去除基站下行信号信息的反馈信号作为线性辨识的第二输入信号。
请参见图 3 ,为本发明辨识装置第一实施例的组成示意图。在本实施例中， 所述装置包括： 接收模块 100及计算模块 200。
所述接收模块 100用于接收注入单元产生的注入信号，将所述注入信号作 为线性辨识的第一输入信号， 以及接收第二输入信号， 其中， 所述第二输入信 号包含用于对基站下行信号进行预失真处理的预失真内环的线性失真信息以 及经过所述预失真内环处理后的第一输入信号；
一般地，数字预失真单元其输入信号即基站下行信号的带宽不超过数字预 失真单元最大输出带宽的三分之一。如果基于基站下行信号来对预失真内环做 线性补偿， 由于输入信号带宽随基站业务配置而变化， 最窄的时候可能只有一 个 GSM载波， 即只有 200kHz, 此时数字预失真单元输出信号的带宽只能小于 或等于这个带宽， 由于带宽过窄， 无法完成对预失真内环特性的有效辨识。 一 般来说， 输出带宽越大， 越有利于预失真内环特性的有效辨识。
具体地，在本实施例中， 所述第一输入信号即注入信号的带宽大于带宽阈 值 K, 且所述带宽阈值 K大于 0, 根据大量的模拟仿真及实际操作经验， 此处阈 值 K的值可以在配置为 0.8fs或以上， 其中， fs为数字预失真单元通过信号的采 样率， 当注入信号的带宽数值大于 0.8fs时， 所述注入信号可以称为宽带信号， 利于线性辨识及后续的线性补偿。 当然， 在 K小于 0.8fs的时候也能对预失真内 环的特性进行线性辨识， 但是无论是辨识效率及辨识精度均大幅度降低。
更具体地， 所述注入信号的幅度较小， 其幅度大小在发射单元输出端的表 现与发射单元电路噪声的幅度大小接近， 即两者差值在一预设范围内， 甚至注 入信号的幅度小于发射单元电路噪声的幅度大小。这样，接收的注入信号对基 站下行信号造成的干扰基本可以忽略。在没有基站下行信号经过数字预失真单 元的时候， 由于不存在对基站下行信号的干扰问题， 因此可以适当提高注入信 号输出的幅度。
其中，所述第二输入信号包含用于对基站下行信号进行预失真处理的预失 真内环的线性失真信息以及经过所述预失真内环处理后的第一输入信号。
在本实施例中 ,所述第二输入信号中包含预失真内环的线性失真信息以及 经过所述预失真内环处理后的第一输入信号。所述第一输入信号不仅用于作为 线性辨识的基准信号，同时还会与经过数字预失真处理及线性补偿后的基站下 行信号相加输出至所述发射单元并经过预失真内环的处理， 因此，在所述第二 输入信号中将包含预失真内环的线性失真信息以及经过所述预失真内环处理 后的第一输入信号。
所述计算模块 200用于根据所述接收模块接收的所述第一输入信号及所 述第二输入信号， 计算线性补偿系数。
当所述注入信号即第一输入信号为宽带信号时，可以对预失真内环特性进 行有效的线性辨识，得到较为精确的线性补偿系数从而对数字预失真单元输出 信号进行良好的线性补偿， 使得数字预失真单元计算预失真系数时误差较小， 最终降低发射失真， 因为加入了注入信号， 所以线性辨识及补偿的效果与数字 预失真单元输入的信号带宽无关， 提高了系统的适用性。 其中， 所述第二输入信号可以为第一反馈信号经过小数延时之后， 与整数 延时的基站下行信号进行幅度与相位对齐处理后生成的第二反馈信号。
所述第一反馈信号为反馈接收单元根据接收到的发射单元输出的发射信 号所产生的信号。所述发射信号为所述发射单元根据合路信号转换并输出的信 号，。 所述合路信号为所述加法单元将接收到的线性补偿单元输出的经过线性 补偿后的基站下行信号及所述注入单元产生的所述注入信号，也即第一输入信 号， 相加后输出的信号。
优选地， 所述第二输入信号信号为第一反馈信号经过小数延时之后， 与整 数延时的基站下行信号进行幅度和相位对齐处理，再与所述整数延时的基站下 行信号进行减法处理，去除所述整数延时的基站下行信号信息后生成的误差信 号。所述整数延时具体表示对基站下行信号进行整数个时钟周期的延时； 所述 小数延时具体表示对所述反馈接收单元输出的第一反馈信号进行非整数个时 钟周期的小数延时以使所述反馈接收单元输出的第一反馈信号与整数延时的 基站下行信号的幅度和相位对齐。
因为所述第二反馈信号来源于基站下行信号，所以所述第二反馈信号中包 含大量基站下行信号的信息。 而所述注入信号的幅度一般较小， 因此在所述第 二反馈信号中所述注入信号的幅度同样较小，相对于基站下行信号与电路噪声 的比例也较小，进行线性辨识时需要较长时间的相关积累来提升所述注入信号 相对于基站下行信号与电路噪声的比例。通常基站下行信号的幅度远大于电路 噪声。
所述第二反馈信号因为经过了一系列处理，与所述基站下行信号具有一定 时差。如果能够去除接收的所述第二反馈信号中包含的所述基站下行信号的信 息， 那么所述注入信号的相关积累时间将大大缩短。 而采用减法处理得到的误 差信号中关于基站下行信号的内容已经去除，因此可以得到理想的注入信号的 相关积累时间。
当然， 在发射通道启动时， 由于没有基站下行信号输入， 因此可以接收幅 度大的注入信号来获取线性补偿系数， 同样可以缩短相关积累时间。 这时可以 直接用未去除基站下行信号信息的反馈信号作为线性辨识的第二输入信号。
请参见图 4, 为本发明辨识系统的第一实施例的组成示意图。 在本实施例 中， 所述系统包括： 线性辨识单元 1、 第一线性补偿单元 2、 注入单元 3、 加 法单元 4、 发射单元 5、 反馈接收单元 6、 小数延时和幅相对齐单元 7、 整数延 时单元 8、 减法单元 9、 数字预失真单元 10。
所述线性辨识单元 1用于接收注入信号，将所述注入信号作为线性辨识的 第一输入信号， 以及接收第二输入信号，根据所述第一输入信号及所述第二输 入信号， 计算线性补偿系数； 其中， 所述第二输入信号包含用于对基站下行信 号进行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处 理后的第一输入信号；
所述第一线性补偿单元 2用于接收预失真处理后的基站下行信号，根据所 述线性辨识单元 1 计算的线性补偿系数对所述预失真处理后的基站下行信号 进行线性补偿后输出；
所述注入单元 3用于输出所述注入信号；
所述加法单元 4用于接收所述注入信号及所述第一线性补偿单元线性补 偿后的基站下行信号，将所述注入信号及所述线性补偿后的基站下行信号相加 后输出；
所述发射单元 5用于接收所述加法单元 4输出的合路信号，将所述合路信 号转换为发射信号并输出；
所述反馈接收单元 6用于接收所述发射单元 5输出的发射信号，将所述发 射信号转换为第一反馈信号并输出；
所述小数延时和幅相对齐单元 7 用于接收整数延时的基站下行信号及所 述反馈接收单元 6输出的第一反馈信号，将所述第一反馈信号小数延时后与所 述整数延时的基站下行信号的幅度和相位对齐生成第二反馈信号并输出；
所述整数延时单元 8用于接收所述基站下行信号，对所述基站下行信号进 行整数延时处理后输出至所述小数延时和幅相对齐单元 7;
所述减法单元 9用于接收所述小数延时和幅相对齐单元 7输出的第二反馈 信号及所述整数延时单元 8输出的整数延时的基站下行信号，将所述第二反馈 信号与所述整数延时单元 8输出的整数延时的基站下行信号相减，去除所述整 数延时的基站下行信号信息得到误差信号并输出；
所述数字预失真单元 10用于接收所述减法单元 9输出的误差信号及所述 基站下行信号， 根据所述误差信号及所述基站下行信号计算得到预失真系数， 根据所述预失真系数对所述基站下行信号进行预失真处理并输出至所述第一 线性补偿单元 2。
所述整数延时单元 8 具体用于对所述基站下行信号进行整数个时钟周期 的整数延时；所述小数延时和幅相对齐单元 7具体用于对所述反馈接收单元输 出的第一反馈信号进行非整数个时钟周期的小数延时以使所述反馈接收单元 6输出的第一反馈信号与所述整数延时单元 8输出的整数延时的基站下行信号 的幅度和相位对齐。
一般地，数字预失真单元其输入信号即基站下行信号的带宽不超过数字预 失真单元最大输出带宽的三分之一。如果基于基站下行信号来对预失真内环做 线性补偿， 由于输入信号带宽随基站业务配置而变化， 最窄的时候可能只有一 个 GSM载波， 即只有 200kHz, 此时数字预失真单元输出信号的带宽只能小于 或等于这个带宽， 由于带宽过窄， 无法完成对预失真内环特性的有效辨识。 一 般来说， 输出带宽越大， 越有利于预失真内环特性的有效辨识。
具体地，在本实施例中， 所述第一输入信号即注入信号的带宽大于带宽阈 值 K, 且所述带宽阈值 K大于 0, 根据大量的模拟仿真及实际操作经验， 此处阈 值 K的值可以在配置为 0.8fs或以上， 其中， fs为数字预失真单元通过信号的采 样率， 当注入信号的带宽数值大于 0.8fs时， 所述注入信号可以称为宽带信号， 利于线性辨识及后续的线性补偿。 当然， 在 K小于 0.8fs的时候也能对预失真内 环的特性进行线性辨识， 但是无论是辨识效率及辨识精度均大幅度降低。
更具体地， 所述注入信号的幅度较小， 其幅度大小在发射单元输出端的表 现与发射单元电路噪声的幅度大小接近， 即两者差值在一预设范围内， 甚至注 入信号的幅度小于发射单元电路噪声的幅度大小。这样，接收的注入信号对基 站下行信号造成的干扰基本可以忽略。在没有基站下行信号经过数字预失真单 元的时候， 由于不存在对基站下行信号的干扰问题， 因此可以适当提高注入信 号输出的幅度。
其中，所述第二输入信号包含用于对基站下行信号进行预失真处理的预失 真内环的线性失真信息以及经过所述预失真内环处理后的第一输入信号。
在本实施例中 ,所述第二输入信号中包含预失真内环的线性失真信息以及 经过所述预失真内环处理后的第一输入信号。所述第一输入信号不仅用于作为 线性辨识的基准信号，同时还会与经过数字预失真处理及线性补偿后的基站下 行信号相加输出至所述发射单元并经过预失真内环的处理， 因此，在所述第二 输入信号中将包含预失真内环的线性失真信息以及经过所述预失真内环处理 后的第一输入信号。
当所述注入信号即第一输入信号为宽带信号时，可以对预失真内环特性进 行有效的线性辨识，得到较为精确的线性补偿系数从而对数字预失真单元输出 信号进行良好的线性补偿， 使得数字预失真单元计算预失真系数时误差较小， 最终降低发射失真， 因为加入了注入信号， 所以线性辨识及补偿的效果与数字 预失真单元输入的信号带宽无关， 提高了系统的适用性。
在本实施例中，通过配置注入单元及加法单元， 利用注入信号作为线性辨 识的第一输入信号， 利用第二反馈信号作为线性辨识的第二输入信号，且第二 反馈信号中同时包括第一输入信号即注入信号及预失真内环的线性失真信息， 从而计算得到准确的线性补偿系数，提高了线性补偿的效果， 降低了计算预失 真系数时的误差， 最终降低了发射失真。
当然，在本实施例中， 所述加法单元 4中相加的信号也可以是所述第一线 性补偿单元 3线性补偿前的基站下行信号， 即先注入所述注入信号，再对相加 后的信号进行线性补偿。 具体算法稍有不同， 线性辨识的效果相似。
请参见图 5 , 为本发明辨识系统的第二实施例的组成示意图。 在本实施例 中， 所述系统包括： 线性辨识单元 1、 第一线性补偿单元 2、 注入单元 3、 加 法单元 4、 发射单元 5、 反馈接收单元 6、 小数延时和幅相对齐单元 7、 整数延 时单元 8、 减法单元 9、 数字预失真单元 10。
所述线性辨识单元 1用于接收注入信号，将所述注入信号作为线性辨识的 第一输入信号， 以及接收第二输入信号，根据所述第一输入信号及所述第二输 入信号， 计算线性补偿系数； 其中， 所述第二输入信号包含用于对基站下行信 号进行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处 理后的第一输入信号；
所述第一线性补偿单元 2用于接收预失真处理后的基站下行信号，根据所 述线性辨识单元 1 计算的线性补偿系数对所述预失真处理后的基站下行信号 进行线性补偿后输出；
所述注入单元 3用于输出所述注入信号；
所述加法单元 4用于接收所述注入信号及所述第一线性补偿单元线性补 偿后的基站下行信号，将所述注入信号及所述线性补偿后的基站下行信号相加 后输出；
所述发射单元 5用于接收所述加法单元 4输出的合路信号，将所述合路信 号转换为发射信号并输出；
所述反馈接收单元 6用于接收所述发射单元 5输出的发射信号，将所述发 射信号转换为第一反馈信号并输出；
所述小数延时和幅相对齐单元 7 用于接收整数延时的基站下行信号及所 述反馈接收单元 6输出的第一反馈信号，将所述第一反馈信号小数延时后与所 述整数延时的基站下行信号的幅度和相位对齐生成第二反馈信号并输出；
所述整数延时单元 8用于接收所述基站下行信号，对所述基站下行信号进 行整数延时处理后输出至所述小数延时和幅相对齐单元 7;
所述减法单元 9用于接收所述小数延时和幅相对齐单元 7输出的第二反馈 信号及所述整数延时单元 8输出的整数延时的基站下行信号，将所述第二反馈 信号与所述整数延时单元 8输出的整数延时的基站下行信号相减，去除所述整 数延时的基站下行信号信息得到误差信号并输出；
所述数字预失真单元 10用于接收所述减法单元 9输出的误差信号及所述 基站下行信号， 根据所述误差信号及所述基站下行信号计算得到预失真系数， 根据所述预失真系数对所述基站下行信号进行预失真处理并输出至所述第一 线性补偿单元 2。
所述整数延时单元 8 具体用于对所述基站下行信号进行整数个时钟周期 的整数延时；
所述小数延时和幅相对齐单元 7 具体用于对所述反馈接收单元输出的第 一反馈信号进行非整数个时钟周期的小数延时以使所述反馈接收单元 6 输出 的第一反馈信号与所述整数延时单元 8 输出的整数延时的基站下行信号的幅 度和相位对齐。
一般地，数字预失真单元其输入信号即基站下行信号的带宽不超过数字预 失真单元最大输出带宽的三分之一。如果基于基站下行信号来对预失真内环做 线性补偿， 由于输入信号带宽随基站业务配置而变化， 最窄的时候可能只有一 个 GSM载波， 即只有 200kHz, 此时数字预失真单元输出信号的带宽只能小于 或等于这个带宽， 由于带宽过窄， 无法完成对预失真内环特性的有效辨识。 一 般来说， 输出带宽越大， 越有利于预失真内环特性的有效辨识。 具体地，在本实施例中， 所述第一输入信号即注入信号的带宽大于带宽阈 值 K, 且所述带宽阈值 K大于 0, 根据大量的模拟仿真及实际操作经验， 此处阈 值 K的值可以在配置为 0.8fs或以上， 其中， fs为数字预失真单元通过信号的采 样率， 当注入信号的带宽数值大于 0.8fs时， 所述注入信号可以称为宽带信号， 利于线性辨识及后续的线性补偿。 当然， 在 K小于 0.8fs的时候也能对预失真内 环的特性进行线性辨识， 但是无论是辨识效率及辨识精度均大幅度降低。
更具体地， 所述注入信号的幅度较小， 其幅度大小在发射单元输出端的表 现与发射单元电路噪声的幅度大小接近， 即两者差值在一预设范围内， 甚至注 入信号的幅度小于发射单元电路噪声的幅度大小。这样，接收的注入信号对基 站下行信号造成的干扰基本可以忽略。在没有基站下行信号经过数字预失真单 元的时候， 由于不存在对基站下行信号的干扰问题， 因此可以适当提高注入信 号输出的幅度。
其中，所述第二输入信号包含用于对基站下行信号进行预失真处理的预失 真内环的线性失真信息以及经过所述预失真内环处理后的第一输入信号。
在本实施例中，所述第二输入信号中包含预失真内环的线性失真信息以及 经过所述预失真内环处理后的第一输入信号。所述第一输入信号不仅用于作为 线性辨识的基准信号，同时还会与经过数字预失真处理及线性补偿后的基站下 行信号相加输出至所述发射单元并经过预失真内环的处理， 因此，在所述第二 输入信号中将包含预失真内环的线性失真信息以及经过所述预失真内环处理 后的第一输入信号。
当所述注入信号即第一输入信号为宽带信号时，可以对预失真内环特性进 行有效的线性辨识，得到较为精确的线性补偿系数从而对数字预失真单元输出 信号进行良好的线性补偿， 使得数字预失真单元计算预失真系数时误差较小， 最终降低发射失真， 因为加入了注入信号， 所以线性辨识及补偿的效果与数字 预失真单元输入的信号带宽无关， 提高了系统的适用性。
所述第二输入信号信号为第一反馈信号经过小数延时之后，与整数延时的 基站下行信号进行幅度和相位对齐处理，再与所述整数延时的基站下行信号进 行减法处理，去除所述整数延时的基站下行信号信息后生成的误差信号。所述 整数延时具体表示对基站下行信号进行整数个时钟周期的延时；所述小数延时 具体表示对所述反馈接收单元输出的第一反馈信号进行非整数个时钟周期的 小数延时以使所述反馈接收单元输出的第一反馈信号与整数延时的基站下行 信号的幅度和相位对齐。
因为所述第二反馈信号来源于基站下行信号，所以所述第二反馈信号中包 含大量基站下行信号的信息。 而所述注入信号的幅度一般较小， 因此在所述第 二反馈信号中所述注入信号的幅度同样较小，相对于基站下行信号与电路噪声 的比例也较小，进行线性辨识时需要较长时间的相关积累来提升所述注入信号 相对于基站下行信号与电路噪声的比例。通常基站下行信号的幅度远大于电路 噪声。
所述第二反馈信号因为经过了一系列处理，与所述基站下行信号具有一定 时差。如果能够去除接收的所述第二反馈信号中包含的所述基站下行信号的信 息， 那么所述注入信号的相关积累时间将大大缩短。 而采用减法处理得到的误 差信号中关于基站下行信号的内容已经去除，因此可以得到理想的注入信号的 相关积累时间。
当然， 在发射通道启动时， 由于没有基站下行信号输入， 因此可以接收幅 度大的注入信号来获取线性补偿系数， 同样可以缩短相关积累时间，且不会对 基站下行信号造成较大干扰。这时可以直接用未去除基站下行信号信息的反馈 信号作为线性辨识的第二输入信号。
在本实施例中，所述加法单元 4中相加的信号也可以是所述第一线性补偿 单元 3线性补偿前的基站下行信号， 即先注入所述注入信号，再对相加后的信 号进行线性补偿。 具体算法稍有不同， 线性辨识的效果相似。
利用注入信号作为线性辨识的第一输入信号，利用去除了基站下行信号信 息的误差信号作为线性辨识的第二输入信号，且误差信号中同时包括第一输入 信号即注入信号及预失真内环的线性失真信息，这样大大降低了注入信号的积 累时间， 提高了系统的效率。
请参见图 6, 为本发明辨识系统的第三实施例的组成示意图。 在本实施例 中， 所述系统包括： 线性辨识单元 1、 第一线性补偿单元 2、 注入单元 3、 加 法单元 4、 发射单元 5、 反馈接收单元 6、 小数延时和幅相对齐单元 7、 整数延 时单元 8、 减法单元 9、 数字预失真单元 10、 开关选择单元 11。
所述线性辨识单元 1用于接收注入信号，将所述注入信号作为线性辨识的 第一输入信号， 以及接收第二输入信号，根据所述第一输入信号及所述第二输 入信号， 计算线性补偿系数； 其中， 所述第二输入信号包含用于对基站下行信 号进行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处 理后的第一输入信号；
所述第一线性补偿单元 2用于接收预失真处理后的基站下行信号，根据所 述线性辨识单元 1 计算的线性补偿系数对所述预失真处理后的基站下行信号 进行线性补偿后输出；
所述注入单元 3用于输出所述注入信号；
所述加法单元 4用于接收所述注入信号及所述第一线性补偿单元线性补 偿后的基站下行信号，将所述注入信号及所述线性补偿后的基站下行信号相加 后输出；
所述发射单元 5用于接收所述加法单元 4输出的合路信号，将所述合路信 号转换为发射信号并输出；
所述反馈接收单元 6用于接收所述发射单元 5输出的发射信号，将所述发 射信号转换为第一反馈信号并输出；
所述小数延时和幅相对齐单元 7 用于接收整数延时的基站下行信号及所 述反馈接收单元 6输出的第一反馈信号，将所述第一反馈信号小数延时后与所 述整数延时的基站下行信号的幅度和相位对齐生成第二反馈信号并输出；
所述整数延时单元 8用于接收所述基站下行信号，对所述基站下行信号进 行整数延时处理后输出至所述小数延时和幅相对齐单元 7;
所述减法单元 9用于接收所述小数延时和幅相对齐单元 7输出的第二反馈 信号及所述整数延时单元 8输出的整数延时的基站下行信号，将所述第二反馈 信号与所述整数延时单元 8输出的整数延时的基站下行信号相减，去除所述整 数延时的基站下行信号信息得到误差信号并输出；
所述数字预失真单元 10用于接收所述减法单元 9输出的误差信号及所述 基站下行信号， 根据所述误差信号及所述基站下行信号计算得到预失真系数， 根据所述预失真系数对所述基站下行信号进行预失真处理并输出至所述第一 线性补偿单元 2。
所述整数延时单元 8 具体用于对所述基站下行信号进行整数个时钟周期 的整数延时；所述小数延时和幅相对齐单元 7具体用于对所述反馈接收单元输 出的第一反馈信号进行非整数个时钟周期的小数延时以使所述反馈接收单元 6输出的第一反馈信号与所述整数延时单元 8输出的整数延时的基站下行信号 的幅度和相位对齐。
所述开关选择单元 11 , 用于接收所述减法单元 9输出的误差信号及所述 小数延时和幅相对齐单元 7输出的第二反馈信号，并选择所述误差信号或所述 第二反馈信号输出至所述线性辨识单元 1。
例如， 为了缩短相关积累时间， 那么可以在发射通道启动时接收幅度大的 注入信号来获取线性补偿系数。这时可以直接用未去除基站下行信号信息的反 馈信号作为线性辨识的对比信号，并通过所述开关选择单元 11选择关闭所述误 差信号的通路即可。 当然， 所述开关选择单元 11还可以用于在所述数字预失真 单元 10进行训练的时候， 关闭所述线性辨识单元 1的输入信号以减少干扰。
请参见图 7, 为本发明辨识系统的第四实施例的组成示意图。 在本实施例 中， 所述系统包括： 线性辨识单元 1、 第一线性补偿单元 2、 注入单元 3、 加 法单元 4、 发射单元 5、 反馈接收单元 6、 小数延时和幅相对齐单元 7、 整数延 时单元 8、 减法单元 9、 数字预失真单元 10、 开关选择单元 11、 第二线性补偿 单元 12。
所述线性辨识单元 1用于接收注入信号，将所述注入信号作为线性辨识的 第一输入信号， 以及接收第二输入信号，根据所述第一输入信号及所述第二输 入信号， 计算线性补偿系数； 其中， 所述第二输入信号包含用于对基站下行信 号进行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处 理后的第一输入信号；
所述第一线性补偿单元 2用于接收预失真处理后的基站下行信号，根据所 述线性辨识单元 1 计算的线性补偿系数对所述预失真处理后的基站下行信号 进行线性补偿后输出；
所述注入单元 3用于输出所述注入信号；
所述加法单元 4用于接收所述注入信号及所述第一线性补偿单元线性补 偿后的基站下行信号，将所述注入信号及所述线性补偿后的基站下行信号相加 后输出；
所述发射单元 5用于接收所述加法单元 4输出的合路信号，将所述合路信 号转换为发射信号并输出；
所述反馈接收单元 6用于接收所述发射单元 5输出的发射信号，将所述发 射信号转换为第一反馈信号并输出；
所述小数延时和幅相对齐单元 7 用于接收整数延时的基站下行信号及所 述反馈接收单元 6输出的第一反馈信号，将所述第一反馈信号小数延时后与所 述整数延时的基站下行信号的幅度和相位对齐生成第二反馈信号并输出；
所述整数延时单元 8用于接收所述基站下行信号，对所述基站下行信号进 行整数延时处理后输出至所述小数延时和幅相对齐单元 7;
所述减法单元 9用于接收所述小数延时和幅相对齐单元 7输出的第二反馈 信号及所述整数延时单元 8输出的整数延时的基站下行信号，将所述第二反馈 信号与所述整数延时单元 8输出的整数延时的基站下行信号相减，去除所述整 数延时的基站下行信号信息得到误差信号并输出；
所述数字预失真单元 10用于接收所述减法单元 9输出的误差信号及所述 基站下行信号， 根据所述误差信号及所述基站下行信号计算得到预失真系数， 根据所述预失真系数对所述基站下行信号进行预失真处理并输出至所述第一 线性补偿单元 2。
所述整数延时单元 8 具体用于对所述基站下行信号进行整数个时钟周期 的整数延时；所述小数延时和幅相对齐单元 7具体用于对所述反馈接收单元输 出的第一反馈信号进行非整数个时钟周期的小数延时以使所述反馈接收单元 6输出的第一反馈信号与所述整数延时单元 8输出的整数延时的基站下行信号 的幅度和相位对齐。
所述开关选择单元 11 , 用于接收所述减法单元 9输出的误差信号及所述 小数延时和幅相对齐单元 7输出的第二反馈信号，并选择所述误差信号或所述 第二反馈信号输出至所述线性辨识单元 1。
所述第二线性补偿单元 12用于接收所述小数延时和幅相对齐单元 7输出 的第二反馈信号，根据所述线性辨识单元 1计算的线性补偿系数对所述小数延 时和幅相对齐单元 7输出的第二反馈信号进行线性补偿后生成第三反馈信号， 并输出至所述减法单元 9。
所述第一线性补偿单元 2与所述数字预失真单元 10集成在一起或单独设 置。
在本实施例中， 所述注入信号可以是伪噪声 （Pseudo-Noise, 筒称 PN ) , 使用时域相关积累。 也可以是周期信号如正交频分复用技术 (Orthogonal Frequency Division Multiplexing , 筒称 OFDM) , 使用周期内的时域或频域相关 积累。
总体来说： 基站下行信号一部分输入整数延时单元 8 , 另一部分输入所述 数字预失真单元 10, 经过预失真处理后输出至所述第一线性补偿单元 2, 经过 线性补偿后输出至所述加法单元 4,与所述注入单元 3输出的注入信号相加后输 出至所述发射单元 5 , 经过数模转换、 上变频、 功率放大之后转换为发射信号 输出至无线空间， 发射信号的一部分输出至所述反馈接收单元 6进行下变频及 模数转换后输出至所述小数延时和幅相对齐单元 7, 所述小数延时和幅相对齐 单元 7接收来自所述整数延时单元 8中延时的基站下行信号，将所述反馈接收单 元 6输出的第一反馈信号小数延时后再与所述延时的基站下行信号幅相对齐输 出至所述第二线性补偿单元 12进行线性补偿， 再输出至所述开关选择单元 11 及所述减法单元 9, 所述减法单元 9接收所述整数延时单元 8中延时的基站下行 信号，将所述第二线性补偿模块 12输出的第三反馈信号与整数延时的基站下行 信号相减后得到误差信号并输出至所述开关选择单元 11及所述数字预失真单 元 10,所述开关选择单元 11再根据需要选择合适的信号输出至所述线性辨识单 元 1 ,所述线性辨识单元 1接收所述开关选择单元 11输出的信号及所述注入单元 3输出的注入信号计算得到线性补偿系数并输出至所述第一线性补偿单元 2及 所述第二线性补偿单元 12, 完成线性补偿， 所述数字预失真单元 10根据基站下 行信号及所述减法单元 9输出的误差信号计算预失真系数， 完成对基站下行信 号的数字预失真处理。
基于本发明辨识系统的第一、第二及第三实施例， 本发明实施例还包括一 种基站， 所述基站包括如上所述的任意一种辨识系统， 需要说明的是， 在本发 明实施例所述的基站中，以上任意一种辨识系统中的各个单元可以以硬件的形 式单独设置， 也可以以硬件形式集成在一起， 还可以一部分以硬件形式设置、 一部分以软件形成存储到存储器中， 本发明实施例不做任何限制。
请参见图 8,为本发明辨识装置第二实施例的组成示意图。在本实施例中， 所述装置包括：
处理器 300及与所述处理器 300相配合的存储器 400;
所述存储器 400用于存储所述处理器 300执行的程序；
所述处理器 300用于接收注入单元产生的注入信号，将所述注入信号作为 线性辨识的第一输入信号， 以及接收第二输入信号， 其中， 所述第二输入信号 包含用于对基站下行信号进行预失真处理的预失真内环的线性失真信息以及 经过所述预失真内环处理后的第一输入信号；根据接收的所述第一输入信号及 所述第二输入信号， 计算线性补偿系数。
其中， 所述第二输入信号为第一反馈信号经过小数延时之后， 与整数延时 的基站下行信号进行幅度与相位对齐处理后生成的第二反馈信号。
或者， 所述第二输入信号为第一反馈信号经过小数延时之后， 与整数延时 的基站下行信号进行幅度和相位对齐处理，再与所述整数延时的基站下行信号 进行减法处理， 去除所述整数延时的基站下行信号信息后生成的误差信号。
具体地，所述第一反馈信号为反馈接收单元根据接收到的发射单元输出的 发射信号所产生的信号。所述发射信号为所述发射单元根据合路信号转换并输 出的信号，。 所述合路信号为所述加法单元将接收到的线性补偿单元输出的经 过线性补偿后的基站下行信号及所述注入单元产生的所述注入信号相加后输 出的信号。 所述注入信号的带宽大于带宽阈值 K, 且所述带宽阈值 K大于 0。
通过上述实施例的描述， 本发明具有以下优点：
通过接收可以对系统特性进行有效线性辨识的第一输入信号即注入信号， 以及包含预失真内环线性失真信息以及经过所述预失真内环处理后的第一输 入信号的第二输入信号， 经过计算可以得到较为精确的线性补偿系数，使得线 性辨识及补偿的效果与数字预失真单元输出的信号带宽无关，提高了系统的适 用性； 实现了对数字预失真单元输出信号进行良好的线性补偿，使得数字预失 真单元计算预失真系数时误差较小， 最终降低发射失真； 而利用去除了延时的 基站下行信号信息的误差信号计算线性补偿系数，大大缩短了线性辨识的时间 , 提高了系统的工作效率； 通过增加开关选择单元， 可以根据实际需要选择进行 线性辨识的对比信号， 自由度高， 适用性强； 在前向通道及反馈环路中均设置 线性补偿单元， 可以提高线性补偿的效果， 减低计算预失真系数时的误差， 最 终减少发射失真。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可 以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存 储介质中， 该程序在执行时， 执行包括上述方法实施例的步骤； 而前述的存储 介质包括： ROM、 RAM, 磁碟或者光盘等各种可以存储程序代码的介质。 以上对本发明实施例所提供的一种辨识方法、装置及系统进行了详细介绍, 说明只是用于帮助理解本发明的方法及其核心思想； 同时，对于本领域的一般 技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处， 综上所述， 本说明书内容不应理解为对本发明的限制。

Claims

权 利 要 求
1、 一种辨识方法， 其特征在于， 包括：
接收注入单元产生的注入信号，将所述注入信号作为线性辨识的第一输入 信号；
接收第二输入信号， 其中， 所述第二输入信号包含用于对基站下行信号进 行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处理后 的第一输入信号；
根据所述第一输入信号及所述第二输入信号， 计算线性补偿系数。
2、 如权利要求 1所述的方法， 其特征在于， 所述第二输入信号为第一反 馈信号经过小数延时之后，与整数延时的基站下行信号进行幅度与相位对齐处 理后生成的第二反馈信号， 其中， 所述第一反馈信号为反馈接收单元根据接收 到的发射单元输出的发射信号所产生的信号。
3、 如权利要求 1所述的方法， 其特征在于， 所述第二输入信号为第一反 馈信号经过小数延时之后，与整数延时的基站下行信号进行幅度和相位对齐处 理，再与所述整数延时的基站下行信号进行减法处理，去除所述整数延时的基 站下行信号信息后生成的误差信号，其中， 所述第一反馈信号为反馈接收单元 根据接收到的发射单元输出的发射信号所产生的信号。
4、 如权利要求 2或者 3所述的方法， 其特征在于， 所述发射信号为所述 发射单元根据合路信号转换并输出的信号， 其中， 所述合路信号为所述加法单 元将接收到的线性补偿单元输出的经过线性补偿后的基站下行信号及所述注 入单元产生的所述注入信号相加后输出的信号。
5、 如权利要求 1-4任一项所述的方法， 其特征在于， 所述注入信号的带 宽大于带宽阈值 K, 且所述带宽阈值 K大于 0。
6、 一种辨识装置， 其特征在于， 包括：
接收模块， 用于接收注入单元产生的注入信号，将所述注入信号作为线性 辨识的第一输入信号， 以及接收第二输入信号， 其中， 所述第二输入信号包含 用于对基站下行信号进行预失真处理的预失真内环的线性失真信息以及经过 所述预失真内环处理后的第一输入信号；
计算模块，用于根据所述接收模块接收的所述第一输入信号及所述第二输 入信号， 计算线性补偿系数。
7、 如权利要求 6所述的装置， 其特征在于， 所述第二输入信号为第一反 馈信号经过小数延时之后，与整数延时的基站下行信号进行幅度与相位对齐处 理后生成的第二反馈信号， 其中， 所述第一反馈信号为反馈接收单元根据接收 到的发射单元输出的发射信号所产生的信号。
8、 如权利要求 6所述的装置， 其特征在于， 所述第二输入信号为第一反 馈信号经过小数延时之后，与整数延时的基站下行信号进行幅度和相位对齐处 理，再与所述整数延时的基站下行信号进行减法处理，去除所述整数延时的基 站下行信号信息后生成的误差信号，其中， 所述第一反馈信号为反馈接收单元 根据接收到的发射单元输出的发射信号所产生的信号。
9、 如权利要求 7或 8所述的装置， 其特征在于， 所述发射信号为所述发 射单元根据合路信号转换并输出的信号， 其中， 所述合路信号为所述加法单元 将接收到的线性补偿单元输出的经过线性补偿后的基站下行信号及所述注入 单元产生的所述注入信号相加后输出的信号。
10、 如权利要求 6-9任一项所述的装置， 其特征在于， 所述注入信号的带 宽大于带宽阈值 K, 且所述带宽阈值 K大于 0。
11、 一种辨识系统， 其特征在于， 包括：
线性辨识单元， 用于接收注入信号，将所述注入信号作为线性辨识的第一 输入信号， 以及接收第二输入信号，根据所述第一输入信号及所述第二输入信 号， 计算线性补偿系数； 其中， 所述第二输入信号包含用于对基站下行信号进 行预失真处理的预失真内环的线性失真信息以及经过所述预失真内环处理后 的第一输入信号；
第一线性补偿单元， 用于接收预失真处理后的基站下行信号，根据所述线 性辨识单元计算的线性补偿系数对所述预失真处理后的基站下行信号进行线 性补偿后输出；
注入单元， 用于输出所述注入信号；
加法单元，用于接收所述注入信号及所述第一线性补偿单元线性补偿后的 基站下行信号，将所述注入信号及所述线性补偿后的基站下行信号相加后输出； 发射单元， 用于接收所述加法单元输出的合路信号，将所述合路信号转换 为发射信号并输出；
反馈接收单元， 用于接收所述发射单元输出的发射信号，将所述发射信号 转换为第一反馈信号并输出；
小数延时和幅相对齐单元，用于接收整数延时的基站下行信号及所述反馈 接收单元输出的第一反馈信号，将所述第一反馈信号小数延时后与所述整数延 时的基站下行信号的幅度和相位对齐后生成第二反馈信号并输出；
整数延时单元， 用于接收所述基站下行信号，对所述基站下行信号进行整 数延时处理后输出至所述小数延时和幅相对齐单元；
减法单元，用于接收所述小数延时和幅相对齐单元输出的第二反馈信号及 所述整数延时单元输出的整数延时的基站下行信号，将所述第二反馈信号与所 述整数延时单元输出的整数延时的基站下行信号相减，去除所述整数延时的基 站下行信号信息得到误差信号并输出；
数字预失真单元，用于接收所述减法单元输出的误差信号及所述基站下行 信号，根据所述误差信号及所述基站下行信号计算得到预失真系数，根据所述 预失真系数对所述基站下行信号进行预失真处理并输出至所述第一线性补偿 单元。
12、 如权利要求 11所述的系统， 其特征在于， 所述第二输入信号为所述 小数延时和幅相对齐单元输出的第二反馈信号，或者为所述减法单元输出的误 差信号。
13、 如权利要求 11或 12所述的系统， 其特征在于， 所述整数延时单元具 体用于对所述基站下行信号进行整数个时钟周期的整数延时；所述小数延时和 幅相对齐单元具体用于对所述反馈接收单元输出的第一反馈信号进行非整数 个时钟周期的小数延时以使所述反馈接收单元输出的第一反馈信号与所述整 数延时单元输出的整数延时的基站下行信号的幅度和相位对齐。
14、如权利要求 11-13任一项所述的系统，其特征在于，所述系统还包括： 开关选择单元，用于接收所述减法单元输出的误差信号及所述小数延时和 幅相对齐单元输出的第二反馈信号，并选择所述误差信号或所述第二反馈信号 输出至所述线性辨识单元。
15、如权利要求 11-14任一项所述的系统，其特征在于，所述系统还包括： 第二线性补偿单元，用于接收所述小数延时和幅相对齐单元输出的第二反 馈信号，根据所述线性辨识单元计算的线性补偿系数对所述小数延时和幅相对 齐单元输出的第二反馈信号进行线性补偿后生成第三反馈信号，并输出至所述 减法单元。
16、 如权利要求 12-15任一项所述的系统， 其特征在于， 所述第一线性补 偿单元与所述数字预失真单元集成在一起或单独设置。
17、 一种辨识装置， 其特征在于， 包括：
处理器及与所述处理器相配合的存储器；
所述存储器用于存储所述处理器执行的程序；
所述处理器用于接收注入单元产生的注入信号，将所述注入信号作为线性 辨识的第一输入信号， 以及接收第二输入信号， 其中， 所述第二输入信号包含 用于对基站下行信号进行预失真处理的预失真内环的线性失真信息以及经过 所述预失真内环处理后的第一输入信号；根据接收的所述第一输入信号及所述 第二输入信号， 计算线性补偿系数。
18、 如权利要求 17所述的装置， 其特征在于， 所述第二输入信号为第一 反馈信号经过小数延时之后，与整数延时的基站下行信号进行幅度与相位对齐 处理后生成的第二反馈信号， 其中， 所述第一反馈信号为反馈接收单元根据接 收到的发射单元输出的发射信号所产生的信号。
19、 如权利要求 18所述的装置， 其特征在于， 所述第二输入信号为第一 反馈信号经过小数延时之后，与整数延时的基站下行信号进行幅度和相位对齐 处理，再与所述整数延时的基站下行信号进行减法处理，去除所述整数延时的 基站下行信号信息后生成的误差信号， 其中， 所述第一反馈信号为反馈接收单 元根据接收到的发射单元输出的发射信号所产生的信号。
20、 如权利要求 18或 19所述的装置， 其特征在于， 所述发射信号为所述 发射单元根据合路信号转换并输出的信号， 其中， 所述合路信号为所述加法单 元将接收到的线性补偿单元输出的经过线性补偿后的基站下行信号及所述注 入单元产生的所述注入信号相加后输出的信号。
21、 如权利要求 17-20任一项所述的装置， 其特征在于， 所述注入信号的 带宽大于带宽阈值 K, 且所述带宽阈值 K大于 0。
22、 一种基站， 其特征在于， 包括：
如权利要求 11-16任一项所述的系统。
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