WO2014199592A1 - Multilayer substrate and method for manufacturing multilayer substrate - Google Patents

Multilayer substrate and method for manufacturing multilayer substrate Download PDF

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Publication number
WO2014199592A1
WO2014199592A1 PCT/JP2014/002941 JP2014002941W WO2014199592A1 WO 2014199592 A1 WO2014199592 A1 WO 2014199592A1 JP 2014002941 W JP2014002941 W JP 2014002941W WO 2014199592 A1 WO2014199592 A1 WO 2014199592A1
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WO
WIPO (PCT)
Prior art keywords
layer
glass cloth
insulating layer
multilayer substrate
prepreg
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PCT/JP2014/002941
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French (fr)
Japanese (ja)
Inventor
英二 藪田
俊浩 中村
祐紀 眞田
正英 辰己
Original Assignee
株式会社デンソー
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Publication of WO2014199592A1 publication Critical patent/WO2014199592A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material

Definitions

  • the present disclosure relates to a multilayer substrate and a method for manufacturing the multilayer substrate.
  • a plurality of conductors arranged on the surface of the insulating layer are spaced apart from each other, and the surface side of the insulating layer and the surface side of the insulating layer are sealed so as to seal the plurality of conductors.
  • the prepreg is configured to include a glass cloth and to seal both sides of the glass cloth with a resin material.
  • a resin material is embedded between each of the plurality of conductors.
  • the prepreg is made of a resin material mixed with many fillers in order to increase the thermal conductivity of the prepreg, the fluidity of the resin material constituting the prepreg becomes low.
  • the prepreg when the resin material constituting the prepreg is filled between each of the plurality of conductors, even if the prepreg is laminated on the surface side of the insulating layer and the prepreg is pressed against the insulating layer, the prepreg is interposed between the plurality of conductors. A sufficient amount of resin material cannot be supplied. For this reason, there exists a possibility that the unfilled part of a resin material, ie, a void, may generate
  • a multilayer substrate includes an insulating layer made of an electrically insulating material, a conductor provided on the surface of the insulating layer, spaced apart, a first glass cloth, and a first glass.
  • a prepreg having a resin layer that seals both surfaces of the cloth with a resin material, and a build-up layer that is laminated on the insulating layer so as to cover the surface of the insulating layer together with the conductor, and on the surface side of the insulating layer
  • the conductor is sealed in a state where the resin material constituting the resin layer is filled in the region constituting the interval, and the first glass cloth is formed so as to continuously cover the conductor and the region constituting the interval.
  • interval among the 1st glass cloths is a multilayer substrate bent so that it may approach the insulating layer side rather than the part which covers a conductor among 1st glass cloths.
  • a conductor disposed at an interval includes, in addition to a plurality of conductors spaced apart from each other, a conductor having two portions facing each other through a gap. Defined. In the case where a plurality of conductors are arranged apart from each other, a region between two adjacent conductors among the plurality of conductors is defined as a “region forming a gap”. In the case of one conductor having two parts facing each other through a gap, an area between the two parts is defined as an “area constituting an interval”.
  • the resin material constituting the prepreg is pushed into the region constituting the interval by the glass cloth. Therefore, a sufficient amount of the resin material can be filled in the region constituting the interval. For this reason, generation
  • conductors arranged at intervals are formed on the surface of an insulating layer made of an electrically insulating material, and both surfaces of the glass cloth and the glass cloth are made of a resin material.
  • the resin material constituting the prepreg is pushed into the region constituting the interval by the glass cloth, similarly to the multilayer substrate described above. Therefore, a sufficient amount of the resin material can be filled in the region constituting the interval. For this reason, generation
  • FIG. 1 is a cross-sectional view of the electronic device according to the first embodiment.
  • FIG. 2 is an enlarged view of a II part of the core layer in FIG. 3 (a) is a front view of the glass cloth in FIG. 2, and
  • FIG. 3 (b) is a cross-sectional view taken along the line IIIB-IIIB in FIG. 3 (a).
  • FIG. 4 is an enlarged view of a portion IV in FIG.
  • FIG. 5 is an enlarged view of a portion V in FIG. 6 (a) to 6 (d) are cross-sectional views showing manufacturing steps of the multilayer substrate of FIG. 7A to 7D are cross-sectional views illustrating the manufacturing process of the multilayer substrate subsequent to FIG.
  • FIGS. 8A to 8D are cross-sectional views showing the manufacturing process of the multilayer substrate following FIG.
  • FIG. 9 is a flowchart showing manufacturing steps of the multilayer substrate according to the first embodiment.
  • FIG. 10 is a diagram showing a prepreg in a comparative example.
  • FIGS. 11A and 11B are cross-sectional views illustrating the manufacturing process of the multilayer substrate according to the second embodiment.
  • FIGS. 12A and 12B are cross-sectional views illustrating the manufacturing process of the multilayer substrate according to the third embodiment.
  • FIGS. 13A and 13B are cross-sectional views showing the manufacturing process of the multilayer substrate according to the fourth embodiment.
  • FIG. 14 is a cross-sectional view showing a multilayer substrate according to the fifth embodiment.
  • the electronic device according to the present embodiment is preferably mounted on a vehicle such as an automobile, for example, and applied to drive various electronic devices for the vehicle. 2 to 4, a part of the mold resin layer 150, the solder resist 110, and the like are omitted.
  • the electronic device includes a multilayer substrate 10 having one surface 10a and another surface 10b, and electronic components 121 to 123 mounted on the one surface 10a of the multilayer substrate 10.
  • An electronic device is configured by forming a mold resin layer member 150 that seals the one surface 10a side of the multilayer substrate 10 and the electronic components 121 to 123 with a mold resin layer.
  • the multilayer substrate 10 includes a core layer 20, a buildup layer 30 on the front surface 20a side disposed on the front surface 20a of the core layer 20, and a buildup layer 40 on the back surface 20b side disposed on the back surface 20b side of the core layer 20. Is a laminated substrate.
  • the core layer 20 is configured as a prepreg layer made of an electrically insulating prepreg. As shown in FIG. 2, the core layer 20 includes a glass cloth 1 a and resin layers 21 and 22.
  • the resin layer 21 is formed by sealing the surface on the buildup layer 30 side of the glass cloth 1a with a resin material.
  • the resin layer 22 is formed by sealing the surface on the buildup layer 40 side of the glass cloth 1a with a resin material.
  • a resin material constituting the resin layers 21 and 22 a thermosetting resin material (for example, epoxy resin) having electrical insulation is used.
  • filler 3 made of ceramic having electrical insulation and thermal conductivity such as alumina and silica and excellent heat dissipation is mixed.
  • the glass cloth 1a is woven using a plurality of horizontal yarns 33 and a plurality of vertical yarns 34, as shown in FIG.
  • the horizontal yarn 33 is a bundle of a plurality of glass fibers extending in the horizontal direction (first direction).
  • the vertical yarn 34 is a bundle of a plurality of glass fibers extending in the vertical direction (second direction) orthogonal to the horizontal yarn 33.
  • Glass fiber has electrical insulation.
  • the central portion in the width direction is formed to have the largest thickness dimension.
  • the central part in the width direction is formed so as to have the largest thickness dimension.
  • the glass cloth 1a includes a plurality of bellies 35 and a plurality of basket holes 36.
  • the plurality of antinodes 35 are portions where the horizontal yarn 33 and the vertical yarn 34 overlap in the thickness direction.
  • the plurality of basket holes 36 are holes surrounded by two adjacent horizontal yarns 33 of the plurality of horizontal yarns 33 and two adjacent vertical yarns 34 of the plurality of vertical yarns 34.
  • the plurality of basket holes 36 are provided at positions surrounded by the four adjacent stomachs 35 among the plurality of stomachs 35.
  • FIG. 3A eight bells 35 are shown, and four basket holes 36 are shown.
  • the buildup layers 30 and 40 in FIG. 1 are configured as prepreg layers made of prepreg.
  • the buildup layer 30 includes a glass cloth 1 b and resin layers 31 and 32.
  • the resin layer 31 is formed by sealing the surface of the glass cloth 1b on the surface side surface layer wirings 61 to 63 (indicated by 61 and 62 in FIG. 4) with a resin material.
  • the resin layer 32 is formed by sealing the surface of the glass cloth 1b on the surface side inner layer wiring 511, 512 (shown 512 in FIG. 4) side with a resin material.
  • thermosetting resin material for example, epoxy resin
  • fillers made of ceramics having electrical insulation and thermal conductivity, such as alumina and silica, and excellent in heat dissipation are mixed.
  • the build-up layer 40 includes a glass cloth 1 c and resin layers 41 and 42.
  • the resin layer 41 is formed by sealing the surface of the glass cloth 1c on the rear surface layer wirings 71 and 72 (shown 71 in FIG. 5) side with a resin material.
  • the resin layer 42 is formed by sealing the surfaces of the glass cloth 1c on the back side inner layer wirings 521 and 522 (shown 522 in FIG. 5) with a resin material.
  • a thermosetting resin material for example, epoxy resin
  • the resin material constituting the resin layers 41 and 42 is mixed with a filler (not shown) made of ceramic having electrical insulation and thermal conductivity, such as alumina and silica, and excellent heat dissipation.
  • the glass cloths 1b and 1c of the present embodiment are woven using a plurality of horizontal yarns and a plurality of vertical yarns similarly to the glass cloth 1a. For this reason, the glass cloths 1b and 1c have a plurality of bellies 35 and a plurality of basket holes 36 (see FIG. 3A).
  • the plurality of surface-side inner layer wirings 511 and 512 are formed on the surface 20 a of the core layer 20 at the interface between the core layer 20 and the buildup layer 30.
  • the plurality of front-side inner layer wirings 511 and 512 are arranged separately on the surface 20 a of the core layer 20. That is, the plurality of front-side inner layer wirings 511 and 512 are arranged on the surface 20a of the core layer 20 with a space therebetween.
  • a region between two adjacent surface-side inner layer wirings among the plurality of surface-side inner layer wirings 511 and 512 is referred to as a region 513.
  • the plurality of back surface inner layer wirings 521 and 522 are formed on the back surface 20 b of the core layer 20 at the interface between the core layer 20 and the buildup layer 40.
  • the plurality of back side inner layer wirings 521 and 522 are arranged separately on the back side 20 b of the core layer 20. That is, the plurality of back surface inner layer wirings 521 and 522 are arranged on the back surface 20b of the core layer 20 with a space therebetween.
  • a region between two adjacent back surface side inner layer wirings among the plurality of back surface side inner layer wirings 521 and 522 (that is, a region between back surface side inner layer wirings forming an interval) is referred to as a region 514.
  • the build-up layer 30 is laminated on the core layer 20 so as to cover the surface 20a of the core layer 20 together with the plurality of surface-side inner layer wirings 511 and 512.
  • the buildup layer 40 is laminated on the core layer 20 so as to cover the back surface 20b of the core layer 20 together with the plurality of back surface side inner layer wirings 521 and 522.
  • the resin layer 32 of the buildup layer 30 seals the plurality of front side inner layer wirings 511 and 512 in a state where the plurality of regions 513 are filled. Then, on the back surface 20 b of the core layer 20, the resin layers 40 b of the build-up layer 40 seal the plurality of back surface inner layer wirings 521 and 522 in a state where the plurality of regions 514 are filled.
  • the surface side surface wirings 61 to 63 are formed on the surface 30 a of the buildup layer 30.
  • the surface-side surface layer wirings 61 to 63 are bonded electrically connected to the mounting land 61 on which the electronic components 121 to 123 are mounted and the electronic components 121 and 122 via the bonding wires 141 and 142.
  • backside surface layer wirings 71 and 72 are formed on the surface 40 a of the buildup layer 40.
  • the back surface layer wirings 71 and 72 are a back surface pattern 71 connected to the back surface inner layer wirings 521 and 522 through filled vias, which will be described later, and a heat sink pattern 72 provided with a heat sink for heat dissipation. .
  • the inner layer wirings 511, 512, 521, and 522 constitute conductors.
  • the surface 30 a of the buildup layer 30 is one surface of the buildup layer 30 opposite to the core layer 20, and is a surface that becomes the one surface 10 a of the multilayer substrate 10.
  • the surface 40 a of the buildup layer 40 is one surface of the buildup layer 40 opposite to the core layer 20, and is a surface that becomes the other surface 10 b of the multilayer substrate 10.
  • the inner layer wirings 511, 512, 521, 522, the surface side surface layer wirings 61 to 63, and the back side surface layer wirings 71 and 72 are specifically described later, but a metal foil such as copper or metal plating is appropriately laminated. Consists of conductors.
  • the inner layer wirings 511, 512, 521, 522, the surface side surface layer wirings 61 to 63, and the back surface side surface layer wirings 71 and 72 have a thickness dimension of 35 ⁇ m or more.
  • the front side inner layer wirings 511 and 512 and the rear side inner layer wirings 521 and 522 are electrically and thermally connected through a through via 81 provided through the core layer 20.
  • the through via 81 is configured such that a through electrode 81b such as copper is formed on the wall surface of the through hole 81a penetrating the core layer 20 in the thickness direction, and a filler 81c is filled in the through hole 81a. Has been.
  • front side inner layer wirings 511 and 512, the front side surface layer wirings 61 to 63, and the rear side inner layer wirings 521 and 522 and the rear side surface layer wirings 71 and 72 are appropriately connected to the buildup layers 30 and 40 in the thickness direction. They are electrically and thermally connected through filled vias 91 and 101 provided therethrough.
  • the filled vias 91 and 101 are configured such that through holes 91a and 101a penetrating the build-up layers 30 and 40 in the thickness direction are filled with through electrodes 91b and 101b such as copper.
  • the through electrodes 81b, 91b, and 101b are made of metal plating such as copper.
  • the solder resist 110 that covers the front surface pattern 63 and the back surface pattern 71 is formed on the front surfaces 30a and 40a of the buildup layers 30 and 40.
  • the solder resist 110 that covers the surface pattern 63 is formed with an opening that exposes a portion of the surface pattern 63 that is connected to an external circuit in a cross section different from that in FIG.
  • the electronic parts 121 to 123 are passive power elements 121 such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductors Field-Effect Transistors), control elements 122 such as microcomputers, and chip capacitors and resistors. Element 123.
  • passive power elements 121 such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductors Field-Effect Transistors), control elements 122 such as microcomputers, and chip capacitors and resistors.
  • control elements 122 such as microcomputers, and chip capacitors and resistors.
  • the electronic components 121 to 123 are mounted on the land 61 via the solder 130 and are electrically and mechanically connected to the land 61.
  • the power element 121 and the control element 122 are also electrically connected to the land 62 formed in the periphery via bonding wires 141 and 142 such as Al and Au.
  • the first wiring groups 511 and 521 described above are the front and back inner layer wirings 511 and 521 connected to the power element 121 having a relatively large current, while the second wiring groups 512 and 522 described above. These are front and back inner layer wirings 512 and 522 connected to the control element 122 and the passive element 123 having a relatively small current.
  • the power element 121, the control element 122, and the passive element 123 are described as examples of the electronic components 121 to 123, but the electronic components 121 to 123 are not limited to these.
  • the mold resin layer 150 seals the lands 61 and 62 and the electronic components 121 to 123, and a general mold material such as an epoxy resin is formed by a transfer mold method using a mold, a compression mold method, or the like. It is a thing.
  • the mold resin layer 150 is formed only on the one surface 10a of the multilayer substrate 10. That is, the electronic device of this embodiment has a so-called half mold structure. Further, on the other surface 10b side of the multilayer substrate 10, although not particularly shown, a heat sink is provided on the heat sink pattern 72 via heat radiation grease or the like.
  • the glass cloth 1b is formed so as to continuously cover the plurality of surface-side inner layer wirings 511 and 512 and the plurality of regions 513.
  • region 513 among the glass cloth 1b is bent so that it may approach the core layer 20 side rather than the part which covers the some surface side inner layer wiring 511,512 among the glass cloth 1b.
  • the portion of the glass cloth 1b that covers the region 513 is located closer to the core layer 20 than the upper surfaces 512a of the plurality of front-side inner-layer wirings 511 and 512.
  • the upper surface 512 a is an end portion on the opposite side to the core layer 20 among the plurality of front surface side inner layer wirings 511 and 512.
  • the portion of the glass cloth 1 b that covers the region 513 enters the core layer 20 side from the extension line Y ⁇ b> 1 (dashed line in FIG. 4) of the upper surface 512 a of the two surface side inner layer wirings 512 adjacent to the region 513.
  • An example is shown.
  • the thickness dimension L1 is the thickness dimension of the central portion of the belly 35 constituting the glass cloth 1b.
  • the central portion of the belly 35 is a portion where the central portion in the width direction of the horizontal yarn 33 overlaps with the central portion in the width direction of the vertical yarn 34, and is the portion of the belly 35 having the largest thickness dimension.
  • the reference position of the glass cloth 1b for setting the thickness dimension L2 is the upper part of the glass cloth 1b.
  • the upper part of the glass cloth 1b is the central part of the antinode 35 located on the surface side surface layer wiring 61 to 63 side among the antinodes 35.
  • the glass cloth 1c is formed so as to continuously cover the plurality of back side inner layer wirings 521 and 522 and the plurality of regions 514.
  • region 514 among the glass cloth 1c is bent so that it may approach the core layer 20 side rather than the part which covers the some back surface side inner layer wiring 521,522 of the glass cloth 1c.
  • the portion of the glass cloth 1c that covers the region 514 enters the core layer 20 side from the lower surfaces 522a of the plurality of back surface inner layer wirings 521 and 522.
  • the said lower surface is a surface on the opposite side to the core layer 20 among the plurality of back side inner layer wirings 521 and 522.
  • the portion of the glass cloth 1 c that covers the region 514 enters the core layer 20 side from the extension line Y ⁇ b> 2 (dashed line in FIG. 5) on the lower surface of the two surface-side inner layer wirings 522 adjacent to the region 514.
  • An example is shown.
  • the thickness dimension L3 is the thickness dimension of the central portion of the belly 35 constituting the glass cloth 1c.
  • the central portion of the belly 35 is a portion where the central portion in the width direction of the horizontal yarn 33 overlaps with the central portion in the width direction of the vertical yarn 34, and is the portion of the belly 35 having the largest thickness dimension.
  • the reference position of the glass cloth 1c for setting the dimension L4 is the lower part of the glass cloth 1c.
  • the lower part of the glass cloth 1c is a central portion of the belly 35 located on the back surface side surface wiring 71, 72 side among the plurality of belly 35.
  • the thickness dimensions L3 and L4 of the glass cloths 1b and 1c of the present embodiment are set to 10 ⁇ m to 30 ⁇ m.
  • the basket holes of the glass cloths 1 b and 1 c are smaller than the basket holes of the glass cloth 1 a of the core layer 20.
  • the basket holes of the glass cloths 1b and 1c have a diameter set to 100 ⁇ m or less.
  • the ratio (wt%) occupied by the mass of the resin material in the mass of the buildup layer 30 is set to be 80% or more.
  • the ratio (wt%) occupied by the mass of the resin material in the mass of the buildup layer 40 is set to be 80% or more.
  • the ratio (wt%) of the mass of the buildup layer 30 occupied by the filler mass (wt%) is larger than the ratio (wt%) of the mass of the core layer 20 occupied by the filler.
  • the ratio (wt%) of the mass of the buildup layer 40 occupied by the filler mass (wt%) is larger than the ratio (wt%) of the mass of the core layer 20 occupied by the filler.
  • the ratio (wt%) of the mass of the filler to the mass of the buildup layers 30 and 40 is set to 50% or more.
  • FIGS. 5, 6, and 7 are cross-sectional views of the vicinity of a portion where the power element 121 is mounted in the multilayer substrate 10.
  • FIG. 6 (a) a structure in which metal foils 161 and 162 such as copper foil are arranged on the front surface 20a and the back surface 20b of the core layer 20 is prepared. Then, as shown in FIG. 6B, a through hole 81a penetrating the metal foil 161, the core layer 20, and the metal foil 162 is formed by a drill or the like.
  • electroless plating or electroplating is performed to form a metal plating 163 such as copper on the wall surface of the through hole 81a and the metal foils 161 and 162.
  • a through electrode 81b composed of the metal plating 163 is formed on the wall surface of the through hole 81a.
  • catalysts such as palladium.
  • a filler 81 c is arranged in a space surrounded by the metal plating 163.
  • the through via 81 having the through hole 81a, the through electrode 81b, and the filler 81c is formed.
  • lid plating is performed by electroless plating, electroplating, or the like, and metal plating 164, 165 such as copper is formed on the metal plating 163 and the filler 81c.
  • the metal layer M1 in which the metal foil 161, the metal plating 163, and the metal plating 164 are sequentially laminated is formed on the front surface 20a side of the core layer 20, and on the back surface 20b side, A metal layer M2 in which a metal foil 162, a metal plating 163, and a metal plating 165 are sequentially laminated is formed.
  • a resist (not shown) is disposed on the metal platings 164 and 165. Then, wet etching or the like is performed using the resist as a mask, and the metal plating 164, the metal plating 163, and the metal foil 161 are appropriately patterned to form a plurality of surface side inner layer wirings 511 and 512, and the metal plating 165 and the metal plating 163.
  • the metal foil 162 is appropriately patterned to form a plurality of back surface inner layer wirings 521 and 522.
  • the plurality of front surface side inner layer wirings 511 and 512 are configured by the metal layer M1 in which the metal foil 161, the metal plating 163, and the metal plating 164 are laminated, and the plurality of back surface side inner layer wirings 521 and 522 are
  • the metal layer 162 includes a metal foil 162, a metal plating 163, and a metal plating 165.
  • the plurality of front surface side inner layer wirings 511 and 512 are arranged on the front surface 20a of the core layer 20, and are arranged on the rear surface 20b of the plurality of back surface side inner layer wirings 521 and 522 core layer 20 (step 100).
  • the metal foil 161, the metal plating 163, the metal plating 164, the metal foil 162, the metal plating 163, and the metal plating 165 are collectively shown as one layer.
  • prepregs 30A and 40A are prepared (step 110).
  • the prepreg 30A is composed of resin layers 31 and 32 and a glass cloth 1b.
  • the prepreg 40A is composed of resin layers 41 and 42 and a glass cloth 1c.
  • a prepreg 30 ⁇ / b> A and a metal plate 166 such as copper are laminated on the surface-side inner layer wirings 511 and 512 on the surface 20 a side in the core layer 20. Further, on the back surface 20 b side of the core layer 20, a prepreg 40 ⁇ / b> A and a metal plate 167 such as copper are laminated on the back surface inner layer wirings 521 and 522.
  • the laminate 168 in which the metal plate 166, the prepreg 30A, the front surface inner layer wirings 511 and 512, the core layer 20, the back surface inner layer wirings 521 and 522, the prepreg 40A, and the metal plate 167 are sequentially stacked from the top.
  • the resin material constituting the prepregs 30A and 40A is temporarily cured and has fluidity.
  • the laminated body 168 is heated while being pressed in the laminating direction (step 120). That is, the laminate 168 is heated to flow the resin material constituting the prepregs 30A and 40A, one of the core layer 20 and the prepreg 30A is pressed against the other, and one of the core layer 20 and the prepreg 40A is pressed to the other Press against.
  • the portion of the glass cloth 1b of the build-up layer 30 that covers the region 513 is bent so as to be closer to the core layer 20 than the portion of the glass cloth 1b that covers the plurality of front side inner layer wirings 511 and 512.
  • region 513 among the glass cloth 1b penetrates into the core layer 20 side rather than the upper surface of the some surface side inner layer wiring 511,512.
  • the resin material constituting the prepreg 30 ⁇ / b> A is filled in a region other than the plurality of surface side inner layer wirings 511 and 512 in the surface 20 a of the core layer 20. Thereby, the resin material constituting the prepreg 30 ⁇ / b> A is embedded between the plurality of regions 513. Further, a resin material constituting the prepreg 40 ⁇ / b> A is embedded between the plurality of regions 514.
  • the prepregs 30A and 40A are cured to integrate the laminate 168.
  • the cured prepreg 30 ⁇ / b> A is formed as the buildup layer 30
  • the cured prepreg 40 ⁇ / b> A is formed as the buildup layer 40.
  • a through hole 91a that penetrates the metal plate 166 and the build-up layer 30 and reaches the surface-side inner-layer wirings 511 and 512 is formed by a laser or the like.
  • a through hole 101a that penetrates through the metal plate 167 and the buildup layer 40 and reaches the back surface inner wirings 521 and 522 is formed.
  • the through electrode 91b and the through electrode 101b shown in FIG. 1 are configured by the metal plating 169 embedded in the through holes 91a and 101a formed in the buildup layer 30. Further, filled vias 91 and 101 in which through electrodes 91b and 101b are embedded in the through holes 91a and 101a are formed.
  • the metal plate 166 and the metal plating 169 are collectively shown as one layer.
  • a resist (not shown) is disposed on the metal plates 166 and 167.
  • the metal plates 166 and 167 are patterned by performing wet etching or the like using a resist as a mask, and the surface side surface layer wirings 61 to 63 and the back side surface layer wirings 71 and 72 are formed by appropriately forming metal plating.
  • the front surface side wirings 61 to 63 are configured to have the metal plate 166 and the metal plating 169
  • the back surface side wirings 71 and 72 are configured to have the metal plate 167 and the metal plating 169. ing.
  • the multilayer substrate 10 is manufactured by arranging the solder resist 110 on the surfaces 30a and 40a of the buildup layers 30 and 40, respectively, and appropriately patterning them. 8D, all of the solder resist 110 on the surface 30a has been removed, but the solder resist 110 remains in other regions as shown in FIG. Yes.
  • the electronic components 121 to 123 are mounted on the land 61 via the solder 130. Then, wire bonding is performed between the power element 121 and the control element 122 and the land 62, and the power element 121 and the control element 122 and the land 62 are electrically connected. Subsequently, the mold resin layer 150 is formed by a transfer molding method using a mold, a compression molding method, or the like so that the lands 61 and 62 and the electronic components 121 to 123 are sealed.
  • the plurality of surface-side inner-layer wirings 511 and 512 are arranged at intervals on the surface 20 a of the core layer 20.
  • a plurality of back surface side inner layer wirings 521 and 522 are arranged on the back surface 20b of the core layer 20 with a space therebetween.
  • a prepreg 30A formed by sealing both surfaces of the glass cloth 1b with a resin material and a prepreg 40A formed by sealing both surfaces of the glass cloth 1c with a resin material are prepared.
  • the prepreg 30 ⁇ / b> A is opposed to the front surface 20 a of the core layer 20, and the prepreg 40 ⁇ / b> A is opposed to the back surface 20 b of the core layer 20.
  • the glass cloth 1b is formed so as to continuously cover the plurality of surface-side inner layer wirings 511 and 512 and the plurality of regions 513.
  • the glass cloth 1c is formed so as to continuously cover the plurality of back surface side inner layer wirings 521 and 522 and the plurality of regions 513. Then, pressure is applied to the prepreg 30A, the core layer 20, and the prepreg 40A in the stacking direction.
  • region 513 among the glass cloth 1b is bent so that it may approach the core side 20 rather than the site
  • the portion of the glass cloth 1c that covers the region 514 is bent so as to be closer to the core side 20 than the portion of the glass cloth 1c that covers the plurality of back side inner layer wirings 521 and 522. Therefore, the part which covers the area
  • the ratio “wt%” of the mass of the resin material out of the mass of the buildup layers 30 and 40 is set to be 80% or more. For this reason, since the resin material of sufficient quantity can be supplied with respect to the area
  • the thickness dimension L1 of the glass cloth 1b is smaller than the distance L2 between the upper part of the glass cloth 1b and the surface-side surface wirings 61 to 63.
  • the thickness dimension L3 of the glass cloth 1c is smaller than the distance L4 between the lower part of the glass cloth 1c and the back surface side wirings 71 and 72. For this reason, even if it pressurizes in a manufacturing process, it can fully curve corresponding to field 513,514.
  • the basket holes of the glass cloths 1b and 1c are set to have a diameter of 100 ⁇ m or less.
  • the basket hole of the glass cloth 1 is set to have a diameter larger than 100 ⁇ m, when the laminate 168 is pressed, the basket hole is passed through the basket hole from the resin layer 31 side as indicated by the thick line arrow in FIG. The resin material moves to the resin layer 32 side. Therefore, no pressure is applied from the resin layer 31 to the glass cloth 1. For this reason, the glass cloth 1 cannot be curved.
  • the basket holes of the glass cloths 1b and 1c are set to have a diameter of 100 ⁇ m or less as described above. For this reason, when the laminated body 168 is pressurized, it becomes difficult for the resin material to move from the resin layer 31 side to the resin layer 32 side through the basket hole. Therefore, sufficient pressure can be applied from the resin layer 31 to the glass cloths 1b and 1c. Thereby, the glass cloth 1b, 1c can be curved sufficiently.
  • the diameter of the basket hole of the glass cloth 1b, 1c is smaller than the diameter of the basket hole of the glass cloth 1a. For this reason, compared with the case where the diameter of the basket hole of the glass cloth 1b, 1c is larger than the diameter of the basket hole of the glass cloth 1a, the resin is passed through the basket hole from the resin layer 31 side when the laminate 168 is pressed. It becomes difficult for the resin material to move to the layer 32 side. Therefore, sufficient pressure can be applied from the resin layer 31 to the glass cloths 1b and 1c. Thereby, the glass cloth 1b, 1c can be curved sufficiently.
  • the ratio “wt%” of the mass of the buildup layers 30 and 40 occupied by the filler mass is larger than the ratio “wt%” of the mass of the core layer 20 occupied by the filler. .
  • the viscosity of the resin material mixed with filler can be increased. Therefore, when the laminated body 168 is pressurized, sufficient pressure can be applied from the resin layer 31 to the glass cloths 1b and 1c. Thereby, the glass cloth 1b, 1c can be curved sufficiently. In addition, sufficient thermal conductivity can be secured in the buildup layers 30 and 40.
  • the glass cloth 1b is formed so as to continuously cover the plurality of front side inner layer wirings 511 and 512 and the plurality of regions 513. For this reason, the strength of the buildup layer 30 can be increased. In addition to this, when a crack occurs in the resin layer 31 in the build-up layer 30, the crack occurs in the resin layer 31 from the resin layer 31 side through the cut of the glass cloth 1 b due to the crack in the resin layer 31. Progress can be suppressed.
  • the glass cloth 1c is formed so as to continuously cover the plurality of back surface side inner layer wirings 521 and 522 and the plurality of regions 514. For this reason, the same effect as the buildup layer 30 is obtained in the buildup layer 40.
  • FIGS. 11A and 11B show a part of the manufacturing process of the multilayer substrate 10 of the present embodiment.
  • the metal plate 166 is provided with a convex portion 166a.
  • the convex portion 166a is formed so as to protrude from the portion corresponding to the region 513 in the metal plate 166 to the core layer 20 side.
  • the metal plate 166 pressurizes the prepreg 30 ⁇ / b> A toward the core layer 20 by the convex portion 166 a. That is, the metal plate 166 is pressed against the prepreg 30 ⁇ / b> A from the opposite side of the core layer 20. Thereby, the convex part 166a can press the part which covers the area
  • the portion of the glass cloth 1b that covers the region 513 is reliably bent so as to be closer to the core layer 20 side than the portion of the glass cloth 1b that covers the plurality of front-side inner layer wirings 511 and 512. it can. Thereby, the resin material which comprises the prepreg 30A can be reliably filled in the some area
  • the example using the metal plate 166 provided with the convex portion 166a has been described, but in addition to this, the metal plate 167 provided with the convex portion may be used.
  • transformation of the glass sheet 1c of the prepreg 40A can be urged
  • the resin material which comprises the prepreg 40A can be reliably filled in the some area
  • FIGS. 12A and 12B show a part of the manufacturing process of the multilayer substrate 10 of the present embodiment.
  • a press machine 600 including a convex mold 601 is used.
  • the molding die 601 is a metal mold body 603 provided with a metal convex portion 604.
  • the convex portion 604 is formed so as to protrude from the portion corresponding to the region 513 in the mold body 603 to the core layer 20 side.
  • the mold 601 is disposed on the upper side of the metal base 602.
  • the laminated body 168 is configured by laminating the surface side inner layer wirings 511 and 512 excluding the metal plates 166 and 167, the prepreg 30A, and the like on the core layer 20. Then, with the release sheet 620 made of a Teflon (registered trademark) sheet or the like sandwiched between the laminate 168 and the mold 600, the release sheet 620 and the laminate 168 are replaced with the mold 600 and the metal. It arrange
  • molding die 600 can urge the curve of the site
  • the release sheet 620 is removed from the upper surface 300 of the prepreg 30 ⁇ / b> A after the laminate 168 is pressed. Then, by further laminating a resin layer on the upper surface 300 of the prepreg 30A, the upper surface 300 side of the prepreg 30A is flattened.
  • the base 610 is provided with the convex portion.
  • a thing may be used.
  • the deformation of the glass sheet 1c of the prepreg 40A can be urged by the convex portion.
  • the resin material which comprises the prepreg 40A can be reliably filled in the some area
  • FIGS. 13A and 13B show a part of the manufacturing process of the multilayer substrate 10 of the present embodiment.
  • a hydrostatic press 600A including a molding die 601A made of a rubber mold formed in a balloon shape is used.
  • the pressure applied with respect to the prepreg 30A can be made uniform in a surface direction. Therefore, as in the second and third embodiments, the portion of the glass cloth 1b that covers the region 513 can be reliably bent.
  • the glass cloth 1b shape of the prepreg 30A can be made to follow the unevenness
  • the upper surface 300 side of the prepreg 30A may be flattened by pressurizing the prepreg 30A and then laminating a resin layer on the upper surface 300 of the prepreg 30A.
  • the portion of the glass cloth 1b that covers the region 513 is bent, and the portion of the glass cloth 1b that covers the region 513 is closer to the core layer 20 than the upper surface 512a of the surface-side inner layer wirings 511 and 512.
  • the present invention is not limited to this, and the following may be used.
  • the portion of the glass cloth 1 b that covers the region 513 is bent so that it is closer to the core side 20 than the portion of the glass cloth 1 b that covers the plurality of front surface inner layer wirings 511 and 512.
  • a portion of the glass cloth 1b that covers the region 513 may be positioned on the opposite side of the core layer 20 with respect to the upper surface 512a of the front-side inner-layer wirings 511 and 512.
  • the example using the core layer 20 made of the prepreg layer has been described.
  • the core layer 20 made of ceramic or the like may be used as the insulating layer.
  • the embodiment according to the present disclosure is not limited to the above-described embodiment, and can be appropriately changed within the scope of the technical idea of the present disclosure.
  • the above embodiments are not irrelevant to each other, and can be combined as appropriate unless the combination is clearly impossible. Also, the above embodiments are not limited to the illustrated examples. Absent.

Abstract

Provided is a multilayer substrate (10) such that occurrence of voids is suppressed, and a method for manufacturing the multilayer substrate. According to one embodiment, in the manufacturing of the multilayer substrate (10), a pre-preg (30A) is brought into opposition with a surface (20a) of a core layer (20). A glass cloth (1b) is formed so as to continuously cover a plurality of surface-side inner-layer wires (511 and 512) and a plurality of regions (513). Subsequently, pressure is applied to the pre-preg (30A), the core layer (20), and a pre-preg (40A) in the direction of stacking. By bending the portions of the glass cloth (1b）at regions (513) forming gaps so as to be closer to the core layer side than the portions of the glass cloth (1b) at the regions covering the plurality of surface-side inner-layer wires (511 and 512) are, resin material is filled within the regions (513) forming the gaps.

Description

多層基板、および多層基板の製造方法Multilayer substrate and method for manufacturing multilayer substrate 関連出願の相互参照Cross-reference of related applications
　本出願は、２０１３年６月１３日に出願された日本国特許出願２０１３－１２４９６９号に基づくものであり、ここにこれを参照により援用する。 This application is based on Japanese Patent Application No. 2013-124969 filed on June 13, 2013, which is incorporated herein by reference.
　本開示は、多層基板、および多層基板の製造方法に関するものである。 The present disclosure relates to a multilayer substrate and a method for manufacturing the multilayer substrate.
　従来、多層基板では、絶縁層の表面上にそれぞれ間隔を空けて配置されている複数の導体と、絶縁層の表面側および複数の導体を封止するように絶縁層の表面側に積層されているプリプレグとを備えるものがある（例えば、特許文献１参照）。 Conventionally, in a multilayer substrate, a plurality of conductors arranged on the surface of the insulating layer are spaced apart from each other, and the surface side of the insulating layer and the surface side of the insulating layer are sealed so as to seal the plurality of conductors. Some prepregs are provided (see, for example, Patent Document 1).
　プリプレグは、ガラスクロスを備えてこのガラスクロスの両面側を樹脂材料によって封止するように構成されている。そして、複数の導体のそれぞれの間には樹脂材料が埋め込まれている。 The prepreg is configured to include a glass cloth and to seal both sides of the glass cloth with a resin material. A resin material is embedded between each of the plurality of conductors.
特開２００７－１７６１６９号公報JP 2007-176169 A
　上記特許文献１の基板において、プリプレグの熱伝導率を高めるために、多くのフィラが混ざった樹脂材料でプリプレグを構成すると、プリプレグを構成する樹脂材料の流動性が低くなる。 In the substrate of Patent Document 1, if the prepreg is made of a resin material mixed with many fillers in order to increase the thermal conductivity of the prepreg, the fluidity of the resin material constituting the prepreg becomes low.
　このため、プリプレグを構成する樹脂材料を複数の導体のそれぞれの間に充填する場合、絶縁層の表面側にプリプレグを積層して絶縁層にプリプレグを押し付けても、複数の導体のそれぞれの間に十分な量の樹脂材料を供給することができない。このため、上記それぞれの間に、樹脂材料の未充填部分、すなわちボイドが発生する恐れがある。 Therefore, when the resin material constituting the prepreg is filled between each of the plurality of conductors, even if the prepreg is laminated on the surface side of the insulating layer and the prepreg is pressed against the insulating layer, the prepreg is interposed between the plurality of conductors. A sufficient amount of resin material cannot be supplied. For this reason, there exists a possibility that the unfilled part of a resin material, ie, a void, may generate | occur | produce between said each.
　本開示は上記点に鑑みて、ボイドの発生を抑制するようにした多層基板、および多層基板の製造方法を提供することを目的とする。 In view of the above points, it is an object of the present disclosure to provide a multilayer substrate and a method for manufacturing the multilayer substrate that suppress generation of voids.
　本開示の一例に係る多層基板は、電気絶縁材料からなる絶縁層と、絶縁層の表面に設けられたもので、間隔を空けて配置された導体と、第１のガラスクロスと第１のガラスクロスの両面側を樹脂材料で封止する樹脂層とを備えるプリプレグを、導体と共に絶縁層の表面を覆うように絶縁層に積層されてなるビルドアップ層と、を備え、絶縁層の表面側では、樹脂層を構成する樹脂材料が間隔を構成する領域内に充填された状態で導体を封止しており、第１のガラスクロスが導体および間隔を構成する領域を連続して覆うように形成されており、第１のガラスクロスのうち間隔を構成する領域を覆う部位は、第１のガラスクロスのうち導体を覆う部位よりも絶縁層側に近づくように曲がっている多層基板である。 A multilayer substrate according to an example of the present disclosure includes an insulating layer made of an electrically insulating material, a conductor provided on the surface of the insulating layer, spaced apart, a first glass cloth, and a first glass. A prepreg having a resin layer that seals both surfaces of the cloth with a resin material, and a build-up layer that is laminated on the insulating layer so as to cover the surface of the insulating layer together with the conductor, and on the surface side of the insulating layer The conductor is sealed in a state where the resin material constituting the resin layer is filled in the region constituting the interval, and the first glass cloth is formed so as to continuously cover the conductor and the region constituting the interval. The part which covers the area | region which comprises a space | interval among the 1st glass cloths is a multilayer substrate bent so that it may approach the insulating layer side rather than the part which covers a conductor among 1st glass cloths.
　本開示において、「間隔を空けて配置された導体」とは、それぞれ離れて配置されている複数の導体以外に、１つの導体において隙間を介して対向する２つの部位を有するものを含むものとして定義される。複数の導体がそれぞれ離れて配置されている場合には、複数の導体のうち隣接する２つの導体の間を「間隔を構成する領域」と定義する。１つの導体において隙間を介して対向する２つの部位を有するものの場合には、２つの部位の間の領域を「間隔を構成する領域」と定義する。 In the present disclosure, “a conductor disposed at an interval” includes, in addition to a plurality of conductors spaced apart from each other, a conductor having two portions facing each other through a gap. Defined. In the case where a plurality of conductors are arranged apart from each other, a region between two adjacent conductors among the plurality of conductors is defined as a “region forming a gap”. In the case of one conductor having two parts facing each other through a gap, an area between the two parts is defined as an “area constituting an interval”.
　上記多層基板によれば、プリプレグを構成する樹脂材料がガラスクロスによって間隔を構成する領域内に押し込まれる形となる。よって、間隔を構成する領域内に十分な量の樹脂材料を充填することができる。このため、ボイドの発生を抑制することができる。 According to the multilayer substrate, the resin material constituting the prepreg is pushed into the region constituting the interval by the glass cloth. Therefore, a sufficient amount of the resin material can be filled in the region constituting the interval. For this reason, generation | occurrence | production of a void can be suppressed.
　本開示の一例に係る多層基板の製造方法は、間隔を空けて配置された導体を、電気絶縁材料からなる絶縁層の表面に形成することと、ガラスクロスとガラスクロスの両面側を樹脂材料で封止する樹脂層とを備えるプリプレグを用意することと、絶縁層の表面側における導体と間隔を構成する領域とをガラスクロスが連続して覆うように絶縁層およびプリプレグを対向させることと、絶縁層およびプリプレグを対向させた後に、絶縁層およびプリプレグのうち一方を他方に対して加圧して、ガラスクロスのうち間隔を構成する領域を覆う部位を、ガラスクロスのうち導体を覆う部位よりも縁層側に近づくように曲げることにより、樹脂層を構成する樹脂材料を間隔を構成する領域内に充填することと、を備える。 In the method for manufacturing a multilayer substrate according to an example of the present disclosure, conductors arranged at intervals are formed on the surface of an insulating layer made of an electrically insulating material, and both surfaces of the glass cloth and the glass cloth are made of a resin material. Preparing a prepreg having a resin layer to be sealed, making the insulating layer and the prepreg face each other so that a glass cloth continuously covers a conductor and a region forming a space on the surface side of the insulating layer, and insulating After the layer and the prepreg are made to face each other, one of the insulating layer and the prepreg is pressed against the other, and the part of the glass cloth that covers the region forming the interval is bordered more than the part of the glass cloth that covers the conductor Filling the resin material constituting the resin layer into the region constituting the interval by bending the layer so as to approach the layer side.
　このような多層基板の製造方法によれば、上述の多層基板と同様に、間隔を構成する領域内に、プリプレグを構成する樹脂材料がガラスクロスによって押し込まれる。よって、間隔を構成する領域内に十分な量の樹脂材料を充填することができる。このため、ボイドの発生を抑制することができる。 According to such a method for manufacturing a multilayer substrate, the resin material constituting the prepreg is pushed into the region constituting the interval by the glass cloth, similarly to the multilayer substrate described above. Therefore, a sufficient amount of the resin material can be filled in the region constituting the interval. For this reason, generation | occurrence | production of a void can be suppressed.
図１は、第１実施形態にかかる電子装置の断面図である。FIG. 1 is a cross-sectional view of the electronic device according to the first embodiment. 図２は、図１中のコア層のII部の拡大図である。FIG. 2 is an enlarged view of a II part of the core layer in FIG. 図３（ａ）は、図２中のガラスクロスの正面図であり、図３（ｂ）は、図３（ａ）中のIIIB-IIIB線断面図である。3 (a) is a front view of the glass cloth in FIG. 2, and FIG. 3 (b) is a cross-sectional view taken along the line IIIB-IIIB in FIG. 3 (a). 図４は、図１中のIV部の拡大図である。FIG. 4 is an enlarged view of a portion IV in FIG. 図５は、図１中のV部の拡大図である。FIG. 5 is an enlarged view of a portion V in FIG. 図６（ａ）～（ｄ）は、図１の多層基板の製造工程を示す断面図である。6 (a) to 6 (d) are cross-sectional views showing manufacturing steps of the multilayer substrate of FIG. 図７（ａ）～（ｄ）は、図６に続く多層基板の製造工程を示す断面図である。7A to 7D are cross-sectional views illustrating the manufacturing process of the multilayer substrate subsequent to FIG. 図８（ａ）～（ｄ）は、図７に続く多層基板の製造工程を示す断面図である。8A to 8D are cross-sectional views showing the manufacturing process of the multilayer substrate following FIG. 図９は、第１実施形態の多層基板の製造工程を示すフローチャートである。FIG. 9 is a flowchart showing manufacturing steps of the multilayer substrate according to the first embodiment. 図１０は、比較例におけるプリプレグを示す図である。FIG. 10 is a diagram showing a prepreg in a comparative example. 図１１（ａ）と（ｂ）は、第２実施形態にかかる多層基板の製造工程を示す断面図である。FIGS. 11A and 11B are cross-sectional views illustrating the manufacturing process of the multilayer substrate according to the second embodiment. 図１２（ａ）と（ｂ）は、第３実施形態にかかる多層基板の製造工程を示す断面図である。FIGS. 12A and 12B are cross-sectional views illustrating the manufacturing process of the multilayer substrate according to the third embodiment. 図１３（ａ）と（ｂ）は、第４実施形態にかかる多層基板の製造工程を示す断面図である。FIGS. 13A and 13B are cross-sectional views showing the manufacturing process of the multilayer substrate according to the fourth embodiment. 図１４は、第５実施形態にかかる多層基板を示す断面図である。FIG. 14 is a cross-sectional view showing a multilayer substrate according to the fifth embodiment.
　以下、実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、説明の簡略化を図るべく、図中、同一符号を付してある。 Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.
　（第１実施形態）
　以下、第１実施形態にかかる電子装置について、図１、図２を参照して説明する。本実施形態にかかる電子装置は、例えば、自動車等の車両に搭載され、車両用の各種電子装置を駆動するために適用されると好適である。なお、図２～図４では、モールド樹脂層１５０やソルダーレジスト１１０等を一部省略してある。 (First embodiment)
Hereinafter, the electronic device according to the first embodiment will be described with reference to FIGS. 1 and 2. The electronic device according to the present embodiment is preferably mounted on a vehicle such as an automobile, for example, and applied to drive various electronic devices for the vehicle. 2 to 4, a part of the mold resin layer 150, the solder resist 110, and the like are omitted.
　図１に示されるように、電子装置は、一面１０ａおよび他面１０ｂを有する多層基板１０と、多層基板１０の一面１０ａ上に搭載された電子部品１２１～１２３と、を備えている。そして、多層基板１０の一面１０ａ側と電子部品１２１～１２３とをモールド樹脂層によって封止するモールド樹脂層部材１５０を構成することにより、電子装置が構成されている。 As shown in FIG. 1, the electronic device includes a multilayer substrate 10 having one surface 10a and another surface 10b, and electronic components 121 to 123 mounted on the one surface 10a of the multilayer substrate 10. An electronic device is configured by forming a mold resin layer member 150 that seals the one surface 10a side of the multilayer substrate 10 and the electronic components 121 to 123 with a mold resin layer.
　多層基板１０は、コア層２０と、コア層２０の表面２０ａに配置された表面２０ａ側のビルドアップ層３０と、コア層２０の裏面２０ｂ側に配置された裏面２０ｂ側のビルドアップ層４０とを備える積層基板である。 The multilayer substrate 10 includes a core layer 20, a buildup layer 30 on the front surface 20a side disposed on the front surface 20a of the core layer 20, and a buildup layer 40 on the back surface 20b side disposed on the back surface 20b side of the core layer 20. Is a laminated substrate.
　コア層２０は、電気絶縁性を有するプリプレグよりなるプリプレグ層として構成されている。コア層２０は、図２に示すように、ガラスクロス１ａと、樹脂層２１、２２とから構成されている。樹脂層２１は、ガラスクロス１ａのうちビルドアップ層３０側の面を樹脂材料で封止してなるものである。樹脂層２２は、ガラスクロス１ａのうちビルドアップ層４０側の面を樹脂材料で封止してなるものである。樹脂層２１、２２を構成する樹脂材料としては、電気絶縁性を有する熱硬化性樹脂材料（例えば、エポキシ樹脂）が用いられる。樹脂層２１、２２を構成する樹脂材料中には、アルミナやシリカ等の電気絶縁性かつ熱伝導性を有し、放熱性に優れたセラミックよりなるフィラ３が混ざっている。 The core layer 20 is configured as a prepreg layer made of an electrically insulating prepreg. As shown in FIG. 2, the core layer 20 includes a glass cloth 1 a and resin layers 21 and 22. The resin layer 21 is formed by sealing the surface on the buildup layer 30 side of the glass cloth 1a with a resin material. The resin layer 22 is formed by sealing the surface on the buildup layer 40 side of the glass cloth 1a with a resin material. As a resin material constituting the resin layers 21 and 22, a thermosetting resin material (for example, epoxy resin) having electrical insulation is used. In the resin material constituting the resin layers 21 and 22, filler 3 made of ceramic having electrical insulation and thermal conductivity such as alumina and silica and excellent heat dissipation is mixed.
　ガラスクロス１ａは、図３（ａ）に示されるように、複数本の横ヤーン３３と複数本の縦ヤーン３４とを用いて織られたものである。横ヤーン３３は、横方向（第１方向）に延びる複数本のガラス繊維を束にしたものである。縦ヤーン３４は、横ヤーン３３に直交する縦方向（第２方向）に延びる複数本のガラス繊維を束にしたものである。ガラス繊維は、電気絶縁性を有するものである。 The glass cloth 1a is woven using a plurality of horizontal yarns 33 and a plurality of vertical yarns 34, as shown in FIG. The horizontal yarn 33 is a bundle of a plurality of glass fibers extending in the horizontal direction (first direction). The vertical yarn 34 is a bundle of a plurality of glass fibers extending in the vertical direction (second direction) orthogonal to the horizontal yarn 33. Glass fiber has electrical insulation.
　縦ヤーン３４では、図３（ｂ）における図３（ａ）中のIIIＢ－IIIＢ断面図に示されるように、幅方向中央部が、厚み寸法が最も大きくなるように形成されている。同様に、横ヤーン３３では、幅方向中央部が、厚み寸法が最も大きくなるように形成されている。 In the vertical yarn 34, as shown in the IIIB-IIIB cross-sectional view in FIG. 3A in FIG. 3B, the central portion in the width direction is formed to have the largest thickness dimension. Similarly, in the horizontal yarn 33, the central part in the width direction is formed so as to have the largest thickness dimension.
　ガラスクロス１ａは、複数の腹３５および複数のバスケットホール３６を備える。複数の腹３５は、横ヤーン３３と縦ヤーン３４とが厚み方向に重なる部分である。複数のバスケットホール３６は、複数本の横ヤーン３３のうち隣り合う２本の横ヤーン３３と複数本の縦ヤーン３４のうち隣り合う２本の縦ヤーン３４とによって囲まれる穴部である。すなわち、複数のバスケットホール３６は、複数の腹３５のうち隣接する４つの腹３５に囲まれる位置に設けられている。なお、図３（ａ）では、８つの腹３５を示し、４つのバスケットホール３６を示している。 The glass cloth 1a includes a plurality of bellies 35 and a plurality of basket holes 36. The plurality of antinodes 35 are portions where the horizontal yarn 33 and the vertical yarn 34 overlap in the thickness direction. The plurality of basket holes 36 are holes surrounded by two adjacent horizontal yarns 33 of the plurality of horizontal yarns 33 and two adjacent vertical yarns 34 of the plurality of vertical yarns 34. In other words, the plurality of basket holes 36 are provided at positions surrounded by the four adjacent stomachs 35 among the plurality of stomachs 35. In FIG. 3A, eight bells 35 are shown, and four basket holes 36 are shown.
　図１のビルドアップ層３０、４０は、プリプレグよりなるプリプレグ層として構成されている。ビルドアップ層３０は、図４に示されるように、ガラスクロス１ｂと、樹脂層３１、３２とから構成されている。樹脂層３１は、ガラスクロス１ｂのうち表面側表層配線６１～６３（図４中６１、６２を示す）側の面を樹脂材料で封止してなるものである。樹脂層３２は、ガラスクロス１ｂのうち表面側内層配線５１１、５１２（図４中５１２を示す）側の面を樹脂材料で封止してなるものである。 The buildup layers 30 and 40 in FIG. 1 are configured as prepreg layers made of prepreg. As shown in FIG. 4, the buildup layer 30 includes a glass cloth 1 b and resin layers 31 and 32. The resin layer 31 is formed by sealing the surface of the glass cloth 1b on the surface side surface layer wirings 61 to 63 (indicated by 61 and 62 in FIG. 4) with a resin material. The resin layer 32 is formed by sealing the surface of the glass cloth 1b on the surface side inner layer wiring 511, 512 (shown 512 in FIG. 4) side with a resin material.
　樹脂層３１、３２を構成する樹脂材料としては、電気絶縁性を有する熱硬化性樹脂材料（例えば、エポキシ樹脂）が用いられる。樹脂層３１、３２を構成する樹脂材料中には、アルミナやシリカ等の電気絶縁性かつ熱伝導性を有し、放熱性に優れたセラミックよりなるフィラ（図示省略）が混ざっている。 As the resin material constituting the resin layers 31 and 32, a thermosetting resin material (for example, epoxy resin) having electrical insulation is used. In the resin material constituting the resin layers 31 and 32, fillers (not shown) made of ceramics having electrical insulation and thermal conductivity, such as alumina and silica, and excellent in heat dissipation are mixed.
　ビルドアップ層４０は、図５に示されるように、ガラスクロス１ｃと、樹脂層４１、４２とから構成されている。樹脂層４１は、ガラスクロス１ｃのうち裏面側表層配線７１、７２（図５中７１を示す）側の面を樹脂材料で封止してなるものである。樹脂層４２は、ガラスクロス１ｃのうち裏面側内層配線５２１、５２２（図５中５２２を示す）側の面を樹脂材料で封止してなるものである。樹脂層４１、４２を構成する樹脂材料としては、電気絶縁性を有する熱硬化性樹脂材料（例えば、エポキシ樹脂）が用いられる。樹脂層４１、４２を構成する樹脂材料中には、アルミナやシリカ等の電気絶縁性かつ熱伝導性を有し、放熱性に優れたセラミックよりなるフィラ（図示省略）が混ざっている。 As shown in FIG. 5, the build-up layer 40 includes a glass cloth 1 c and resin layers 41 and 42. The resin layer 41 is formed by sealing the surface of the glass cloth 1c on the rear surface layer wirings 71 and 72 (shown 71 in FIG. 5) side with a resin material. The resin layer 42 is formed by sealing the surfaces of the glass cloth 1c on the back side inner layer wirings 521 and 522 (shown 522 in FIG. 5) with a resin material. As the resin material constituting the resin layers 41 and 42, a thermosetting resin material (for example, epoxy resin) having electrical insulation is used. The resin material constituting the resin layers 41 and 42 is mixed with a filler (not shown) made of ceramic having electrical insulation and thermal conductivity, such as alumina and silica, and excellent heat dissipation.
　本実施形態のガラスクロス１ｂ、１ｃは、ガラスクロス１ａと同様に、複数本の横ヤーンと複数本の縦ヤーンとを用いて織られたものである。このため、ガラスクロス１ｂ、１ｃは、複数の腹３５および複数のバスケットホール３６（図３（ａ）参照）を有することになる。 The glass cloths 1b and 1c of the present embodiment are woven using a plurality of horizontal yarns and a plurality of vertical yarns similarly to the glass cloth 1a. For this reason, the glass cloths 1b and 1c have a plurality of bellies 35 and a plurality of basket holes 36 (see FIG. 3A).
　図１に示されるように、複数の表面側内層配線５１１、５１２は、コア層２０とビルドアップ層３０との間の界面において、コア層２０の表面２０ａに形成されている。複数の表面側内層配線５１１、５１２は、それぞれ、コア層２０の表面２０ａ上にて離れて配置されている。つまり、複数の表面側内層配線５１１、５１２は、それぞれ、コア層２０の表面２０ａ上にて間隔を空けて配置されている。本実施形態では、複数の表面側内層配線５１１、５１２のうち隣接する２つの表面側内層配線の間の領域（すなわち、間隔を構成する表面側内層配線の間の領域）を領域５１３という。 As shown in FIG. 1, the plurality of surface-side inner layer wirings 511 and 512 are formed on the surface 20 a of the core layer 20 at the interface between the core layer 20 and the buildup layer 30. The plurality of front-side inner layer wirings 511 and 512 are arranged separately on the surface 20 a of the core layer 20. That is, the plurality of front-side inner layer wirings 511 and 512 are arranged on the surface 20a of the core layer 20 with a space therebetween. In the present embodiment, a region between two adjacent surface-side inner layer wirings among the plurality of surface-side inner layer wirings 511 and 512 (that is, a region between the surface-side inner layer wirings forming the interval) is referred to as a region 513.
　複数の裏面側内層配線５２１、５２２は、コア層２０とビルドアップ層４０との間の界面において、コア層２０の裏面２０ｂに形成されている。複数の裏面側内層配線５２１、５２２は、それぞれ、コア層２０の裏面２０ｂ上にて離れて配置されている。つまり、複数の裏面側内層配線５２１、５２２は、それぞれ、コア層２０の裏面２０ｂ上にて間隔を空けて配置されている。本実施形態では、複数の裏面側内層配線５２１、５２２のうち隣接する２つの裏面側内層配線の間の領域（すなわち、間隔を構成する裏面側内層配線の間の領域）を領域５１４という。 The plurality of back surface inner layer wirings 521 and 522 are formed on the back surface 20 b of the core layer 20 at the interface between the core layer 20 and the buildup layer 40. The plurality of back side inner layer wirings 521 and 522 are arranged separately on the back side 20 b of the core layer 20. That is, the plurality of back surface inner layer wirings 521 and 522 are arranged on the back surface 20b of the core layer 20 with a space therebetween. In the present embodiment, a region between two adjacent back surface side inner layer wirings among the plurality of back surface side inner layer wirings 521 and 522 (that is, a region between back surface side inner layer wirings forming an interval) is referred to as a region 514.
　ビルドアップ層３０は、複数の表面側内層配線５１１、５１２と共にコア層２０の表面２０ａを覆うようにコア層２０に積層されている。ビルドアップ層４０は、複数の裏面側内層配線５２１、５２２と共にコア層２０の裏面２０ｂを覆うようにコア層２０に積層されている。 The build-up layer 30 is laminated on the core layer 20 so as to cover the surface 20a of the core layer 20 together with the plurality of surface-side inner layer wirings 511 and 512. The buildup layer 40 is laminated on the core layer 20 so as to cover the back surface 20b of the core layer 20 together with the plurality of back surface side inner layer wirings 521 and 522.
　コア層２０の表面２０ａにおいて、ビルドアップ層３０の樹脂層３２が、複数の領域５１３に充填された状態で複数の表面側内層配線５１１、５１２を封止している。そして、コア層２０の裏面２０ｂにおいて、ビルドアップ層４０の樹脂層４０ｂが、複数の領域５１４に充填された状態で複数の裏面側内層配線５２１、５２２を封止している。 On the surface 20 a of the core layer 20, the resin layer 32 of the buildup layer 30 seals the plurality of front side inner layer wirings 511 and 512 in a state where the plurality of regions 513 are filled. Then, on the back surface 20 b of the core layer 20, the resin layers 40 b of the build-up layer 40 seal the plurality of back surface inner layer wirings 521 and 522 in a state where the plurality of regions 514 are filled.
　また、表面側表層配線６１～６３は、ビルドアップ層３０の表面３０ａに形成されている。本実施形態では、表面側表層配線６１～６３は、電子部品１２１～１２３が搭載される搭載用のランド６１、電子部品１２１、１２２とボンディングワイヤ１４１、１４２を介して電気的に接続されるボンディング用のランド６２、外部回路と電気的に接続される表面パターン６３とされている。 Further, the surface side surface wirings 61 to 63 are formed on the surface 30 a of the buildup layer 30. In the present embodiment, the surface-side surface layer wirings 61 to 63 are bonded electrically connected to the mounting land 61 on which the electronic components 121 to 123 are mounted and the electronic components 121 and 122 via the bonding wires 141 and 142. Land 62 for use, and a surface pattern 63 electrically connected to an external circuit.
　同様に、裏面側表層配線７１、７２がビルドアップ層４０の表面４０ａに形成されている。本実施形態では、裏面側表層配線７１、７２は、後述するフィルドビアを介して裏面側内層配線５２１、５２２と接続される裏面パターン７１、放熱用のヒートシンクが備えられるヒートシンク用パターン７２とされている。 Similarly, backside surface layer wirings 71 and 72 are formed on the surface 40 a of the buildup layer 40. In this embodiment, the back surface layer wirings 71 and 72 are a back surface pattern 71 connected to the back surface inner layer wirings 521 and 522 through filled vias, which will be described later, and a heat sink pattern 72 provided with a heat sink for heat dissipation. .
　なお、内層配線５１１、５１２、５２１、５２２は、導体を構成している。ビルドアップ層３０の表面３０ａとは、ビルドアップ層３０のうちコア層２０と反対側の一面のことであり、多層基板１０の一面１０ａとなる面のことである。また、ビルドアップ層４０の表面４０ａとは、ビルドアップ層４０のうちコア層２０と反対側の一面のことであり、多層基板１０の他面１０ｂとなる面のことである。 The inner layer wirings 511, 512, 521, and 522 constitute conductors. The surface 30 a of the buildup layer 30 is one surface of the buildup layer 30 opposite to the core layer 20, and is a surface that becomes the one surface 10 a of the multilayer substrate 10. Further, the surface 40 a of the buildup layer 40 is one surface of the buildup layer 40 opposite to the core layer 20, and is a surface that becomes the other surface 10 b of the multilayer substrate 10.
　そして、内層配線５１１、５１２、５２１、５２２、表面側表層配線６１～６３、裏面側表層配線７１、７２は、具体的には後述するが、銅等の金属箔や金属メッキが適宜積層された導体から構成されている。 The inner layer wirings 511, 512, 521, 522, the surface side surface layer wirings 61 to 63, and the back side surface layer wirings 71 and 72 are specifically described later, but a metal foil such as copper or metal plating is appropriately laminated. Consists of conductors.
　なお、内層配線５１１、５１２、５２１、５２２、表面側表層配線６１～６３、裏面側表層配線７１、７２は、それぞれの厚み方向の寸法が３５μｍ以上になっている。 The inner layer wirings 511, 512, 521, 522, the surface side surface layer wirings 61 to 63, and the back surface side surface layer wirings 71 and 72 have a thickness dimension of 35 μm or more.
　また、表面側内層配線５１１、５１２と裏面側内層配線５２１、５２２とは、コア層２０を貫通して設けられた貫通ビア８１を介して電気的および熱的に接続されている。具体的には、貫通ビア８１は、コア層２０を厚さ方向に貫通する貫通孔８１ａの壁面に銅等の貫通電極８１ｂが形成され、貫通孔８１ａの内部に充填材８１ｃが充填されて構成されている。 Also, the front side inner layer wirings 511 and 512 and the rear side inner layer wirings 521 and 522 are electrically and thermally connected through a through via 81 provided through the core layer 20. Specifically, the through via 81 is configured such that a through electrode 81b such as copper is formed on the wall surface of the through hole 81a penetrating the core layer 20 in the thickness direction, and a filler 81c is filled in the through hole 81a. Has been.
　また、表面側内層配線５１１、５１２と表面側表層配線６１～６３、および裏面側内層配線５２１、５２２と裏面側表層配線７１、７２とは、適宜各ビルドアップ層３０、４０を厚さ方向に貫通して設けられたフィルドビア９１、１０１を介して電気的および熱的に接続されている。 Further, the front side inner layer wirings 511 and 512, the front side surface layer wirings 61 to 63, and the rear side inner layer wirings 521 and 522 and the rear side surface layer wirings 71 and 72 are appropriately connected to the buildup layers 30 and 40 in the thickness direction. They are electrically and thermally connected through filled vias 91 and 101 provided therethrough.
　具体的には、フィルドビア９１、１０１は、各ビルドアップ層３０、４０を厚さ方向に貫通する貫通孔９１ａ、１０１ａが銅等の貫通電極９１ｂ、１０１ｂによって充填された構成とされている。 Specifically, the filled vias 91 and 101 are configured such that through holes 91a and 101a penetrating the build-up layers 30 and 40 in the thickness direction are filled with through electrodes 91b and 101b such as copper.
　なお、充填材８１ｃは、樹脂、セラミック、金属等が用いられるが、本実施形態では、エポキシ樹脂とされている。また、貫通電極８１ｂ、９１ｂ、１０１ｂは、銅等の金属メッキにて構成されている。 In addition, although resin, ceramic, metal, etc. are used for the filler 81c, it is set as the epoxy resin in this embodiment. The through electrodes 81b, 91b, and 101b are made of metal plating such as copper.
　そして、各ビルドアップ層３０、４０の表面３０ａ、４０ａには、表面パターン６３および裏面パターン７１を覆うソルダーレジスト１１０が形成されている。なお、表面パターン６３を覆うソルダーレジスト１１０には、図１とは別断面において、表面パターン６３のうち外部回路と接続される部分を露出させる開口部が形成されている。 The solder resist 110 that covers the front surface pattern 63 and the back surface pattern 71 is formed on the front surfaces 30a and 40a of the buildup layers 30 and 40. The solder resist 110 that covers the surface pattern 63 is formed with an opening that exposes a portion of the surface pattern 63 that is connected to an external circuit in a cross section different from that in FIG.
　電子部品１２１～１２３は、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）やＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）等の発熱が大きいパワー素子１２１、マイコン等の制御素子１２２、チップコンデンサや抵抗等の受動素子１２３である。 The electronic parts 121 to 123 are passive power elements 121 such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductors Field-Effect Transistors), control elements 122 such as microcomputers, and chip capacitors and resistors. Element 123.
　そして、各電子部品１２１～１２３は、はんだ１３０を介してランド６１上に搭載されてランド６１と電気的、機械的に接続されている。また、パワー素子１２１および制御素子１２２は、周囲に形成されているランド６２ともＡｌやＡｕ等のボンディングワイヤ１４１、１４２を介して電気的に接続されている。 The electronic components 121 to 123 are mounted on the land 61 via the solder 130 and are electrically and mechanically connected to the land 61. The power element 121 and the control element 122 are also electrically connected to the land 62 formed in the periphery via bonding wires 141 and 142 such as Al and Au.
　ここで、上記した第１の配線群５１１、５２１は、比較的大電流のパワー素子１２１に接続されている表裏の内層配線５１１、５２１であり、一方、上記した第２の配線群５１２、５２２は、比較的小電流の制御素子１２２、受動素子１２３に接続されている表裏の内層配線５１２、５２２である。 Here, the first wiring groups 511 and 521 described above are the front and back inner layer wirings 511 and 521 connected to the power element 121 having a relatively large current, while the second wiring groups 512 and 522 described above. These are front and back inner layer wirings 512 and 522 connected to the control element 122 and the passive element 123 having a relatively small current.
　なお、ここでは、電子部品１２１～１２３としてパワー素子１２１、制御素子１２２、受動素子１２３を例に挙げて説明したが、電子部品１２１～１２３はこれらに限定されるものではない。 Here, the power element 121, the control element 122, and the passive element 123 are described as examples of the electronic components 121 to 123, but the electronic components 121 to 123 are not limited to these.
　モールド樹脂層１５０は、ランド６１、６２および電子部品１２１～１２３を封止するものであり、エポキシ樹脂等の一般的なモールド材料が金型を用いたトランスファーモールド法やコンプレッションモールド法等により形成されたものである。 The mold resin layer 150 seals the lands 61 and 62 and the electronic components 121 to 123, and a general mold material such as an epoxy resin is formed by a transfer mold method using a mold, a compression mold method, or the like. It is a thing.
　なお、本実施形態では、モールド樹脂層１５０は、多層基板１０の一面１０ａのみに形成されている。つまり、本実施形態の電子装置は、いわゆるハーフモールド構造とされている。また、多層基板１０の他面１０ｂ側には、特に図示していないが、ヒートシンク用パターン７２に放熱グリス等を介してヒートシンクが備えられている。 In the present embodiment, the mold resin layer 150 is formed only on the one surface 10a of the multilayer substrate 10. That is, the electronic device of this embodiment has a so-called half mold structure. Further, on the other surface 10b side of the multilayer substrate 10, although not particularly shown, a heat sink is provided on the heat sink pattern 72 via heat radiation grease or the like.
　次に、本実施形態のビルドアップ層３０、４０の構造の詳細について図４～図６を用いて説明する。 Next, details of the structure of the build-up layers 30 and 40 of the present embodiment will be described with reference to FIGS.
　図４のビルドアップ層３０において、ガラスクロス１ｂは、複数の表面側内層配線５１１、５１２、および複数の領域５１３を連続して覆うように形成されている。 4, the glass cloth 1b is formed so as to continuously cover the plurality of surface-side inner layer wirings 511 and 512 and the plurality of regions 513.
　ガラスクロス１ｂのうち領域５１３を覆う部位は、ガラスクロス１ｂのうち複数の表面側内層配線５１１、５１２を覆う部位よりもコア層２０側に近づくように曲がっている。具体的には、ガラスクロス１ｂのうち領域５１３を覆う部位は、複数の表面側内層配線５１１、５１２の上面５１２ａよりもコア層２０側に入り込んでいる。当該上面５１２ａとは、複数の表面側内層配線５１１、５１２のうちコア層２０に対して反対側端部のことである。図４では、ガラスクロス１ｂのうち領域５１３を覆う部位は、当該領域５１３に隣接する２つの表面側内層配線５１２の上面５１２ａの延長線Ｙ１（図４中鎖線）よりもコア層２０側に入り込んでいる例を示している。 The part which covers the area | region 513 among the glass cloth 1b is bent so that it may approach the core layer 20 side rather than the part which covers the some surface side inner layer wiring 511,512 among the glass cloth 1b. Specifically, the portion of the glass cloth 1b that covers the region 513 is located closer to the core layer 20 than the upper surfaces 512a of the plurality of front-side inner- layer wirings 511 and 512. The upper surface 512 a is an end portion on the opposite side to the core layer 20 among the plurality of front surface side inner layer wirings 511 and 512. In FIG. 4, the portion of the glass cloth 1 b that covers the region 513 enters the core layer 20 side from the extension line Y <b> 1 (dashed line in FIG. 4) of the upper surface 512 a of the two surface side inner layer wirings 512 adjacent to the region 513. An example is shown.
　図４のビルドアップ層３０において、ガラスクロス１ｂの厚み寸法をＬ１とし、樹脂層３１のうちコア層２０の反対側面３１ａとガラスクロス１ｂとの間の寸法（すなわち、最短距離）をＬ２とすると、Ｌ１、Ｌ２は、Ｌ１＜Ｌ２を満足する。 In the buildup layer 30 of FIG. 4, when the thickness dimension of the glass cloth 1b is L1, and the dimension (that is, the shortest distance) between the opposite side surface 31a of the core layer 20 and the glass cloth 1b in the resin layer 31 is L2. , L1 and L2 satisfy L1 <L2.
　本実施形態において、厚み寸法Ｌ１は、ガラスクロス１ｂを構成する腹３５の中央部の厚み寸法である。腹３５の中央部とは、横ヤーン３３の幅方向中央部と縦ヤーン３４の幅方向中央部とが重なる部分であって、腹３５のうち最も厚み寸法が大きくなる部位である。厚み寸法Ｌ２を設定するためのガラスクロス１ｂの基準位置を、ガラスクロス１ｂの上部としている。ガラスクロス１ｂの上部は、複数の腹３５のうち最も表面側表層配線６１～６３側に位置する腹３５の中央部である。 In the present embodiment, the thickness dimension L1 is the thickness dimension of the central portion of the belly 35 constituting the glass cloth 1b. The central portion of the belly 35 is a portion where the central portion in the width direction of the horizontal yarn 33 overlaps with the central portion in the width direction of the vertical yarn 34, and is the portion of the belly 35 having the largest thickness dimension. The reference position of the glass cloth 1b for setting the thickness dimension L2 is the upper part of the glass cloth 1b. The upper part of the glass cloth 1b is the central part of the antinode 35 located on the surface side surface layer wiring 61 to 63 side among the antinodes 35.
　図５のビルドアップ層４０において、ガラスクロス１ｃは、複数の裏面側内層配線５２１、５２２、および複数の領域５１４を連続して覆うように形成されている。 In the build-up layer 40 of FIG. 5, the glass cloth 1c is formed so as to continuously cover the plurality of back side inner layer wirings 521 and 522 and the plurality of regions 514.
　ガラスクロス１ｃのうち領域５１４を覆う部位は、ガラスクロス１ｃのうち複数の裏面側内層配線５２１、５２２を覆う部位よりもコア層２０側に近づくように曲がっている。具体的には、ガラスクロス１ｃのうち領域５１４を覆う部位は、複数の裏面側内層配線５２１、５２２の下面５２２ａよりもコア層２０側に入り込んでいる。当該下面とは、複数の裏面側内層配線５２１、５２２のうちコア層２０に対して反対側の面のことである。図５では、ガラスクロス１ｃのうち領域５１４を覆う部位は、当該領域５１４に隣接する２つの表面側内層配線５２２の下面の延長線Ｙ２（図５中鎖線）よりもコア層２０側に入り込んでいる例を示している。 The part which covers the area | region 514 among the glass cloth 1c is bent so that it may approach the core layer 20 side rather than the part which covers the some back surface side inner layer wiring 521,522 of the glass cloth 1c. Specifically, the portion of the glass cloth 1c that covers the region 514 enters the core layer 20 side from the lower surfaces 522a of the plurality of back surface inner layer wirings 521 and 522. The said lower surface is a surface on the opposite side to the core layer 20 among the plurality of back side inner layer wirings 521 and 522. In FIG. 5, the portion of the glass cloth 1 c that covers the region 514 enters the core layer 20 side from the extension line Y <b> 2 (dashed line in FIG. 5) on the lower surface of the two surface-side inner layer wirings 522 adjacent to the region 514. An example is shown.
　図５のビルドアップ層４０において、ガラスクロス１ｃの厚み寸法をＬ３とし、樹脂層４１のうちコア層２０の反対側面４１ａとガラスクロス１ｃとの間の寸法（すなわち、最短距離）をＬ４とすると、Ｌ３、Ｌ４の大小関係は、Ｌ３＜Ｌ４を満足する。 In the buildup layer 40 of FIG. 5, when the thickness dimension of the glass cloth 1c is L3, and the dimension (that is, the shortest distance) between the opposite side surface 41a of the core layer 20 and the glass cloth 1c in the resin layer 41 is L4. , L3, and L4 satisfy the relationship L3 <L4.
　本実施形態において、厚み寸法Ｌ３は、ガラスクロス１ｃを構成する腹３５の中央部の厚み寸法である。腹３５の中央部とは、横ヤーン３３の幅方向中央部と縦ヤーン３４の幅方向中央部とが重なる部分であって、腹３５のうち最も厚み寸法が大きくなる部位である。寸法Ｌ４を設定するためのガラスクロス１ｃの基準位置を、ガラスクロス１ｃの下部としている。ガラスクロス１ｃの下部は、複数の腹３５のうち最も裏面側表層配線７１、７２側に位置する腹３５の中央部である。 In the present embodiment, the thickness dimension L3 is the thickness dimension of the central portion of the belly 35 constituting the glass cloth 1c. The central portion of the belly 35 is a portion where the central portion in the width direction of the horizontal yarn 33 overlaps with the central portion in the width direction of the vertical yarn 34, and is the portion of the belly 35 having the largest thickness dimension. The reference position of the glass cloth 1c for setting the dimension L4 is the lower part of the glass cloth 1c. The lower part of the glass cloth 1c is a central portion of the belly 35 located on the back surface side surface wiring 71, 72 side among the plurality of belly 35.
　本実施形態のガラスクロス１ｂ、１ｃの厚み寸法Ｌ３、Ｌ４は、１０μｍ～３０μｍに設定されている。ガラスクロス１ｂ、１ｃのバスケットホールは、コア層２０のガラスクロス１ａのバスケットホールよりも小さくなっている。ガラスクロス１ｂ、１ｃのバスケットホールは、直径が１００μｍ以下に設定されている。ビルドアップ層３０の質量のうち樹脂材料の質量が占める比率（ｗｔ％）が８０％以上になるように設定されている。ビルドアップ層４０の質量のうち樹脂材料の質量が占める比率（ｗｔ％）が８０％以上になるように設定されている。 The thickness dimensions L3 and L4 of the glass cloths 1b and 1c of the present embodiment are set to 10 μm to 30 μm. The basket holes of the glass cloths 1 b and 1 c are smaller than the basket holes of the glass cloth 1 a of the core layer 20. The basket holes of the glass cloths 1b and 1c have a diameter set to 100 μm or less. The ratio (wt%) occupied by the mass of the resin material in the mass of the buildup layer 30 is set to be 80% or more. The ratio (wt%) occupied by the mass of the resin material in the mass of the buildup layer 40 is set to be 80% or more.
　ビルドアップ層３０の質量のうちフィラの質量が占める比率（ｗｔ％）は、コア層２０の質量のうちフィラの質量が占める比率（ｗｔ％）よりも大きくなっている。ビルドアップ層４０の質量のうちフィラの質量が占める比率（ｗｔ％）は、コア層２０の質量のうちフィラの質量が占める比率（ｗｔ％）よりも大きくなっている。例えば、ビルドアップ層３０、４０の質量のうちフィラの質量が占める比率（ｗｔ％）は、５０％以上に設定されている。 The ratio (wt%) of the mass of the buildup layer 30 occupied by the filler mass (wt%) is larger than the ratio (wt%) of the mass of the core layer 20 occupied by the filler. The ratio (wt%) of the mass of the buildup layer 40 occupied by the filler mass (wt%) is larger than the ratio (wt%) of the mass of the core layer 20 occupied by the filler. For example, the ratio (wt%) of the mass of the filler to the mass of the buildup layers 30 and 40 is set to 50% or more.
　以上が本実施形態における電子装置の構成である。次に、上記電子装置の製造方法について図５、図６、図７を参照しつつ説明する。なお、図５、図６、図７は、多層基板１０のうちパワー素子１２１が搭載される部分近傍の断面図である。 The above is the configuration of the electronic device in the present embodiment. Next, a method for manufacturing the electronic device will be described with reference to FIGS. 5, 6, and 7 are cross-sectional views of the vicinity of a portion where the power element 121 is mounted in the multilayer substrate 10.
　まず、図６（ａ）に示されるように、コア層２０の表面２０ａおよび裏面２０ｂに銅箔等の金属箔１６１、１６２が配置されたものを用意する。そして、図６（ｂ）に示されるように、ドリル等によって金属箔１６１、コア層２０、金属箔１６２を貫通する貫通孔８１ａを形成する。 First, as shown in FIG. 6 (a), a structure in which metal foils 161 and 162 such as copper foil are arranged on the front surface 20a and the back surface 20b of the core layer 20 is prepared. Then, as shown in FIG. 6B, a through hole 81a penetrating the metal foil 161, the core layer 20, and the metal foil 162 is formed by a drill or the like.
　その後、図６（ｃ）に示されるように、無電解メッキや電気メッキを行い、貫通孔８１ａの壁面および金属箔１６１、１６２上に銅等の金属メッキ１６３を形成する。これにより、貫通孔８１ａの壁面に、金属メッキ１６３にて構成される貫通電極８１ｂが形成される。なお、無電解メッキおよび電気メッキを行う場合には、パラジウム等の触媒を用いて行うことが好ましい。 Then, as shown in FIG. 6C, electroless plating or electroplating is performed to form a metal plating 163 such as copper on the wall surface of the through hole 81a and the metal foils 161 and 162. As a result, a through electrode 81b composed of the metal plating 163 is formed on the wall surface of the through hole 81a. In addition, when performing electroless plating and electroplating, it is preferable to carry out using catalysts, such as palladium.
　続いて、図６（ｄ）に示されるように、金属メッキ１６３で囲まれる空間に充填材８１ｃを配置する。これにより、貫通孔８１ａ、貫通電極８１ｂ、充填材８１ｃを有する上記貫通ビア８１が形成される。 Subsequently, as shown in FIG. 6 (d), a filler 81 c is arranged in a space surrounded by the metal plating 163. Thus, the through via 81 having the through hole 81a, the through electrode 81b, and the filler 81c is formed.
　その後、図７（ａ）に示されるように、無電解メッキおよび電気メッキ等でいわゆる蓋メッキを行い、金属メッキ１６３および充填材８１ｃ上に銅等の金属メッキ１６４、１６５を形成する。 Thereafter, as shown in FIG. 7A, so-called lid plating is performed by electroless plating, electroplating, or the like, and metal plating 164, 165 such as copper is formed on the metal plating 163 and the filler 81c.
　こうして、図７（ａ）に示されるように、コア層２０の表面２０ａ側では、金属箔１６１、金属メッキ１６３、金属メッキ１６４が順次積層された金属層Ｍ１が形成され、裏面２０ｂ側では、金属箔１６２、金属メッキ１６３、金属メッキ１６５が順次積層された金属層Ｍ２が形成される。 Thus, as shown in FIG. 7A, the metal layer M1 in which the metal foil 161, the metal plating 163, and the metal plating 164 are sequentially laminated is formed on the front surface 20a side of the core layer 20, and on the back surface 20b side, A metal layer M2 in which a metal foil 162, a metal plating 163, and a metal plating 165 are sequentially laminated is formed.
　次に、図７（ｂ）に示されるように、金属メッキ１６４、１６５上に図示しないレジストを配置する。そして、当該レジストをマスクとしてウェットエッチング等を行い、金属メッキ１６４、金属メッキ１６３、金属箔１６１を適宜パターニングして複数の表面側内層配線５１１、５１２を形成すると共に、金属メッキ１６５、金属メッキ１６３、金属箔１６２を適宜パターニングして複数の裏面側内層配線５２１、５２２を形成する。 Next, as shown in FIG. 7B, a resist (not shown) is disposed on the metal platings 164 and 165. Then, wet etching or the like is performed using the resist as a mask, and the metal plating 164, the metal plating 163, and the metal foil 161 are appropriately patterned to form a plurality of surface side inner layer wirings 511 and 512, and the metal plating 165 and the metal plating 163. The metal foil 162 is appropriately patterned to form a plurality of back surface inner layer wirings 521 and 522.
　つまり、本実施形態では、複数の表面側内層配線５１１、５１２は、金属箔１６１、金属メッキ１６３、金属メッキ１６４が積層された金属層Ｍ１によって構成され、複数の裏面側内層配線５２１、５２２は、金属箔１６２、金属メッキ１６３、金属メッキ１６５が積層された金属層Ｍ２によって構成されている。このことにより、複数の表面側内層配線５１１、５１２がコア層２０の表面２０ａに配列され、複数の裏面側内層配線５２１、５２２コア層２０の裏面２０ｂに配列されることになる（ステップ１００）。図７（ｃ）以降では、金属箔１６１、金属メッキ１６３、金属メッキ１６４、および金属箔１６２、金属メッキ１６３、金属メッキ１６５をまとめて１層として示してある。 That is, in the present embodiment, the plurality of front surface side inner layer wirings 511 and 512 are configured by the metal layer M1 in which the metal foil 161, the metal plating 163, and the metal plating 164 are laminated, and the plurality of back surface side inner layer wirings 521 and 522 are The metal layer 162 includes a metal foil 162, a metal plating 163, and a metal plating 165. As a result, the plurality of front surface side inner layer wirings 511 and 512 are arranged on the front surface 20a of the core layer 20, and are arranged on the rear surface 20b of the plurality of back surface side inner layer wirings 521 and 522 core layer 20 (step 100). . In FIG. 7C and thereafter, the metal foil 161, the metal plating 163, the metal plating 164, the metal foil 162, the metal plating 163, and the metal plating 165 are collectively shown as one layer.
　その後、プリプレグ３０Ａ、４０Ａを用意する（ステップ１１０）。プリプレグ３０Ａは、樹脂層３１、３２およびガラスクロス１ｂから構成されている。プリプレグ４０Ａは、樹脂層４１、４２およびガラスクロス１ｃから構成されている。 Thereafter, prepregs 30A and 40A are prepared (step 110). The prepreg 30A is composed of resin layers 31 and 32 and a glass cloth 1b. The prepreg 40A is composed of resin layers 41 and 42 and a glass cloth 1c.
　次に、図７（ｃ）に示されるように、コア層２０における表面２０ａ側において、表面側内層配線５１１、５１２上にプリプレグ３０Ａおよび銅等の金属板１６６を積層する。さらに、コア層２０における裏面２０ｂ側において、裏面側内層配線５２１、５２２上にプリプレグ４０Ａおよび銅等の金属板１６７を積層する。 Next, as shown in FIG. 7C, a prepreg 30 </ b> A and a metal plate 166 such as copper are laminated on the surface-side inner layer wirings 511 and 512 on the surface 20 a side in the core layer 20. Further, on the back surface 20 b side of the core layer 20, a prepreg 40 </ b> A and a metal plate 167 such as copper are laminated on the back surface inner layer wirings 521 and 522.
　このようにして、上から順に、金属板１６６、プリプレグ３０Ａ、表面側内層配線５１１、５１２、コア層２０、裏面側内層配線５２１、５２２、プリプレグ４０Ａおよび金属板１６７が順に積層された積層体１６８を構成する。なお、プリプレグ３０Ａ、４０Ａを構成する樹脂材料は、この状態では、仮硬化されたもので流動性を有している。 In this way, the laminate 168 in which the metal plate 166, the prepreg 30A, the front surface inner layer wirings 511 and 512, the core layer 20, the back surface inner layer wirings 521 and 522, the prepreg 40A, and the metal plate 167 are sequentially stacked from the top. Configure. In this state, the resin material constituting the prepregs 30A and 40A is temporarily cured and has fluidity.
　続いて、積層体１６８を一体化するために、図７（ｄ）に示されるように、積層体１６８を積層方向に加圧しつつ加熱する（ステップ１２０）。つまり、積層体１６８を加熱してプリプレグ３０Ａ、４０Ａを構成する樹脂材料を流動させ、コア層２０およびプリプレグ３０Ａのうち一方を他方に対して押し付け、かつコア層２０およびプリプレグ４０Ａのうち一方を他方に対して押し付ける。 Subsequently, in order to integrate the laminated body 168, as shown in FIG. 7D, the laminated body 168 is heated while being pressed in the laminating direction (step 120). That is, the laminate 168 is heated to flow the resin material constituting the prepregs 30A and 40A, one of the core layer 20 and the prepreg 30A is pressed against the other, and one of the core layer 20 and the prepreg 40A is pressed to the other Press against.
　これに伴い、ビルドアップ層３０のガラスクロス１ｂのうち領域５１３を覆う部位が、ガラスクロス１ｂのうち複数の表面側内層配線５１１、５１２を覆う部位よりもコア層２０側に近づくように曲がる。このため、ガラスクロス１ｂのうち領域５１３を覆う部位が、複数の表面側内層配線５１１、５１２の上面よりもコア層２０側に入り込む。 Accordingly, the portion of the glass cloth 1b of the build-up layer 30 that covers the region 513 is bent so as to be closer to the core layer 20 than the portion of the glass cloth 1b that covers the plurality of front side inner layer wirings 511 and 512. For this reason, the site | part which covers the area | region 513 among the glass cloth 1b penetrates into the core layer 20 side rather than the upper surface of the some surface side inner layer wiring 511,512.
　これに伴い、プリプレグ３０Ａを構成する樹脂材料がコア層２０の表面２０ａのうち複数の表面側内層配線５１１、５１２のうち以外の領域に充填される。これにより、プリプレグ３０Ａを構成する樹脂材料を複数の領域５１３間に埋め込む。さらに、プリプレグ４０Ａを構成する樹脂材料を複数の領域５１４間に埋め込む。 Accordingly, the resin material constituting the prepreg 30 </ b> A is filled in a region other than the plurality of surface side inner layer wirings 511 and 512 in the surface 20 a of the core layer 20. Thereby, the resin material constituting the prepreg 30 </ b> A is embedded between the plurality of regions 513. Further, a resin material constituting the prepreg 40 </ b> A is embedded between the plurality of regions 514.
　そして、積層体１６８を加熱することにより、プリプレグ３０Ａ、４０Ａを硬化して積層体１６８を一体化する。このとき、プリプレグ３０Ａを硬化したものがビルドアップ層３０として形成され、かつプリプレグ４０Ａを硬化したものがビルドアップ層４０として形成されることになる。 Then, by heating the laminate 168, the prepregs 30A and 40A are cured to integrate the laminate 168. At this time, the cured prepreg 30 </ b> A is formed as the buildup layer 30, and the cured prepreg 40 </ b> A is formed as the buildup layer 40.
　次に、図８（ａ）に示されるように、レーザ等により、金属板１６６、ビルドアップ層３０を貫通して表面側内層配線５１１、５１２に達する貫通孔９１ａを形成する。同様に、図８（ａ）とは別断面において、金属板１６７、ビルドアップ層４０を貫通して裏面側内層配線５２１、５２２に達する貫通孔１０１ａを形成する。 Next, as shown in FIG. 8A, a through hole 91a that penetrates the metal plate 166 and the build-up layer 30 and reaches the surface-side inner- layer wirings 511 and 512 is formed by a laser or the like. Similarly, in a cross section different from that shown in FIG. 8A, a through hole 101a that penetrates through the metal plate 167 and the buildup layer 40 and reaches the back surface inner wirings 521 and 522 is formed.
　そして、図８（ｂ）に示されるように、無電解メッキや電気メッキ等でいわゆるフィルドメッキを行い、貫通孔９１ａ、１０１ａを金属メッキ１６９で埋め込む。これにより、ビルドアップ層３０に形成された貫通孔９１ａ、１０１ａに埋め込まれた金属メッキ１６９にて貫通電極９１ｂおよび図１に示した貫通電極１０１ｂが構成される。また、貫通孔９１ａ、１０１ａに貫通電極９１ｂ、１０１ｂが埋め込まれたフィルドビア９１、１０１が形成される。なお、次の図８（ｃ）以降では、金属板１６６および金属メッキ１６９をまとめて１層として示してある。 Then, as shown in FIG. 8B, so-called filled plating is performed by electroless plating, electroplating, or the like, and the through holes 91a and 101a are embedded with metal plating 169. Thus, the through electrode 91b and the through electrode 101b shown in FIG. 1 are configured by the metal plating 169 embedded in the through holes 91a and 101a formed in the buildup layer 30. Further, filled vias 91 and 101 in which through electrodes 91b and 101b are embedded in the through holes 91a and 101a are formed. In FIG. 8C and subsequent figures, the metal plate 166 and the metal plating 169 are collectively shown as one layer.
　続いて、図８（ｃ）に示されるように、金属板１６６、１６７上に図示しないレジストを配置する。そして、レジストをマスクとしてウェットエッチング等を行って金属板１６６、１６７をパターニングすると共に、適宜金属メッキを形成することにより、表面側表層配線６１～６３および裏面側表層配線７１、７２を形成する。 Subsequently, as shown in FIG. 8C, a resist (not shown) is disposed on the metal plates 166 and 167. Then, the metal plates 166 and 167 are patterned by performing wet etching or the like using a resist as a mask, and the surface side surface layer wirings 61 to 63 and the back side surface layer wirings 71 and 72 are formed by appropriately forming metal plating.
　つまり、本実施形態では、表面側表層配線６１～６３は、金属板１６６および金属メッキ１６９を有する構成とされ、裏面側表層配線７１、７２は、金属板１６７および金属メッキ１６９を有する構成とされている。 That is, in the present embodiment, the front surface side wirings 61 to 63 are configured to have the metal plate 166 and the metal plating 169, and the back surface side wirings 71 and 72 are configured to have the metal plate 167 and the metal plating 169. ing.
　次に、図８（ｄ）に示されるように、ビルドアップ層３０、４０の表面３０ａ、４０ａにそれぞれソルダーレジスト１１０を配置して適宜パターニングすることにより、上記多層基板１０が製造される。なお、図８（ｄ）に示される範囲内において、表面３０ａ上のソルダーレジスト１１０がすべて除去されているが、図１に示すように他の領域においてソルダーレジスト１１０が残された状態になっている。 Next, as shown in FIG. 8D, the multilayer substrate 10 is manufactured by arranging the solder resist 110 on the surfaces 30a and 40a of the buildup layers 30 and 40, respectively, and appropriately patterning them. 8D, all of the solder resist 110 on the surface 30a has been removed, but the solder resist 110 remains in other regions as shown in FIG. Yes.
　その後は、特に図示しないが、はんだ１３０を介して電子部品１２１～１２３をランド６１に搭載する。そして、パワー素子１２１および制御素子１２２とランド６２との間でワイヤボンディングを行い、パワー素子１２１および制御素子１２２とランド６２とを電気的に接続する。続いて、ランド６１、６２および電子部品１２１～１２３が封止されるように、金型を用いたトランスファーモールド法やコンプレッションモールド法等によってモールド樹脂層１５０を形成する。 Thereafter, although not particularly shown, the electronic components 121 to 123 are mounted on the land 61 via the solder 130. Then, wire bonding is performed between the power element 121 and the control element 122 and the land 62, and the power element 121 and the control element 122 and the land 62 are electrically connected. Subsequently, the mold resin layer 150 is formed by a transfer molding method using a mold, a compression molding method, or the like so that the lands 61 and 62 and the electronic components 121 to 123 are sealed.
　以上説明した本実施形態によれば、多層基板１０の製造過程において、コア層２０の表面２０ａに間隔を空けて複数の表面側内層配線５１１、５１２を配置する。コア層２０の裏面２０ｂに間隔を空けて複数の裏面側内層配線５２１、５２２を配置する。次に、ガラスクロス１ｂの両面側を樹脂材料で封止してなるプリプレグ３０Ａとガラスクロス１ｃの両面側を樹脂材料で封止してなるプリプレグ４０Ａとを用意する。これに伴い、コア層２０の表面２０ａにプリプレグ３０Ａを対向させ、かつコア層２０の裏面２０ｂにプリプレグ４０Ａを対向させる。このとき、ガラスクロス１ｂは、複数の表面側内層配線５１１、５１２および複数の領域５１３を連続して覆うように形成されている。ガラスクロス１ｃは、複数の裏面側内層配線５２１、５２２および複数の領域５１３を連続して覆うように形成されている。その後、プリプレグ３０Ａ、コア層２０、およびプリプレグ４０Ａを積層方向に圧力を加える。これにより、ガラスクロス１ｂのうち領域５１３を覆う部位を、ガラスクロス１ｂのうち複数の表面側内層配線５１１、５１２を覆う部位よりもコア側２０に近づくように曲げる。よって、ガラスクロス１ｂのうち領域５１３を覆う部位が表面側内層配線５１１、５１２の上面５１２ａよりもコア層２０側に入り込む。したがって、プリプレグ３０Ａを構成する樹脂材料がガラスクロス１ｂによって複数の領域５１３内に押し込まれる。よって、複数の領域５１３内に十分な量の樹脂材料を充填することができる。 According to the present embodiment described above, in the manufacturing process of the multilayer substrate 10, the plurality of surface-side inner- layer wirings 511 and 512 are arranged at intervals on the surface 20 a of the core layer 20. A plurality of back surface side inner layer wirings 521 and 522 are arranged on the back surface 20b of the core layer 20 with a space therebetween. Next, a prepreg 30A formed by sealing both surfaces of the glass cloth 1b with a resin material and a prepreg 40A formed by sealing both surfaces of the glass cloth 1c with a resin material are prepared. Accordingly, the prepreg 30 </ b> A is opposed to the front surface 20 a of the core layer 20, and the prepreg 40 </ b> A is opposed to the back surface 20 b of the core layer 20. At this time, the glass cloth 1b is formed so as to continuously cover the plurality of surface-side inner layer wirings 511 and 512 and the plurality of regions 513. The glass cloth 1c is formed so as to continuously cover the plurality of back surface side inner layer wirings 521 and 522 and the plurality of regions 513. Then, pressure is applied to the prepreg 30A, the core layer 20, and the prepreg 40A in the stacking direction. Thereby, the site | part which covers the area | region 513 among the glass cloth 1b is bent so that it may approach the core side 20 rather than the site | part which covers several surface side inner layer wiring 511,512 among the glass cloth 1b. Therefore, the part which covers the area | region 513 among the glass cloth 1b penetrates into the core layer 20 side rather than the upper surface 512a of the surface side inner layer wiring 511,512. Therefore, the resin material constituting the prepreg 30A is pushed into the plurality of regions 513 by the glass cloth 1b. Therefore, a sufficient amount of resin material can be filled in the plurality of regions 513.
　さらに、ガラスクロス１ｃのうち領域５１４を覆う部位を、ガラスクロス１ｃのうち複数の裏面側内層配線５２１、５２２を覆う部位よりもコア側２０に近づくように曲げる。よって、ガラスクロス１ｃのうち領域５１４を覆う部位が裏面側内層配線５２１、５２２の下面５２２ａよりもコア層２０側に入り込む。したがって、プリプレグ４０Ａを構成する樹脂材料がガラスクロス１ｃによって複数の領域５１４内に押し込まれる。よって、複数の領域５１４内に十分な量の樹脂材料を充填することができる。以上により、領域５１３、５１４に十分な量の樹脂材料を充填することができるので、領域５１３、５１４でボイドの発生を抑制することができる。 Further, the portion of the glass cloth 1c that covers the region 514 is bent so as to be closer to the core side 20 than the portion of the glass cloth 1c that covers the plurality of back side inner layer wirings 521 and 522. Therefore, the part which covers the area | region 514 among the glass cloth 1c penetrates into the core layer 20 side rather than the lower surface 522a of the back surface side inner layer wiring 521,522. Therefore, the resin material constituting the prepreg 40A is pushed into the plurality of regions 514 by the glass cloth 1c. Therefore, a sufficient amount of resin material can be filled in the plurality of regions 514. As described above, since a sufficient amount of the resin material can be filled in the regions 513 and 514, generation of voids in the regions 513 and 514 can be suppressed.
　本実施形態では、ビルドアップ層３０、４０の質量のうち樹脂材料の質量が占める比率「ｗｔ％」が８０％以上になるように設定されている。このため、ビルドアップ層３０、４０としては領域５１３、５１４に対して十分な量の樹脂材料を供給することができるので、樹脂材料によって領域５１３、５１４を確実に埋め込むことができる。このため、ボイドの発生を確実に抑制することができる。 In the present embodiment, the ratio “wt%” of the mass of the resin material out of the mass of the buildup layers 30 and 40 is set to be 80% or more. For this reason, since the resin material of sufficient quantity can be supplied with respect to the area | regions 513 and 514 as the buildup layers 30 and 40, the area | regions 513 and 514 can be reliably embedded with a resin material. For this reason, generation | occurrence | production of a void can be suppressed reliably.
　本実施形態では、ガラスクロス１ｂの厚み寸法Ｌ１は、ガラスクロス１ｂの上部と表面側表層配線６１～６３との間の距離Ｌ２よりも小さくなっている。ガラスクロス１ｃの厚み寸法Ｌ３は、ガラスクロス１ｃの下部と裏面側表層配線７１、７２との間の距離Ｌ４よりも小さくなっている。このため、製造過程で加圧されても、領域５１３、５１４に対応して十分に湾曲することができる。 In this embodiment, the thickness dimension L1 of the glass cloth 1b is smaller than the distance L2 between the upper part of the glass cloth 1b and the surface-side surface wirings 61 to 63. The thickness dimension L3 of the glass cloth 1c is smaller than the distance L4 between the lower part of the glass cloth 1c and the back surface side wirings 71 and 72. For this reason, even if it pressurizes in a manufacturing process, it can fully curve corresponding to field 513,514.
　本実施形態では、ガラスクロス１ｂ、１ｃのバスケットホールは、直径が１００μｍ以下に設定されている。例えば、ガラスクロス１のバスケットホールを、直径が１００μｍよりも大きくなるように設定すると、積層体１６８を加圧した際に、図１０中の太線の矢印の如く、樹脂層３１側からバスケットホールを通して樹脂層３２側に樹脂材料が移動してしまう。よって、樹脂層３１からガラスクロス１に圧力が加わらない。このため、ガラスクロス１を湾曲させることができない。 In this embodiment, the basket holes of the glass cloths 1b and 1c are set to have a diameter of 100 μm or less. For example, if the basket hole of the glass cloth 1 is set to have a diameter larger than 100 μm, when the laminate 168 is pressed, the basket hole is passed through the basket hole from the resin layer 31 side as indicated by the thick line arrow in FIG. The resin material moves to the resin layer 32 side. Therefore, no pressure is applied from the resin layer 31 to the glass cloth 1. For this reason, the glass cloth 1 cannot be curved.
　これに対して、ガラスクロス１ｂ、１ｃのバスケットホールは、上述の如く、直径が１００μｍ以下に設定されている。このため、積層体１６８を加圧した際に、樹脂層３１側からバスケットホールを通して樹脂層３２側に樹脂材料が移動し難くなる。よって、樹脂層３１からガラスクロス１ｂ、１ｃに十分に圧力を加えることができる。これにより、ガラスクロス１ｂ、１ｃを十分に湾曲させることができる。 On the other hand, the basket holes of the glass cloths 1b and 1c are set to have a diameter of 100 μm or less as described above. For this reason, when the laminated body 168 is pressurized, it becomes difficult for the resin material to move from the resin layer 31 side to the resin layer 32 side through the basket hole. Therefore, sufficient pressure can be applied from the resin layer 31 to the glass cloths 1b and 1c. Thereby, the glass cloth 1b, 1c can be curved sufficiently.
　本実施形態では、ガラスクロス１ｂ、１ｃのバスケットホールの直径は、ガラスクロス１ａのバスケットホールの直径よりも小さくなっている。このため、ガラスクロス１ｂ、１ｃのバスケットホールの直径が、ガラスクロス１ａのバスケットホールの直径よりも大きい場合に比べて、積層体１６８を加圧した際に、樹脂層３１側からバスケットホールを通して樹脂層３２側に樹脂材料が移動し難くなる。よって、樹脂層３１からガラスクロス１ｂ、１ｃに十分に圧力を加えることができる。これにより、ガラスクロス１ｂ、１ｃを十分に湾曲させることができる。 In this embodiment, the diameter of the basket hole of the glass cloth 1b, 1c is smaller than the diameter of the basket hole of the glass cloth 1a. For this reason, compared with the case where the diameter of the basket hole of the glass cloth 1b, 1c is larger than the diameter of the basket hole of the glass cloth 1a, the resin is passed through the basket hole from the resin layer 31 side when the laminate 168 is pressed. It becomes difficult for the resin material to move to the layer 32 side. Therefore, sufficient pressure can be applied from the resin layer 31 to the glass cloths 1b and 1c. Thereby, the glass cloth 1b, 1c can be curved sufficiently.
　本実施形態では、ビルドアップ層３０、４０の質量のうちフィラの質量が占める比率「ｗｔ％」は、コア層２０の質量のうちフィラの質量が占める比率「ｗｔ％」よりも大きくなっている。これにより、ビルドアップ層３０、４０において、フィラが混ざった樹脂材料の粘度を高めることができる。したがって、積層体１６８を加圧した際に、樹脂層３１からガラスクロス１ｂ、１ｃに十分に圧力を加えることができる。これにより、ガラスクロス１ｂ、１ｃを十分に湾曲させることができる。これに加えて、ビルドアップ層３０、４０において十分な熱伝導率を確保することができる。 In the present embodiment, the ratio “wt%” of the mass of the buildup layers 30 and 40 occupied by the filler mass is larger than the ratio “wt%” of the mass of the core layer 20 occupied by the filler. . Thereby, in the buildup layers 30 and 40, the viscosity of the resin material mixed with filler can be increased. Therefore, when the laminated body 168 is pressurized, sufficient pressure can be applied from the resin layer 31 to the glass cloths 1b and 1c. Thereby, the glass cloth 1b, 1c can be curved sufficiently. In addition, sufficient thermal conductivity can be secured in the buildup layers 30 and 40.
　本実施形態では、ガラスクロス１ｂは、複数の表面側内層配線５１１、５１２および複数の領域５１３を連続して覆うように形成されている。このため、ビルドアップ層３０の強度を増すことができる。これに加えて、ビルドアップ層３０において樹脂層３１にクラックが生じた場合、樹脂層３１のクラックが起因して、樹脂層３１側からガラスクロス１ｂの切れ目を介して樹脂層３２側にクラックが進展することを抑制することができる。 In the present embodiment, the glass cloth 1b is formed so as to continuously cover the plurality of front side inner layer wirings 511 and 512 and the plurality of regions 513. For this reason, the strength of the buildup layer 30 can be increased. In addition to this, when a crack occurs in the resin layer 31 in the build-up layer 30, the crack occurs in the resin layer 31 from the resin layer 31 side through the cut of the glass cloth 1 b due to the crack in the resin layer 31. Progress can be suppressed.
　さらに、ガラスクロス１ｃは、複数の裏面側内層配線５２１、５２２および複数の領域５１４を連続して覆うように形成されている。このため、ビルドアップ層４０においてビルドアップ層３０と同様の効果が得られる。 Furthermore, the glass cloth 1c is formed so as to continuously cover the plurality of back surface side inner layer wirings 521 and 522 and the plurality of regions 514. For this reason, the same effect as the buildup layer 30 is obtained in the buildup layer 40.
　（第２実施形態）
　本第２実施形態では、凸部を設けた金属板１６６を用いてプリプレグ３０Ａのガラスクロス１ｂの変形を加勢する例について説明する。 (Second Embodiment)
In the second embodiment, an example in which the deformation of the glass cloth 1b of the prepreg 30A is energized using the metal plate 166 provided with the convex portions will be described.
　図１１（ａ）、（ｂ）に本実施形態の多層基板１０の製造過程の一部を示す。 FIGS. 11A and 11B show a part of the manufacturing process of the multilayer substrate 10 of the present embodiment.
　本実施形態の多層基板１０では、金属板１６６に凸部１６６ａが設けられている。凸部１６６ａは、金属板１６６のうち領域５１３に対応する部位からコア層２０側に突起するように形成されている。 In the multilayer substrate 10 of the present embodiment, the metal plate 166 is provided with a convex portion 166a. The convex portion 166a is formed so as to protrude from the portion corresponding to the region 513 in the metal plate 166 to the core layer 20 side.
　このため、コア層２０にプリプレグ３０Ａ、および金属板１６６等を積層して積層体１６８を構成して、積層体１６８を積層方向に加圧しつつ加熱した際に、
金属板１６６が凸部１６６ａによってプリプレグ３０Ａをコア層２０側に加圧することになる。つまり、金属板１６６がプリプレグ３０Ａに対してコア層２０の反対側から押し付けることになる。これにより、凸部１６６ａがプリプレグ３０Ａのうち領域５１３を覆う部分を押し付けてガラスクロス１ｂの変形を加勢することができる。 For this reason, when the prepreg 30A and the metal plate 166 are laminated on the core layer 20 to form the laminated body 168, and the laminated body 168 is heated while being pressed in the laminating direction,
The metal plate 166 pressurizes the prepreg 30 </ b> A toward the core layer 20 by the convex portion 166 a. That is, the metal plate 166 is pressed against the prepreg 30 </ b> A from the opposite side of the core layer 20. Thereby, the convex part 166a can press the part which covers the area | region 513 among prepreg 30A, and can energize the deformation | transformation of the glass cloth 1b.
　以上により、ガラスクロス１ｂのうち領域５１３を覆う部分を、ガラスクロス１ｂのうち複数の表面側内層配線５１１、５１２を覆う部位よりもコア層２０側に近づくように湾曲させることを確実に行うことできる。これにより、複数の領域５１３内にプリプレグ３０Ａを構成する樹脂材料を確実に充填することができる。 As described above, the portion of the glass cloth 1b that covers the region 513 is reliably bent so as to be closer to the core layer 20 side than the portion of the glass cloth 1b that covers the plurality of front-side inner layer wirings 511 and 512. it can. Thereby, the resin material which comprises the prepreg 30A can be reliably filled in the some area | region 513. FIG.
　なお、図１１（ａ）、（ｂ）では、積層体１６８のうちプリプレグ３０Ａ、および金属板１６６以外の裏面側内層配線５２１、５２２、プリプレグ４０Ａおよび金属板１６７の図示を省略している。 11A and 11B, the illustration of the prepreg 30A and the backside inner layer wirings 521 and 522 other than the metal plate 166, the prepreg 40A, and the metal plate 167 in the laminated body 168 is omitted.
　上記第２実施形態では、凸部１６６ａを設けた金属板１６６を用いた例について説明したが、これに加えて、凸部を設けた金属板１６７を用いてもよい。これにより、凸部によってプリプレグ４０Ａのガラスシート１ｃの変形を加勢することができる。これにより、複数の領域５１４内にプリプレグ４０Ａを構成する樹脂材料を確実に充填することができる。 In the second embodiment, the example using the metal plate 166 provided with the convex portion 166a has been described, but in addition to this, the metal plate 167 provided with the convex portion may be used. Thereby, a deformation | transformation of the glass sheet 1c of the prepreg 40A can be urged | biased by a convex part. Thereby, the resin material which comprises the prepreg 40A can be reliably filled in the some area | region 514. FIG.
　（第３実施形態）
　本第３実施形態では、凸部の成形型を備えるプレス機を用いて積層体１６８を加圧することにより、プリプレグ３０Ａのガラスクロス１ｂの変形を加勢する例について説明する。 (Third embodiment)
In the third embodiment, an example will be described in which the deformation of the glass cloth 1b of the prepreg 30A is urged by pressurizing the laminated body 168 using a press provided with a convex mold.
　図１２（ａ）、（ｂ）に本実施形態の多層基板１０の製造過程の一部を示す。 FIGS. 12A and 12B show a part of the manufacturing process of the multilayer substrate 10 of the present embodiment.
　本実施形態では、積層体１６８を加圧する際に、図１２（ａ）に示されるように、凸状の成形型６０１を備えるプレス機６００を用いる。成形型６０１は、金属製の金型本体６０３に金属製の凸部６０４が設けられたものである。凸部６０４は、金型本体６０３のうち領域５１３に対応する部位からコア層２０側に突起するように形成されている。成形型６０１は、金属製のベース６０２の上側に配置されている。 In this embodiment, when pressurizing the laminated body 168, as shown in FIG. 12A, a press machine 600 including a convex mold 601 is used. The molding die 601 is a metal mold body 603 provided with a metal convex portion 604. The convex portion 604 is formed so as to protrude from the portion corresponding to the region 513 in the mold body 603 to the core layer 20 side. The mold 601 is disposed on the upper side of the metal base 602.
　本実施形態では、金属板１６６、１６７を除いた表面側内層配線５１１、５１２、プリプレグ３０Ａ等をコア層２０に積層して積層体１６８を構成する。そして、積層体１６８と成形型６００との間に、テフロン（登録商標）シート等からなる離型性シート６２０を挟んだ状態で、離型性シート６２０および積層体１６８を、成形型６００および金属製のベース６１０の間に配置する。このとき、積層体１６８を加熱しつつ、積層体１６８を成形型６００およびベース６１０によって加圧する。したがって、成形型６００の凸部６０１がガラスクロス１ｂのうち領域５１３を覆う部位の湾曲を加勢することができる。よって、上記第２実施形態と同様に、ガラスクロス１ｂのうち領域５１３を覆う部位を確実に湾曲させることできる。これにより、複数の領域５１３内にプリプレグ３０Ａを構成する樹脂材料を確実に充填することができる。 In this embodiment, the laminated body 168 is configured by laminating the surface side inner layer wirings 511 and 512 excluding the metal plates 166 and 167, the prepreg 30A, and the like on the core layer 20. Then, with the release sheet 620 made of a Teflon (registered trademark) sheet or the like sandwiched between the laminate 168 and the mold 600, the release sheet 620 and the laminate 168 are replaced with the mold 600 and the metal. It arrange | positions between the bases 610 made from. At this time, the laminate 168 is pressed by the mold 600 and the base 610 while the laminate 168 is heated. Therefore, the convex part 601 of the shaping | molding die 600 can urge the curve of the site | part which covers the area | region 513 among the glass cloth 1b. Therefore, the part which covers the area | region 513 among the glass cloth 1b can be curved reliably like the said 2nd Embodiment. Thereby, the resin material which comprises the prepreg 30A can be reliably filled in the some area | region 513. FIG.
　なお、本実施形態では、成形型６００およびベース６１０によって積層体１６８を加圧するため、成形型６００の形状に沿うようにプリプレグ３０Ａの上面３００が変形する。そこで、積層体１６８の加圧後に、プリプレグ３０Ａの上面３００から離型性シート６２０を外す。そして、プリプレグ３０Ａの上面３００に更に樹脂層を積層することにより、プリプレグ３０Ａの上面３００側を平坦にする。 In this embodiment, since the laminate 168 is pressed by the mold 600 and the base 610, the upper surface 300 of the prepreg 30A is deformed along the shape of the mold 600. Therefore, the release sheet 620 is removed from the upper surface 300 of the prepreg 30 </ b> A after the laminate 168 is pressed. Then, by further laminating a resin layer on the upper surface 300 of the prepreg 30A, the upper surface 300 side of the prepreg 30A is flattened.
　上記第３実施形態では、積層体１６８を加圧する際に、成形型６００に凸部６０１を設けたプレス機を用いた例について説明したが、これに加えて、ベース６１０に凸部を設けたものを用いてもよい。凸部によってプリプレグ４０Ａのガラスシート１ｃの変形を加勢することができる。これにより、複数の領域５１４内にプリプレグ４０Ａを構成する樹脂材料を確実に充填することができる。 In the third embodiment, the example in which the press machine provided with the convex portion 601 is provided in the mold 600 when pressing the laminated body 168 has been described, but in addition to this, the base 610 is provided with the convex portion. A thing may be used. The deformation of the glass sheet 1c of the prepreg 40A can be urged by the convex portion. Thereby, the resin material which comprises the prepreg 40A can be reliably filled in the some area | region 514. FIG.
　（第４実施形態）
　上記第３実施形態では、金属製の成形型６００を用いたプレス機を用いた例について説明したが、これに代えて、静水圧成形法により積層体１６８を加圧してもよい。 (Fourth embodiment)
Although the said 3rd Embodiment demonstrated the example using the press using the metal shaping | molding die 600, it may replace with this and you may pressurize the laminated body 168 by an isostatic pressing method.
　図１３（ａ）、（ｂ）に本実施形態の多層基板１０の製造過程の一部を示す。 FIGS. 13A and 13B show a part of the manufacturing process of the multilayer substrate 10 of the present embodiment.
　本実施形態では、積層体１６８を加圧する際に、図１３（ａ）に示されるように、バルーン状に形成されているゴム型からなる成形型６０１Ａを備える静水圧プレス機６００Ａを用いる。これにより、プリプレグ３０Ａに対して加える圧力を面方向に均一にすることができる。よって、上記第２、３の実施形態と同様に、ガラスクロス１ｂのうち領域５１３を覆う部位を確実に湾曲させることができる。これにより、複数の領域５１３および表面側内層配線５１１、５１２から構成されるコア層２０の表面側の凹凸にプリプレグ３０Ａのガラスクロス１ｂ形状を追従させることができる。よって、複数の領域５１３内にプリプレグ３０Ａを構成する樹脂材料を確実に充填することができる。 In this embodiment, when pressurizing the laminate 168, as shown in FIG. 13A, a hydrostatic press 600A including a molding die 601A made of a rubber mold formed in a balloon shape is used. Thereby, the pressure applied with respect to the prepreg 30A can be made uniform in a surface direction. Therefore, as in the second and third embodiments, the portion of the glass cloth 1b that covers the region 513 can be reliably bent. Thereby, the glass cloth 1b shape of the prepreg 30A can be made to follow the unevenness | corrugation of the surface side of the core layer 20 comprised from the some area | region 513 and the surface side inner layer wiring 511,512. Accordingly, the resin material constituting the prepreg 30 </ b> A can be reliably filled in the plurality of regions 513.
　なお、上記第３の実施形態と同様に、プリプレグ３０Ａを加圧後、プリプレグ３０Ａの上面３００に樹脂層を積層することにより、プリプレグ３０Ａの上面３００側を平坦にしてもよい。 As in the third embodiment, the upper surface 300 side of the prepreg 30A may be flattened by pressurizing the prepreg 30A and then laminating a resin layer on the upper surface 300 of the prepreg 30A.
　（第４実施形態）
　上記第１～３実施形態では、ガラスクロス１ｂのうち領域５１３を覆う部位を曲げて、ガラスクロス１ｂのうち領域５１３を覆う部位が表面側内層配線５１１、５１２の上面５１２ａよりもコア層２０側に入り込むようにした例について説明したが、これに限らず、次のようにしてもよい。 (Fourth embodiment)
In the first to third embodiments, the portion of the glass cloth 1b that covers the region 513 is bent, and the portion of the glass cloth 1b that covers the region 513 is closer to the core layer 20 than the upper surface 512a of the surface-side inner layer wirings 511 and 512. Although the example of entering is described, the present invention is not limited to this, and the following may be used.
　すなわち、図１４に示すように、ガラスクロス１ｂのうち領域５１３を覆う部位が、ガラスクロス１ｂのうち複数の表面側内層配線５１１、５１２を覆う部位よりもコア側２０に近づくように曲げるのであれば、ガラスクロス１ｂのうち領域５１３を覆う部位が表面側内層配線５１１、５１２の上面５１２ａに対してコア層２０と反対側に位置してもよい。 That is, as shown in FIG. 14, the portion of the glass cloth 1 b that covers the region 513 is bent so that it is closer to the core side 20 than the portion of the glass cloth 1 b that covers the plurality of front surface inner layer wirings 511 and 512. For example, a portion of the glass cloth 1b that covers the region 513 may be positioned on the opposite side of the core layer 20 with respect to the upper surface 512a of the front-side inner- layer wirings 511 and 512.
　（他の実施形態）
　上記第１～第４の実施形態では、プリプレグ層からなるコア層２０を用いた例について説明したが、これに代えて、絶縁層としては、セラミック等からコア層２０を用いてもよい。 (Other embodiments)
In the first to fourth embodiments, the example using the core layer 20 made of the prepreg layer has been described. However, instead of this, the core layer 20 made of ceramic or the like may be used as the insulating layer.
　上記第１～第４の実施形態では、「間隔を空けて配置された導体」としての複数の表面側内層配線５１１、５１２をそれぞれ離れて配置した例について説明したが、これに代えて、互いに対向する２つの部位を有するように湾曲した１つの導体を表面側内層配線として用いてもよい。この場合、２つの部位の間の領域が本発明の「間隔を構成する領域」になる。同様に、互いに対向する２つの部位を有するように湾曲した１つの導体を裏面側内層配線として用いてもよい。この場合も、２つの部位の間の領域が本発明の「間隔を構成する領域」になる。 In the first to fourth embodiments described above, examples in which the plurality of front side inner layer wirings 511 and 512 as “conductors arranged at intervals” are arranged apart from each other have been described. One conductor curved so as to have two portions facing each other may be used as the front-side inner layer wiring. In this case, the region between the two parts is the “region constituting the interval” in the present invention. Similarly, a single conductor curved so as to have two portions facing each other may be used as the back side inner layer wiring. Also in this case, the region between the two parts is the “region constituting the interval” of the present invention.
　また、本開示に係る実施形態は、上記した実施形態に限定されるものではなく、本開示の技術思想の範囲内において適宜変更が可能である。また、上記各実施形態は、互いに無関係なものではなく、組み合わせが明らかに不可な場合を除き、適宜組み合わせが可能であり、また、上記各実施形態は、上記の図示例に限定されるものではない。 Further, the embodiment according to the present disclosure is not limited to the above-described embodiment, and can be appropriately changed within the scope of the technical idea of the present disclosure. The above embodiments are not irrelevant to each other, and can be combined as appropriate unless the combination is clearly impossible. Also, the above embodiments are not limited to the illustrated examples. Absent.

Claims (10)

  1. 　電気絶縁材料からなる絶縁層（２０）と、
    　前記絶縁層の表面（２０ａ、２０ｂ）に設けられたもので、間隔を空けて配置された導体（５１１、５１２、５２１、５２２）と、
    　第１のガラスクロス（１ｂ、１ｃ）と前記第１のガラスクロスの両面側を樹脂材料で封止する樹脂層（３１、３２、４１、４２）とを備えるプリプレグ（３０Ａ、４０Ａ）を、前記導体と共に前記絶縁層の表面を覆うように前記絶縁層に積層されてなるビルドアップ層（３０、４０）と、を備え、
    　前記絶縁層の表面側では、前記樹脂層を構成する樹脂材料が前記間隔を構成する領域（５１３、５１４）内に充填された状態で前記導体を封止しており、
    　前記第１のガラスクロスが前記導体および前記間隔を構成する領域を連続して覆うように形成されており、
    　前記第１のガラスクロスのうち前記間隔を構成する領域を覆う部位は、前記第１のガラスクロスのうち前記導体を覆う部位よりも前記絶縁層側に近づくように曲がっている多層基板。     An insulating layer (20) made of an electrically insulating material;
    Conductors (511, 512, 521, 522) provided on the surfaces (20a, 20b) of the insulating layer and spaced apart; and
    A prepreg (30A, 40A) comprising a first glass cloth (1b, 1c) and resin layers (31, 32, 41, 42) for sealing both surfaces of the first glass cloth with a resin material, A buildup layer (30, 40) laminated on the insulating layer so as to cover the surface of the insulating layer together with the conductor, and
    On the surface side of the insulating layer, the conductor is sealed in a state in which the resin material constituting the resin layer is filled in the regions (513, 514) constituting the gap,
    The first glass cloth is formed so as to continuously cover the conductor and the region constituting the interval,
    A portion of the first glass cloth that covers a region that forms the interval is a multilayer substrate that is bent so as to be closer to the insulating layer than a portion of the first glass cloth that covers the conductor.
  2. 　前記第１のガラスクロスのうち前記間隔を構成する領域を覆う部位は、前記導体のうち前記絶縁層の反対側端部（５１２ａ、５２２ａ）よりも前記絶縁層側に入り込んでいる請求項１に記載の多層基板。 The part which covers the area | region which comprises the said space | interval among the said 1st glass cloth has penetrated into the said insulating layer side rather than the opposite side edge part (512a, 522a) of the said insulating layer among the said conductors. The multilayer substrate described.
  3. 　前記ビルドアップ層の厚み方向において前記ビルドアップ層のうち前記絶縁層の反対側の面（３１ａ、４１ａ）と前記第１のガラスクロスとの間の寸法よりも、前記第１のガラスクロスの厚さ寸法の方が小さい請求項１または２に記載の多層基板。 The thickness of the first glass cloth is larger than the dimension between the first glass cloth and the surface (31a, 41a) opposite to the insulating layer in the buildup layer in the thickness direction of the buildup layer. The multilayer substrate according to claim 1 or 2, wherein the thickness dimension is smaller.
  4. 　前記絶縁層は、第２のガラスクロス（１ａ）と前記第２のガラスクロスの両面側を樹脂材料で封止する樹脂層（２１、２２）を備えるプリプレグから構成されている請求項１ないし３のいずれか１つに記載の多層基板。 The said insulating layer is comprised from the prepreg provided with the resin layer (21, 22) which seals the double-sided side of the 2nd glass cloth (1a) and the said 2nd glass cloth with a resin material. A multilayer substrate according to any one of the above.
  5. 　前記第１、第２のガラスクロスは、第１方向に延びるガラス繊維からそれぞれ構成される複数本の第１のヤーン（３３）と、前記第１方向に直交する第２方向に延びるガラス繊維からそれぞれ構成される複数本の第２のヤーン（３４）とを備え、前記複数本の第１のヤーンのうち隣り合う２本の第１のヤーンと前記複数本の第２のヤーンのうち隣り合う２本の第２のヤーンとが穴（３６）を囲むように織られたものであり、
    　前記第１のガラスクロスの前記穴は、前記第２のガラスクロスの前記穴よりも小さい請求項４に記載の多層基板。     The first and second glass cloths include a plurality of first yarns (33) each composed of glass fibers extending in a first direction, and glass fibers extending in a second direction orthogonal to the first direction. A plurality of second yarns (34) each configured, and adjacent to each other between the two first yarns adjacent to each other among the plurality of first yarns and the plurality of second yarns. Two second yarns are woven to surround the hole (36),
    The multilayer substrate according to claim 4, wherein the hole of the first glass cloth is smaller than the hole of the second glass cloth.
  6. 　前記ビルドアップ層の前記樹脂層を構成する樹脂材料には、第１のフィラが混ざっており、
    　前記絶縁層の前記樹脂層を構成する樹脂材料には、第２のフィラが混ざっており、
    　前記ビルドアップ層の質量のうち前記第１のフィラの質量が占める比率は、前記絶縁層の質量のうち前記第２のフィラの質量が占める比率よりも大きい請求項４または５に記載の多層基板。     The resin material constituting the resin layer of the build-up layer is mixed with a first filler,
    The resin material constituting the resin layer of the insulating layer is mixed with a second filler,
    The multilayer substrate according to claim 4 or 5, wherein a ratio of the mass of the first filler to a mass of the buildup layer is larger than a ratio of the mass of the second filler to the mass of the insulating layer. .
  7. 　前記ビルドアップ層の質量のうち前記樹脂材料の質量が占める比率は、８０％以上である請求項１ないし６のいずれか１つに記載の多層基板。 The multilayer substrate according to any one of claims 1 to 6, wherein a ratio of the mass of the resin material to the mass of the buildup layer is 80% or more.
  8. 　間隔を空けて配置された導体（５１１、５１２、５２１、５２２）を、電気絶縁材料からなる絶縁層（２０）の表面（２０ａ、２０ｂ）に形成すること（Ｓ１００）と、
    　ガラスクロス（１ｂ、１ｃ）と前記ガラスクロスの両面側を樹脂材料で封止する樹脂層（３１、３２、４１、４２）とを備えるプリプレグ（３０Ａ、４０Ａ）を用意すること（Ｓ１１０）と、
    　前記絶縁層の表面側における前記導体と前記間隔を構成する領域（５１３、５１４）とを前記ガラスクロスが連続して覆うように前記絶縁層および前記プリプレグを対向させること（Ｓ１２０）と、
    　前記絶縁層および前記プリプレグを対向させた後に、前記絶縁層および前記プリプレグのうち一方を他方に対して加圧して、前記ガラスクロスのうち前記間隔を構成する領域を覆う部位を、前記ガラスクロスのうち前記導体を覆う部位よりも前記縁層側に近づくように曲げることにより、前記樹脂層を構成する樹脂材料を前記間隔を構成する領域内に充填すること（Ｓ１２０）と、を備える多層基板の製造方法。     Forming spaced apart conductors (511, 512, 521, 522) on the surface (20a, 20b) of the insulating layer (20) made of an electrically insulating material (S100);
    Preparing a prepreg (30A, 40A) comprising a glass cloth (1b, 1c) and resin layers (31, 32, 41, 42) for sealing both surfaces of the glass cloth with a resin material (S110);
    Making the insulating layer and the prepreg face each other so that the glass cloth continuously covers the conductor on the surface side of the insulating layer and the region (513, 514) constituting the gap;
    After making the insulating layer and the prepreg face each other, pressurize one of the insulating layer and the prepreg against the other to cover a portion of the glass cloth that covers the region of the gap. And filling the resin material constituting the resin layer into the region constituting the gap by bending the portion closer to the edge layer side than the portion covering the conductor (S120). Production method.
  9. 　前記樹脂層を構成する樹脂材料を前記間隔を構成する領域内に充填する際には、前記ガラスクロスのうち前記間隔を構成する領域を覆う部位を、前記導体のうち前記絶縁層の反対側端部（５１２ａ、５２２ａ）よりも前記絶縁層側に入れ込む請求項８に記載の多層基板の製造方法。 When the resin material constituting the resin layer is filled in the region constituting the gap, the portion of the glass cloth covering the region constituting the gap is arranged on the opposite end of the conductor to the insulating layer. The method for manufacturing a multilayer substrate according to claim 8, wherein the multilayer substrate is inserted closer to the insulating layer than the portions (512 a, 522 a).
  10. 　前記樹脂層を構成する樹脂材料を前記間隔を構成する領域内に充填する際には、前記間隔を構成する領域に向けて凸となる凸部（１６６ａ）が設けられた金属板（１６６）を、前記プリプレグに対して前記絶縁層の反対側に配置して、前記金属板が前記凸部によって前記プリプレグのうち前記間隔を構成する領域に対応する部位を前記絶縁層側に加圧する請求項８または９に記載の多層基板の製造方法。 When the resin material constituting the resin layer is filled in the region constituting the interval, the metal plate (166) provided with the convex portion (166a) protruding toward the region constituting the interval is provided. The metal plate is arranged on the opposite side of the insulating layer with respect to the prepreg, and the metal plate pressurizes a portion corresponding to a region constituting the interval in the prepreg to the insulating layer side by the convex portion. Or a method for producing a multilayer substrate according to 9.
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