JP2013089745A - Multi-layer printed wiring board and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that it is difficult to improve heat conductivity and insulation reliability of a build up layer concurrently, in a multi-layer printed wiring board having a core layer part and the build up layer formed on the core layer part.SOLUTION: A multilayer printed wiring board 101 has: a core layer 108 formed with first wiring layers 103 protruding on a surface layer; a first insulation layer 102 embedding the first wiring layers 103 on the core layer 108; and metal plating vias 105, each of which connects each first wiring layer 103 with a second wiring layer 104 formed on the first insulation layer 102. A filler 114 exists between a core material 112 included in the first insulation layer 102 and the first wiring layer 103 thereby making a distance between the core material 112 and the embedded first wiring layer 103 equal to or larger than a particle diameter of the filler 114 even when the thickness of the first wiring layer 103 is increased and improving heat conductivity and insulation reliability of a build up layer 109 concurrently.

Description

  The present invention relates to a multilayer printed wiring board having a plurality of insulating layers and having a plurality of wiring layers formed on the main plane and vias electrically connecting the wiring layers.

  In recent years, with the miniaturization and high performance of electronic devices, there is a strong demand for multilayer printed wiring boards capable of mounting semiconductor chips such as LSIs in high density not only for industrial use but also in the field of consumer equipment. . Further, as the function of semiconductors to be mounted increases, the amount of heat generated from the semiconductors increases, and along with narrow adjacent mounting, the increase in semiconductor temperature is a serious problem. For this reason, the demand for countermeasures against heat generation of semiconductors is also important in multilayer printed wiring boards, and the need for high-density wiring multilayer printed wiring boards for countermeasures against heat generation is increasing.

  Here, as a countermeasure against heat generation of the semiconductor in the multilayer printed wiring board, there is a thermal via that does not correspond to electrical connection directly under the semiconductor, but as one effective countermeasure, the thickness of the metal conductor foil used for the wiring layer By increasing the thickness of the multilayer printed wiring board, a method of improving heat transferability in the planar direction of the multilayer printed wiring board and diffusing the generated heat is often used.

  On the other hand, in a multilayer printed wiring board that realizes high-density wiring, it is important that a plurality of wiring layers formed at a fine wiring pitch can be electrically connected with high connection reliability. As an interlayer connection method, there is a method of forming a metal plating conductor or a conductive resin composition in a hole formed in an insulating layer.

  In the multilayer printed wiring board using the conductive resin composition as a means for interlayer connection, a hole is formed in the uncured insulating base material (prepreg) by a laser or the like, and the conductive resin composition is filled in the hole. A metal conductor foil such as copper foil is laminated on both sides of the prepreg. Then, by heating the laminate while applying pressure, the conductive resin composition is cured and electrically connected to the metal conductor foil as the conductive resin cured product, and the prepreg is cured, so that the electrical connection between the wiring layers is achieved. Connection (conductive resin composition) is provided.

  Here, since the conductive resin composition is composed of a metal and a resin, the thermal conductivity is lower than that of a metal plating via formed only by a metal conductor, which will be described later, and heat transferability at the interlayer connection Is low. In addition, since the insulating layer is formed at the same time when the interlayer connection by the conductive resin composition is obtained, there is a need to restrict the resin flow of the prepreg, and thus the thickness of the inner layer copper foil is limited when forming a multilayer. Therefore, the heat transferability by the inner metal foil is limited.

  In a multilayer printed wiring board that uses metal plating vias as a means for interlayer connection, the core layer is formed of a metal layer via an uncured insulating base material (prepreg) in a core layer having a desired wiring circuit formed on both sides or one side. The conductor foil is integrally laminated by heating and pressing processes. Then, a hole is formed at a predetermined position by a carbon dioxide laser or the like, and further, a metal plating conductor is provided thickly by an electroless plating process, further by an electrolytic plating process by chemical and electrical treatment in a liquid, Electrical connection (metal plating via) is provided between the wiring layers. Here, since the metal plating via is formed only by the metal conductor, the heat transferability in the interlayer connection is higher than that of the conductive resin composition. Furthermore, the prepreg heating and pressurizing process and the conductor via formation are separate processes. Therefore, there is no need to restrict the resin flow, and it is possible to use a thick inner layer metal foil as compared with the conductive resin composition. Therefore, it is considered more effective as a multilayer printed wiring board capable of taking measures against heat generation of semiconductors with high density wiring.

  As described above, the insulating layer of the conventional general multilayer printed wiring board is used to obtain the organic resin that forms the insulating layer by thermosetting and mechanical strength (bending strength, thermal expansion suppression, crack strength, etc.). It is generally composed of a core material included and a filler included for reinforcement of flame retardancy and mechanical strength.

  FIG. 8 is an enlarged schematic cross-sectional view of a build-up layer in a conventional multilayer printed wiring board and having a metal plating via connection. FIG. 8 is an enlarged cross-sectional view of a buildup layer of a conventional multilayer printed wiring board (not numbered). The core layer portion formed under the buildup layer 1 is not shown. As shown in FIG. 8, the first wiring layer 2 formed on the core layer portion (not shown) is embedded in the buildup layer 1. And the core material 5. Organic resin A metal plating via 4 connects the first insulating layer (not numbered) made of filler 7 and the like to the second wiring layer 3 formed on the upper surface (or exposed surface) of the buildup layer 1. Has been.

  FIG. 9 is a cross-sectional view illustrating a problem that occurs when the thickness of the first wiring layer embedded in the buildup layer is increased in the conventional multilayer printed wiring board.

  As shown in FIG. 9, the build-up layer 1 has a high-thickness first wiring layer 2 embedded therein, and an insulating layer (not numbered) constituting the build-up layer 1 is used as a reinforcing material. Core material 5, organic resin 6, and filler 7.

  Here, the insulating layer (number is not given) is formed by heating and further pressurizing an uncured insulating base material with an organic resin called a prepreg. This prepreg is formed through a process of drying and semi-curing by impregnating and applying a varnish in which an organic resin and a filler are dispersed in a solvent to a core material. At that time, if air bubbles are present in the varnish or if the wettability between the core material and the varnish is insufficient, the coating is applied between the core material and the core material (gap between multiple fibers or weaves). There is a possibility that voids such as voids 8 are generated between the organic resin and the filler.

  There is a possibility that voids such as voids 8 may remain even after the prepreg is cured by heating and pressing to form an insulating layer (for example, not exposed to the outside, that is, remain as cracks). When drilling with a carbon dioxide laser or drilling, cracks may occur between the core material and the cured organic resin and in the core material itself.

  The remaining voids and cracks themselves naturally lead to a decrease in insulation, and in metal plating via connections involving treatment in chemicals, the voids and cracks (for example, the side portions of via holes) More) There is concern about defects in plating reliability due to the penetration of plating solution.

  In particular, when a woven fabric core material woven with glass fibers is used in the core material of the prepreg from the viewpoint of strength and cost, the interface between the core material and the outside increases, so the organic resin extends to the inside of the core material. In many cases, the components are not filled and voids and cracks remain.

  As a countermeasure against such penetration of the plating solution, in Patent Document 1, glass balls or glass weaves on the hole walls generated when drilling with a laser is performed in a CCL in which a metal conductor foil is laminated on the surface layer of a prepreg and an insulator. We pay attention to cracks between the fabrics and the glass woven fabric itself. And in order to reduce the generation, as a means to efficiently transmit the energy of laser irradiation to the entire insulating layer, heat transfer by the filler is increased, and as a result, the damage of the hole processing is suppressed and the penetration of the plating solution is suppressed. I was doing.

  However, as a countermeasure against heat generation of the semiconductor, in a high-density multilayer board having a metal conductor foil having a constant thickness, unlike the CCL or the like, a first wiring layer having a certain thickness is embedded in the first insulating layer, and The second wiring layer is provided on the opposite surface, and the thickness of the first insulating layer itself is also reduced for higher density wiring, so the distance between the first wiring layer and the second wiring layer is shortened, Along with the narrow pitch wiring, the distance between the metal plating via and the first wiring layer is also shortened.

  Therefore, the distance between the core material 5 sandwiched between the first wiring layer 2 and the second wiring layer 3 and the first and second wiring layers 2 and 3 is reduced, and an insulating layer is formed by a process of heating and pressurizing the prepreg. In doing so, the increase in fluidity causes the insulating organic resin to flow greatly, and the core material 5 directly contacts the first wiring layer 2 and the second wiring layer 3.

  In some cases, the proposal of Patent Document 1 that has been conventionally proposed cannot sufficiently cope with such a problem.

  As described above, in the case of the conventional multilayer printed wiring board, in the buildup layer 1 formed on the surface layer, the first wiring layer 2 increases as the thickness of the first wiring layer 2 embedded in the buildup layer 1 increases. There is an increased possibility that 2 and the core material 5 are in contact with each other and affect the insulation reliability.

Japanese Patent No. 4433651

  In the case of the conventional multilayer printed wiring board disclosed in Patent Document 1, when the thickness of the wiring embedded in the buildup layer is increased in the buildup layer, it contacts the core material constituting the buildup layer. Or, the insulation reliability may be affected.

  In order to solve the above problems, the present invention provides a multilayer printed wiring board having a core layer and a buildup layer, wherein the buildup layer includes a first insulating layer including a core material, an organic resin, and a filler. A first wiring layer embedded in the first insulating layer, a second wiring layer formed on a surface of the first insulating layer opposite to the surface in contact with the first wiring layer, the first and second layers Containing between the wiring layers has at least one layer composed of metal plating vias, and the thickness of the first wiring layer is 25% or more and 60% or less of the thickness of the first insulating layer. The amount is 10 vol% or more and 30 vol% or less of the first insulating layer, the content of the filler is 30 vol% or more and 60 vol% or less of the first insulating layer, and the core material and the first wiring layer The filler is present between the core material and the first wiring layer. In which the short-range and multi-layer printed wiring board is the particle size or less of the filler.

  According to the present invention, the build-up layer provided on the surface layer of the core layer, the build-up layer formed by embedding the first wiring layer, the first wiring layer embedded in the build-up layer, and the build-up layer Since the contact with the core material constituting the layer can be suppressed, it is possible to improve both the thermal conductivity of the buildup layer and the insulation reliability thereof.

(A) and (B) are schematic sectional views of the multilayer printed wiring board of the first embodiment. (A) and (B) are schematic sectional views of the multilayer printed wiring board of the first embodiment. Sectional drawing which expands and explains a part of buildup layer typically in a section (A), (B) is sectional drawing explaining an example of the manufacturing method of a multilayer printed wiring board both (A), (B) is sectional drawing explaining an example of the manufacturing method of a multilayer printed wiring board both (A), (B) is sectional drawing explaining an example of the manufacturing method of a multilayer printed wiring board both Sectional drawing explaining the cause of the insulation fall in the comparative example Expanded schematic cross-sectional view of a build-up layer in a conventional multilayer printed wiring board, which has a metal plating via connection Sectional drawing explaining the problem which generate | occur | produces when the thickness of the 1st wiring layer embedded in the buildup layer becomes thick in the conventional multilayer printed wiring board

(Embodiment 1)
In the first embodiment, an example of the multilayer printed wiring board of the present invention will be described with reference to FIG. 1A and 1B are cross-sectional views of the multilayer printed wiring board of the present invention described in the first embodiment, both having a core layer and a buildup layer.

  As shown in FIGS. 1A and 1B, a multilayer printed wiring board 101 according to Embodiment 1 includes a core layer 108 and one or more build-up layers 109 formed on both surfaces of the core layer 108. Have.

  The buildup layer 109 has one or more insulating layers made of the first insulating layer 102 and the like, and on the core layer 108 side, a first wiring layer 103 embedded in the first insulating layer 102 and a core layer And a second wiring layer 104 formed on a different surface from the 108 side. A metal plating via 105 for electrically connecting the first wiring layer 103 and the second wiring layer 104 is provided.

  In FIG. 1A, the core layer 108 in the multilayer printed wiring board 101 has the first wiring layer 103 formed on the main plane on the buildup layer 109 side. The core layer 108 has the third wiring layer 110 on the inner side through the second insulating layer 106, and the through-hole plated conductor 107 conducts electrical conduction between the wiring layers.

  FIG. 1B is a cross-sectional view illustrating the case where the buildup layer 109 is formed using a multilayer insulating layer. As shown in FIG. 1B, the insulating layer included in the build-up layer 109 may be a plurality of layers.

  Next, an application example of another multilayer printed wiring board 101 will be described with reference to FIGS. As shown in FIG. 2A, the core layer 108 may include a metal plating via 105a in the buildup layer 109 and a metal plating via 105b in the core layer 108. Alternatively, as illustrated in FIG. 2B, the via may have a conductive resin composition 111.

  A conductive resin composition 111 illustrated in FIG. 2B includes a conductive filler and an organic resin. As the conductive filler constituting the conductive resin composition 111, for example, metal particles such as gold, silver, copper, palladium, nickel, or alloy particles can be used. Copper is particularly preferable because of its high conductivity and low migration. As the organic resin, basically the same resin as the organic resin used for the first or second insulating layer can be used, and the same effect can be obtained. Further, when a liquid resin is used at room temperature (for example, 20 to 25 ° C.), the conductive resin composition 111 (so-called conductive paste) can be produced without a solvent.

  In FIGS. 1A, 1B, 2A, and 2B, the first wiring layer 103 and the second wiring layer 104 are made of an electrically conductive material such as a metal conductor foil 115 or a conductive resin. It consists of the composition 111. In particular, it is preferable to use a copper foil in terms of conductivity, thermal conductivity, and cost. When using copper foil, it is desirable to roughen the surface in contact with the insulating layer in order to improve the adhesion between the first insulating layer 102 and the second insulating layer 106. Also, copper foil with a copper foil surface that has been subjected to a coupling treatment or a copper foil surface that has been plated with tin, zinc, or nickel is used to improve adhesion to the insulating layer and further improve oxidation resistance. It is useful to do.

  Next, how the first wiring layer 103 embedded in the first insulating layer 102 is prevented from contacting the core material 112 in the buildup layer 109 of the present invention will be described with reference to FIG.

  FIG. 3 is a cross-sectional view schematically illustrating a part of the buildup layer 109 in an enlarged manner.

  As shown in FIG. 3, the first wiring layer 103 and the second wiring layer 104 formed on both surfaces of the first insulating layer 102 in the multilayer printed wiring board 101 of the first embodiment are connected by the metal plating via 105. . The first wiring layer 103 is embedded in the first insulating layer 102 constituting the buildup layer 109. The first insulating layer 102 includes a core material 112 serving as a reinforcing material, an organic resin 113 and a filler 114.

  As shown in FIG. 3, in the buildup layer 109 of the present embodiment, a filler having excellent electrical insulation between the first wiring layer 103 embedded in the buildup layer 109 and the core material 112. 114 is present. The filler 114 functions as a kind of insulating spacer that insulates between the first wiring layer 103 and the core material 112, thereby preventing contact between the first wiring layer 103 and the core material 112. In addition, the insulation of the first insulating layer 102 is enhanced.

  1A, 1B, 2A, 2B, FIG. 4 and FIG. 5 to be described later, the filler 114 and the core material 112 included in the first insulating layer 102 are illustrated. Absent.

  In FIG. 3, the thickness of the first wiring layer 103 is preferably 25% or more and 60% or less of the thickness of the first insulating layer 102. When the thickness is less than 25%, the heat spread effect by the first wiring layer 103 may be affected. If it is 60% or more, the patterning of the first wiring layer 103 becomes special and the cost may increase. Further, the content of the core material 112 is desirably 10 vol% or more and 30 vol% or less of the first insulating layer 102. Further, the content of the filler 114 is desirably 30 vol% or more and 60 vol% or less of the insulating layer. Further, it is desirable that the filler 114 be present between the core material 112 and the first wiring layer 103, and the presence of the filler 114 makes the shortest distance between the core material 112 and the first wiring layer 103 equal to or greater than the particle size of the filler 114. Thus, even when the thickness of the first wiring layer 103 is increased, the contact between the core material 112 and the first wiring layer 103 can be prevented. As described above, in the present invention, by increasing the content of the filler 114, the filler 114 having electrical insulation prevents contact between the core material 112 and the first wiring layer 103 (for example, the filler 114 is a kind of insulating spacer. To contribute as). In addition, when content of the filler 114 is less than 30 vol% of an insulating layer, the contact prevention effect of the core material 112 and the 1st wiring layer 103 may be affected. If it exceeds 60 vol%, the embedding property of the first wiring layer 103 may be affected. In addition, when the thickness of the first wiring layer 103 is less than 25% of the thickness of the first insulating layer 102, the heat dissipation property (heat spread property) through the first wiring layer 103 may be affected. Moreover, when the thickness of the 1st wiring layer 103 exceeds 60% of the thickness of the 1st insulating layer 102, the 1st wiring layer 103 and the core material 112 may contact. Moreover, when the content rate with respect to the 1st insulating layer 102 of the core material 112 is less than 10 vol%, the intensity | strength of the buildup layer 109 may be affected. Moreover, when it exceeds 30 vol%, the 1st wiring layer 103 and the core material 112 may contact.

  In addition, the contact between the core material 112 and the first wiring layer 103 by the filler 114 is not limited to the gap between the core material 112 but also the gaps between a plurality of glass fibers constituting the core material 112 or the core material 112 and the core material. The effect of preventing the penetration of the plating solution or the like into the gap with the organic resin 113 surrounding 112 is also obtained.

  Here, the resin material constituting the organic resin 113 is not particularly limited. For example, a thermosetting resin, a thermoplastic resin, a photocurable resin, or the like can be used, and an epoxy resin system or a polyimide resin system can be used. , Triazine resin system, phenol resin system, isocyanate resin system, melamine resin system and modified resins of these resins. Moreover, you may use various hardening | curing agents and hardening accelerators as needed other than mixing the said various resin 2 or more types. If an epoxy resin, a polyimide resin, a phenol resin, an isocyanate resin, or the like is used, the heat resistance of the first insulating layer 102 or the like can be increased. Epoxy resins are also suitable for multilayer printed wiring boards because of their properties such as strength and adhesion. When a curing agent is used for the resin, it is not particularly limited. For example, when used for an epoxy resin, an amine-based or phenol-based curing agent can be used, and the curing agent is used alone. In addition, a plurality of types can be used in combination, and the type and amount thereof are not limited and can be appropriately determined. In the case of using an accelerator for the resin, it can be used in a variety of manners similar to the curing agent described above. Specifically, imidazole compounds, organic phosphorus compounds, amines, ammonium salts, and the like are used. Two or more kinds may be used in combination. Also, rubber or thermoplastic resin may be added.

  The organic resin 113 is desirably soluble in a solvent in order to facilitate the impregnation and coating of the core material 112.

  The first insulating layer 102 may further contain a wetting and dispersing agent, a colorant, a coupling agent, a release agent, or the like. When the wetting and dispersing agent is included, the dispersion of the filler 114 in the organic resin 113 can be made uniform. If the insulating layer is colored with a colorant, the automatic recognition device can be easily used. When the coupling agent is included, the adhesive strength between the organic resin 113 and the filler 114 is improved, and the insulating property of the insulating layer can be increased. When a release agent is included, the releasability from the mold is improved, so that productivity can be improved.

  Here, the metal plating via 105 can be selected from materials having electrical conductivity such as copper, solder, and gold, and is formed of, for example, copper produced by a combination of electroless plating and electrolytic plating. . In the present invention, even if these metal plating vias 105 are formed in the buildup layer, even if the thickness of the wiring embedded in the buildup layer is increased, the core material constituting the buildup layer There is no problem when plating.

(Embodiment 2)
In the second embodiment, an example of a method for manufacturing the multilayer printed wiring board 101 described in the first embodiment will be described.

  An example of a method for manufacturing the multilayer printed wiring board 101 will be described in detail with reference to the drawings.

  4A, 4B, 5A, B), 6A, and 6B are cross-sectional views illustrating an example of a method for manufacturing a multilayer printed wiring board.

  First, the core layer 108 is prepared. Thereafter, the core layer 108 is disposed as shown in FIG. 4A, and an uncured insulator (prepreg 119) that forms the first insulating layer after curing is disposed on both surfaces thereof. Further, the metal conductor foil 115 is disposed on each outer surface of the first insulating layer 102, and then heated and pressed to soften the prepreg 119 and embed the first wiring layer 103 in the first insulating layer 102. . Thereafter, by continuing heating and pressurization, the prepreg 119 is cured to form the first insulating layer 102, and a predetermined molded body 116 is formed. The heating and pressurizing conditions are not particularly limited, but the organic resin 113 (shown in FIG. 3 described above but not shown in FIG. 4) contained in the prepreg 119 (first insulating layer 102) is softened, and further, The amount of heat for curing needs to be added.

  Thus, as shown in FIG. 4B, a molded body 116 formed by integrating these members is formed.

  After that, as shown in FIG. 5A, the metal conductor foil 115 is partially removed according to the position where the interlayer connection is formed. As the method, after forming a photoresist film on the surface of the metal conductor foil 115 of the molded body 116, the photoresist film is exposed through a photomask and developed to pattern the photoresist. Thereafter, the foil other than the resist pattern is etched, the metal conductor foil 115 at the position where the interlayer connection is formed is partially removed, and the unnecessary photoresist film is further removed. A liquid resist or film can be used for forming the photoresist film.

  Thereafter, as shown in FIG. 5B, a non-through hole 117 is formed in a portion where the interlayer connection is formed by a carbon dioxide gas laser at the removed portion.

  Thereafter, as shown in FIG. 6A, the metal plating 118 is applied on the non-through holes 117 and the metal conductor foil 115 to form the molded body 116. Thereafter, if necessary, a step treatment by etching (a treatment peculiar to the wiring board) is performed so that the wiring thickness with the metal conductor foil 115 formed by the metal plating 118 becomes a thickness required for the first wiring layer 103. Do. Thereafter, a photoresist film is formed on the surface of the metal conductor foil 115 after further processing. After that, the second wiring layer 104 is formed as shown in FIG. 6B by using the same process as the patterning described in FIG. 5B.

  By repeating such a multilayering process, the first wiring layer 103 is embedded in the first insulating layer 102 having the metal plating via 105 as the interlayer connection, and the metal plating via 105 is used as the interlayer connection of the first insulating layer 102. The multilayer printed wiring board 101 is formed.

  4A and 4B, when the first wiring layer 103 is buried by the first insulating layer 102 as shown in FIG. 3 described above, the thickness of the first wiring layer 103 is the first thickness. It is useful that the thickness of one insulating layer 102 is 25% or more and 60% or less and the content of the core material 112 is 10 vol% or more and 30 vol% or less of the first insulating layer 102. Furthermore, when the content of the filler 114 is 30 vol% or more and 60 vol% or less of the insulating layer, the filler 114 exists between the core material 112 and the first wiring layer 103, and the core material 112 and the first wiring layer are present. It is possible to make the shortest distance to 103 greater than the particle size of the filler 114. As a result, even when the thickness of the first wiring layer 103 is increased, the contact between the core material 112 and the first wiring layer 103 can be prevented. Further, in the metal plating step described with reference to FIGS. 6A and 6B, the plating solution is prevented from entering the first insulating layer 102 and the like, and the reliability is improved.

(Embodiment 3)
In the third embodiment, optimization of the constituent members of the multilayer printed wiring board 101 described in the first and second embodiments will be described in detail.

  In order to evaluate the insulation in the multilayer printed wiring board 101, in order to evaluate the insulation reliability between the metal plating via 105 and the first wiring layer 103 adjacent to the metal plating via 105 but not directly conductively connected, A first interlayer connection pattern formed from the second wiring layer 104, the first wiring layer 103, and the metal plating via 105 was formed. Further, 500 first wiring patterns were formed in the first wiring layer 103 so that the closest distance was 50 μm, though not directly conductively connected to the interlayer connection pattern.

  Furthermore, in order to evaluate the insulation reliability between the wiring layers sandwiching the first insulating layer 102 (between the first wiring layer 103 and the second wiring layer 104), various types that are not directly connected by the metal plating via 105, Evaluation wiring patterns (not shown) were provided so as to correspond to the first wiring layer 103 and the second wiring layer 104, respectively.

  Here, the evaluation pattern is set so that the line width of the second and third wiring patterns (both wiring patterns for evaluating reliability, etc.) is 500 μm, and the length of the tangent to each other for evaluating reliability is 20 cm. 500 pieces were formed.

  The multilayer printed wiring board obtained by these methods was then subjected to surface finishing treatment such as gold plating on the surface layer of the multilayer printed wiring board on the solder resist and further on the outermost second wiring layer 104 as necessary.

  Next, the present invention will be described more specifically. The scope of the present invention is not construed as being limited in any way by the contents of the embodiment.

(Description of the core layer forming process)
First, the core layer forming process will be described in detail.

  Using CCL (CCL is a name unique to a wiring board) having a thickness of 100 μmt as the second insulating layer and 18 μmt of copper foil laminated as the third wiring layer on both sides, a resist film is pasted on both sides and exposed. And it developed, the wiring pattern was formed by the etching, and the double-sided wiring board was produced. A semi-cured second insulating layer 106 material was laminated on the upper and lower sides of the double-sided wiring board thus formed, and a copper foil corresponding to the first wiring layer 103 was further laminated, followed by heating press.

  Thereafter, a through hole was created with a drill at a predetermined interlayer conductive position, and copper plating was applied to the through hole in an electroless plating and electrolytic plating process to form a through hole plated conductor 107.

  Thereafter, a stepping process is performed on the entire surface of the copper wiring layer so that the first wiring layer 103 has a predetermined film thickness, if necessary, and then a resist film is attached, exposed and developed, and etched to form the first wiring layer 103. A pattern of one wiring layer 103 was formed. Further, the through hole was filled with an epoxy resin to form a four-layer through-hole substrate as the core layer 108.

Here, in the second insulating layer 106 used for the core layer 108, the thickness is 100 μmt, the core material 112 is a glass woven fabric (IPC standard 2116), and the organic resin 113 is a thermosetting epoxy resin. As the filler 114, Al (OH) ₃ having an average particle diameter of 0.8 μm was used.

  The volume ratio of the glass woven fabric, the organic resin 113, and the filler 114 in the second insulating layer was 48 vol%, 8 vol%, and 44 vol%.

(Explanation of build-up layer formation process)
Next, the process for forming the buildup layer will be described in detail.

  This four-layer through-hole substrate is used as the core layer 108, and a semi-cured insulating material (prepreg 119) for forming the first insulating layer 102 is laminated on both surfaces of the core layer 108, and further corresponds to the first wiring layer 103. The copper foil was laminated and the heating and pressurizing steps were performed. Thereafter, a resist film was attached, exposed and developed, and the copper foil at a predetermined interlayer connection position was removed by etching, and a non-through hole with a hole diameter of 120 μm was formed at the interlayer connection position with a carbon dioxide laser.

  The non-through hole was subjected to copper plating in an electroless plating and electrolytic plating process, and a metal conductor was formed in a filled via shape to obtain a metal plating via 105.

  Thereafter, a stepping process was performed on the entire surface of the copper wiring layer so that the first wiring layer 103 had a predetermined thickness as needed. Thereafter, a resist film was attached, exposed and developed, and a wiring pattern was formed by etching, whereby a multilayer printed wiring board 101 was obtained.

  Further, a material such as prepreg 119 was again laminated on both surfaces, and a copper foil corresponding to the second wiring layer 104 was further laminated. Thereafter, the heating press, laser drilling, plating process, and wiring pattern process are repeated, and the four-layer TH substrate of Example 1 is used as the core layer, and the two-layered build-up layer 109 is provided on the surface layer. The multilayer printed wiring board of FIG. 1 (B) having 8 layers was formed.

  Here, for the first insulating layer 102 and the first wiring layer 103, the multilayer printed wiring board 101 was formed under the conditions shown in the following examples and comparative examples.

  Hereinafter, as (Experiment 1), a prototype (Example 1) will be described as Example 1 of the present invention.

(Explanation of Experiment 1: Comparative Experiment on Example 1 and Comparative Examples 1 and 2)
The substrate for evaluation in (Example 1) was prepared as follows. First, the first insulating layer 102 has a thickness of 70 μmt, the core material 112 uses a glass woven fabric (IPC standard 1037), the organic resin 113 uses a thermosetting epoxy resin, and the filler 114 has an average. Al (OH) ₃ having a particle diameter of 5 μm and MgO having an average particle diameter of 3 μm were combined in a ratio of Al (OH) ₃ : MgO = 1: 2. Moreover, the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the 1st insulating layer 102 was 16 vol%, 48 vol%, and 36 vol%. At this time (Example 1), the ratio of the filler 114 to the total of the organic resin 113 and the filler 114 excluding the core material 112 (glass woven fabric) is approximately 57 vol%. The thickness of the first wiring layer 103 is 35 μm made of Furukawa Electric copper foil at the time of lamination, and the thickness is increased by the plating process, but is adjusted by the entire etching process, and the thickness of the first wiring layer 103 is 40 μm as the first insulating layer. Embedding was performed by 102.

  Next, as comparative examples, substrates for evaluation of (Comparative Example 1) to (Comparative Example 3) were prepared as follows.

The substrate for evaluation of (Comparative Example 1) was prepared as follows. First, the thickness of the first insulating layer 102 was 70 μmt, and the core material 112 was a glass woven fabric (IPC standard 1280). The organic resin 113 was a thermosetting epoxy resin, and the filler 114 was Al (OH) ₃ having an average particle diameter of 5 μm. Moreover, the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the 1st insulating layer 102 was 35 vol%, 10 vol%, and 55 vol%. At this time, the ratio of the filler 114 to the total of the organic resin 113 and the filler 114 excluding the core material 112 (glass woven fabric) was about 15 vol%.

  The thickness of the 1st wiring layer 103 was 12 micrometers by the copper foil thickness at the time of lamination | stacking, and the whole surface etching process after plating.

  The substrate for evaluation of (Comparative Example 2) was prepared as follows. First, the first insulating layer 102 is the same as that of (Comparative Example 1), and the thickness of the first wiring layer 103 is evaluated for (Example 1) by the copper foil thickness at the time of lamination and the entire etching process after plating. The thickness was 40 μm, the same as the substrate.

  The substrate for evaluation of (Comparative Example 3) was prepared as follows. First, the thickness of the first insulating layer 102 was 70 μmt, and the same glass woven fabric (IPC standard 1037) as that of the core material 112 (Example 1) was used. Moreover, as the organic resin 113 and the filler 114, the ratio of the filler 114 to the total of the organic resin 113 and the filler 114 excluding the component and the core material 112 (glass woven fabric) was the same as that of (Comparative Example 1). At that time (Comparative Example 3), the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the first insulating layer 102 was 16 vol%, 13 vol%, and 71 vol%. The thickness of the first wiring layer 103 was set to 40 μm, which was the same as that in Example 1, by the thickness of the copper foil at the time of lamination and the entire etching process after plating.

  In the evaluation substrates of (Example 1), (Comparative Example 1), and (Comparative Example 2) created above, the first interlayer connection pattern for evaluation, the first wiring pattern for evaluation, and the evaluation substrate The insulation reliability of the second wiring pattern and the third wiring pattern for evaluation was evaluated, and the presence or absence of a short circuit was examined.

  Further, a semiconductor is mounted on each of the substrates of (Example 1), (Comparative Example 1), and (Comparative Example 2), and the temperature rise during operation is based on the temperature rise of the substrate of (Comparative Example 1). And the rate of temperature rise of each substrate relative to that was compared.

  In the substrate of (Comparative Example 1), the temperature rise rate R is T0 as the initial operating temperature, T1 as the semiconductor temperature when the temperature rise reaches the steady state, and the temperature rise of each substrate is in the steady state. Assuming that the semiconductor temperature when the temperature is reached is T2, R = (T2−T0) / (T1−T0) × 100 (%).

  Here, the configurations of the first insulating layer 102 and the first wiring layer 103 used for the buildup layer 109 of each of the eight-layer substrates of (Example 1), (Comparative Example 1), and (Comparative Example 2), and the insulation The table below summarizes the reliability evaluation and the semiconductor temperature rise evaluation.

  In [Table 1], in the semiconductor temperature rise 100 shown in (Comparative Example 1), the semiconductor temperature rises to 90 ° C. after 45 minutes at the same external temperature T0 = 25 ° C. as the initial operating temperature. It was a level that raised concerns about the guarantee.

  On the other hand, when the thickness of the first wiring layer 103 is increased to 40 μm as in (Comparative Example 2), the numerical value is reduced to 90 in comparison with (Comparative Example 1), that is, the semiconductor temperature rise is suppressed by 10%. In other words, it was at a level that could afford a margin for guaranteeing semiconductor operation.

  However, in (Comparative Example 2), since the thickness of the first wiring layer 103 occupies about 57% of the thickness of the first insulating layer 102, the thickness of the core material 112 occupying 35 vol% in the first wiring layer 103 as a volume ratio is around 50 μm. When a certain glass woven fabric (IPC standard 1280) is used, the glass woven fabric (core material 112) comes into contact with the first wiring layer 103 and the second wiring layer 104 as shown in FIG. This was thought to be due to a drop in reliability.

  In response to such a problem, in the case of using a glass woven fabric (IPC standard 1037) in which only the volume ratio of the glass woven fabric is reduced to 16 vol% as in (Comparative Example 3), the glass woven fabric is thickened to prevent heat generation. Even when the first wiring layer 103 is used, it is possible to secure a distance at which the glass woven fabric (core material 112) and the first wiring layer 103 do not contact each other. However, as shown in FIG. 7 to be described later, in the heating and pressurizing steps when the first wiring layer 103 is embedded in the first insulating layer 102, the organic resin flows, and the glass woven fabric (core material 112) is also formed. As a result, it may move and contact the first wiring layer 103. As a result, as shown in [Table 1], in (Comparative Example 3), it seems that the insulating property was lowered.

  Next, the cause of the decrease in the insulation of Comparative Example 3 will be considered with reference to FIG. FIG. 7 is a cross-sectional view for explaining the cause of the decrease in insulation in the comparative example.

  FIG. 7 particularly shows a case where the connection between the first insulating layers of the buildup layer is a metal plating via, and the thickness of the core material in the first insulating layer is reduced and the thickness of the first wiring layer is increased. The problem that occurs in the case is explained.

  For example, in (Comparative Example 3), as shown in FIG. 7, the core material 112 made of glass woven fabric or the like is in contact with, for example, the first wiring layer 103 or the second wiring layer 104 as indicated by an arrow 120. It is considered that the insulating property has decreased.

  On the other hand, in the case of each prototype of the present invention, the filler 114 is always present between the first insulating layer 102 and the core material 112 as shown in FIG. 7 and the core material 112 are prevented from contacting each other, and the problem shown in FIG. 7 does not occur.

  That is, as shown in (Example 1) of the present invention, when the volume ratio of the glass woven fabric is reduced to 16 vol% and the filler 114 is added to the volume ratio of 48 vol%, the above-described FIG. As described above, it is possible to secure a distance at which the glass woven fabric (core material 112) and the wiring layer do not contact each other. Furthermore, when the organic resin 113 flows in the heating and pressurizing steps, the filler 114 inhibits the flow and is sandwiched between the glass woven fabric (core material 112) and the first wiring layer 103. The distance between the glass woven fabric (core material 112) and the first wiring layer 103 is at least as large as the particle size of the filler 114, and the contact between the glass woven fabric (core material 112) and the first wiring layer 103 is as a result. It can be seen that the penetration of the plating solution or the like is suppressed, and the insulation is ensured.

  Here, the ratio of the filler 114 to the total of the organic resin 113 excluding the glass woven fabric and the filler 114 in Example 1 is about 57 vol%. The rate approaches close-packing. It can be easily inferred that the organic resin 113 is approaching a shape that exists only between the filler 114 and the filler 114, and depending on this filling state, the glass woven fabric (core material 112) and the wiring layer in the heating and pressurizing steps It can be inferred that this leads to inhibition of contact.

  Furthermore, in (Example 1), the amount of the filler 114 having higher thermal conductivity than that of the organic resin 113 is increased, so that the thermal conductivity of the entire first insulating layer 102 is improved, and the temperature rise of the semiconductor is further suppressed. The effect is seen. As a result, as shown in [Table 1], it is needless to say that a multilayer printed wiring board that can further suppress the temperature rise of the semiconductor and ensure insulation reliability can be obtained.

  Next, based on the structure of (Example 1), further, as (Experiment 2), the results of experiments on the application of the present invention are shown.

(Explanation of Experiment 2: An example of an experimental result when the thickness of the first insulating layer 102 is changed)
First, the thickness of the 1st wiring layer 103 was changed and the board | substrate for evaluation used as (Example 2), (Example 3), (Comparative Example 4), and (Comparative Example 5) was produced.

  An evaluation substrate to be (Example 2) as an example of the present invention was prepared, and an evaluation substrate to be (Comparative Example 4) and (Comparative Example 5) was prepared as a comparative example to the present invention.

  The substrate for evaluation to be (Example 2) was prepared as follows. First, the first insulating layer 102 is the same as (Comparative Example 1), and the thickness of the first wiring layer 103 is set to 18 μm by the copper foil thickness at the time of lamination and the entire etching process after plating.

  The substrate for evaluation to be (Example 3) was prepared as follows. First, the first insulating layer 102 is the same as (Comparative Example 1), and the thickness of the first wiring layer 103 is set to 35 μm by the copper foil thickness at the time of lamination and the entire etching process after plating.

  The substrate for evaluation to be (Comparative Example 4) was prepared as follows. First, the first insulating layer 102 was the same as (Comparative Example 1), and the thickness of the first wiring layer 103 was set to 12 μm by the thickness of the copper foil during lamination and the entire etching process after plating.

  The substrate for evaluation to be (Comparative Example 5) was prepared as follows. First, the first insulating layer 102 is the same as (Comparative Example 1), and the thickness of the first wiring layer 103 is set to 50 μm by the copper foil thickness at the time of lamination and the entire etching process after plating.

  Next, the build of the 8-layer board which becomes the board for evaluation used as (Example 1) to (Example 3) which is an example of the invention of the present application, and (Comparative example 4) and (Comparative example 5) which are comparative examples. Table 1 below summarizes the configurations of the first insulating layer 102 and the first wiring layer 103 used for the up layer 109, the evaluation of the insulation reliability, and the evaluation of the semiconductor temperature rise. In [Table 2], the unit of the semiconductor temperature rise is (° C.).

  From [Table 2], when the thickness of the first wiring layer 103 of (Comparative Example 4) is 12 μm, the semiconductor temperature rise is 95% and 5% even if the volume fraction of the filler 114 of the first insulating layer 102 is increased. It is considered to be insufficient because only the degree can be suppressed. On the other hand, if the thickness of the first wiring layer 103 is increased as in (Embodiment 1) to (Embodiment 3), the increase in the semiconductor temperature can be suppressed to 91% or less and almost 9% or less. Yes.

  However, in the case where the thickness of the first wiring layer 103 occupies 71% of the thickness of the first insulating layer 102 as in (Comparative Example 5), the first wiring layer 103 is embedded in the heating and pressurizing steps. Some defects will occur. Furthermore, it has been impossible to obtain adhesion with the core layer in the reflow process when mounting semiconductor components. As a result, the insulation test and the semiconductor temperature rise could not be evaluated (not evaluated).

  Further, in (Comparative Example 4), the semiconductor temperature rise is as high as 95 ° C., so that the cooling effect on the semiconductor is low.

  As shown in [Table 2], in (Example 1) to (Example 3) of the present invention, the occurrence of short circuit was “None” in the insulation reliability test. Also, the semiconductor temperature rise was 85 ° C. to 91 ° C., and it was confirmed that there was a semiconductor cooling effect.

  Furthermore, in order to investigate the application range of the present invention, as Experiment 3, it becomes further an example (Example 4), (Example 5), becomes a comparative example of the present invention (Comparative Example 6), (Comparative Example 7). It was created.

(Explanation of Experiment 3: An example when the ratio of the core material in the first insulating layer 102 is changed)
From the structure of (Example 1), the ratio of the core material 112 in the first insulating layer 102 is changed to be (Example 4), (Example 5), (Comparative Example 6), and (Comparative Example 7). Each substrate for evaluation was prepared.

  The substrate for evaluation to be (Example 4) was prepared as follows. First, the thickness of the first wiring layer 103 is the same as that in Example 1, and the filler with respect to the thickness of the first insulating layer 102 and the total of the organic resin 113 and the filler 114 excluding the components of the organic resin 113 and the filler 114 and the glass woven fabric. The ratio of 114 was also the same as (Example 1). Furthermore, a glass woven fabric (IPC standard 1027) was used only for the core material 112 of the first insulating layer 102. In this manner (Example 4), the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the first insulating layer 102 was set to 13 vol%, 50 vol%, and 37 vol%.

  A substrate for evaluation to be (Example 5) was prepared as follows. First, the thickness of the first wiring layer 103 is the same as that in Example 1, and the filler with respect to the thickness of the first insulating layer 102 and the total of the organic resin 113 and the filler 114 excluding the components of the organic resin 113 and the filler 114 and the glass woven fabric. The ratio of 114 was also the same as (Example 1). Only the core material 112 of the first insulating layer 102 was made of glass woven fabric (IPC standard 1067).

  As a result, the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the first insulating layer 102 was 20 vol%, 46 vol%, and 34 vol%.

  The substrate for evaluation to be (Comparative Example 6) was prepared as follows. The thickness of the first wiring layer 103 is the same as that of the first embodiment, and the filler 114 with respect to the thickness of the first insulating layer 102 and the total of the organic resin 113 and the filler 114 excluding the components of the organic resin 113 and the filler 114 and the glass woven fabric. The ratio was also the same as in (Example 1). Only the core material 112 of the first insulating layer 102 was made of glass woven fabric (IPC standard 1010). Thus (Comparative Example 6), the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the first insulating layer 102 was 8 vol%, 52 vol%, and 40 vol%.

  A substrate for evaluation to be (Comparative Example 7) was prepared as follows. First, the thickness of the first wiring layer 103 is the same as that in Example 1, and the filler with respect to the thickness of the first insulating layer 102 and the total of the organic resin 113 and the filler 114 excluding the components of the organic resin 113 and the filler 114 and the glass woven fabric. The ratio of 114 was also the same as (Example 1). Only the core material 112 of the first insulating layer 102 was made of glass woven fabric (IPC standard 1280). In (Comparative Example 7), the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the first insulating layer 102 was set to 35 vol%, 37 vol%, and 28 vol%.

  Here, the build-up layers of the respective 8-layer substrates, which are evaluation substrates to be (Example 1), (Example 4), (Example 5), (Comparative Example 6), and (Comparative Example 7) Table 1 below summarizes the configurations of the first insulating layer 102 and the first wiring layer 103 used in 109, the evaluation of the insulation reliability, and the evaluation of the semiconductor temperature rise.

  From [Table 3], since the thickness of the first wiring layer 103 is 40 μm and the ratio of the filler 114 of the first insulating layer 102 is 37 vol% or more in any substrate, the temperature rise of the semiconductor is the maximum However, it is suppressed to 87%. However, in the case where the core material 112 (glass woven fabric) occupies as much as 35 vol% of the first insulating layer 102 as in (Comparative Example 7), a defect occurs in the insulating property despite the filling of the filler 114. It has been.

  Further, as in (Comparative Example 6), when the core material 112 (glass woven fabric) is present only in 8 vol% of the first insulating layer 102, there is no problem in insulation reliability and a rise in the temperature of the semiconductor. The mechanical strength of the base material is reduced, and in the heat test after component mounting: -45 ° C (30 minutes) ⇔ 125 ° C (30 minutes), the occurrence of part negotiations due to the decrease in the solder life occurs. There is a problem in use.

  On the other hand, as shown in [Table 3], (Example 1), (Example 4), and (Example 5) of the present invention showed no occurrence of a short circuit in the insulation reliability test. Further, the increase in semiconductor temperature was 84 ° C. to 85 ° C., and it was confirmed that there was a semiconductor cooling effect.

(Explanation of Experiment 4: An example of an experimental result when the ratio of the filler 114 is changed)
Next, as Experiment 4, the ratio of the filler 114 in the first insulating layer 102 is changed from the structure of (Example 1), and Examples (Example 6) and (Example 7) of the present invention are applied. A substrate for evaluation, which is a comparative example of the invention (Comparative Example 8) and (Comparative Example 9), was prepared.

  A substrate for evaluation to be (Example 6) was prepared as follows. First, as the first insulating layer 102, the thickness and the core material 112 were the same as those in (Example 1). The compositions of the organic resin 113 and the filler 114 were also the same as in (Example 1). On the other hand, the filling amount of the filler 114 was changed, and the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the first insulating layer 102 was set to 16 vol%, 34 vol%, and 50 vol%.

  At this time, the ratio of the filler 114 to the total of the organic resin 113 and the filler 114 excluding the core material 112 (glass woven fabric) was approximately 40 vol%.

  The thickness of the first wiring layer 103 was set to 40 μm as in (Example 1), and the first insulating layer 102 was embedded.

  A substrate for evaluation to be (Example 7) was prepared as follows. First, as the first insulating layer 102, the thickness and the core material 112 were the same as those in (Example 1). The compositions of the organic resin 113 and the filler 114 were also the same as (Example 1). On the other hand, the filling amount of the filler 114 was changed, and the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the first insulating layer 102 was set to 16 vol%, 59 vol%, and 25 vol%.

  At this time, the ratio of the filler 114 to the total of the organic resin 113 and the filler 114 excluding the core material 112 (glass woven fabric) is approximately 70 vol%.

  The thickness of the first wiring layer 103 was set to 40 μm as in (Example 1), and the first insulating layer 102 was embedded.

  The substrate for evaluation to be (Comparative Example 8) was prepared as follows. First, as the first insulating layer 102, the thickness and the core material 112 were the same as in (Example 1), and the compositions of the organic resin 113 and the filler 114 were also the same as in (Example 1). On the other hand, the filling amount of the filler 114 was changed, and the volume ratio of the core material 112 (glass woven fabric), the filler 114, and the organic resin 113 in the first insulating layer 102 was set to 16 vol%, 25 vol%, and 59 vol%.

  At this time, the ratio of the filler 114 to the total of the organic resin 113 and the filler 114 excluding the core material 112 (glass woven fabric) was approximately 30 vol%.

  The thickness of the first wiring layer 103 was set to 40 μm as in (Example 1), and the first insulating layer 102 was embedded.

  A substrate for evaluation to be (Comparative Example 9) was prepared as follows. First, as the first insulating layer 102, the thickness and the core material 112 were the same as those in (Example 1). The compositions of the organic resin 113 and the filler 114 were also the same as in Example 1. On the other hand, the filling amount of the filler 114 was changed, and the core material 112 (glass woven fabric) and the filler 114 in the first insulating layer 102 were changed. The volume ratio of the organic resin 113 was 16 vol%, 63 vol%, and 21 vol%.

  At this time, the ratio of the filler 114 to the total of the organic resin 113 and the filler 114 excluding the core material 112 (glass woven fabric) was approximately 75 vol%.

  The thickness of the first wiring layer 103 was set to 40 μm as in (Example 1), and the first insulating layer 102 was embedded.

  (Embodiment 1), (Embodiment 6), (Embodiment 7), (Comparative Example 8), (Comparative Example 9), each of the substrates for evaluation used for the build-up layer 109 of each 8-layer substrate The following table 4 summarizes the configurations of the first insulating layer 102 and the first wiring layer 103, the evaluation of the insulation reliability, and the evaluation of the semiconductor temperature rise.

  In [Table 4], since the thickness of the first wiring layer 103 is 40 μm and the ratio of the filler 114 in the first insulating layer 102 is 25 vol% or more in any substrate, the temperature rise of the semiconductor is a problem. However, however, when the amount of filler 114 added in the first insulating layer 102 is reduced to 25 vol% as in (Comparative Example 8), a problem occurs in the insulation.

  Further, as in (Comparative Example 9), when the volume ratio of the filler 114 is increased to 63 vol%, the content of the organic resin is reduced, and thus the fluidity component of the organic resin in the heating and pressurizing steps is insufficient. . Further, a part of the embedding failure of the first wiring layer 103 occurred. Furthermore, in the reflow process at the time of semiconductor component mounting, it was impossible to obtain adhesion with the core layer, and it was impossible to reach an insulation test and an evaluation of the semiconductor temperature rise.

  On the other hand, as shown in [Table 4], in (Example 1), (Example 6), and (Example 7) of the present invention, the occurrence of short circuit was “None” in the insulation reliability test. Also, the semiconductor temperature rise was 82 ° C. to 87 ° C., and it was confirmed that there was a semiconductor cooling effect.

  As described above, the first insulating layer 102 including the core material 112, the organic resin 113, and the filler 114, the first wiring layer 103 embedded in the first insulating layer 102, and the first wiring layer 103 of the first insulating layer 102. A second printed wiring layer 104 formed on a surface opposite to the surface in contact with the first printed wiring board 104, and a multilayer printed wiring board 101 having at least one layer in which conduction between the first and second wiring layers is made of a metal plating via 105; It is desirable to do. Furthermore, the thickness of the first wiring layer 103 is 25% or more and 60% or less of the thickness of the first insulating layer 102, and the content of the core material 112 is 10 vol% or more and 30 vol% or less of the first insulating layer 102. It is desirable that Furthermore, it is preferable that the content of the filler 114 is 30 vol% or more and 60 vol% or less of the first insulating layer 102, and the filler 114 exists between the core material 112 and the first wiring layer 103. Furthermore, by setting the shortest distance between the core material 112 and the first wiring layer 103 to be equal to or larger than the particle diameter of the filler 114, the multilayer printed wiring board 101 having excellent heat dissipation can be provided. In this way, the multilayer printed wiring board 101 has excellent insulation even when the build-up layer 109 is thin or the first wiring layer 103 embedded in the build-up layer is thick. It has reliability, and also has adhesion with the core layer and impact reliability of the mounted components.

  Here, as the core material 112, in particular, when a glass woven fabric is used, since it has a woven fabric structure unlike a film material or the like, there is a gap between the core materials 112. It is easy to decrease, and even at the same volume content, the thickness becomes thicker than a film material without voids, so that contact with the embedded first wiring layer 103 is likely to occur, and the insulation according to the present invention can be ensured. The effect is more effective.

Further, Al (OH) ₃ having an average particle diameter of 5 μm and MgO having an average particle diameter of 3 μm were used as the filler 114, but the larger the particle diameter of the filler 114, the greater the gap between the core material 112 and the first wiring layer 103. However, it is impossible to have a uniform particle size with too large particles. Further, the smoothness and wiring patternability of the first insulating layer 102 are deteriorated. In addition, the smaller the particle diameter, the more the fluidity of the organic resin 113 is suppressed in the heating and pressurizing steps. However, even if the particles are too small, contact with the filler 114 is impossible. The particle diameter is desirably 1% or more and 12% or less of the thickness of the first insulating layer 102.

  Furthermore, by combining particles having a plurality of particle sizes, small particles can enter between large particles, and an improvement in filling property can be expected. Furthermore, it is possible to more effectively obtain the two effects of securing the distance between the core material 112 and the first wiring layer 103 and suppressing fluidity in the heating and pressurizing steps of the organic resin 113.

  Thus, by optimizing the core material 112 and the filler 114 that form the first wiring layer 103, the first wiring layer 103 is formed using the prepreg 119 in which the organic resin of the first wiring layer 103 is semi-cured. On the formed core layer, the first insulating layer 102 can be provided by heating and pressing. Further, the first wiring layer 103 is buried, the first insulating layer 102 is formed, and the core layer 108 and the buildup layer 109 are formed at the same time, so that a multilayer printed wiring board can be easily obtained.

Moreover, as a kind of filler 114, it is desirable that at least one of MgO, Al ₂ O ₃ , Mg (OH) ₂ , AlOOH, Al (OH) ₃ , BN, and SiO ₂ is included. Moreover, you may combine multiple. In order to obtain flame retardancy without containing a halogen compound or an antimony compound, it is desirable to include a hydroxide or oxide hydrate such as Mg (OH) ₂ , AlOOH, Al (OH) ₃ . In particular, the use of MgO, Al ₂ O ₃ , or BN having a high thermal conductivity is more effective in a multilayer printed wiring board considering heat transfer. Moreover, the heat conductivity as a multilayer printed wiring board improves more because the heat conductivity of the 1st insulating layer 102 shall be 1 W / mK or more. In addition, in order to realize mechanical strength and the like in addition to ensuring thermal conductivity and flame retardancy in the first insulating layer 102 at a lower cost, it is parallel to selecting a plurality of types of fillers 114. It is more desirable to consider the selection of the plurality of particle sizes.

  In order to obtain a higher-density wiring structure, the thickness of the first insulating layer 102 used for the buildup layer 109 is desirably 100 μm or less. Further, when the build-up layer is provided in multiple layers, it is preferable to use the present invention on the outermost layer on which the heat-generating semiconductor component is mounted and on the second layer from the outermost layer.

  However, when a large-sized mounting component is used in combination with a semiconductor component that generates a large amount of heat, mechanical strength is important and mounting reliability may be required. In such a case, in the outermost layer, the thickness of the glass woven fabric is not limited, the mechanical strength is prioritized, and the structure using the present invention may be used as the second layer from the outermost layer. At that time, a thermal via is arranged directly under the semiconductor component that generates a large amount of heat, and the heat generation amount is transmitted from the outermost layer to the second layer of the present invention, so that the mechanical strength of the mounted component and the heat transferability of the heat generating component are achieved. Side by side becomes possible.

  In the description of the present invention, a four-layer through-hole substrate is used for the core layer shown in FIGS. 1A and 1B. However, as shown in FIG. A substrate formed by the conductive resin composition 111 may be used as shown in FIG. 2B. Further, as shown in FIG.

  In particular, when a substrate formed of the conductive resin composition 111 is used for conduction between insulating layers, a multilayer printed wiring board that is a higher density wiring called an all-layer IVH structure resin multilayer printed wiring board is inexpensive. Although the lead time is short, it can be formed. However, as described above, the heat transferability of the core layer has been a problem due to limitations in the production process.

  As described above, the build-up layer 109 according to the present invention is used in the above-described build-up layer forming step by using the substrate in which the conduction between the insulating layers is formed in the core layer 108 with the conductive resin composition 111. To provide a multilayer printed wiring board 101 having both higher density wiring and heat transfer properties.

  ADVANTAGE OF THE INVENTION According to this invention, in a high-density wiring multilayer printed wiring board with which a semiconductor with high calorific value is mounted, a multilayer printed wiring board can be realized with high reliability and improved heat transfer.

DESCRIPTION OF SYMBOLS 101 Multilayer printed wiring board 102 1st insulating layer 103 1st wiring layer 104 2nd wiring layer 105, 105a, 105b Metal plating via 106 2nd insulating layer 107 Through-hole plating conductor 108 Core layer 109 Build-up layer 110 3rd wiring layer 111 Conductive Resin Composition 112 Core Material 113 Organic Resin 114 Filler 115 Metal Conductor Foil 116 Molded Body 117 Non-Through Hole 118 Metal Plating 119 Prepreg 120 Arrow

Claims (10)

A multilayer printed wiring board having a core layer and a buildup layer, wherein the buildup layer includes a first insulating layer including a core material, an organic resin, and a filler, and a first insulating layer embedded in the first insulating layer. A wiring layer, a second wiring layer formed on a surface of the first insulating layer opposite to the surface in contact with the first wiring layer, and a layer in which conduction between the first and second wiring layers is made of a metal plating via, Having at least one layer,
The thickness of the first wiring layer is 25% or more and 60% or less of the thickness of the first insulating layer, the content of the core material is 10 vol% or more and 30 vol% or less of the first insulating layer, and the filler The content of is not less than 30 vol% and not more than 60 vol% of the first insulating layer, the filler is present between the core material and the first wiring layer, and the shortest distance between the core material and the first wiring layer A multilayer printed wiring board having a particle diameter greater than or equal to the filler. The multilayer printed wiring board according to claim 1, wherein the core material included in the first insulating layer is a glass woven fabric. The multilayer printed wiring board according to claim 1, wherein the filler contained in the first insulating layer includes a filler having a particle diameter of 1% or more and 12% or less of the thickness of the first insulating layer. The filler contained in the first insulating layer includes at least one of MgO, Al ₂ O ₃ , Mg (OH) ₂ , AlOOH, Al (OH) ₃ , BN, and SiO _2. 1. The multilayer printed wiring board according to 1. The multilayer printed wiring board according to claim 1, wherein the first insulating layer has a thickness of 10 μm to 100 μm. A first insulating layer containing a core material, an organic resin, and a filler; a first wiring layer embedded in the first insulating layer; and a surface of the first insulating layer opposite to the surface in contact with the first wiring layer. The second wiring layer and the layer formed of metal plating vias for conduction between the first and second wiring layers are in the outermost layer, the outermost layer to the second layer, or both. Item 11. A multilayer printed wiring board according to Item 1. A first insulating layer containing a core material, an organic resin, and a filler; a first wiring layer embedded in the first insulating layer; and a surface of the first insulating layer opposite to the surface in contact with the first wiring layer. 2. The multilayer printed wiring board according to claim 1, wherein the second wiring layer and the layer made of metal plating vias for conduction between the first and second wiring layers are in the second layer from the outermost layer. The multilayer printed wiring board according to claim 1, wherein the first insulating layer has a thermal conductivity of 1.0 W / mK or more and 5.0 W / mK or less. A first insulating layer containing a core material, an organic resin, and a filler; a first wiring layer embedded in the first insulating layer; and a surface of the first insulating layer opposite to the surface in contact with the first wiring layer. The electrical connection means between the wiring layers of the core layer is formed of a conductive resin composition other than the second wiring layer and the buildup layer in which the conduction between the first and second wiring layers is made of a metal plating via. The multilayer printed wiring board according to claim 1. A first step of preparing a core layer having a first wiring on a surface layer;
A second step of setting a prepreg and a metal conductor foil on both surfaces of the core layer, heating and pressing, embedding the first wiring layer, forming a first insulating layer, and forming a molded body;
A third step of laser processing the molded body and providing a non-through hole in which the first wiring is exposed at the bottom of the hole;
A multilayer printed wiring board having a fourth step of forming a metal plating film by either or both of electroless plating and electrolytic plating in the non-through hole,
The thickness of the first wiring layer is 25% or more and 60% or less of the thickness of the first insulating layer in which the prepreg is formed by the pressurization and heating process,
The prepreg consists of a core material, a semi-cured organic resin and a filler,
The core material content is 10 vol% or more and 30 vol% or less of the first insulating layer, the filler content is 30 vol% or more and 60 vol% or less of the first insulating layer, A method for producing a multilayer printed wiring board, wherein the filler is present between one wiring layer, and the shortest distance between the core material and the first wiring layer is equal to or larger than a particle diameter of the filler.

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