JP6643956B2 - Printed wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a printed wiring board having a hybrid structure using two or more types of insulating materials having different physical properties such as electrical properties, mechanical properties, and workability, and a method for manufacturing the same.

2. Description of the Related Art In recent years, as electronic devices have become more sophisticated and more sophisticated, there has been a demand for a printed wiring board used for the electronic devices to have a higher density and a smaller thickness. Therefore, the development and practical use of a high-performance build-up board suitable for semiconductor mounting using a combination of a high heat-resistant and low-thermal-expansion base material and a high-thermal-conductivity base material are progressing.
As such a printed wiring board, a hybrid structure substrate using two or more kinds of insulating materials having different physical properties such as electric properties, mechanical properties, and workability is exemplified.

  2. Description of the Related Art Conventionally, the manufacture of a hybrid structure substrate has been performed by bonding each functional substrate with a special adhesive after divisional manufacture. As such a manufacturing method, for example, a board having a normal function on which components are mounted and wiring for connecting the mounted components is formed, and an antenna board are separately manufactured, and then finally laminated and integrated to form a single board. A method of manufacturing the substrate.

  Alternatively, a method in which two or more types of insulating materials having different physical properties are used and integrally manufactured. In such a method, first, a laminated plate including a plurality of layers such as a four-layer plate and a two-layer plate is formed for each material type. Next, the respective laminates are laminated with a resin used as one of the materials or a completely different thermosetting resin to be integrated. After that, a printed wiring board having a hybrid structure is manufactured by forming a pattern by through-hole drilling, plating, and a subtractive method, or forming a pattern by pattern plating such as MSAP after drilling the through-hole.

FIG. 9 shows a printed wiring board having such a hybrid structure. A printed wiring board 100 'shown in FIG. 9 includes a core layer 10' having a conductor circuit 2 'formed on an insulator 1', a build-up layer 3 'formed on the surface of the core layer 10', and a build-up layer 3 ' 3 ′ and an outermost build-up layer 30 ′ made of a different insulating material (resin). A through hole 5 'penetrating the front and back surfaces of the printed wiring board 100' is provided. A conductor layer (through-hole plating) 7 'is provided around the inner wall surface and the opening of the through-hole 5'.
Of these, different resins are used for the buildup layer 3 ′ and the outermost buildup layer 30 ′. In particular, as the outermost buildup layer 30 ', a liquid crystal polymer (LCP), which is a low dielectric material, is used.

  However, in the case of processing the through hole 5 'in a printed wiring board using two or more kinds of insulating materials having different physical properties, there is a problem of an electroless plating process (including resin roughening) for two or more kinds of insulating materials having different physical properties. Also, there is a problem of through-hole disconnection due to a difference in thermal expansion coefficient.

That is, there is a difference in resistance to roughening including desmear (permanganese acid resistance and plasma resistance) depending on the resin of the build-up layer 3 ′ and the outermost build-up layer 30 ′ shown in FIG. For this reason, a difference occurs in the processability (easiness of roughening of the resin), and the unevenness of the resin surface after the roughening is different. If the unevenness of the resin surface is small, the adhesion of the electroless plating is deteriorated, and as a result, the adhesion of the electrolytic plating to the inner wall surface of the through hole is also deteriorated, the plating is peeled off, and the connection reliability of the through hole 5 'is reduced. Deteriorates the performance.
Since different resins have different thermal expansion coefficients, when two or more insulating materials having different physical properties are used, the thermal expansion coefficient changes from the boundary of the resin in the longitudinal direction of the through hole. The stress is concentrated on the boundary of the resin due to the expansion and contraction of the resin due to the heat generated by the entire device when the component is mounted or operated as a device after the component mounting. For this reason, cracks occur in the conductor layer 7 ', or resin cracks occur at the boundary of the resin, causing cracks in the conductor layer 7', thereby causing through-hole disconnection.

In order to solve such a problem, for example, Japanese Patent Application Laid-Open No. H11-163873 discloses that a difference in physical property values between a double-structured through-hole via and a single-structured through-hole via is eliminated so that stress is not concentrated on one of the through-hole vias. Describes that cracks in through-hole vias are prevented.
However, when two or more types of insulating materials having different physical properties are used, the thickness of the conductor layer 7 ′ becomes large (30 μm or more) in order to prevent the occurrence of disconnection of the through-hole, and fine wiring cannot be formed by the subtractive method. If the subtractive method and the pattern plating method such as MSAP are used together, fine wiring can be formed, but the number of manufacturing steps increases, the work becomes complicated, and the manufacturing cost increases.

JP 2013-089902 A

  The present invention relates to a printed wiring board on which a build-up layer made of two or more insulating materials having different physical properties is formed, wherein a printed wiring board in which a through-hole is easily formed in the build-up layer and through-hole disconnection does not occur during lamination. It is an object to provide a board and a method for manufacturing the board.

The present invention has been completed to solve the above problems, and has the following configuration.
(1) A core layer having a conductor circuit formed on an insulator, at least one first buildup layer made of a first resin laminated on at least one surface of the core layer, and a surface of the first buildup layer. A second build-up layer made of a second resin having a cavity or a through-hole laminated thereon; and a through-hole passing through the cavity or the through-hole and penetrating the core layer and the first and second build-up layers. A printed wiring board, wherein a cavity or a through hole is filled with a first resin.
(2) The printed wiring board according to (1), wherein the resin forming the insulator of the core layer and the first resin forming the first buildup layer are the same resin.
(3) The printed wiring board according to (1) or (2), wherein a plurality of filled vias filled with a conductor are arranged around the opening of the through hole in the second buildup layer.
(4) The printed wiring board according to (3), wherein the filled via is arranged so as to surround at least a part of the opening of the through hole.
(5) The printed wiring board according to (4), wherein the filled vias are arranged on the same circumference around the through hole.
(6) A step of forming a conductor circuit on an insulator to obtain a core layer, and having at least one first buildup layer made of a first resin and a cavity or a through hole on at least one surface of the core layer. A step of laminating a second build-up layer made of a second resin in this order, and a step of forming a through-hole passing through the cavity or the through-hole and penetrating the core layer and the first and second build-up layers. Wherein the step of laminating the first build-up layer and the second build-up layer comprises a semi-cured resin having at least one layer of a first prepreg and a cavity or through hole on at least one surface of a core layer This is performed by stacking layers or cured resin layers in this order and subjecting them to hot pressing, so that the melted resin of the first prepreg is removed from the cavity or through-hole. Method of manufacturing a printed wiring board characterized in that it is filled in.
(7) A copper foil is formed on one surface of the semi-cured resin layer or the cured resin layer having the cavity, and the opening of the cavity is located on the first prepreg side. The method for producing a printed wiring board according to the above.
(8) The method of manufacturing a printed wiring board according to (6) or (7), wherein the resin forming the insulator of the core layer and the resin forming the first prepreg are the same resin.
(9) The method for manufacturing a printed wiring board according to any one of (6) to (8), wherein the cavity is formed by laser processing.
(10) The printed wiring board according to any one of (6) to (9), further including a step of forming a plurality of filled vias filled with a conductor around the opening of the through hole in the second buildup layer. Manufacturing method.

According to the present invention, the cavity in which the through hole is formed is filled with the first resin forming the first buildup layer. Therefore, the electroless plating process (roughening of resin) of the through-hole is easy, and even if the plating thickness of the inner wall surface of the through-hole is relatively thin, the through-hole disconnection does not occur due to the difference in thermal expansion coefficient, and the through-hole connection is performed. Reliability is improved.
Further, at the time of hot pressing at the time of manufacturing the printed wiring board, the cavity in which the through hole is formed is filled with the molten first resin. Therefore, the difference in thermal expansion coefficient of the resin can be reduced, and a through hole with improved connection reliability can be easily formed.

It is an explanatory view showing one embodiment of a printed wiring board concerning the present invention. (A)-(d) is process explanatory drawing which shows one Embodiment of the manufacturing method of the printed wiring board which concerns on this invention. (E)-(f) is process explanatory drawing which shows one Embodiment of the manufacturing method of the printed wiring board which concerns on this invention. (F ') is explanatory drawing which shows the modification of one Embodiment of the manufacturing method of the printed wiring board which concerns on this invention. (A)-(d) is process explanatory drawing which shows another embodiment of the manufacturing method of the printed wiring board which concerns on this invention. (E)-(f) is process explanatory drawing which shows another embodiment of the manufacturing method of the printed wiring board which concerns on this invention. (F ') is explanatory drawing which shows the modification of another embodiment of the manufacturing method of the printed wiring board which concerns on this invention. (A) is explanatory drawing which shows another embodiment of the printed wiring board which concerns on this invention, (b) is the 2nd buildup layer which looked at area | region X enclosed with the broken line of (a) from arrow Y direction. 3 is a plan sectional view of the lowermost part of FIG. It is an explanatory view showing still another embodiment of a printed wiring board concerning the present invention. It is explanatory drawing which shows an example of the some filled via arrange | positioned around the opening part of a through-hole. It is explanatory drawing which shows the conventional printed wiring board.

As shown in FIG. 1, a printed wiring board 100 includes a core layer 10 having a conductor circuit 2 formed on an insulator 1, and a first build formed of a resin serving as an insulating material and a conductor circuit on both surfaces of the core layer 10. And a second build-up layer formed on the surface of the first build-up layer, and a through-hole.
The through hole 5 penetrates the core layer 10, the first buildup layer 3, and the second buildup layer 30. The inside of the through hole 5 is not filled with resin, and the inner wall surface has a conductor layer 7 made of metal plating such as copper plating as through hole plating.
In the printed wiring board 100, a via 4 connected to the conductor circuit 2 of the core layer 10, a via 40 connected to the conductor circuit 20, and provided in the outermost layer of the printed wiring board 100, for protecting the via 40. May be appropriately provided.

  The insulator 1 is not particularly limited as long as it is formed of a material having an insulating property. Examples of such a material having an insulating property include an organic resin such as an epoxy resin, a bismaleimide-triazine resin, and a polyimide resin. These organic resins may be used as a mixture of two or more kinds.

  When using an organic resin as the insulator 1, it is preferable to use the organic resin in combination with a reinforcing material. Examples of the reinforcing material include insulating cloth materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more of these reinforcing materials may be used in combination. The insulator 1 is preferably formed from an organic resin containing a glass material such as glass fiber. Further, the insulator 1 may include an inorganic filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Further, the insulator 1 may have an insulating cloth material. The insulator 1 may have a single-layer structure or a multilayer structure.

Conductor circuits 2 are formed on both surfaces of the insulator 1. The conductive circuit 2 is not particularly limited as long as it is a conductive circuit that is electrically connected to another component or a base material. For example, a conductive resin or metal plating is used. Particularly preferred is copper plating. This copper plating may be chemical copper plating (electroless copper plating), but is preferably electrolytic copper plating.
The conductor circuit 2 may be formed, for example, by forming a hole in the insulator 1 by drilling or laser processing and providing a conductor in the hole by plating. May be filled with a resin if necessary.

The core layer 10 is obtained by forming the conductor circuit 2 on the insulator 1. The first buildup layer 3 is provided on both surfaces of the core layer 10. The first buildup layer 3 is formed by laminating a layer made of an insulating resin and a conductor circuit. In the embodiment shown in FIG. 1, the first buildup layer 3 has a two-layer structure, and is formed from the same insulating resin layers 31 and 32 and the conductor circuits 20 and 21.
The insulating resin layer 31 includes a via 4 electrically connected to the conductor circuit 2 of the core layer 10. The via 4 is formed by applying or filling a conductive material on the inner wall surface of the hole. The insulating resin layer 32 includes a via 40 connected to the conductor circuit 20 provided on the insulating resin layer 31. The via 40 is formed by applying or filling a conductive material in the hole.
Examples of the first resin forming the first buildup layer 3 (the insulating resin layers 31 and 32) include an epoxy resin, a bismaleimide-triazine resin, and a polyimide resin. The first buildup layer 3 and the insulator 1 forming the core layer 10 are preferably formed of the same resin (first resin). The formation positions and the numbers of the vias 4 and the vias 40 are not limited, and may be provided in any of the first buildup layers 3 as appropriate.

  The second buildup layer 30 having the cavity 6 is provided in the first buildup layer 3. This second buildup layer 30 is formed of a resin (second resin) different from the first buildup layer 3. The second resin is not particularly limited as long as it is different from the first resin. For example, the second resin is appropriately selected according to desired characteristics such as a resin having a low dielectric property. Examples of such a second resin include a liquid crystal polymer (LCP), a fluorine resin, a polyphenylene ether (PPE) resin, a polyphenylene oxide (PPO) resin, and the like.

  The through holes 5 pass through the upper and lower surfaces of the printed wiring board 100 through the cavities 6 of the core layer 10, the first buildup layer 3, and the second buildup layer 30. A conductor layer 7 made of, for example, metal plating such as copper plating is formed on the inner wall surface and the opening of the through hole 5. The conductor layer 7 is connected to wiring patterns (not shown) on the upper and lower surfaces of the printed wiring board 100.

  The cavity 6 through which the through-hole 5 penetrates is filled with the first resin forming the first build-up layer 3. That is, in the cavity 6, the conductor layer 7 formed on the inner wall surface of the through hole 5 is in contact with the first resin forming the first buildup layer 3 instead of the resin of the second buildup layer 30. The number and locations of the cavities 6 correspond to the number and locations of the through holes 5. The shape of the cavity 6 is not particularly limited. For example, as shown in FIG. 1, the cavity 6 is formed in a tapered shape narrowing from the core layer 10 side to the surface side.

  The second buildup layer 30 may include a via 41 connected to the conductor circuit 21 on the insulating resin layer 32. The via 41 is formed by depositing or filling a conductive material in a hole like the vias 4 and 40 described above. As shown in FIG. 1, if necessary, a solder resist layer 9 for protecting the via 41 and a wiring pattern (not shown) may be formed.

  In the printed wiring board 104 shown in FIG. 6A, a plurality of filled vias 44 are arranged around the opening of the through hole 5 in the second buildup layer 30. The filled via 44 functions like a rivet, and has a function of fixing the second buildup layer 30, that is, pressing the second buildup layer 30 against the core layer 10. Therefore, even when the printed wiring board 104 is exposed to a high temperature environment, for example, the thermal expansion of the second resin having a large thermal expansion coefficient can be suppressed. As a result, even when the thickness of the conductor layer 7 formed around the inner wall surface and the opening of the through hole is small, the occurrence of corner cracks in the conductor layer 7 is further suppressed. The filled vias 44 are electrically independent and are not connected to a wiring pattern (not shown) or the like.

  The conductor filled in the filled via 44 is not particularly limited. For example, a conductor having a smaller thermal expansion coefficient than that of the second resin is preferable. Examples of such a conductor include copper, aluminum, gold, silver, cobalt, iron, and palladium. However, this conductor is preferably made of copper in order not to contaminate the cost or the copper surface mainly used for forming the through hole 5 and the wiring pattern. The diameter of the opening of the filled via 44 is not limited. For example, the diameter is smaller than the diameter of the opening of the through hole 5. Although it depends on the size of the printed wiring board 104, the diameter of the opening of the filled via 44 is preferably about 20 to 40% of the diameter of the opening of the through hole 5.

  Regarding the arrangement of the filled vias 44, as shown in FIG. 6B, it is preferable that the distance d between the wall surface of the through hole 5 and the wall surface of each filled via 44 is constant. Thus, when the distance d is constant, that is, when the filled vias 44 are arranged on the same circumference with the through hole 5 as the center, the effect as a rivet is exerted more strongly. As a result, the thermal expansion of the second resin can be more efficiently suppressed. In FIG. 6B, eight filled vias 44 are formed for one through hole 5. However, if the number is two or more, preferably three or more, the thermal expansion of the second resin can be suppressed.

  The distance between the through hole 5 and the filled via 44 is not particularly limited. The through hole 5 and the filled via 44 are preferably arranged with a distance between the wall surfaces of at least 0.3 mm (the distance d1 in the case of FIG. 6B). By providing a distance between the wall surfaces of at least 0.3 mm, the effect as a rivet is more strongly exerted, and the thermal expansion of the second resin can be suppressed more efficiently. The upper limit depends on the space existing around the through hole 5 and the types of the first resin and the second resin, but is preferably about 0.5 mm.

  The distance between adjacent filled vias 44 is not particularly limited. Adjacent filled vias 44 are preferably arranged with a distance between the wall surfaces of at least 0.3 mm (distance d2 in FIG. 6B). By providing a distance between the wall surfaces of at least 0.3 mm, the effect as a rivet is more strongly exerted, and the thermal expansion of the second resin can be suppressed more efficiently. The upper limit depends on the space existing around the through hole 5 and the types of the first resin and the second resin, but is preferably about 0.5 mm.

  The above-described cavity 6 may be larger than a region where the lower land 8 is formed as in the printed wiring board 101 shown in FIG. By making the area of the cavity 6 larger than the lower land 8, the lower land 8 does not contact the resin (cured resin) 30c of the second buildup layer. That is, the lower land 8 contacts only the first resin forming the first buildup layer 3. The electroless plating process (roughening of the resin) is also easy at the location where the lower land 8 is formed, the land does not peel off, and the through-hole connection reliability is further improved. Also, in the printed wiring board 101, if a plurality of filled vias 44 filled with a conductor are formed around the opening of the through hole 5 in the resin 30c of the second buildup layer, stress on the corner of the through hole is reduced. The occurrence of corner cracks is further suppressed, and the reliability of through-hole connection is further improved.

Next, a method for manufacturing a printed wiring board according to the present invention will be described. The method for manufacturing a printed wiring board according to the present invention includes the following steps (I) to (III).
(I) A step of forming a conductor circuit on an insulator to obtain a core layer.
(II) A step of laminating at least one first buildup layer made of a first resin and a second buildup layer made of a second resin having a cavity on at least one surface of the core layer in this order. .
(III) A step of forming a through hole passing through the cavity and penetrating the core layer and the first and second buildup layers.

  One embodiment of a method for manufacturing a printed wiring board according to the present invention will be described with reference to FIGS. The description of the members described above is omitted.

  First, a dry film (not shown), which is an etching resist, was attached to the insulator 1 on which a conductor (copper foil) had been formed by a known method, exposed and developed. After the conductor was etched, a conductor circuit 2 was formed. When the dry film at the location is peeled off, a core layer 10 having a conductor circuit 2 as shown in FIG. The hole 1a in which the conductor layer is attached to the inner wall surface is formed by drilling or laser-cutting the conductor (copper foil) formed in the insulator 1 and plating the entire insulator 1 by plating. It is formed by providing a conductor in the hole.

  Next, as shown in FIG. 2B, an insulating resin layer 31 is formed on both surfaces of the core layer 10. The insulating resin forming the insulating resin layer 31 is the first resin described above, and is preferably the same as the resin forming the insulator 1 of the core layer 10. The conductor circuit 20 is further formed on the surface of the insulating resin layer 31. The method of forming the conductor circuit 20 may be the same as that of the conductor circuit 2 of the core layer 10 described above. Vias 4 that are electrically connected to the conductor circuits 2 of the core layer 10 are formed in the insulating resin layer 31.

  Next, as shown in FIG. 2C, a first prepreg 32 ′ for forming the insulating resin layer 32 and a copper foil 21a are formed on the surface of the insulating resin layer 31 formed on the upper surface side of the core layer 10. Lay up (place in order, aligning each other).

Further, on the surface of the insulating resin layer 31 formed on the lower surface side of the core layer 10, a first prepreg 32 ′ for forming the insulating resin layer 32 and a hole 6 a in advance at a position corresponding to the cavity 6 described later are formed by laser. The copper foil 21a formed by processing or drilling and the copper foil 30a with resin forming the cavity 6 are laid up. The hole 6 a is preferably provided so as to have substantially the same diameter as the opening of the cavity 6.
The resin-attached copper foil 30a is obtained by attaching a resin (semi-cured resin) 30b different from the resin of the first prepreg 32 'to one surface of the copper foil 30d and integrating them. The cavity 6 is formed in the resin-coated copper foil 30a so as not to penetrate the copper foil 30d by, for example, trepanning with a laser. At this time, in mechanical processing such as drilling, there is a risk that the copper foil 30d may be penetrated or resin residue may remain on the copper foil 30d. Further, if the resin is dissolved and removed with a chemical or the like, the resin other than the removed portion may be deteriorated. Therefore, laser processing is preferable.
The resin (semi-cured resin) 30b of the copper foil with resin 30a becomes the second build-up layer 30 after hot pressing. As such a resin-attached copper foil 30a, R-F705T (manufactured by Panasonic Corporation) or the like may be used.

  By subjecting the laid-up laminate to hot pressing, a laminate 11 including the core layer 10, the first build-up layer 3, and the second build-up layer 30 is obtained, as shown in FIG. At this time, the resin contained in the first prepreg 32 'is melted by heat, and the melted resin is filled into the cavity 6 as shown in FIG. Further, the inside of the via 4 is simultaneously filled with the resin contained in the first prepreg 32 '.

(Modification)
A through hole 60 may be used instead of the cavity 6. As for the processing method, not only the laser but also a variety of options such as drilling and punching with a mold are increased.
In this case, by laying up a release film (Aflex 25 MW manufactured by Asahi Glass Co., Ltd.) on the lower surface of the resin-coated copper foil 30 a, the molten resin of the first prepreg 32 ′ is heated by hot-pressing. It prevents the copper foil 30d from being excessively spread on the lower surface of the foil 30a.
After the hot pressing, the resin of the first prepreg 32 'slightly spread from the through hole 60 to the surface of the copper foil 30d is cut or polished, and is processed so as to have the same height as the surface of the copper foil 30d.

Next, as shown in FIG. 3E, through-hole pilot holes 5a are formed by drilling or laser processing so as to pass through the inside of the cavity 6 and penetrate the upper and lower surfaces of the laminated plate 11. At this time, a hole 40 a for forming a via 40 electrically connected to the conductor circuit 20 of the insulating resin layer 31 is formed in the insulating resin layer 32 by laser processing. Examples of the laser light used in this laser processing include a CO ₂ laser, a UV-YAG laser, and the like.
Residue (not shown) of the resin at the time of opening may remain on the periphery of the opening of the through-hole pilot hole 5a and the hole 40a formed by drilling or laser processing or on the inner wall surface. In that case, the residue is removed by desmear treatment.

  Next, a conductor layer is formed from a conductor material in each of the through-hole pilot hole 5a and the hole 40a and on both surfaces of the laminate 11 (plating process). The conductor material is preferably the same as that in which the vias 4 are formed. For example, copper plating is preferable, and copper plating may be chemical copper plating (electroless copper plating) or electrolytic copper plating.

  After plating the hole 40a and the through-hole pilot hole 5a, a dry film is attached to the surface of the laminated board 11 by a known method. Thereafter, exposure and development are performed to remove the dry film other than the positions where the holes 40a and the through-hole pilot holes 5a are formed. When the dry film at the place where the conductor circuit or the like is formed is peeled off after etching the conductor, the via 40 electrically connected to the conductor circuit 20 and the upper and lower surfaces of the laminated board 11 penetrate and the conductor layer is formed on the periphery and the inner wall surface of the opening. 7 can be obtained. The thickness of the conductor layer 7 is not particularly limited as long as it is 15 μm or more, but is preferably less than 30 μm.

Finally, a solder resist layer 9 is formed as an insulating resin layer on the surface of the second build-up layer 30, and the surface treatment is performed. Thus, the printed wiring board 100 shown in FIG.
Further, the printed wiring board 102 shown in FIG. 3 (f ') is a completed view according to a modified example.
In the present embodiment, the second buildup layer 30 is provided only on one side of the printed wiring board 100. However, the present invention is not limited to this, and the second buildup layer 30 may be provided on both sides. In that case, the cavities 6 may be provided in the formation regions of the through holes 5 of the second buildup layers 30 on both sides.

The method for manufacturing a printed wiring board according to the present invention may further include the following step (IV) in addition to the above steps (I) to (III).
(IV) forming a plurality of filled vias filled with a conductor around the opening of the through hole in the second build-up layer;

  In order to form the filled vias 44, a plurality of holes for forming the filled vias 44 are formed around the opening of the through hole lower hole 5a in the resin-coated copper foil 30a shown in FIG. I do. This hole may be formed simultaneously with the formation of the hole 40 a for forming the via 40. Next, a conductor (such as copper) is applied to the inner wall surface of the through-hole prepared hole 5a and the periphery of the opening by plating to form the conductor layer 7. Similarly to the via 40 described above, a conductor (such as copper) is filled in the hole for forming the filled via 44 by plating, and the filled via 44 is formed. After that, when the solder resist layer 9 is formed and the surface treatment is performed, the printed wiring board 104 as shown in FIG. 6A is formed.

  Although the embodiment using the resin-added copper foil as the second buildup layer has been described above, the present invention is not limited to the resin-added copper foil, and a two-layer substrate may be used. An embodiment using a two-layer substrate will be described with reference to FIGS. Note that FIGS. 4A and 4B are as described above, and thus description thereof is omitted.

  As shown in FIG. 4C, a first prepreg 32 ′ for forming the insulating resin layer 32 and a copper foil 21a are laid up on the surface of the insulating resin layer 31 formed on the upper surface side of the core layer 10. .

  Further, on the surface of the insulating resin layer 31 formed on the lower surface side of the core layer 10, the first prepreg 32 'forming the insulating resin layer 32 and the two-layer substrate 35a are laid up.

The following processing needs to be performed on the two-layer substrate 35a prior to the lay-up.
First, a lower hole of the via 45 is formed by drilling or laser processing so as to penetrate the upper and lower surfaces of the two-layer substrate 35a. Examples of the laser light used in this laser processing include a CO ₂ laser, a UV-YAG laser, and the like.
Resin residue (not shown) at the time of opening may remain on the periphery of the opening of the prepared hole of the via 45 or the inner wall surface formed by drilling or laser processing. In that case, the residue is removed by desmear treatment.
For the two-layer substrate 35a, it is preferable to use an insulator 35 on which a conductor (copper foil) has been formed.

Next, a conductor layer is formed by applying or filling a conductor material on the inside of the lower hole of the via 45 and on both surfaces of the two-layer substrate 35a (plating process). The conductor material is preferably the same as the one in which the via 4 is formed. For example, copper plating is preferable, and the copper plating may be chemical copper plating (electroless copper plating) or electrolytic copper plating.
Further, after plating the via 45, a dry film is attached to both surfaces of the two-layer substrate 35a by a known method. A mask (not shown) is attached only to the upper surface of the two-layer substrate 35a, and is exposed and developed. That is, the land (not shown) of the via 4 on the upper surface of the two-layer substrate 35a, the opening other than the opening 6b at the position corresponding to the formation position of the conductive circuit 25 and the cavity 6 described later, and the entire lower surface of the two-layer substrate 35a are dry-dried. Form a film. When the dry film at the place where the conductor circuit or the like is formed is peeled off after etching the conductor, the conductor circuit 25, the via 45 electrically connected to the conductor circuit 25, and the opening 6b can be obtained. The thickness of the conductor circuit 25 and the conductor 35d is not particularly limited as long as it is 15 μm or more, but is preferably less than 30 μm.

Next, the cavity 6 is formed at the position of the opening 6b on the upper surface of the two-layer substrate 35a. The cavity 6 is formed so as not to penetrate the conductor 35d by, for example, trepanning with a laser.
Examples of the material constituting the two-layer substrate 35a include RO3003 (Rogers Corporation), NPC-F275 (Nippon Pillar Industry Co., Ltd.), R-5785 (Panasonic Corporation), Astra MT (Isola), and the like. May be used.

  By subjecting the laid-up laminate to hot pressing, a laminate 12 including the core layer 10, the first build-up layer 3, and the two-layer substrate 35a is obtained as shown in FIG. 4D. At this time, the resin contained in the first prepreg 32 'is melted by heat, and the melted resin is filled into the cavity 6 as shown in FIG. Further, the inside of the via 4 is simultaneously filled with the resin contained in the first prepreg 32 '.

  The filled vias 44 may be formed in the two-layer substrate 35a. In this case, the hole for forming the filled via 44 is formed by, for example, the above-described laser processing. The plurality of holes are provided around the through hole, that is, around the opening of the through hole. Residue (not shown) of the resin at the time of opening may remain around the opening of the hole or on the inner wall surface. In that case, the residue is removed by desmear treatment. The hole is filled with a conductor (such as copper) by the above-described plating, and a filled via 44 is formed. Note that the filled vias 44 need not be formed at this stage. For example, after the two-layer substrate 35b is hot-pressed as shown in FIG. 4D, a hole for forming the filled vias 44 is formed. The hole may be formed by filling a conductor.

(Modification)
A through hole 60 may be used instead of the cavity 6. As for the processing method, not only the laser but also a variety of options such as drilling and punching with a die are increased.
In this case, by releasing a release film (Aflex 25 MW manufactured by Asahi Glass Co., Ltd.) on the lower surface of the two-layer substrate 35 a, the molten resin of the first prepreg 32 ′ is heated during hot pressing. Is prevented from excessively spreading on the surface of the conductor 35d on the lower surface.
After the hot pressing, the resin of the first prepreg 32 'slightly spread from the through hole 60 to the surface of the conductor 35d is cut or polished, and is processed so as to have the same height as the surface of the conductor 35d.

  Finally, through the manufacturing steps shown in FIGS. 5E and 5F, the printed wiring board 110 is completed. 5 (e) and 5 (f) are the same as FIGS. 3 (e) and 3 (f), and a description thereof will be omitted. Further, the printed wiring board 112 shown in FIG. 5 (f ') is a completed view according to a modified example. Although a two-layer substrate has been described, the number of layers is not limited to two, and it goes without saying that the present invention can be applied to a multilayer having more than two layers.

  As described above, according to this method for manufacturing a printed wiring board, the molten first resin is filled into the cavity in which the through hole is formed during hot pressing. Therefore, the electroless plating process (resin roughening) is easy, and even if the plating thickness on the inner wall surface of the through hole is relatively small, the disconnection of the through hole due to the difference in the coefficient of thermal expansion does not occur, and the connection reliability of the through hole is improved. improves. In addition, since it can be manufactured only by the subtractive method, the number of manufacturing steps does not increase, leading to cost reduction.

  The printed wiring board according to one embodiment of the present invention is not limited to the above embodiment. For example, in the embodiment shown in FIGS. 6A and 6B, the second buildup layer 30 is provided on only one side of the printed wiring board 104. However, the second buildup layer 30 may be provided on both sides. In this case, a plurality of filled vias 44 may be formed around the opening of the through hole 5 in both the upper and lower second buildup layers 30.

  Further, in the above-described embodiment, as shown in FIG. 6B, the plurality of filled vias 44 are arranged so as to surround the opening of one through hole 5. However, when a plurality of through holes 5 are formed in a concentrated manner, the plurality of through holes 5 may be collectively surrounded by a plurality of filled vias 44 as shown in FIG.

DESCRIPTION OF SYMBOLS 1 Insulator 1a Hole part 2, 20, 21, 25 Conductor circuit 21a Copper foil 3, 3 'Buildup layer 30 Second buildup layer 30' Outermost buildup layer 31 Insulating resin layer 32 Insulating resin layer 32 'First Prepreg 30a resin-coated copper foil 30b resin (semi-cured resin)
30c resin (cured resin)
30d Copper foil 35 Insulator 35a Two-layer board 35d Conductor 4, 40, 41, 45 Via 4a, 40a Hole 44 Filled via 5, 5 'Through hole 5a Through hole lower hole 6 Cavity 6a hole 6b Opening 60 Through hole 7, 7 'Conductor layer 7a Conductor 8 Lower land 9 Solder resist layer 10 Core layer 11, 12 Laminated board 100, 101, 102, 104, 110, 112, 100' Printed wiring board

Claims (10)

A core layer having a conductor circuit formed on an insulator;
At least one first buildup layer made of a first resin laminated on at least one surface of the core layer;
A second build-up layer made of a second resin having a cavity or a through-hole laminated on the surface of the first build-up layer ,
The cavity or the through hole is filled with the first resin,
Said first resin through the cavity or through-hole is filled, the core layer and the printed wiring board, characterized in that there Bei Ete a through hole penetrating the first build-up layer.   The printed wiring board according to claim 1, wherein a resin forming the insulator of the core layer and a first resin forming the first buildup layer are the same resin.   3. The printed wiring board according to claim 1, wherein a plurality of filled vias filled with a conductor are arranged around the opening of the through hole in the second buildup layer. 4.   The printed wiring board according to claim 3, wherein the filled via is arranged so as to surround at least a part of an opening of the through hole.   The printed wiring board according to claim 4, wherein the filled vias are arranged on the same circumference around the through hole. Forming a conductor circuit on the insulator to obtain a core layer;
A step of laminating at least one first buildup layer made of a first resin and a second buildup layer made of a second resin having a cavity or a through hole on at least one surface of the core layer in this order; When,
As the cavity or through-hole, and forming a through hole penetrating the core layer and the first build-up layer,
The step of laminating the first build-up layer and the second build-up layer may include forming a semi-cured resin layer or a cured resin having at least one first prepreg and a cavity or a through hole on at least one surface of a core layer. A method for manufacturing a printed wiring board, wherein layers are stacked in this order and subjected to hot pressing, and the molten resin of the first prepreg is filled in the cavity or the through hole.   The printing according to claim 6, wherein a copper foil is formed on one surface of the semi-cured resin layer or the cured resin layer having the cavity, and an opening of the cavity is located on the first prepreg side. Manufacturing method of wiring board.   8. The method according to claim 6, wherein a resin forming the insulator of the core layer and a resin forming the first prepreg are the same resin. 9.   The method according to claim 6, wherein the cavity is formed by laser processing. The method of manufacturing a printed wiring board according to claim 6, further comprising: forming a plurality of filled vias filled with a conductor around an opening of the through hole in the second buildup layer.

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