JP5983523B2 - Multilayer substrate, electronic device using the same, and method for manufacturing electronic device - Google Patents

Description

  The present invention relates to a multilayer substrate having an inner edge pattern including lands on which electronic components are mounted and an outer edge pattern formed around the inner edge pattern, an electronic device using the same, and a method of manufacturing the electronic device.

  Conventionally, an electronic device in which an electronic component is mounted on one side of a substrate has been proposed (see, for example, Patent Document 1). Specifically, in this electronic device, an inner edge pattern and an outer edge pattern including lands are formed on one surface of the substrate, and a part of the inner edge pattern and the outer edge pattern are covered with a protective film such as a solder resist. . The outer edge pattern is formed around the inner edge pattern, and a part of the inner edge pattern and the outer edge pattern improve the adhesion with the solder resist, so that the contact surface with the solder resist is roughened. The electronic component is mounted on the land in the inner edge pattern via solder or the like. In addition, one side of the substrate including the electronic component is sealed with a mold resin so that the inner edge pattern is sealed.

  Such an electronic device is manufactured as follows. That is, first, an inner edge pattern and an outer edge pattern are formed on one surface of the substrate, and a part of the inner edge pattern that contacts (covers) the solder resist and a contact surface of the outer edge pattern are roughened. Then, a protective film that covers a part of the inner edge pattern and the outer edge pattern is formed. Next, the electronic component is mounted on the land via solder or the like. Subsequently, a mold having a recess formed on one surface is prepared, and one surface of the mold is pressed against one surface of the substrate so that the electronic component and the inner edge pattern are disposed in the recess. That is, one surface of the mold is pressed against the protective film covering the outer edge pattern so that the electronic component and the inner edge pattern are disposed in the recess. Thereafter, the space between the substrate and the concave portion of the mold is filled with mold resin, whereby the electronic device in which one surface of the substrate including the electronic component and the inner edge pattern is sealed is manufactured.

Japanese Patent Laid-Open No. 7-22538

  However, in such a method for manufacturing an electronic device, there is a problem that when one surface of the mold is pressed against one surface of the substrate, cracks may occur in the protective film due to stress generated in the protective film.

  In view of the above points, an object of the present invention is to provide a multilayer substrate capable of suppressing the generation of cracks in a protective film, an electronic device using the same, and a method for manufacturing the electronic device.

  In order to achieve the above object, in the invention according to claim 1, the core layer (20) having the surface (20a), the inner layer wiring (51) formed on the surface of the core layer, and the inner layer on the surface of the core layer. A buildup layer (30) arranged in a state of covering the wiring, and a land (61) formed on one surface (30a) on the opposite side of the core layer of the buildup layer, on which electronic components (121 to 123) are mounted An inner edge pattern (61, 62) sealed with a mold resin (150) together with an electronic component, and a mold resin (150). ), And a protective film (110) that covers a part of the inner edge pattern and the outer edge pattern. The outer edge pattern is a plate having a side surface (63b). At least a side surface roughness than the surface roughness of the portion covered by the protective film of the emission is characterized by being small.

  In such a multilayer substrate, after an electronic component is mounted on a land, when a mold is pressed against one side of the multilayer substrate to manufacture an electronic device including a mold resin, a protective film covering an outer edge pattern is pressed against the mold. Is done. At this time, since the surface roughness of the side surface of the outer edge pattern is reduced, the protective film is easily peeled off from the side surface of the outer edge pattern. Therefore, when the protective film is peeled off from the side surface of the outer edge pattern, the stress generated in the protective film can be released, and the generation of cracks in the protective film can be suppressed.

  According to a third aspect of the present invention, there is provided an electronic device comprising the multilayer substrate according to the first or second aspect, an electronic component mounted on the land, and a mold resin (150) for sealing the electronic component and the inner edge pattern. It is a device.

  The invention described in claim 4 is an invention relating to a method of manufacturing an electronic device according to claim 3, wherein a step of preparing a multilayer substrate, a step of mounting electronic components on lands of the inner edge pattern, And a step of forming a mold resin for sealing the electronic component and the inner edge pattern. In the step of forming the mold resin, a mold (200) having a recess (201) formed on one surface (200a) is prepared, One surface of the mold is pressed against the multilayer substrate so that the electronic component and the inner edge pattern are disposed in the recess, and then a mold resin is filled in a space between the multilayer substrate and the recess.

  According to this, the protective film is easily peeled from the side surface of the outer edge pattern. For this reason, when the mold is pressed against one side of the multilayer substrate, if the protective film peels off from the side surface of the outer edge pattern, the stress generated in the protective film can be released, and cracks are prevented from occurring in the protective film. it can.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is sectional drawing of the electronic device in 1st Embodiment of this invention. (A) is an enlarged view of area A in FIG. 1, and (b) is an enlarged view of area B in FIG. FIG. 7 is a cross-sectional view showing a manufacturing process of the electronic device shown in FIG. 1. FIG. 4 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 3. FIG. 5 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 4. FIG. 6 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 5. It is an enlarged view of the area | region C in FIG. It is sectional drawing of the electronic device in 2nd Embodiment of this invention. It is a top view of the electronic device shown in FIG. It is an enlarged view of the area | region D in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. Note that the electronic device of the present embodiment is preferably mounted on a vehicle such as an automobile, for example, and applied to drive various electronic devices for the vehicle.

  As shown in FIG. 1, the electronic device includes a multilayer substrate 10 having one surface 10 a and another surface 10 b, and electronic components 121 to 123 mounted on one surface 10 a of the multilayer substrate 10. And the electronic device is comprised by sealing the one surface 10a side of the multilayer substrate 10 with the mold resin 150 with the electronic components 121-123.

  The multilayer substrate 10 includes a core layer 20 as an insulating resin layer, a build-up layer 30 on the surface 20a side disposed on the surface 20a of the core layer 20, and a back surface 20b side disposed on the back surface 20b side of the core layer 20. A multilayer substrate including a build-up layer 40.

  In addition, the core layer 20 and the buildup layers 30 and 40 are comprised by the prepreg etc. which seal both surfaces of glass cloth with resin, and epoxy resin etc. are mentioned as resin of a prepreg. In addition, the prepreg resin may contain a filler having excellent electrical insulation and heat dissipation, such as alumina and silica, as necessary.

  A patterned surface-side inner layer wiring 51 (hereinafter simply referred to as an inner layer wiring 51) is formed at the interface between the core layer 20 and the buildup layer 30. Similarly, at the interface between the core layer 20 and the buildup layer 40, a patterned back side inner layer wiring 52 (hereinafter simply referred to as an inner layer wiring 52) is formed.

  Further, patterned surface-side surface wirings 61 to 63 (hereinafter simply referred to as surface layer wirings 61 to 63) are formed on the surface 30 a of the buildup layer 30. In the present embodiment, the surface layer wirings 61 to 63 are used for bonding electrically connected to the mounting lands 61 on which the electronic components 121 to 123 are mounted and the electronic components 121 and 122 via the bonding wires 141 and 142. The land 62 is a surface pattern 63 that is electrically connected to an external circuit.

  The surface pattern 63 is formed around the lands 61 and 62. In the present embodiment, the lands 61 and 62 correspond to the inner edge pattern of the present invention, and the surface pattern 63 corresponds to the outer edge pattern of the present invention. ing.

  On the front surface 40a of the buildup layer 40, patterned back surface side wirings 71 and 72 (hereinafter simply referred to as surface wirings 71 and 72) are formed. In the present embodiment, the surface layer wirings 71 and 72 are a back surface pattern 71 connected to the inner layer wiring 52 through a filled via described later, a heat sink pattern 72 provided with a heat sink for heat dissipation (hereinafter simply referred to as an HS pattern 72). ).

  Note that the surface 30 a of the buildup layer 30 is one surface of the buildup layer 30 opposite to the core layer 20, and is a surface that becomes the one surface 10 a of the multilayer substrate 10. Further, the surface 40 a of the buildup layer 40 is one surface of the buildup layer 40 opposite to the core layer 20, and is a surface that becomes the other surface 10 b of the multilayer substrate 10. The inner layer wirings 51 and 52, the surface layer wirings 61 to 63, and the surface layer wirings 71 and 72 are specifically described later, and are configured by appropriately laminating metal foil such as copper or metal plating.

  The inner layer wiring 51 and the inner layer wiring 52 are electrically and thermally connected through a through via 81 provided through the core layer 20. Specifically, the through via 81 is configured such that a through electrode 81b such as copper is formed on the wall surface of the through hole 81a penetrating the core layer 20 in the thickness direction, and a filler 81c is filled in the through hole 81a. Has been.

  Further, the inner layer wiring 51 and the surface layer wirings 61 to 63, and the inner layer wiring 52 and the surface layer wirings 71 and 72 pass through the filled vias 91 and 101 provided through the respective buildup layers 30 and 40 in the thickness direction as appropriate. Connected electrically and thermally. Accordingly, the lands 61 and 62 and the surface layer wiring 63 are appropriately electrically connected via the inner layer wirings 51 and 52, the back surface pattern 71, the through via 81, and the filled vias 91 and 101.

  The filled vias 91 and 101 are configured such that through holes 91a and 101a penetrating the build-up layers 30 and 40 in the thickness direction are filled with through electrodes 91b and 101b such as copper. The filler 81c is made of resin, ceramic, metal, or the like, but is an epoxy resin in this embodiment. The through electrodes 81b, 91b, 101b are configured by metal plating such as copper.

  A solder resist 110 that covers a part of the land 62 (a part of the inner edge pattern) and the surface pattern 63 is formed on the surface 30 a of the buildup layer 30. Similarly, a solder resist 110 that covers the back surface pattern 71 is formed on the front surface 40 a of the buildup layer 40.

  The solder resist 110 that covers the surface pattern 63 is formed with an opening 110a that exposes a portion of the surface pattern 63 that is connected to an external circuit. In the present embodiment, the solder resist 110 corresponds to the protective film of the present invention.

  The electronic components 121 to 123 include a power element 121 such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a control element 122 such as a microcomputer, and a passive such as a chip capacitor or a resistor. Element 123. Each electronic component 121 to 123 is mounted on the land 61 via the solder 130 and is electrically and mechanically connected to the land 61. The power element 121 and the control element 122 are also electrically connected to the land 62 formed in the periphery via bonding wires 141 and 142 such as aluminum and gold. That is, the land 62 is covered with the solder resist 110 at a portion different from the portion where the bonding wires 141 and 142 are connected.

  In addition, although the power element 121, the control element 122, and the passive element 123 were mentioned as an example and demonstrated here as the electronic components 121-123, the electronic components 121-123 are not limited to these.

  The mold resin 150 seals the lands 61 and 62 and the electronic components 121 to 123, and a general mold material such as an epoxy resin is formed by a transfer molding method using a mold, a compression molding method, or the like. Is.

  In the present embodiment, the mold resin 150 is formed only on the one surface 10 a of the multilayer substrate 10. That is, the electronic device of this embodiment has a so-called half mold structure. Further, on the other surface 10 b side of the multilayer substrate 10, although not particularly shown, a heat sink is provided on the HS pattern 72 via heat dissipation grease or the like.

  The above is the basic configuration of the electronic device according to this embodiment. Next, the structure of the surface pattern 63 that is a characteristic point of the present embodiment will be described.

  As shown in FIG. 2, the surface pattern 63 has a plate shape having a surface 63a and a side surface 63b opposite to the buildup layer 30 side. And as for the surface pattern 63, the unevenness | corrugation is formed in the surface 63a, and the side surface 63b is made into the flat surface. In addition, the portions (surface 62a and side surface 62b) covered with the solder resist 110 in the land 62 are uneven as in the surface 63a.

  That is, in the surface pattern 63, the surface roughness of the side surface 63b is smaller than the surface roughness of the land 62 covered with the solder resist 110 and the surface 63a. That is, in the surface pattern 63, the adhesion between the side surface 63 b and the solder resist 110 is smaller than the adhesion between the land 62 covered with the solder resist 110 and the surface 63 a and the solder resist 110.

  The above is the configuration of the electronic device in this embodiment. Next, a method for manufacturing the electronic device will be described with reference to FIGS. 3 to 5 are cross-sectional views in the vicinity of a portion of the multilayer substrate 10 on which the power element 121 is mounted.

  First, as shown in FIG. 3A, one in which metal foils 161 and 162 such as copper foil are arranged on the front surface 20 a and the back surface 20 b of the core layer 20 is prepared. Then, as shown in FIG. 3B, a through hole 81a penetrating the metal foil 161, the core layer 20, and the metal foil 162 is formed by a drill or the like.

  Thereafter, as shown in FIG. 3C, electroless plating or electroplating is performed to form a metal plating 163 such as copper on the wall surface of the through hole 81 a and the metal foils 161 and 162. As a result, a through electrode 81b composed of the metal plating 163 is formed on the wall surface of the through hole 81a. In addition, when performing electroless plating and electroplating, it is preferable to carry out using catalysts, such as palladium.

  Subsequently, as illustrated in FIG. 3D, a filler 81 c is disposed in a space surrounded by the metal plating 163. Thus, the through via 81 having the through hole 81a, the through electrode 81b, and the filler 81c is formed.

  Thereafter, as shown in FIG. 4A, so-called lid plating is performed by electroless plating, electroplating, or the like, and metal plating 164, 165 such as copper is formed on the metal plating 163 and the filler 81c.

  Next, as shown in FIG. 4B, a resist (not shown) is disposed on the metal platings 164 and 165. Then, wet etching or the like is performed using the resist as a mask, and the metal plating 164, the metal plating 163, and the metal foil 161 are appropriately patterned to form the inner layer wiring 51, and the metal plating 165, the metal plating 163, and the metal foil 162 are appropriately formed. The inner layer wiring 52 is formed by patterning. That is, in this embodiment, the inner layer wiring 51 is configured by laminating the metal foil 161, the metal plating 163, and the metal plating 164, and the inner layer wiring 52 is configured by laminating the metal foil 162, the metal plating 163, and the metal plating 165. It is configured.

  In FIG. 4C and subsequent figures, the metal foil 161, the metal plating 163, the metal plating 164, the metal foil 162, the metal plating 163, and the metal plating 165 are collectively shown as one layer.

  Thereafter, as shown in FIG. 4C, the buildup layer 30 and a metal plate 166 such as copper are laminated on the inner layer wiring 51 on the surface 20 a side in the core layer 20. Further, the buildup layer 40 and a metal plate 167 such as copper are laminated on the inner layer wiring 52 on the back surface 20 b side in the core layer 20. In this way, a stacked body 168 is configured in which the metal plate 166, the buildup layer 30, the inner layer wiring 51, the core layer 20, the inner layer wiring 52, the buildup layer 30, and the metal plate 167 are sequentially stacked from the top.

  Subsequently, as illustrated in FIG. 4D, the stacked body 168 is integrated by heating while pressing from the stacking direction of the stacked body 168. Specifically, by pressurizing the laminate 168, the resin constituting the buildup layer 30 is caused to flow to embed between the inner layer wirings 51, and the resin constituting the buildup layer 40 is caused to flow to cause the inner layer wiring 52 to flow. Embed between. And the buildup layers 30 and 40 are hardened by heating the laminated body 168, and the laminated body 168 is integrated.

  Next, as shown in FIG. 5A, a through hole 91 a that penetrates the metal plate 166 and the buildup layer 30 and reaches the inner layer wiring 51 is formed by a laser or the like. Similarly, as shown in FIG. 1, a through hole 101 a that penetrates the metal plate 167 and the buildup layer 40 and reaches the inner layer wiring 52 is formed in a cross section different from FIG.

  Then, as shown in FIG. 5B, so-called filled plating is performed by electroless plating, electroplating, or the like, and the through holes 91 a and 101 a are embedded with metal plating 169. Thus, the through electrode 91b and the through electrode 101b shown in FIG. 1 are configured by the metal plating 169 embedded in the through holes 91a and 101a formed in the buildup layers 30 and 40. Further, filled vias 91 and 101 in which through electrodes 91b and 101b are embedded in the through holes 91a and 101a are formed. In FIG. 5C and subsequent figures, the metal plate 166 and the metal plating 169 are collectively shown as one layer.

  Subsequently, as shown in FIG. 5C, a resist (not shown) is disposed on the metal plate 166. Next, the metal plate 166 is patterned by performing wet etching or the like using the resist as a mask. Thereafter, portions of the land 61 and land 62 that are connected to the bonding wires 141 and 142 and the side surface 63b of the surface pattern 63 are covered with a resist or the like. Then, the surface wirings 61 to 63 are formed by scrubbing the surface 62a of the land 62 and the surface 63a of the surface pattern 63 or by chemical treatment to form irregularities on the surface. Thereby, the surface pattern 63 whose surface roughness of the side surface 63b is smaller than the surface roughness of the surface 63a and the portion of the land 62 covered with the solder resist 110 is formed.

  Similarly, a resist (not shown) is arranged on the metal plate 167, and wet etching or the like is performed using the resist as a mask to pattern the metal plate 167, thereby forming the surface layer wirings 71 and 72.

  That is, in the present embodiment, the surface layer wirings 61 to 63 are configured to have the metal plate 166 and the metal plating 169, and the surface layer wirings 71 and 72 are configured to have the metal plate 167 and the metal plating 169.

  Next, as shown in FIG. 6A, the multilayer resist 10 is manufactured by disposing solder resists 110 on the surfaces 30a and 40a of the buildup layers 30 and 40, respectively, and patterning them appropriately. In the surface pattern 63, the adhesiveness between the side surface 63 b and the solder resist 110 is smaller than the adhesiveness between the portion of the land 62 covered with the solder resist 110 and the surface 63 a and the solder resist 110.

  Subsequently, as illustrated in FIG. 6B, the electronic components 121 to 123 are mounted on the land 61 via the solder 130. Then, wire bonding is performed between the power element 121 and the control element 122 and the land 62, and the power element 121 and the control element 122 and the land 62 are electrically connected.

  Thereafter, as shown in FIG. 6C, a molding resin 150 is formed by a transfer molding method using a mold, a compression molding method, or the like so that the lands 61 and 62 and the electronic components 121 to 123 are sealed. To do.

  Specifically, a mold 200 having a recess 201 that forms the outer shape of the mold resin 150 on one surface 200 a is prepared, and the electronic components 121 to 123 and the lands 61 and 62 are arranged in the recess 201. The one surface 200 a is pressed against the one surface 10 a side of the multilayer substrate 10.

  At this time, one surface 200a of the mold 200 is in contact with the solder resist 110, but the surface roughness of the side surface 63b of the surface pattern 63 is smaller than the surface roughness of the land 62 covered with the solder resist 110 and the surface 63a. Has been. For this reason, as shown in FIG. 7, the solder resist 110 is peeled off from the side surface 63b of the surface pattern 63, so that the stress generated in the solder resist 110 when the mold 200 is pressed can be released. It is possible to suppress cracks from occurring. In other words, it can be said that the side surface 63b of the surface pattern 63 is configured such that the solder resist 110 is peeled off with a stress smaller than the stress that causes cracks in the solder resist 110.

  As described above, in the present embodiment, the surface roughness of the side surface 63b of the surface pattern 63 is smaller than the surface roughness of the land 62 covered with the solder resist 110 and the surface 63a. For this reason, when the metal mold 200 is pressed against the one surface 10 a side of the multilayer substrate 10, the solder resist 110 can be easily peeled from the side surface 63 b of the surface pattern 63. And when the solder resist 110 peels from the side surface 63b of the surface pattern 63, the stress which generate | occur | produces in the solder resist 110 can be released when the metal mold | die 200 is press-contacted, and it suppresses that a crack generate | occur | produces in the solder resist 110. it can. Moreover, since it can suppress that a crack generate | occur | produces in the soldering resist 110, it can suppress that the crack generate | occur | produced in the soldering resist 110 propagates to the buildup layer 30, and a crack generate | occur | produces in the said buildup layer 30.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the outer edge pattern is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment, and thus the description thereof is omitted here.

  As shown in FIGS. 8 and 9, in the present embodiment, a mold step portion 64 is formed on the surface 30 of the buildup layer 30. In FIG. 9, the solder resist 110 is omitted for easy understanding. FIG. 8 corresponds to the II cross section in FIG.

  The mold step 64 is composed of a surface layer conductor 65 formed on the surface 30 a of the buildup layer 30 and a solder resist 110 that covers the surface layer conductor 65. In the present embodiment, the surface pattern 63 and the surface layer conductor 65 correspond to the outer edge pattern of the present invention.

  As shown in FIGS. 1 and 2, the surface layer conductor 65 has a frame shape surrounding the lands 61 and 62, and is formed between the lands 61 and 62 and the surface pattern 63. As shown in FIG. 10, the surface roughness of the side surface 65b of the surface conductor 65 is made smaller than the surface roughness of the land 62 covered with the solder resist 110 and the surface 65a.

  The surface layer conductor 65 is insulated from the lands 61 and 62 and the surface pattern 63. That is, the surface layer conductor 65 is a so-called dummy pattern for adjusting the height of the mold step portion 64.

  The surface layer conductor 65 is completely covered with the solder resist 110 that covers the surface pattern 63. That is, the height of the solder resist 110 from the surface 30a of the buildup layer 30 in the mold step 64 is constant in the circumferential direction.

  Moreover, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is set to be equal to or higher than the height from the surface 30a of the build-up layer 30 in the part covering the surface pattern 63 in the solder resist 110. ing. In this embodiment, the film thickness of the surface pattern 63 and the surface layer conductor 65 is made equal, and the film thickness of each part of the solder resist 110 is also made equal. For this reason, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is made equal to the height from the surface 30a of the build-up layer 30 in the portion of the solder resist 110 that covers the surface pattern 63. ing.

  The mold resin 150 seals the inner edge side portion of the solder resist 110 constituting the mold step portion 64 while exposing the outer edge side portion of the solder resist 110 constituting the die step portion 64. That is, it can be said that the mold step 64 is formed at the interface between the portion sealed with the mold resin 150 and the portion not sealed on the one surface 10 a of the multilayer substrate 10.

  In addition, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is, in other words, the build-up layer 30 from the surface opposite to the surface layer conductor 65 in the solder resist 110 covering the surface layer conductor 65. It is the length to the surface 30a. In FIG. 8, the surface pattern 63 and the surface layer conductor 65 are covered with the same solder resist 110, but the solder resist 110 that covers the surface pattern 63 and the solder resist 110 that covers the surface layer conductor 65 may be separated. Good.

  As described above, in this embodiment, the mold step portion 64 having the surface conductor 65 is formed between the lands 61 and 62 and the surface pattern 63. For this reason, when the process of FIG.6 (c) is performed, it can suppress that the mold resin 150 flows out from the space between the multilayer substrate 10 and the recessed part 201 of the metal mold | die 200. FIG.

  That is, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is equal to or higher than the height from the surface 30a of the build-up layer 30 in the part of the solder resist 110 that covers the surface pattern 63. ing. For this reason, when the process of FIG. 6C is performed, the mold step 64 is pressed against the mold 200. Moreover, since the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is constant in the circumferential direction, no gap is formed between the mold step 64 and the mold 200. . Therefore, it is possible to suppress the mold resin 150 from flowing out of the space between the multilayer substrate 10 and the concave portion 201 of the mold 200, and the portion of the surface pattern 63 exposed from the opening 110 a of the solder resist 110 is the mold resin 150. It can suppress being covered.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  In each of the embodiments described above, the inner edge pattern is composed of the lands 61 and 62. However, the inner edge pattern is not mounted with the lands 61 and 62 and the electronic components 121 to 123, and the bonding wires 142 and 143 are not mounted. May be provided with a pattern that is not connected.

  In each of the above embodiments, the surface pattern 63 may have a surface roughness of the surface 63 a and the side surface 63 b smaller than that of the land 62 covered with the solder resist 110.

  Furthermore, in the said 2nd Embodiment, the height from the surface 30a of the buildup layer 30 of the solder resist 110 in the type | mold step part 64 is made from the surface 30a of the buildup layer 30 of the part which covers the surface pattern 63 among the solder resists 110. If the height is greater than or equal to, the following may be performed. For example, when the surface pattern 63 and the surface layer conductor 65 are patterned in the step of FIG. 5C, metal plating or the like may be formed only on the surface layer conductor 65.

DESCRIPTION OF SYMBOLS 10 Multilayer substrate 20 Core layer 20a Surface 30 Buildup layer 30a One surface 51 Inner layer wiring 61, 62 Land 63 Surface pattern 63b Side surface 110 Protective film 121-123 Electronic component

Claims (4)

A core layer (20) having a surface (20a);
An inner wiring (51) formed on the surface of the core layer;
A buildup layer (30) arranged in a state of covering the inner layer wiring on the surface of the core layer;
The buildup layer has a land (61) formed on one surface (30a) opposite to the core layer, on which electronic components (121 to 123) are mounted, and is molded resin (150) together with the electronic components. Inner edge patterns (61, 62) to be sealed;
Outer edge patterns (63, 65) formed around a portion of the one surface of the buildup layer where the inner edge pattern is formed and exposed from the mold resin (150);
A protective film (110) covering a part of the inner edge pattern and the outer edge pattern,
The outer edge pattern is a plate having a side surface (63b), and at least the surface roughness of the side surface is smaller than the surface roughness of the portion of the inner edge pattern covered with the protective film. Multilayer board. The outer edge pattern is electrically insulated from the inner edge pattern and the surface pattern, and is surrounded by the surface pattern (63) electrically connected to the inner edge pattern and the inner layer wiring, and surrounds the inner edge pattern and the inner edge pattern and the A frame-shaped surface conductor (65) formed between the surface pattern and at least the surface roughness of the side surface of the surface conductor is smaller than the surface roughness of the portion covered with the protective film in the inner edge pattern And
The height of the part of the protective film covering the surface conductor from the one surface of the buildup layer is equal to or higher than the height of the part of the protective film covering the surface pattern from the one surface of the buildup layer. The multilayer substrate according to claim 1, wherein the multilayer substrate is formed. The multilayer substrate according to claim 1 or 2,
The electronic component mounted on the land;
An electronic device comprising: a mold resin (150) for sealing the electronic component and the inner edge pattern. In the manufacturing method of the electronic device according to claim 3,
Preparing the multilayer substrate;
Mounting the electronic component on the land of the inner edge pattern;
Forming the mold resin for sealing the electronic component and the inner edge pattern,
In the step of forming the molding resin, a mold (200) having a recess (201) formed on one surface (200a) is prepared, and the electronic component and the inner edge pattern are arranged in the recess. A method for manufacturing an electronic device, comprising: pressing a surface of a mold against the multilayer substrate; and then filling the space between the multilayer substrate and the recess with the mold resin.

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