WO2014194638A1 - 像素电路及其驱动方法和像素阵列结构 - Google Patents

像素电路及其驱动方法和像素阵列结构 Download PDF

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Publication number
WO2014194638A1
WO2014194638A1 PCT/CN2013/089522 CN2013089522W WO2014194638A1 WO 2014194638 A1 WO2014194638 A1 WO 2014194638A1 CN 2013089522 W CN2013089522 W CN 2013089522W WO 2014194638 A1 WO2014194638 A1 WO 2014194638A1
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Prior art keywords
node
thin film
film transistor
data signal
module
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PCT/CN2013/089522
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English (en)
French (fr)
Inventor
段立业
王俪蓉
吴仲远
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京东方科技集团股份有限公司
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Priority to US14/355,470 priority Critical patent/US9123291B2/en
Publication of WO2014194638A1 publication Critical patent/WO2014194638A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit and a driving method, and a pixel array structure. Background technique
  • the organic electroluminescence display shows that the brightness of the OLED is proportional to the drive current through it, so the pixel circuit must provide a constant and stable drive current for the entire frame period.
  • the OLED pixel circuit driving method can be divided into current driving and voltage driving, as shown in FIG. 1 and FIG. 2, respectively.
  • I 0LED — ⁇ ⁇ - Cox (Vdata - Noled - Vth)
  • ⁇ ⁇ is the carrier mobility
  • C. x is the gate oxide capacitance
  • W/L is the transistor width to length ratio
  • V data is the data voltage
  • Led is the OLED operating voltage, shared by all sub-pixel units
  • Vth is the threshold voltage of the transistor.
  • Vth is a positive value
  • Vth is a negative value. Therefore, if the Vths between different pixel units are different, there is also a difference in current. If the Vth of a pixel drifts over time, it may cause a change in current over time, resulting in afterimages. And because the OLED device non-uniformity causes the operating voltage of the OLED to be different, it also causes a current difference.
  • FIG. 3 a current-driven pixel driving circuit structure
  • FIG. 4 is a timing chart of the circuit structure shown in FIG. 3. As can be seen from the two figures, the circuit is divided into two stages: a pre-charging stage T1 and illuminating phase t2.
  • Embodiments of the present invention provide a pixel circuit and a driving method, and a pixel array structure for reducing charging time of an OLED pixel circuit.
  • a pixel circuit provided by the embodiment of the invention includes: a load control module, a load module, a grayscale selection module, a driving module, and a light emitting component, wherein
  • the load control module is connected to the first scan signal line and the data signal line for controlling the first scan signal, and outputting the analog data signal through the first node and the second node;
  • the load module is respectively connected to the first power terminal, the driving module, and the first node and the second node, configured to be controlled by the first node signal and the second node signal, and store the analog data signal under the action of the first power source And providing an analog data signal to the driver module;
  • the gray scale selection module is connected to the second scan signal line and the data signal line for controlling the second scan signal, and transmitting the digital data signal to the third node located in the gray scale selection module;
  • the driving module is controlled by the second node signal and the third node signal for driving the light emitting component; the first end of the light emitting component is connected to the second power terminal, the second end is connected to the driving module, and the second power source and the driving The module emits light under the influence of the module.
  • a pixel array structure includes a plurality of column drivers and a plurality of matrix arrays of the pixel circuits, and the column driver is configured to output a data signal to the pixel circuits.
  • the first stage the data signal line outputs an analog data signal, the load control module transmits the analog data signal to the load module, and stores the analog data signal in the load module, the light emitting element does not emit light;
  • the second stage the data signal line outputs the number a data signal, the digital data signal is transmitted to the third node, and the light emitting element does not emit light;
  • the third stage the data signal line outputs a hold signal, and the driving module drives the light emitting element to emit light according to the second node signal and the third node signal.
  • Embodiments of the present invention provide a pixel circuit structure and a driving method thereof, and a pixel array structure.
  • a pixel circuit provided by the embodiment of the present invention includes: a load control module, a load module, a grayscale selection module, a driving module, and a light emitting component, wherein the load control module is connected to the first scan signal line and the data signal line, Controlling the first scan signal, outputting an analog data signal through the first node and the second node; the load module is respectively connected to the first power terminal, the driving module, and the first node and the second node, for controlling a node signal and a second node signal, and storing an analog data signal under the action of the first power source, and providing an analog data signal to the driving module; the gray scale selection module is connected to the second scan signal line and the data signal line, Controlled by the second scan signal, the digital data The signal is transmitted to the third node located in the gray-scale selection module; the driving module is controlled by the second node signal and the third node
  • FIG. 1 is a schematic diagram showing the basic structure of a voltage type driving circuit in the prior art
  • FIG. 2 is a schematic diagram showing the basic structure of a current-type driving circuit in the prior art
  • FIG. 3 is a schematic structural view of a current-type driving circuit in the prior art
  • FIG. 4 is a timing chart of the circuit structure shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a pixel circuit according to Embodiment 1 of the present invention.
  • FIG. 6 is a timing chart of the pixel circuit shown in FIG. 5;
  • FIG. 7 is a schematic structural diagram of a pixel circuit according to Embodiment 2 of the present invention.
  • FIG. 8 is a simulation simulation timing diagram of the pixel circuit shown in FIG. 7;
  • FIG. 9 is a schematic structural diagram of a pixel circuit according to Embodiment 3 of the present invention.
  • Figure 10 is a timing diagram of the pixel circuit shown in Figure 9;
  • FIG. 11 is a schematic structural diagram of a pixel circuit according to Embodiment 4 of the present invention.
  • FIG. 12 is a schematic diagram of a structure of a pixel array according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a pixel circuit and a driving method, and a pixel array structure for reducing d, charging time of an OLED pixel circuit.
  • a pixel circuit provided by the embodiment of the invention includes: a load control module, a load module, a grayscale selection module, a driving module, and a light emitting component, wherein
  • the load control module is connected to the first scan signal line and the data signal line for controlling the first scan signal, and outputting the analog data signal through the first node and the second node;
  • the load module is respectively connected to the first power terminal, the driving module, and the first node and the second node, configured to be controlled by the first node signal and the second node signal, and store the analog data signal under the action of the first power source And providing an analog data signal to the driver module;
  • the gray scale selection module is connected to the second scan signal line and the data signal line for controlling the second scan Transmitting a digital data signal to a third node located in the grayscale selection module; the driving module is controlled by the second node signal and the third node signal for driving the light emitting component; the first end of the light emitting component The second power terminal is connected, and the second end is connected to the driving module to emit light under the action of the second power source and the driving module.
  • the load control module includes a first thin film transistor and a second thin film transistor, wherein
  • the gate of the first thin film transistor is connected to the first scan signal line, the source is connected to the data signal line, and the drain is connected to the first node in the load control module;
  • the gate of the second thin film transistor is connected to the first scan signal line, the source is connected to the data signal line, and the drain is connected to the second node in the load control module.
  • the source and the drain of the thin film transistor used in the embodiment of the present invention are symmetrical, the source and the drain are interchangeable.
  • one of the poles is referred to as a source and the other pole is referred to as a drain. If the source is selected as the signal input, the drain is used as the signal output, and vice versa.
  • the load module includes a first storage capacitor and a third thin film transistor, wherein the first storage capacitor is located between the second node and the first power terminal; and the third thin film transistor The gate is connected to the first end of the first storage capacitor, the source is connected to the first node, and the drain is connected to the first power terminal.
  • the load module further includes a fourth thin film transistor, wherein a gate and a source of the fourth thin film transistor are connected to a second power terminal, and a drain is connected to the first node.
  • the gray scale selection module includes a fifth thin film transistor, a gate of the fifth thin film transistor is connected to the second scan signal line, a source is connected to the data signal line, and a drain is connected to the third node.
  • the driving module includes a second storage capacitor, a sixth thin film transistor, a seventh thin film transistor, and an eighth thin film transistor, wherein
  • the second storage capacitor is located between the third node and the first power terminal; the gate of the sixth thin film transistor is connected to the third node, the source is connected to the second end of the light emitting element, and the drain is connected The source of seven thin film transistors;
  • the gate of the seventh thin film transistor is connected to the second node, the source is connected to the drain of the sixth thin film transistor, and the drain is connected to the first power terminal;
  • the gate of the eighth thin film transistor is connected to the second node, the source is connected to the second end of the light emitting element, and the drain is connected to the first power terminal.
  • the ratio of the aspect ratio of the seventh thin film transistor to the aspect ratio of the eighth thin film transistor is greater than one. Since the sixth thin film transistor, the seventh thin film transistor, and the eighth thin film transistor constitute a current mirror structure, a ratio of a current flowing through the seventh thin film transistor and a current flowing through the eighth thin film transistor is proportional to a width and a length of the seventh thin film transistor.
  • a ratio of a width to a length ratio of the eighth thin film transistor and a current flowing through the third thin film transistor is a sum of a current flowing through the seventh thin film transistor and a current flowing through the eighth thin film transistor, and three sets are set by The proportional relationship of the thin film transistors allows the current flowing through the third thin film transistor to be the analog data current of the data signal line.
  • the ratio of the aspect ratio of the seventh thin film transistor to the aspect ratio of the eighth thin film transistor is N
  • the aspect ratio of the third thin film transistor, the aspect ratio of the seventh thin film transistor, and The ratio of the aspect ratio of the eighth thin film transistor is N+1: N:1
  • the seventh thin film transistor and the eighth thin film transistor are simultaneously turned on, the current value flowing through the seventh thin film transistor flows through the eighth thin film transistor
  • the ratio of the current values is also N.
  • the light emitting element is an organic light emitting diode OLED.
  • a pixel array structure provided by an embodiment of the present invention includes a plurality of pixel circuits arranged in a matrix and a plurality of column drivers.
  • Each pixel unit includes three sub-pixel units, and each of the sub-pixel units corresponds to a pixel circuit for driving the OLED in the driving circuit to realize display.
  • the column driver comprises a plurality of semi-digital current sources for outputting digital data signals and analog data signals.
  • the current source mainly outputs an analog data signal, that is, a driving current corresponding to the brightness of the picture to be displayed for each frame, and the magnitude of the current value of the data signal depends on the brightness value of each frame picture. Therefore, it is generally different, and the brightness has high and low gray levels.
  • the monochrome has a total of 8 bits and 256 gray levels.
  • the 0-31 gray level is a low gray level
  • the 32-255 gray level is a high gray level.
  • the driving current is small, so the process of charging the capacitors takes a long time.
  • a semi-digital current source provided by an embodiment of the present invention corresponds to positive and negative current digital data signals for high gray scale and low gray scale images, respectively.
  • a current higher than the low gray level can be output as an analog data signal, but by outputting a negative digital data signal (negative current), only a current corresponding to the low gray scale picture is passed through the light emitting element. , thereby increasing the charging current, reducing the charging time, and achieving the purpose of low gray scale display.
  • the column driver includes a current source and a voltage source, the current source outputting an analog data signal, the voltage source outputting a digital data signal.
  • the positive and negative voltage digital data signals are respectively associated.
  • a low grayscale picture needs to be displayed, it is possible to output a current higher than the low gray level as an analog data signal, but by outputting a negative digital data signal (negative voltage), Controlling only the current corresponding to the low gray scale picture flows through the light emitting element, thereby increasing the charging current, reducing the charging time, and achieving the purpose of low gray scale display.
  • the first stage the data signal line outputs an analog data signal, the load control module transmits the analog data signal to the load module, and stores the analog data signal in the load module, the light emitting element does not emit light;
  • the second stage the data signal line outputs the number a data signal, the digital data signal is transmitted to the third node, and the light emitting element does not emit light;
  • the third stage the data signal line outputs a hold signal, and the driving module drives the light emitting element to emit light according to the second node signal and the third node signal.
  • the digital data signal is a positive current or a positive voltage in the second stage
  • the digital data signal is a negative current or a negative voltage in the second phase.
  • all of the thin film transistors are N-type thin film transistor TFTs, the N-type TFTs are turned on at a high level, and turned off at a low level, the first power source is a negative power source VSS, and the second power source is a positive power source VDD.
  • the data signal line is provided by the semi-digital current source, and the following embodiments are the same, and are not described herein.
  • a pixel circuit 1 includes: a load control module 101, a load module 102, a grayscale selection module 103, a driving module 104, and a light emitting component 105, wherein the load control module 101 is connected to the first scan signal line scan1 and the data line Idata, controlled by the first scan signal, and output an analog data signal through the first node A1 and the second node A2;
  • the load module 102 is connected to the first power terminal VSS, the driving module 104, and the first node A1 and the second node A2, respectively, for controlling the first node signal and the second node signal, and is under the action of the first power source. And storing an analog data signal, and providing an analog data signal to the driving module 104; the gray scale selecting module 103 is connected to the second scan signal line scan2 and the data signal line Idata for controlling the second scan signal, and the digital data signal Transmitted to the third node A3 located in the grayscale selection module 103;
  • the driving module 104 is controlled by the second node A2 signal and the third node A3 signal for driving Moving light element 105;
  • the first end of the light emitting element 105 is connected to the second power terminal VDD, and the second end is connected to the driving module 104 to emit light under the action of the second power source and the driving module.
  • the load control module includes a first thin film transistor T101 and a second thin film transistor T102, wherein
  • the gate of the first thin film transistor T101 is connected to the first scan signal line scan1, the source is connected to the data signal line I data , and the drain is connected to the first node A1 in the load control module 101;
  • the second thin film transistor T102 is connected to the gate of the first scanning signal line scanl, a source connected to the data signal line I data, a drain connected to a second node located A2 load control module 101.
  • the load module 102 includes a first storage capacitor C11 and a third thin film transistor T103, wherein the first storage capacitor C11 is located between the second node A2 and the first power terminal VSS;
  • the gate of the third thin film transistor T103 is connected to the first end of the first storage capacitor C11, the source is connected to the first node A1, and the drain is connected to the first power terminal VSS.
  • the gray scale selection module 103 includes a fifth thin film transistor T105, the fifth thin film transistor
  • T105 is connected to a second gate signal line scanning scan2, a source connected to the data signal line I data, a drain connected to the third node A3.
  • the driving module 104 includes a second storage capacitor C12, a sixth thin film transistor T106, a seventh thin film transistor T107, and an eighth thin film transistor T108, where
  • the second storage capacitor C12 is located between the third node A3 and the first power terminal VSS;
  • the gate of the sixth thin film transistor T106 is connected to the third node A3, the source is connected to the second end of the light emitting element 105, and the drain is connected to the source of the seventh thin film transistor T107;
  • the gate of the seventh thin film transistor T107 is connected to the second node ⁇ 2, the source is connected to the drain of the sixth thin film transistor T106, the drain is connected to the first power terminal VSS, and the gate of the eighth thin film transistor T108 is connected to the second
  • the node ⁇ 2 has a source connected to the second end of the light emitting element 105 and a drain connected to the first power terminal VSS.
  • the ratio of the aspect ratio of the third thin film transistor, the seventh thin film transistor, and the eighth thin film transistor is N+1: N:1.
  • the driving method of the pixel circuit provided by the embodiment of the present invention is described in detail below. This is illustrated in conjunction with the timing diagram shown in FIG. 6, wherein the timing diagram illustrates two frame periods, with the first period VI. Give an example for a detailed description.
  • a method for driving a pixel circuit according to Embodiment 1 of the present invention includes: a first stage T11: a first scan signal scan1 is a high level, a second scan signal scan2 is a low level, and a second power source
  • the terminal VDD outputs a low level
  • the data signal line Idata outputs an analog data signal
  • the load control module 101 transmits the analog data signal to the load module 102, and stores the analog data signal in the load module 102, and the light emitting element 105 does not emit light;
  • the T11 time is the pre-charging phase, the transistors T101 ⁇ T103 are turned on, and the remaining transistors are turned off. This process completes the charging process of the capacitor C11. Since VDD is low level, the light-emitting element OLED does not emit light; During T11, the data signal is a low-level, low-current analog data signal.
  • the second stage T12 the first scan signal scan1 is low level, the second scan signal scan2 is high level, the second power supply terminal VDD outputs a low level, the data signal line Idata outputs a digital data signal, and the digital data signal is transmitted to The third node A3, the light-emitting element 105 does not emit light;
  • the T12 time is a discharge phase.
  • T101, T102 are turned off, ⁇ 103, ⁇ 107, T108 are turned on. Since the low-gray analog data signal is input in the Til phase, Idata is a negative digital data signal in this phase, so C12 is discharged and T106 is turned off. Assume that the width to length ratio of transistors T107 and T108 is ⁇ :1, in which case only the current of T108 flows through the OLED.
  • the third stage T13 the first scan signal scan1 and the second scan signal scan2 are both low level, the second power supply terminal VDD outputs a high level, the data signal line outputs a hold signal, and the driving module 104 according to the second node A2 signal And the third node A3 signal drives the light emitting element 105 to emit light;
  • the input digital data signal Idata is a high gray level signal
  • C12 is charged and T106 is turned on
  • T13 phase since VDD is high level, the OLED is turned on
  • the current flowing through the OLED includes the currents of T107 and T108, and the ratio of T103 to T103 shows that, in this case, loled is a large current corresponding to a high gray level.
  • the load module 102 further includes a fourth thin film transistor T104, wherein the gate and the source of the fourth thin film transistor T104 are connected.
  • the two power terminals VDD and the drain are connected to the first node A1 as shown in FIG.
  • the driving method of Embodiment 2 of the present invention is different from the pixel circuit of Embodiment 1 in the third stage: T104 is turned on to prevent T103 from entering the deep linear region, preventing the drain voltage drop of T103 from interfering with the gate voltage of T103, thereby enabling It is ensured that T103 can operate in the saturation region to supply current to the seventh thin film transistor T107 and the eighth thin film transistor T108.
  • the addition of the fourth thin film transistor optimizes the pixel circuit structure.
  • Embodiment 2 of the present invention is shown in FIG. 8, and two frame periods are taken as an example for description. Among them, in the first frame period, the low gray level current of ⁇ is written into the pixel, and the high gray level current of 3 ⁇ A is written into the pixel in the second frame period. Moreover, for the structure shown in Fig. 7, the width to length ratio of T107 and T108 is selected to be 9:1. Therefore, in the first stage, the current ⁇ of 10 times ⁇ is used as the analog data signal input. As can be seen from the figure, the Ioled obtained in the first period is ⁇ ; in the second frame period, T107 and T108 are simultaneously Working, the input analog data signal is 3 ⁇ ⁇ . As can be seen from the figure, the current of the Ioled is approximately 3 ⁇ A after the scan is completed.
  • all the TFTs in the third embodiment of the present invention are P-type TFTs, and both are turned on at a low level, and the high level is turned off, the first power source is a positive power source VDD, and the second power source is a negative power source. VSS.
  • the structure of the pixel circuit described in the third embodiment is as shown in FIG. 9, and the timing chart thereof is as shown in FIG. 10. Therefore, the driving method thereof includes:
  • the driving method of the pixel circuit provided in Embodiment 3 of the present invention includes:
  • the first stage T21 the first scan signal scan1 is at a low level, the second scan signal scan2 is at a high level, the second power supply terminal VSS outputs a high level, and the data signal line outputs an analog data signal, and the load control module 101
  • the analog data signal is transmitted to the load module 102, and the analog data signal is stored in the load module 102, and the light emitting element 105 does not emit light;
  • the T21 time is the pre-charging stage, the transistors T201 ⁇ T203 are turned on, and the remaining transistors are turned off. This process completes the charging process of the capacitor C21. Since VSS is at a high level, the light-emitting element OLED does not emit light; During T21, the data signal is a low-level, low-current analog data signal.
  • the second stage ⁇ 22 the first scan signal scanl is at a high level, the second scan signal scan2 is at a low level, the second power supply terminal VSS outputs a high level, the data signal line outputs a digital data signal, and the digital data signal is transmitted to the first The three-node A3, the light-emitting element 105 does not emit light;
  • the T22 time is a discharge phase.
  • T201, ⁇ 202 is turned off, ⁇ 203, ⁇ 207, T208 is turned on.
  • Idata is a negative digital data signal in this phase, so C22 is discharged and T206 is turned off.
  • the width to length ratio of the transistors T207 and T208 is N: 1, in which case only the current of T208 flows through the OLED.
  • the third stage T23 the first scan signal scan1 and the second scan signal scan2 are both high level, the second power supply terminal VSS outputs a low level, the data signal line outputs a hold signal, and the driving module 104 according to the second node A2 signal And the third node A3 signal drives the light emitting element 105 to emit light;
  • the input digital data signal is a high gray level signal
  • C22 is charged, and T206 is turned on
  • VSS is low level
  • the OLED is turned on, then Since T206 is turned on, the current flowing through the OLED includes the currents of T207 and T208, and the ratio of T203 to T203 shows that, in this case, Ioled is a large current corresponding to high gray scale.
  • the load module includes a fourth thin film transistor T204, wherein a gate and a source of the fourth thin film transistor T204 are connected to the second power supply terminal VSS, and the drain connection is A node A1, as shown in Figure 11.
  • the driving method of the embodiment 4 of the present invention is different from the driving method of the pixel circuit in the third embodiment:
  • T204 is turned on to prevent T203 from entering the deep linear region, preventing the T203 drain voltage drop from interfering with the T203 gate voltage, thereby ensuring that T203 can operate in the saturation region, providing the seventh thin film transistor T207 and the eighth thin film transistor T208. Current.
  • the addition of the fourth thin film transistor optimizes the pixel circuit structure.
  • a pixel array structure provided by an embodiment of the present invention includes a plurality of matrix circuits 1 and a plurality of column drivers.
  • the column driver includes a plurality of semi-digital current sources.
  • SI S11, S12, S13, etc.
  • the semi-digital current source SI is used to output digital data signals and analog data signals; the embodiment of the present invention employs a semi-digital current source, which is an alternative.
  • the analog data signal and the digital data signal in the form of current are sequentially output through a current source, that is, when the current value of the analog data signal in the first stage is at 32 gray scales Current or 32 gradation current above, as described in the second phase
  • the digital data signal is a positive current; when the current value of the analog data signal in the first stage is below the current of the 31 gray level, the digital data signal is a negative current in the second stage.
  • a semi-digital current source is convenient for implementation and tubular construction.
  • the column driver includes a current source and a voltage source (VDD1, VDD2, etc.), wherein the current source outputs an analog data signal in the form of a current, and a digital data signal in the form of a voltage source output voltage. That is, when the current value of the analog data signal in the first stage is above 32 gray level current or 32 gray level current, the digital data signal is positive voltage in the second stage; When the current value of the data signal is below the current of the 31 gray scale, the digital data signal is a negative voltage in the second phase.
  • FIG. 12 is only a partial schematic diagram of the pixel array structure, and is not an entire array pixel structure.
  • a pixel circuit provided by the embodiment of the present invention includes: a load control module, a load module, a grayscale selection module, a driving module, and a light emitting component, wherein the load control module is connected to the first scan signal line and the data signal line, Controlling the first scan signal, outputting an analog data signal through the first node and the second node; the load module is respectively connected to the first power terminal, the driving module, and the first node and the second node, for controlling a node signal and a second node signal, and storing an analog data signal under the action of the first power source, and providing an analog data signal to the driving module; the gray scale selection module is connected to the second scan signal line and the data signal line, Controlling the second scan signal, transmitting the digital data signal to a third node located in the grayscale selection module; the driving module is controlled by the second node signal and the third node signal for driving the light
  • the load module stores the analog signal
  • the driving module is controlled by the signals of the second node and the third node to selectively drive the light-emitting component.
  • the multi-current programming input is used to speed up charging. time.
  • the current of the corresponding TFT is turned off, so that a low gray level current flows through the OLED to achieve low gray scale display; when it is required to display a high gray scale picture, the input is high gray.
  • the current corresponding to the order ensures a short charging time.
  • the pixel circuit provided by the embodiment of the invention can effectively reduce the charging time and improve the display effect.
  • embodiments of the present invention can be provided as a method, system, or computer program product.
  • embodiments of the present invention may employ an entirely hardware embodiment, fully software implemented For example, or in combination with an embodiment of software and hardware aspects.
  • embodiments of the invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • Embodiments of the invention are described with reference to flowchart illustrations and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowcharts and/or block diagrams, and combinations of flows and/or blocks in the flowcharts and/or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general purpose computer, dedicated computing, instructions executed by a processor of a computer or other programmable data processing device, for generating a block or multiples in a flow or a flow and/or block diagram of a flowchart The device for the function specified in the box.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

Abstract

像素电路及其驱动方法、像素阵列结构。像素电路包括负载控制模块（101）、负载模块（102）、灰阶选择模块（103）、驱动模块（104）和发光元件（105）。负载控制模块（101）受控于第一扫描信号线（scan1），将数据信号存储在第一节点（A1）和第二节点（A2）。负载模块（102）分别连接第一电源端子（VSS）、驱动模块（104）、第一节点（A1）和第二节点（A2），受控于第一节点信号和第二节点信号，将模拟数据信号存储在该负载模块（102），并向驱动模块（104）提供模拟数据信号。灰阶选择模块（103）受控于第二扫描信号线（scan2），将数字数据信号传输给位于灰阶选择模块（103）的第三节点（A3）。驱动模块（104）受控于第二节点信号和第三节点信号，驱动发光元件（105）。发光元件（105）的第一端连接第二电源端子（VDD），第二端连接驱动模块（104）。上述像素电路可以减小OLED像素电路的充电时间。

Description

像素电路及其驱动方法和像素阵列结构 技术领域
本发明涉及显示技术领域， 尤其涉及一种像素电路及驱动方法， 以及一种 像素阵列结构。 背景技术
有机电致发光显示 OLED的亮度与通过它的驱动电流成正比，所以像素电 路必须在整个帧周期为其提供持续稳定的驱动电流。 目前 OLED像素电路驱动 方式可分为电流驱动和电压驱动， 分别如图 1和图 2所示。
在电压驱动电路中， 流经发光元件的电流 I。led为：
1 W 2
I0LED =—μη - Cox (Vdata - Noled - Vth)
2 L
其中 μ η为载流子迁移率， C。x为栅氧化层电容， W/L为晶体管宽长比， Vdata 为数据电压， V。led为 OLED工作电压， 为所有子像素单元共享， Vth为晶体管 的阈值电压。 对于增强型薄膜晶体管 TFT, Vth为正值， 对于耗尽型 TFT, Vth 为负值。 因此， 如果不同像素单元之间的 Vth不同， 则电流也存在差异。 如果 像素的 Vth随时间发生漂移， 则可能造成电流随时间发生变化， 导致残影。 且 由于 OLED器件非均匀性引起 OLED的工作电压不同， 也会导致电流差异。
而电流驱动相比电压驱动的优点是： 电流 I。led=Idata, 如果像素的阈值电压 随着时间发生漂移， 电流驱动电路具有自主调整当前水平的能力，与 TFT器件 本身的 Vth无关， 可以实现空间上均匀和时间上稳定的显示。 但由于驱动时间 较长， 电流型驱动电路一般用于小尺寸面板。 如图 3所示的一种电流驱动型像 素驱动电路结构，图 4为图 3所示的电路结构的时序图，从两幅图中可以看出， 此电路分为两个阶段： 预充阶段 tl和发光阶段 t2。 在 tl阶段， ARVDD为低电 平， SCAN为高电平， 晶体管 M4关断， Cs充电； 第二阶段， ARVDD为高电 平， SCAN为低电平， 晶体管 Ml和 M2关断， OLED发光。 此类电流型驱动 像素电路有个很大的缺陷是， 电容充电时间过长， 影响显示， 且抑制了电流型 驱动电路的大规模应用。 发明内容 本发明实施例提供了一种像素电路及驱动方法、 一种像素阵列结构， 用以 减小 OLED像素电路的充电时间。
本发明实施例提供的一种像素电路， 包括： 负载控制模块、 负载模块、 灰 阶选择模块、 驱动模块和发光元件， 其中，
所述负载控制模块连接第一扫描信号线和数据信号线， 用于受控于第一扫 描信号， 通过第一节点和第二节点输出模拟数据信号；
所述负载模块分别连接第一电源端子、 驱动模块以及第一节点和第二节 点， 用于受控于第一节点信号和第二节点信号， 并且在第一电源的作用下， 存 储模拟数据信号， 并向驱动模块提供模拟数据信号；
所述灰阶选择模块连接第二扫描信号线和数据信号线， 用于受控于第二扫 描信号， 将数字数据信号传输给位于灰阶选择模块的第三节点；
所述驱动模块受控于第二节点信号和第三节点信号， 用于驱动发光元件； 所述发光元件的第一端连接第二电源端子， 第二端连接驱动模块， 在第二 电源和驱动模块的作用下发光。
本发明实施例提供的一种像素阵列结构， 包括多个列驱动器和多个矩阵排 列的上述的像素电路， 所述列驱动器用于给所述像素电路输出数据信号。
本发明实施例提供的一种像素电路的驱动方法， 包括：
第一阶段： 数据信号线输出模拟数据信号， 所述负载控制模块将模拟数据 信号传输给负载模块， 并将模拟数据信号存储在负载模块， 发光元件不发光； 第二阶段： 数据信号线输出数字数据信号， 将数字数据信号传输给第三节 点， 发光元件不发光；
第三阶段： 数据信号线输出保持信号， 所述驱动模块根据第二节点信号和 第三节点信号驱动发光元件发光。
本发明实施例提供了一种像素电路结构及其驱动方法， 以及像素阵列结 构。 本发明实施例提供的一种像素电路， 包括： 负载控制模块、 负载模块、 灰 阶选择模块、 驱动模块和发光元件， 其中， 所述负载控制模块连接第一扫描信 号线和数据信号线， 用于受控于第一扫描信号， 通过第一节点和第二节点输出 模拟数据信号； 所述负载模块分别连接第一电源端子、 驱动模块以及第一节点 和第二节点， 用于受控于第一节点信号和第二节点信号， 并且在第一电源的作 用下， 存储模拟数据信号， 并向驱动模块提供模拟数据信号； 所述灰阶选择模 块连接第二扫描信号线和数据信号线， 用于受控于第二扫描信号， 将数字数据 信号传输给位于灰阶选择模块的第三节点； 所述驱动模块受控于第二节点信号 和第三节点信号， 用于驱动发光元件； 所述发光元件的第一端连接第二电源端 子， 第二端连接驱动模块， 在第二电源和驱动模块的作用下发光。 负载模块存 储模拟信号， 驱动模块受控于第二节点和第三节点的信号， 选择性的驱动发光 元件， 能够在正常显示的情况下减小 OLED像素电路的充电时间。 附图说明
图 1为现有技术中电压型驱动电路的基本结构示意图；
图 2为现有技术中电流型驱动电路的基本结构示意图；
图 3为现有技术中一种电流型驱动电路的结构示意图；
图 4为图 3所示的电路结构的时序图；
图 5为本发明实施例 1提供的一种像素电路的结构示意图；
图 6为图 5所示的像素电路的时序图；
图 7为本发明实施例 2提供的一种像素电路的结构示意图；
图 8为图 7所示的像素电路的仿真模拟时序图；
图 9为本发明实施例 3提供的一种像素电路的结构示意图；
图 10为图 9所示的像素电路的时序图；
图 11为本发明实施例 4提供的一种像素电路的结构示意图；
图 12为本发明实施例提供的一种像素阵列结构的示意图。 具体实施方式
本发明实施例提供了一种像素电路及驱动方法、 及一种像素阵列结构， 用 以减 d、 OLED像素电路的充电时间。
本发明实施例提供的一种像素电路， 包括： 负载控制模块、 负载模块、 灰 阶选择模块、 驱动模块和发光元件， 其中，
所述负载控制模块连接第一扫描信号线和数据信号线， 用于受控于第一扫 描信号， 通过第一节点和第二节点输出模拟数据信号；
所述负载模块分别连接第一电源端子、 驱动模块以及第一节点和第二节 点， 用于受控于第一节点信号和第二节点信号， 并且在第一电源的作用下， 存 储模拟数据信号， 并向驱动模块提供模拟数据信号；
所述灰阶选择模块连接第二扫描信号线和数据信号线， 用于受控于第二扫 描信号， 将数字数据信号传输给位于灰阶选择模块的第三节点； 所述驱动模块受控于第二节点信号和第三节点信号， 用于驱动发光元件； 所述发光元件的第一端连接第二电源端子， 第二端连接驱动模块， 在第二 电源和驱动模块的作用下发光。
可选择地， 所述负载控制模块包括第一薄膜晶体管和第二薄膜晶体管， 其 中，
所述第一薄膜晶体管的栅极连接第一扫描信号线， 源极连接数据信号线， 漏极连接位于负载控制模块中的第一节点；
所述第二薄膜晶体管的栅极连接第一扫描信号线， 源极连接数据信号线， 漏极连接位于负载控制模块中的第二节点。
需要说明的是， 由于在本发明实施例中采用的薄膜晶体管的源极、 漏极是 对称的， 所以其源极、 漏极是可以互换的。 为区分薄膜晶体管除栅极之外的两 极， 将其中一极称为源极， 另一极称为漏极。 若选取源极作为信号输入端、 则 漏极作为信号输出端， 反之亦然。
可选择地， 所述负载模块包括第一存储电容和第三薄膜晶体管， 其中， 所述第一存储电容位于所述第二节点和所述第一电源端子之间； 所述第三薄膜晶体管的栅极连接第一存储电容的第一端， 源极连接第一节 点， 漏极连接第一电源端子。
可选择地， 所述负载模块还包括第四薄膜晶体管， 其中， 所述第四薄膜晶 体管的栅极和源极连接第二电源端子， 漏极连接所述第一节点。
可选择地， 所述灰阶选择模块包括第五薄膜晶体管， 所述第五薄膜晶体管 的栅极连接第二扫描信号线， 源极连接数据信号线， 漏极连接第三节点。
可选择地， 所述驱动模块包括第二存储电容、 第六薄膜晶体管、 第七薄膜 晶体管和第八薄膜晶体管， 其中，
所述第二存储电容位于所述第三节点和所述第一电源端子之间； 所述第六薄膜晶体管的栅极连接第三节点， 源极连接发光元件的第二端， 漏极连接第七薄膜晶体管的源极；
所述第七薄膜晶体管的栅极连接第二节点， 源极连接第六薄膜晶体管的漏 极， 漏极连接第一电源端子；
所述第八薄膜晶体管的栅极连接第二节点， 源极连接发光元件的第二端， 漏极连接第一电源端子。 可选择地， 所述第七薄膜晶体管的宽长比和第八薄膜晶体管的宽长比的比 值大于 1。 由于第六薄膜晶体管、 第七薄膜晶体管和第八薄膜晶体管组成电流 镜结构， 因此流过第七薄膜晶体管的电流和流过第八薄膜晶体管的电流的比 值，正比于第七薄膜晶体管的宽长比和第八薄膜晶体管的宽长比的比值，同时， 流过第三薄膜晶体管的电流为流过第七薄膜晶体管的电流与流过第八薄膜晶 体管的电流之和， 且通过设定三个薄膜晶体管的比例关系， 可以使流过第三薄 膜晶体管的电流即为数据信号线的模拟数据电流。 例如， 可选择的， 若第七薄 膜晶体管的宽长比和第八薄膜晶体管的宽长比的比值为 N, 则可设第三薄膜晶 体管的宽长比、第七薄膜晶体管的宽长比和第八薄膜晶体管的宽长比的比值为 N+1: N:l , 当第七薄膜晶体管和第八薄膜晶体管同时导通时， 流过第七薄膜晶 体管的电流值和流过第八薄膜晶体管的电流值的比值也为 N。
可选择地， 所述发光元件为有机发光二极管 OLED。
本发明实施例提供的一种像素阵列结构， 包括矩阵排列的多个像素电路和 多个列驱动器。 每一像素单元包括三个子像素单元， 每一子像素单元对应一像 素电路， 该像素电路用于驱动电路中的 OLED发光， 从而实现显示。
可选择地， 所述列驱动器包括多个半数字化电流源， 所述半数字化电流源 用于输出数字数据信号和模拟数据信号。 在现有技术中， 电流源主要输出模拟 数据信号， 也就是对应每一帧需要显示的画面的亮度所对应的驱动电流， 该数 据信号的电流值的大小， 取决于各帧画面的亮度值， 因而一般是不同的， 亮度 有高、 低灰阶之分。 一般的， 对于 RGB 24位的色彩， 单色共有 8位 256灰阶， 在此， 0-31灰阶为低灰阶， 32-255灰阶为高灰阶。 而对于低灰阶图像的显示， 其驱动电流很小， 因此对电容充电的过程将耗时较长。 本发明实施例提供的一 种半数字化电流源， 对于高灰阶和低灰阶的图像， 分别对应正负电流数字数据 信号。 当需要显示低灰阶画面时， 可以通过输出高于低灰阶的电流作为模拟数 据信号， 但通过输出负的数字数据信号 （负电流）， 控制只有低灰阶画面对应 的电流流过发光元件， 从而加大了充电电流， 减小了充电时间， 同时达到低灰 阶显示的目的。
或者，所述列驱动器包括电流源和电压源，所述电流源输出模拟数据信号， 所述电压源输出数字数据信号。 在此情况下， 对于高灰阶和低灰阶的图像， 分 别对应正负电压数字数据信号。 当需要显示低灰阶画面时， 可以通过输出高于 低灰阶的电流作为模拟数据信号， 但通过输出负的数字数据信号 （负电压）， 控制只有低灰阶画面对应的电流流过发光元件， 从而加大了充电电流， 减小了 充电时间， 同时达到低灰阶显示的目的。
本发明实施例提供的像素电路的驱动方法包括：
第一阶段： 数据信号线输出模拟数据信号， 所述负载控制模块将模拟数据 信号传输给负载模块， 并将模拟数据信号存储在负载模块， 发光元件不发光； 第二阶段： 数据信号线输出数字数据信号， 将数字数据信号传输给第三节 点， 发光元件不发光；
第三阶段： 数据信号线输出保持信号， 所述驱动模块根据第二节点信号和 第三节点信号驱动发光元件发光。
可选择地， 当第一阶段所述模拟数据信号的电流值在 32灰阶的电流或 32 灰阶的电流以上时， 在第二阶段中所述数字数据信号为正电流或正电压；
当第一阶段所述模拟数据信号的电流值在 31灰阶的电流以下时， 在第二 阶段中所述数字数据信号为负电流或负电压。
下面结合附图和具体实施例， 对本发明实施例进行详细介绍。 需要说明的 是， 以下实施例是为了更详细的说明本发明的实施例， 但不用来限制本发明。
实施例 1
本实施例 1中， 所有的薄膜晶体管为 N型薄膜晶体管 TFT, N型 TFT在 高电平时打开， 低电平时关断， 第一电源为负极电源 VSS, 第二电源为正极电 源 VDD。 且可选择的， 数据信号线由半数字化电流源提供数据信号， 以下实 施例均相同， 不在赘述。
如图 5所示， 本发明实施例提供的一种像素电路 1 , 包括： 负载控制模块 101、 负载模块 102、 灰阶选择模块 103、 驱动模块 104和发光元件 105, 其中， 所述负载控制模块 101连接第一扫描信号线 scanl和数据线 Idata, 受控于 第一扫描信号， 通过第一节点 A1和第二节点 A2输出模拟数据信号；
所述负载模块 102分别连接第一电源端子 VSS、驱动模块 104以及第一节 点 A1和第二节点 A2, 用于受控于第一节点信号和第二节点信号， 并且在第一 电源的作用下， 存储模拟数据信号， 并向驱动模块 104提供模拟数据信号； 所述灰阶选择模块 103连接第二扫描信号线 scan2和数据信号线 Idata, 用 于受控于第二扫描信号， 将数字数据信号传输给位于灰阶选择模块 103的第三 节点 A3;
所述驱动模块 104受控于第二节点 A2信号和第三节点 A3信号， 用于驱 动发光元件 105;
所述发光元件 105的第一端连接第二电源端子 VDD, 第二端连接驱动模 块 104, 在第二电源和驱动模块的作用下发光。
其中， 所述负载控制模块包括第一薄膜晶体管 T101和第二薄膜晶体管 T102, 其中，
所述第一薄膜晶体管 T101的栅极连接第一扫描信号线 scanl ,源极连接数 据信号线 Idata, 漏极连接位于负载控制模块 101中的第一节点 A1 ;
所述第二薄膜晶体管 T102的栅极连接第一扫描信号线 scanl ,源极连接数 据信号线 Idata, 漏极连接位于负载控制模块 101中的第二节点 A2。
所述负载模块 102包括第一存储电容 C11和第三薄膜晶体管 T103, 其中， 所述第一存储电容 C11位于所述第二节点 A2和所述第一电源端子 VSS之 间；
所述第三薄膜晶体管 T103的栅极连接第一存储电容 C11的第一端， 源极 连接第一节点 A1 , 漏极连接第一电源端子 VSS。
所述灰阶选择模块 103包括第五薄膜晶体管 T105, 所述第五薄膜晶体管
T105的栅极连接第二扫描信号线 scan2, 源极连接数据信号线 Idata, 漏极连接 第三节点 A3。
所述驱动模块 104包括第二存储电容 C12、第六薄膜晶体管 T106、第七薄 膜晶体管 T107和第八薄膜晶体管 T108, 其中，
所述第二存储电容 C12位于所述第三节点 A3和所述第一电源端子 VSS 之间；
所述第六薄膜晶体管 T106的栅极连接第三节点 A3 , 源极连接发光元件 105的第二端， 漏极连接第七薄膜晶体管 T107的源极；
所述第七薄膜晶体管 T107的栅极连接第二节点 Α2,源极连接第六薄膜晶 体管 T106的漏极， 漏极连接第一电源端子 VSS; 所述第八薄膜晶体管 T108 的栅极连接第二节点 Α2, 源极连接发光元件 105的第二端， 漏极连接第一电 源端子 VSS。
其中， 可选择的， 第三薄膜晶体管、 第七薄膜晶体管和第八薄膜晶体管的 宽长比的比值为 N+1: N: 1。
下面对本发明实施例提供的像素电路的驱动方法进行详细介绍。 结合图 6 所示的时序图进行说明， 其中， 该时序图图示出两个帧周期， 以第一周期 VI 为例进行详细说明。
具体实施过程中，本发明实施例 1提供的一种像素电路的驱动方法，包括： 第一阶段 T11: 第一扫描信号 scanl为高电平， 第二扫描信号 scan2为低 电平， 第二电源端子 VDD输出低电平， 数据信号线 Idata输出模拟数据信号， 所述负载控制模块 101将模拟数据信号传输给负载模块 102, 并将模拟数据信 号存储在负载模块 102, 发光元件 105不发光；
具体实施过程中， 该 T11时间为预充阶段， 晶体管 T101~T103打开， 其 余晶体管关断， 此过程完成了对电容 C11的充电过程， 由于 VDD为低电平， 这时发光元件 OLED不发光； 在 T11时间内，数据信号为一低灰阶的小电流的 模拟数据信号。
第二阶段 T12: 第一扫描信号 scanl为低电平， 第二扫描信号 scan2为高 电平， 第二电源端子 VDD输出低电平， 数据信号线 Idata输出数字数据信号， 将数字数据信号传输给第三节点 A3, 发光元件 105不发光；
具体实施过程中，该 T12时间为放电阶段。 T101、 T102关断， Τ103、 Τ107、 T108打开， 由于 Til阶段输入的是低灰阶模拟数据信号， 因此此阶段中 Idata 是负的数字数据信号， 因此 C12放电， T106关断。 假设晶体管 T107和 T108 的宽长比为 Ν:1 , 在此情况下只有 T108的电流流过 OLED。
第三阶段 T13: 第一扫描信号 scanl和第二扫描信号 scan2均为低电平， 第二电源端子 VDD输出高电平，数据信号线输出保持信号，所述驱动模块 104 根据第二节点 A2信号和第三节点 A3信号驱动发光元件 105发光；
具体实施过程中， 由于 VDD输出高电平，那么在这种情况下 OLED导通， 则电流 loled仅为第一阶段的输入电流的 1/ ( N+l )。 从而在第一阶段输入较大 电流 Idata加快对 C11的充电过程， 但驱动电流 loled较小， 实现低灰阶显示。
当然， 具体实施过程中， 在 T12阶段， 如果输入的数字数据信号 Idata是 高灰阶信号， 那么 C12充电， 同时 T106打开； 接下来在 T13阶段， 由于 VDD 是高电平， 因此 OLED导通， 那么由于 T106打开， 因此流过 OLED的电流包 括 T107和 T108的电流， 与 T103的比例可知， 在这种情况下， loled为对应高 灰阶的大电流。
实施例 2
与实施例 1不同的是， 本发明实施例 2中， 如图 7所示， 负载模块 102还 包括第四薄膜晶体管 T104, 其中， 第四薄膜晶体管 T104的栅极和源极连接第 二电源端子 VDD , 漏极连接第一节点 A1 , 如图 7所示。
本发明实施例 2的驱动方法， 与实施例 1中的像素电路不同的是： 第三阶段： T104打开， 防止 T103进入深线性区， 防止 T103漏极电压下 降对 T103栅压造成干扰，从而能够保证 T103能够工作在饱和区， 为第七薄膜 晶体管 T107和第八薄膜晶体管 T108提供电流。
因此第四薄膜晶体管的加入， 优化了像素电路结构。
本发明实施例 2的仿真模拟结果如图 8所示，以两个帧周期为例进行说明。 其中， 第一帧周期内， 把 ΙΟηΑ的低灰阶电流写入像素， 第二帧周期内把 3 μ A 的高灰阶电流写入像素。 且， 针对图 7所示的结构， T107和 T108的宽长比选 择为 9:1。 因此， 在第一阶段， 以 10倍于 ΙΟηΑ的电流 ΙΟΟηΑ作为模拟数据信 号输入， 从图中可以看出， 第一周期中获得的 Ioled为 ΙΟηΑ; 在第二个帧周期 内， T107和 T108同时工作， 输入的模拟数据信号为 3 μ Α, 从图中看出， 扫 描完成后 Ioled的电流近似为 3 μ A。
实施例 3
与实施例 1不同的是， 本发明实施例 3中所有的 TFT为 P型 TFT, 且均 在低电平打开， 高电平关断， 第一电源为正极电源 VDD, 第二电源为负极电 源 VSS。 本实施例 3所述的像素电路结构如图 9所示， 其时序图如图 10所示， 因此其驱动方法， 包括：
本发明实施例 3提供的像素电路的驱动方法， 包括：
第一阶段 T21: 第一扫描信号 scanl为低电平， 第二扫描信号 scan2为高 电平， 第二电源端子 VSS输出高电平， 数据信号线输出模拟数据信号， 所述 负载控制模块 101将模拟数据信号传输给负载模块 102, 并将模拟数据信号存 储在负载模块 102, 发光元件 105不发光；
具体实施过程中， 该 T21时间为预充阶段， 晶体管 T201~T203打开， 其 余晶体管关断， 此过程完成了对电容 C21的充电过程， 由于 VSS为高电平， 这时发光元件 OLED不发光；在 T21时间内，数据信号为一低灰阶的小电流的 模拟数据信号。
第二阶段 Τ22: 第一扫描信号 scanl为高电平， 第二扫描信号 scan2为低 电平， 第二电源端子 VSS输出高电平， 数据信号线输出数字数据信号， 将数 字数据信号传输给第三节点 A3, 发光元件 105不发光；
具体实施过程中，该 T22时间为放电阶段。 T201、 Τ202关断， Τ203、 Τ207、 T208打开， 由于 T21阶段输入的是低灰阶模拟数据信号， 因此此阶段中 Idata 是负的数字数据信号， 因此 C22放电， T206关断。 假设晶体管 T207和 T208 的宽长比为 N: 1 , 在此情况下只有 T208的电流流过 OLED。
第三阶段 T23: 第一扫描信号 scanl和第二扫描信号 scan2均为高电平， 第二电源端子 VSS输出低电平， 数据信号线输出保持信号， 所述驱动模块 104 根据第二节点 A2信号和第三节点 A3信号驱动发光元件 105发光；
具体实施过程中， 由于 VSS输出低电平， 那么在这种情况下 OLED导通， 则电流 Ioled仅为第一阶段的输入电流的 1/ ( N+l )。 从而在第一阶段输入较大 电流加快对 C21的充电过程， 但驱动电流 Ioled较小， 实现低灰阶显示。
当然， 具体实施过程中， 在 T22阶段， 如果输入的数字数据信号是高灰阶 信号， 那么 C22充电， 同时 T206打开； 接下来在 T23阶段， 由于 VSS是低电 平， 因此 OLED导通， 那么由于 T206打开， 因此流过 OLED的电流包括 T207 和 T208的电流， 与 T203的比例可知， 在这种情况下， Ioled为对应高灰阶的 大电流。
实施例 4
在实施例 3所示的像素电路的结构的基础上， 所述负载模块包括第四薄膜 晶体管 T204, 其中， 第四薄膜晶体管 T204的栅极和源极连接第二电源端子 VSS, 漏极连接第一节点 A1 , 如图 11所示。
本发明实施例 4的驱动方法， 与实施例 3中的像素电路的驱动方法不同的 是：
第三阶段： T204打开， 防止 T203进入深线性区， 防止 T203漏极电压下 降对 T203栅压造成干扰，从而能够保证 T203能够工作在饱和区， 为第七薄膜 晶体管 T207和第八薄膜晶体管 T208提供电流。
同样的， 第四薄膜晶体管的加入， 优化了像素电路结构。
本发明实施例提供的一种像素阵列结构， 如图 12所示， 包括多个矩阵排 列的上述像素电路 1 , 以及多个列驱动器， 图 12中， 所述列驱动器包括多个半 数字化电流源 SI ( Sll、 S12、 S13等）， 所述半数字化电流源 SI用于输出数字 数据信号和模拟数据信号； 本发明实施例采用了半数字化电流源， 是可选择方 案。 由于采用的是电流驱动的电路结构， 在具体实施过程中， 通过一个电流源 先后输出电流形式的模拟数据信号和数字数据信号， 即当第一阶段所述模拟数 据信号的电流值在 32灰阶的电流或 32灰阶的电流以上时， 在第二阶段中所述 数字数据信号为正电流； 当第一阶段所述模拟数据信号的电流值在 31灰阶的 电流以下时， 在第二阶段中所述数字数据信号为负电流。 采用半数字化电流源 的方式是方便实施并筒化结构的。 当然， 也可以采用另外一种实施方式， 即所 述列驱动器包括电流源和电压源 （ VDD1,VDD2,等）， 其中电流源输出电流形 式的模拟数据信号， 电压源输出电压形式的数字数据信号， 即当第一阶段所述 模拟数据信号的电流值在 32灰阶的电流或 32灰阶的电流以上时， 在第二阶段 中所述数字数据信号为正电压； 当第一阶段所述模拟数据信号的电流值在 31 灰阶的电流以下时， 在第二阶段中所述数字数据信号为负电压。
需要说明的是， 图 12所示的只是像素阵列结构的部分示意图， 并不是整 个阵列像素结构。
综上所述， 本发明实施例提供了一种像素电路、 像素阵列结构， 以及驱动 方法。 本发明实施例提供的一种像素电路， 包括： 负载控制模块、 负载模块、 灰阶选择模块、 驱动模块和发光元件， 其中， 所述负载控制模块连接第一扫描 信号线和数据信号线， 用于受控于第一扫描信号， 通过第一节点和第二节点输 出模拟数据信号； 所述负载模块分别连接第一电源端子、 驱动模块以及第一节 点和第二节点， 用于受控于第一节点信号和第二节点信号， 并且在第一电源的 作用下， 存储模拟数据信号， 并向驱动模块提供模拟数据信号； 所述灰阶选择 模块连接第二扫描信号线和数据信号线， 用于受控于第二扫描信号， 将数字数 据信号传输给位于灰阶选择模块的第三节点； 所述驱动模块受控于第二节点信 号和第三节点信号， 用于驱动发光元件； 所述发光元件的第一端连接第二电源 端子， 第二端连接驱动模块， 在第二电源和驱动模块的作用下发光。 负载模块 存储模拟信号， 驱动模块受控于第二节点和第三节点的信号， 进而选择性的驱 动发光元件， 当需要显示低灰阶画面时， 其利用多倍的电流编程输入， 来加快 充电时间。 同时， 在显示阶段， 通过数字数据信号的控制， 选择关断相应 TFT 的电流， 来实现低灰阶的电流流过 OLED, 实现低灰阶显示； 当需要显示高灰 阶画面时， 输入高灰阶对应的电流， 保证短的充电时间， 同时， 在显示阶段， 通过数字数据信号的控制，选择导通相应的 TFT的电流， 实现高灰阶的电流流 过 OLED, 实现高灰阶显示。 因此， 本发明实施例提供的像素电路， 能够有效 的减小充电时间， 提高显示效果。
本领域内的技术人员应明白， 本发明的实施例可提供为方法、 系统、 或计 算机程序产品。 因此， 本发明的实施例可采用完全硬件实施例、 完全软件实施 例、 或结合软件和硬件方面的实施例的形式。 而且， 本发明的实施例可采用在 一个或多个其中包含有计算机可用程序代码的计算机可用存储介质 (包括但不 限于磁盘存储器和光学存储器等 )上实施的计算机程序产品的形式。
本发明的实施例是参照根据本发明实施例的方法、 设备（系统）、 和计算 机程序产品的流程图和 /或方框图来描述的。应理解可由计算机程序指令实现 流程图和 /或方框图中的每一流程和 /或方框、 以及流程图和 /或方框图中的 流程和 /或方框的结合。 可提供这些计算机程序指令到通用计算机、 专用计算 通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在 流程图一个流程或多个流程和 /或方框图一个方框或多个方框中指定的功能 的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设 备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中 的指令产生包括指令装置的制造品， 该指令装置实现在流程图一个流程或多个 流程和 /或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使 得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处 理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个 流程或多个流程和 /或方框图一个方框或多个方框中指定的功能的步骤。 脱离本发明的精神和范围。 这样， 倘若本发明实施例的这些修改和变型属于本 发明权利要求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型 在内。

Claims

权 利 要 求 书
1、 一种像素电路， 包括： 负载控制模块、 负载模块、 灰阶选择模块、 驱 动模块和发光元件， 其中，
所述负载控制模块连接第一扫描信号线和数据信号线， 用于受控于第一 扫描信号， 通过第一节点和第二节点输出模拟数据信号；
所述负载模块分别连接第一电源端子、 驱动模块以及第一节点和第二节 点， 用于受控于第一节点信号和第二节点信号， 并且在第一电源的作用下， 存储模拟数据信号， 并向驱动模块提供模拟数据信号；
所述灰阶选择模块连接第二扫描信号线和数据信号线， 用于受控于第二 扫描信号， 将数字数据信号传输给位于灰阶选择模块的第三节点；
所述驱动模块受控于第二节点信号和第三节点信号，用于驱动发光元件； 所述发光元件的第一端连接第二电源端子， 第二端连接驱动模块， 在第 二电源和驱动模块的作用下发光。
2、 根据权利要求 1所述的电路， 其中， 所述负载控制模块包括第一薄膜 晶体管和第二薄膜晶体管， 其中，
所述第一薄膜晶体管的栅极连接第一扫描信号线，源极连接数据信号线， 漏极连接位于负载模块中的第一节点；
所述第二薄膜晶体管的栅极连接第一扫描信号线，源极连接数据信号线， 漏极连接位于负载模块中的第二节点。
3、 根据权利要求 1或 2所述的电路， 其中， 所述负载模块包括第一存储 电容和第三薄膜晶体管， 其中，
所述第一存储电容位于所述第二节点和所述第一电源端子之间； 所述第三薄膜晶体管的栅极连接第一存储电容的第一端， 源极连接第一 节点， 漏极连接第一电源端子。
4、 根据权利要求 3所述的电路， 其中， 所述负载模块还包括第四薄膜晶 体管， 其中所述第四薄膜晶体管的栅极和源极连接第二电源端子， 漏极连接 所述第一节点。
5、 根据权利要求 1-4中任一项所述的电路， 其中， 所述灰阶选择模块包 括第五薄膜晶体管， 所述第五薄膜晶体管的栅极连接第二扫描信号线， 源极 连接数据信号线， 漏极连接第三节点。
6、 根据权利要求 1-5中任一项所述的电路， 其中， 所述驱动模块包括第 二存储电容、 第六薄膜晶体管、 第七薄膜晶体管和第八薄膜晶体管， 其中， 所述第二存储电容位于所述第三节点和所述第一电源端子之间； 所述第六薄膜晶体管的栅极连接第三节点，源极连接发光元件的第二端， 漏极连接第七薄膜晶体管的源极；
所述第七薄膜晶体管的栅极连接第二节点， 源极连接第六薄膜晶体管的 漏极， 漏极连接第一电源端子；
所述第八薄膜晶体管的栅极连接第二节点，源极连接发光元件的第二端， 漏极连接第一电源端子。
7、 根据权利要求 6所述的电路， 其中， 所述第七薄膜晶体管的宽长比和 第八薄膜晶体管的宽长比的比值大于 1。
8、 根据权利要求 1-7中任一项所述的电路， 其中， 所述发光元件为有机 发光二极管 OLED。
9、 一种像素阵列结构， 包括多个列驱动器和多个矩阵排列的权利要求 1-8任一权利要求所述的像素电路， 所述列驱动器用于给所述像素电路输出 数据信号。
10、 根据权利要求 9所述的像素阵列结构， 其中， 所述列驱动器包括多 个半数字化电流源， 所述半数字化电流源用于输出数字数据信号和模拟数据 信号。
11、 根据权利要求 9所述的像素阵列结构， 其特征在于， 所述列驱动器 包括电流源和电压源， 所述电流源输出模拟数据信号， 所述电压源输出数字 数据信号。
12、 一种用于如权利要求 1~8任一项所述的像素电路的驱动方法， 包括： 第一阶段： 数据信号线输出模拟数据信号， 所述负载控制模块将模拟数 据信号传输给负载模块， 并将模拟数据信号存储在负载模块， 发光元件不发 光；
第二阶段： 数据信号线输出数字数据信号， 将数字数据信号传输给第三 节点， 发光元件不发光；
第三阶段： 数据信号线输出保持信号， 所述驱动模块根据第二节点信号 和第三节点信号驱动发光元件发光。
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