WO2014187117A1 - 阵列基板及其制备方法以及包括该阵列基板的显示装置 - Google Patents

阵列基板及其制备方法以及包括该阵列基板的显示装置 Download PDF

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WO2014187117A1
WO2014187117A1 PCT/CN2013/089448 CN2013089448W WO2014187117A1 WO 2014187117 A1 WO2014187117 A1 WO 2014187117A1 CN 2013089448 W CN2013089448 W CN 2013089448W WO 2014187117 A1 WO2014187117 A1 WO 2014187117A1
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thickness
common electrode
region
sub
electrode
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PCT/CN2013/089448
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English (en)
French (fr)
Inventor
徐向阳
邓立赟
金玟秀
操彬彬
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合肥京东方光电科技有限公司
京东方科技集团股份有限公司
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Priority to US14/380,168 priority Critical patent/US9490270B2/en
Publication of WO2014187117A1 publication Critical patent/WO2014187117A1/zh

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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same, and a display device including the array substrate. Background technique
  • the main component of the liquid crystal display device is a liquid crystal panel.
  • the liquid crystal panel mainly includes a color filter substrate and an array substrate, and a liquid crystal substrate is filled between the color filter substrate and the array substrate.
  • An electrode for generating an electric field is also disposed in the array substrate or the color filter substrate. The electrode determines the distribution of the electric field, and the electric field distribution determines the deflection of the liquid crystal, thereby affecting the display of the liquid crystal panel.
  • Each of the pixel points in the liquid crystal display device is provided with a pixel electrode and a common electrode opposed thereto.
  • the pixel electrode is controlled by a thin film transistor (called a TFT) integrated in the array substrate, and a storage capacitor (hereinafter referred to as a Cs, also referred to as a pixel capacitor) to realize active driving, thereby realizing image display.
  • the thin film transistor as a switch for controlling the voltage supplied to the pixel electrode is a key for realizing the display of the LCD display device, and is directly related to the development direction of the high performance flat panel display device.
  • an ADS type array substrate generally includes a pixel electrode and a common electrode on the same side of a liquid crystal cell, and a multi-dimensional electric field generated between the pixel electrode and the common electrode enables deflection of all liquid crystal molecules in the liquid crystal cell, thereby Improves LCD productivity and increases viewing angle.
  • the liquid crystal display device adopting advanced super-dimensional field conversion technology has the advantages of high pixel aperture ratio, wide viewing angle, high brightness, low power consumption and the like.
  • the pixel electrode and the common electrode in the array substrate may include the following two structures.
  • the first structure is: the electrode in the lower layer of the sub-pixel region is a plate-shaped common electrode, and the electrode of the upper layer is a slit-shaped pixel electrode.
  • the second structure is: the electrode in the lower layer of the sub-pixel region is a plate-shaped pixel electrode, the upper layer The electrode is a slit-shaped common electrode.
  • the common electrode 20 has a slit-like structure
  • the pixel electrode is a plate-shaped electrode
  • the thickness of the common electrode 20 is fixed
  • the common electrode 20 has a small electrical conductivity and a weak power supply capability.
  • the common electrode serves as a provider of a common reference voltage whose primary function is to maintain a stable common voltage reference point.
  • AC drive modes are commonly used in liquid crystal display devices, such as frame inversion, line inversion, column inversion, and dot inversion. Due to the presence of Cs and other parasitic capacitances, in AC drive mode, the AC signal is periodically pulled high or low due to the common voltage. If the conductive characteristics of the common electrode are not good, it will affect the display quality of the display screen, such as greenish, green (Flick) and crosstalk (Crosstalk).
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device that can solve at least one of the above problems existing in the prior art.
  • the common electrode of the array substrate can have a strong electrical conductivity so that the voltage distribution of the common electrode over the entire display panel is more uniform.
  • an array substrate which includes a non-pixel region distributed in a grid and a plurality of sub-pixel regions formed by a non-pixel region, and a plurality of intersecting scan lines are disposed in the non-pixel region.
  • a data line the common electrode is disposed in both the sub-pixel region and the non-pixel region, the region of the common electrode corresponding to the sub-pixel region has a first thickness, and the region of the common electrode corresponding to the scan line and/or the data line has the The second thickness may be less than the second thickness.
  • the common electrode may be formed of at least one of indium gallium oxide, indium oxide, indium tin oxide, and indium gallium tin oxide.
  • the portion of the common electrode from the bottom surface to the first thickness in the region corresponding to the sub-pixel region, the scan line, and/or the data line may be indium gallium oxide, indium oxide, indium tin oxide, oxidation. At least one material of indium gallium tin is formed; a portion of the common electrode in a region corresponding to the scan line and/or the data line from the first thickness to the second thickness may be molybdenum, molybdenum-milled alloy, aluminum, aluminum-bismuth alloy, At least one of titanium and copper is formed.
  • a sub-pixel region may be provided with a gate electrode, a gate insulating layer, an active layer, source and drain electrodes, a pixel electrode, and a passivation layer, wherein the scan line may be electrically connected to the gate electrode, and the data line may be Electrically connected to the source electrode, the pixel electrode can be electrically connected to the drain electrode, and the common electrode can be extended to cover the scan line and/or the data line.
  • the organic thin film layer may be disposed between the source and drain electrodes and the pixel electrode, and the organic thin film layer may be formed of a resin material containing the photosensitive material.
  • the active layer may be formed of at least one of indium gallium oxide, indium oxide, indium tin oxide, indium gallium tin oxide; or the active layer may be formed of an amorphous silicon material.
  • the common electrode may be disposed on the passivation layer, and the common electrode is distributed in a slit shape in a region corresponding to the sub-pixel region; or, the pixel electrode may be disposed on the passivation layer, and the pixel electrode corresponds to the sub-pixel The area of the pixel region is distributed in a slit shape.
  • the first thickness may be in the range of 550 to 100? ⁇ and the second thickness may be in the range of 300 to 500.
  • a display device including the above array substrate.
  • a method for fabricating an array substrate comprising: forming a plurality of intersecting scan lines and data lines, wherein the scan lines and the data lines divide the array substrate into a grid distribution a non-pixel region and a plurality of sub-pixel regions formed by the non-pixel region; and a step of forming a pattern including the common electrode over the sub-pixel region, the scan line, and/or the data line, wherein the common electrode corresponds to the sub-pixel region
  • the area has a first thickness
  • the area of the common electrode corresponding to the scan line and/or the data line has a second thickness, the first thickness being less than the second thickness.
  • forming the pattern including the common electrode may include the following steps:
  • the photoresist is completely retained, the photoresist corresponding to the partially reserved region is partially retained, and the photoresist corresponding to the completely removed region is completely removed;
  • Step S 17 The remaining photoresist is peeled off.
  • step S11): at least one of indium gallium oxide, indium oxide, indium tin oxide, indium gallium tin oxide may be used to form a conductive film by deposition, sputtering or thermal evaporation. a layer, wherein a thickness of the conductive film layer may be equal to a second thickness;
  • the conductive film layer includes the first conductive film layer and the second conductive film layer
  • at least one of indium gallium oxide, indium oxide, indium tin oxide, indium gallium tin oxide is used first, and deposition is performed.
  • a second conductive film layer is formed on the first conductive film layer, wherein a thickness of the first conductive film layer is equal to a first thickness, and a thickness of the second conductive film layer is equal to a difference between the second thickness and the first thickness.
  • step S16 After etching, the second conductive film layer in the sub-pixel region is completely removed and the first conductive film layer in the sub-pixel region is completely exposed.
  • the common electrode by arranging the common electrode to have a structure having a thickness corresponding to a region of the scan line and/or the data line larger than a region corresponding to the sub-pixel region, correspondingly, the common electrode is implemented by an ashing process
  • the preparation of such structures having different thicknesses can enhance the conductivity of the common electrode, so that the voltage distribution of the common electrode on the entire display panel is more uniform and stable, the picture display quality is improved, and the quality level of the display device is improved.
  • 1A is a schematic plan view showing an array substrate in the prior art
  • Figure 1B is a plan view showing the common electrode of Figure 1A;
  • FIG. 2 is a plan view showing a sub-pixel region and a non-pixel region in an array substrate
  • FIG. 3A is a plan view showing an array substrate according to a first embodiment of the present invention
  • FIG. 3B is a cross-sectional view taken along line AA of FIG. 3A
  • Figure 4 is a plan view showing the common electrode of Figure 3A;
  • 5A-5D, 5F and 6A-6F are a plan view schematically showing a flow chart of the preparation of the array substrate of Fig. 3A and a cross-sectional view taken along line A-A in Fig. 3A;
  • 5A is a schematic plan view showing a pattern including a gate electrode
  • Figure 6A is a cross-sectional view corresponding to Figure 5A;
  • 5B is a schematic plan view showing a pattern including a gate insulating layer and an active layer
  • Figure 6B is a cross-sectional view corresponding to Figure 5B;
  • 5C is a schematic plan view showing a pattern including a source electrode and a drain electrode
  • Figure 6C is a cross-sectional view corresponding to Figure 5C;
  • 5D is a schematic plan view showing formation of a pattern including a pixel electrode
  • Figure 6D is a cross-sectional view corresponding to Figure 5D;
  • 6E is a cross-sectional view of forming a pattern including a passivation layer
  • Figure 5F is a schematic plan view showing the formation of a pattern including a common electrode
  • Fig. 6F is a cross-sectional view corresponding to Fig. 5F. detailed description
  • the embodiment provides an array substrate including a non-pixel region 2 distributed in a grid and a plurality of sub-pixel regions 1 formed by the non-pixel region 2, and the non-pixel region 2 is disposed.
  • the common electrode 20 may be disposed in the sub-pixel region 1 and the non-pixel region 2.
  • a region of the common electrode 20 corresponding to the sub-pixel region 1 may have a first thickness
  • a region of the common electrode 20 corresponding to the scan line 12 and/or the data line 16 may have a second thickness, and the first thickness may be smaller than the second thickness.
  • the thickness of the region of the common electrode 20 corresponding to the scan line may be greater than the thickness of the region of the common electrode 20 corresponding to the sub-pixel region 1, or the region of the common electrode 20 corresponding to the data line.
  • the thickness of the common electrode 20 may be greater than the thickness of the region of the common electrode 20 corresponding to the sub-pixel region 1; or the thickness of the region of the common electrode 20 corresponding to both the scan line and the data line may be greater than the corresponding sub-pixel of the common electrode 20.
  • a gate electrode 11, a gate insulating layer 13, an active layer 14, and a source electrode 17 and a drain electrode 18 in the same layer may be disposed in the sub-pixel region 1.
  • the scan line 12 can be electrically connected to the gate electrode 11, the data line 16 can be electrically connected to the source electrode 17, and the common electrode 20 can be disposed on the passivation layer 19.
  • the common electrode 20 extends to cover the area of the scan line 12 and the data line 16, and the thickness of the area of the common electrode 20 corresponding to the scan line 12 and the data line 16 is larger than the common electrode.
  • the thickness of the region corresponding to the sub-pixel region 1 of 20 (the thickness difference of the common electrode 20 in the sub-pixel region 1 and the non-pixel region 2 is shown by the color depth in FIG. 4, and the thickness of the deep color region is larger than the thickness of the light color region ).
  • the common electrode 20 may be formed of at least one of indium gallium oxide, indium oxide, indium tin oxide, and indium gallium tin oxide.
  • the first thickness may be in the range of 550 to 100? ⁇
  • the second thickness may be in the range of 300 to 50? ⁇ .
  • the common electrode 20 is distributed in a slit shape in a region corresponding to the sub-pixel region 1.
  • the gate electrode 11, the source electrode 17, and the drain electrode 18 may each be formed of at least one of molybdenum, phase alloy, aluminum, aluminum-niobium alloy, titanium, and copper.
  • the gate insulating layer 13 may be formed of at least one of silicon oxide, silicon nitride, tantalum oxide, silicon oxynitride, and aluminum oxide.
  • the active layer 14 may be formed of an amorphous silicon material.
  • the passivation layer 19 may be formed using at least two materials of silicon oxide, silicon nitride, tantalum oxide, and aluminum oxide.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include printing, inkjet, etc.
  • a process of forming a predetermined pattern; a photolithography process refers to a process of forming a pattern using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the embodiment of the present invention.
  • the photoresist is exemplified by a positive photoresist, but the embodiment of the invention is not limited thereto.
  • the method for fabricating the above array substrate may include: forming a plurality of intersecting scan lines and data lines, wherein the scan lines and the data lines divide the array substrate into non-pixel regions distributed in a grid and surrounded by non-pixel regions a plurality of sub-pixel regions; a step of forming a pattern including a common electrode over the sub-pixel region, the scan line, and/or the data line, wherein a region of the common electrode corresponding to the sub-pixel region has a first thickness, and a common electrode corresponds to the scan
  • the area of the line and/or data line has a second thickness, and the first thickness may be less than the second thickness.
  • the method for preparing the array substrate may include:
  • Step S1) forming a pattern including a gate electrode on the substrate.
  • a metal thin film i.e., a gate electrode metal thin film
  • a pattern including the gate electrode 11 and the scanning line 12 is formed on the substrate 10 by a patterning process as shown in Figs. 5A and 6A.
  • the metal thin film can be formed by a deposition method, a sputtering method, or a thermal evaporation method.
  • a photoresist may be formed on the metal film, and then the photoresist may be exposed, developed, etched, and stripped using a mask to form a pattern including the gate electrode 11 and the scan line 12.
  • the cross-sectional view 5A and the plan view 6A are set to different scales; at the same time, in order to facilitate understanding of the layer structure and layers of the thin film transistor Between the positional relationship, the layers in the plan view 5A are set to have a certain transparency, and the following plan views are similar to the respective cross-sectional views.
  • Step S2) A pattern including a gate insulating layer and an active layer is formed on the substrate on which the step S1) is completed.
  • a gate insulating layer film and an active layer film are sequentially formed on the substrate 10 on which the step S1) is completed, and a pattern including the active layer 14 is formed by one patterning process.
  • the gate insulating layer is formed by a chemical vapor deposition (CVD) method, and the gate insulating layer 13 is provided to cover the entire substrate on which the step S1) has been completed.
  • CVD chemical vapor deposition
  • a photoresist is formed on the active layer film, and the photoresist is exposed, developed, etched, and stripped using a mask to form a pattern including the active layer 14, as shown in FIG. 5B.
  • Figure 6B shows.
  • the active layer 14 may be formed of an amorphous silicon material.
  • the gate insulating layer 13 covers the entire substrate 10, and the gate insulating layer is generally made of a transparent material (at least one of silicon oxide, silicon nitride, tantalum oxide, silicon oxynitride, aluminum oxide). The material is formed so that the observation of the plan view of the gate insulating layer is not hindered, so that the gate insulating layer 13 is not shown in the plan view of FIG. 5B, so that the gate electrode 11 and the scan line 12 can be better illustrated. Relative positional relationship with the active layer 14.
  • Step S3) forming a pattern including the source electrode and the drain electrode on the substrate on which the step S2) is completed.
  • a metal thin film ie, a metal thin film forming a source electrode and a drain electrode
  • a pattern including the source electrode 17, the drain electrode 18, and the data line 16 is formed by one patterning process.
  • the source electrode 17 and the drain electrode 18 are located above the active layer 14 and on opposite sides with respect to the gate electrode 11.
  • the metal thin film can be formed by a deposition method, a sputtering method, or a thermal evaporation method.
  • a photoresist is formed on the metal film, and then the photoresist is exposed, developed, etched, and stripped using a mask to form the source electrode 17, the drain electrode 18, and the data line 16.
  • the figure is shown in Figure 5C and Figure 6C.
  • Step S4) forming a pattern including the pixel electrode on the substrate on which the step S3) is completed.
  • a pixel electrode film is formed on the substrate 10 on which the step S3) is completed, and a pattern including the pixel electrode 15 is formed by a patterning process.
  • the formation of the pixel electrode film can be carried out by a deposition method, a sputtering method or a thermal evaporation method.
  • a photoresist may be formed on the pixel electrode film, and then the photoresist is exposed, developed, etched, and stripped using a mask to form a pattern including the pixel electrode 15.
  • the drain electrode 18 may be Directly electrically connected to the pixel electrode 15, as shown in FIGS. 5D and 6D.
  • Step S5) forming a pattern including a passivation layer on the substrate on which step S4) is completed, as shown in FIG. 6E.
  • the passivation layer 19 covers the entire substrate 10. Similar to the gate insulating layer 13, the passivation layer 19 is generally formed of a transparent material such as silicon oxide, silicon nitride, tantalum oxide or aluminum oxide, so that the observation of the plan view is not hindered, and thus passivation is performed. The layers are not shown in the corresponding plan view.
  • Step S6) forming a pattern including the common electrode on the substrate on which the step S5) is completed.
  • a common electrode film is formed on the substrate 10 on which the step S5) is completed, and a pattern including the common electrode 20 is formed on the passivation layer 19 by a one-time patterning process.
  • the formation of the common electrode film can be carried out by a deposition method, a sputtering method or a thermal evaporation method.
  • a layer of photoresist may be formed on the common electrode film, and then a lithography is performed using a two-tone mask such as a half tone mask or a gray tone mask.
  • the glue is exposed, developed, etched, and peeled off to form a pattern including the common electrode 20 as shown in FIGS. 5F and 6F.
  • the passivation layer 19 is provided with a via hole at a position corresponding to the common electrode connection line, and the common electrode 20 can be electrically connected to the common electrode connection line through the via hole.
  • the common electrode connection line can be formed on the substrate 10 simultaneously with the gate electrode 11 and the scan line 12. In this step, it is only necessary to ensure that the common electrode connection line is electrically connected to the common electrode 20.
  • a passivation layer film is formed on the substrate 10 on which step S4) is completed, and a passivation layer 19 pattern is formed by one patterning process, and the passivation layer 19 pattern covers portions of the source electrode 17, the drain electrode 18, and the pixel electrode 15.
  • the passivation layer film can be formed by a deposition method, a sputtering method, or a thermal evaporation method.
  • a layer of photoresist may be applied to the passivation layer film, and then the photoresist is exposed, developed, etched, and stripped using a mask to form a pattern including the passivation layer 19.
  • At least one of indium gallium oxide, indium oxide, indium tin oxide, indium gallium tin oxide may be used to form a layer on the passivation layer 19 by deposition, sputtering or thermal evaporation.
  • Step S612 forming a photoresist on the conductive film layer.
  • the photoresist may be formed by using a positive photoresist or a negative photoresist to form a photoresist on the conductive film layer by a coating method.
  • Step S613 exposing and developing the photoresist by using a two-tone mask, the double-tone mask is provided with a completely reserved area, a partially reserved area and a completely removed area, and the area of the photoresist corresponding to the completely reserved area is completely Retained, the region of the photoresist corresponding to the portion of the remaining region is partially retained, and the region of the photoresist corresponding to the completely removed region is completely removed.
  • the area of the slit of the two-tone mask corresponding to the common electrode may be set as a slit-shaped complete removal area, and an area corresponding to the portion other than the slit in the sub-pixel area 1 may be set as a partial retention area, corresponding to The area of the scan line and/or the data line can be set as a full reserved area.
  • the area of the photoresist corresponding to the completely removed region of the two-tone mask can be completely removed.
  • the photoresist is a positive photoresist, a portion of the positive photoresist which is irradiated with light during the exposure is easily dissolved in the developer by the photosensitive chemical reaction, thereby being removed.
  • the photoresist employs a negative photoresist, a portion of the negative photoresist which is irradiated with light during the exposure is not easily dissolved in the developer by the photosensitive chemical reaction, thereby being retained.
  • the etching may employ a wet etching process. After the etching step, the conductive film layer corresponding to the slit of the common electrode is completely removed, thereby forming a slit of the common electrode in the sub-pixel region 1.
  • Step S615) The photoresist of the step S614 is subjected to ashing treatment to ash away the partially retained photoresist.
  • the photoresist in the sub-pixel region 1 corresponding to the region of the partial remaining region of the two-tone mask is further completely removed, so that the conductive film layer in the sub-pixel region 1 is completely exposed.
  • the etching may be performed by a wet etching process, and the conductive film layer corresponding to the sub-pixel region 1 is thinned to have a first thickness; and corresponds to the scan line 12 and/or the data line.
  • the conductive film layer of the region of 16 is completely retained, having a second thickness, the second thickness being greater than the first thickness, thereby forming a complete pattern of the common electrode 20.
  • the remaining photoresist is completely removed, that is, the photoresist corresponding to the area of the scan line and/or the data line is completely removed to expose the conductive film corresponding to the area of the scan line and/or the data line.
  • the remaining photoresist is completely removed, that is, the photoresist corresponding to the area of the scan line and/or the data line is completely removed to expose the conductive film corresponding to the area of the scan line and/or the data line.
  • common electrodes having unequal thicknesses are formed in the sub-pixel region 1 and the non-pixel region 2 by the two-tone mask, and the corresponding conductivity is larger and the resistivity is smaller in the thicker portion of the common electrode.
  • the corresponding resistance is small; in the thinner part of the common electrode, the corresponding conductivity is smaller, the resistivity is larger, and the corresponding resistance is larger. Therefore, the voltage distribution of the common electrode in the sub-pixel region 1 and the non-pixel region 2 can be equalized, so that the voltage supplied from the common electrode 20 is more uniform and more stable throughout the display region.
  • the electrode in the lower layer is a plate-shaped pixel electrode
  • the pixel electrode is electrically connected to the drain electrode of the TFT
  • the electrode in the upper layer is a slit-shaped common electrode.
  • a multi-dimensional electric field is formed by the electric field generated between the slit electrode edge and the plate electrode layer and the electric field generated between the slit electrodes, so that all liquid crystal molecules in the liquid crystal cell can be deflected, thereby realizing image display.
  • Second embodiment The difference between this embodiment and the first embodiment is that, in this embodiment, the common electrode 20 in the array substrate can be formed of two different materials, that is, the common electrode 20 is in an area corresponding to the scan line and/or the data line.
  • the portion protruding with respect to the common electrode in the sub-pixel region 1 can be formed using a material having a higher conductivity.
  • the portion of the common electrode 20 from the bottom surface to the first thickness in the region corresponding to the sub-pixel region 1, the scan line, and/or the data line may be indium gallium oxide, indium oxide, indium tin oxide, or oxidation. At least one material of indium gallium tin is formed; the portion of the common electrode 20 from the first thickness to the second thickness in a region corresponding to the scan line and/or the data line may be molybdenum, molybdenum-milled alloy, aluminum, aluminum-niobium alloy Forming at least one of titanium and copper.
  • the method for preparing the array substrate of the embodiment may specifically include the following steps: Step S600): forming other layers of the array substrate other than the common electrode.
  • the uppermost layer of the array substrate is a passivation layer.
  • the conductive film layer may include a first conductive film layer and a second conductive film layer, and may first pass at least one of indium gallium oxide, indium oxide, indium tin oxide, and indium gallium tin oxide.
  • a method of sputtering or thermal evaporation to form a first conductive film layer on the passivation layer then, using at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium, and copper, by sputtering or thermal evaporation
  • the method comprises forming a second conductive film layer on the first conductive film layer; wherein the thickness of the first conductive film layer may be equal to the first thickness, and the thickness of the second conductive film layer may be equal to the difference between the second thickness and the first thickness.
  • the first thickness may range from 550 to 100 ⁇
  • the second thickness may range from 300 to 50 ⁇ .
  • Step S612 forming a photoresist on the conductive film layer.
  • Step S613 exposing and developing the photoresist by using a two-tone mask, the double-tone mask is provided with a completely reserved area, a partially reserved area and a completely removed area, and the area of the photoresist corresponding to the completely reserved area is completely retained. The area corresponding to the partial reserved area is partially retained, and the area corresponding to the completely removed area is completely removed.
  • a region of the dichroic mask corresponding to the slit of the common electrode is provided as a slit-shaped complete removal region, and a region corresponding to the portion other than the slit in the sub-pixel region 1 is a partial retention region corresponding to the scanning line
  • the area of the and/or data lines is set to a fully reserved area.
  • the photoresist corresponding to the slits in the common electrode can be completely removed.
  • the etching may be performed by a wet etching process in which the conductive film layer corresponding to the slit in the common electrode is completely removed, thereby forming a slit of the common electrode.
  • Step S615) The photoresist of the step S614 is subjected to ashing treatment to ash away the partially retained photoresist.
  • the photoresist in the sub-pixel region 1 corresponding to the region of the partial remaining region of the two-tone mask is further completely removed, so that the second conductive film layer in the sub-pixel region 1 is completely exposed.
  • Step S616) etching the conductive film layer of the step S615).
  • the etching may be performed by a wet etching process.
  • the second conductive film layer in the sub-pixel region 1 is completely removed, so that the first conductive film layer is completely exposed, thereby forming the common electrode 20.
  • the partial common electrode has a first thickness; and the second conductive film layer in the region corresponding to the scan line 12 and/or the data line 16 is completely retained, the portion of the common electrode (including The first conductive film layer and the second conductive film layer) have a second thickness, and the second thickness is greater than the first thickness, thereby forming a complete pattern of the common electrode 20.
  • the remaining photoresist is completely removed, that is, the photoresist corresponding to the region of the scan line and/or the data line is completely removed, and the second region corresponding to the scan line and/or the data line is exposed.
  • the organic thin film layer may be further disposed between the source electrode and the drain electrode and the pixel electrode.
  • the organic film layer may be formed of a resin material containing a photosensitive material, and the thickness of the organic film layer may be 2-4 ⁇ m (thickness is greater than the thickness of the passivation layer).
  • the organic thin film layer may be formed on the source electrode and the drain electrode, and a via hole may be formed in a region corresponding to the drain electrode through which the drain electrode may be electrically connected to the pixel electrode.
  • the preparation method of the array substrate of the embodiment is as follows: gate electrode deposition ⁇ using ordinary mask
  • the template is formed by a patterning process to form a gate electrode ⁇ gate insulating layer deposition ⁇ active layer deposition ⁇ forming a active layer by one patterning process using a common mask ⁇ metal film deposition ⁇ forming a source electrode and a leakage current by a patterning process using a common mask
  • the other structures of the array substrate in this embodiment are the same as those of the array substrate in the first or second embodiment, and other steps of the preparation method are the same as those of the array substrate in the first or second embodiment, and no longer Narration.
  • the organic thin film layer is disposed between the source and the drain electrode and the pixel electrode, the coupling capacitance in the array substrate can be further reduced, the influence of the coupling capacitance on the common electrode is weakened, and the common electrode is ensured.
  • the voltage distribution on the device is more uniform and stable, so that the display device can obtain better picture display quality.
  • the active layer in the array substrate of the present embodiment is formed using a metal oxide semiconductor.
  • the active layer may be formed of at least one of indium gallium oxide (IGZO), indium oxide, indium tin oxide, and indium gallium tin oxide.
  • IGZO indium gallium oxide
  • indium oxide indium oxide
  • indium tin oxide indium gallium tin oxide
  • the active layer is formed of a metal oxide semiconductor, the electron mobility between the source electrode and the drain electrode is increased, so that the electron mobility between the source electrode and the drain electrode can be better improved.
  • the other structures of the array substrate in this embodiment are the same as those of the array substrate of any one of the first to third embodiments, and the other steps of the preparation method are the same as those of the array substrate of any of the first to third embodiments. I won't go into details here.
  • the present invention is not limited thereto.
  • the pixel electrode may have a slit shape
  • the common electrode may have a plate shape, as long as the electrode above is a slit shape, and the electrode below is a plate shape.
  • Embodiments of the present invention also provide a display device including any of the above array substrates.
  • the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
  • the thickness of the region of the common electrode corresponding to the non-pixel region in the bottom gate type thin film transistor array substrate (specifically, the thickness of the region corresponding to the scan line and/or the data line)
  • the structure of the thickness of the region corresponding to the sub-pixel region of the common electrode is taken as an example, and the structure and preparation method of the array substrate are described in detail.
  • the common electrode has the non-pixel region and the sub-pixel region.
  • Different thickness structures are also suitable for top-gate thin film transistor array substrates, and only need to be adaptively adjusted during design and production.
  • the common electrode by setting the common electrode to a structure in which the thickness of the region corresponding to the scan line and/or the data line of the non-pixel region is larger than the thickness of the region corresponding to the sub-pixel region, correspondingly
  • the use of the ashing process to realize the preparation of the structure of the common electrode having different thicknesses can enhance the conductivity of the common electrode, so that the voltage distribution of the common electrode on the entire liquid crystal display panel is more uniform and stable, and the picture display quality is improved. , improve the quality level of the display device.

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Abstract

提供一种阵列基板及其制备方法以及具有该阵列基板的显示装置。该阵列基板包括呈网格分布的非像素区以及由非像素区包围形成的多个子像素区，非像素区内设置有多条交叉设置的扫描线（12）和数据线（16），公共电极（20）设置在子像素区和非像素区中，其中公共电极（20）的对应于子像素区的区域具有第一厚度，公共电极（20）的对应于扫描线（12）和/或数据线（16）的区域具有第二厚度，并且第一厚度小于第二厚度。通过将公共电极（20）设置为对应于扫描线（12）和/或数据线（16）的区域的厚度大于对应于子像素区的区域的厚度的结构，能够增强公共电极（20）的导电能力，使得公共电极（20）在整个显示面板上的电压分布更均匀，提高了画面显示质量，并提升了显示装置的品质等级。

Description

阵列基板及其制备方法以及包括该阵列基板的显示装置 技术领域
本发明的实施例涉及显示技术领域， 更具体地， 涉及一种阵列基板及其 制备方法以及包括该阵列基板的显示装置。 背景技术
随着科学技术的发展， 平板显示装置已经取代笨重的阴极射线管 (CRT) 显示装置而日益深入人们的日常生活中， 液晶显示装置（筒称 LCD )是平板 显示装置中的一种。 液晶显示装置的主要构成部件是液晶面板， 液晶面板主 要包括彩膜基板和阵列基板， 彩膜基板和阵列基板之间填充有液晶。 在阵列 基板或彩膜基板中还设置有用于产生电场的电极， 电极决定电场的分布， 电 场分布决定液晶的偏转， 进而影响液晶面板的显示。 液晶显示装置中的每一 个像素点均设置有像素电极以及与其相对的公共电极。 在成像过程中， 像素 电极由集成在阵列基板中的薄膜晶体管 （筒称 TFT ) 、 存储电容（以下筒称 Cs, 也称像素电容）来控制， 实现有源驱动， 从而实现图像显示。 薄膜晶体 管作为控制向像素电极提供的电压的开关， 是实现 LCD显示装置显示的关 键， 直接关系到高性能平板显示装置的发展方向。
随着显示技术的发展， 同时为了满足人们对高亮度、 高对比度、 低能耗 的要求，高级超维场转换技术（ ADvanced Super Dimension Switch,筒称 ADS, 又称 ADSDS )应运而生。 在现有技术中， ADS型阵列基板通常包括位于液 晶盒的同一侧的像素电极和公共电极， 像素电极与公共电极之间产生的多维 电场使液晶盒内的所有液晶分子都能够发生偏转， 从而提高了液晶工作效率 并增大了视角。采用高级超维场转换技术的液晶显示装置具有高像素开口率、 宽视角、 高亮度， 低能耗等优点。
作为 ADS技术的改进，目前出现了高透过率 I-ADS技术、高开口率 ADS ( High aperture ADS, 筒称 H- ADS )和高分辨率 S- ADS技术等。 一般地， 阵 列基板中的像素电极和公共电极可以包括以下两种结构， 第一种结构是： 子 像素区中处于下层的电极为板状的公共电极， 上层的电极为狭缝状的像素电 极； 第二种结构是： 子像素区中处于下层的电极为板状的像素电极， 上层的 电极为狭缝状的公共电极。 如图 1A和图 1B所示， 公共电极 20为狭缝状结 构， 像素电极为板状电极， 并且公共电极 20的厚度是固定的， 公共电极 20 的电导率较小， 供电能力弱。
公共电极作为公共基准电压的提供者， 其最主要的功能在于能保持一个 稳定的公共电压参考点。 但是由于液晶的特殊性质， 液晶显示装置中一般采 用交流驱动模式， 例如帧反转、 行反转、 列反转以及点反转等模式。 由于 Cs 以及其他寄生电容的存在， 在交流驱动模式下， 交流信号会对公共电压产生 周期性地被拉高或拉低的影响。 如果公共电极的导电特性不好， 就会影响显 示装置画面的显示质量， 例如在显示图像的同时还伴随有绿条（Greenish )、 抖动（Flick )和串扰（Crosstalk )等现象。
为保证子像素区中 TFT稳定工作，需要存储在 Cs上的电荷继续维持 TFT 的驱动电压， 以使液晶分子在一个帧周期内维持稳定的工作状态。 相应地， 如何保证阵列基板中的公共电极的电压的稳定性、提高公共电极的供电能力、 提高显示画面质量成为目前业界 待解决的问题。 发明内容
本发明的实施例提供一种阵列基板及其制备方法以及显示装置， 其可以 解决现有技术中存在的以上问题中的至少一个。 该阵列基板的公共电极可以 具有较强的导电能力， 使得公共电极在整个显示面板上的电压分布更均匀。
根据本发明的一个方面， 提供一种阵列基板， 其包括呈网格分布的非像 素区以及由非像素区包围形成的多个子像素区 , 在非像素区内设置有多条交 叉设置的扫描线和数据线， 公共电极设置在子像素区和非像素区两者中， 公 共电极的对应于子像素区的区域具有第一厚度， 公共电极的对应于扫描线和 / 或数据线的区域具有第二厚度， 第一厚度可以小于第二厚度。
在实施例中， 公共电极可以采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧 化铟镓锡中的至少一种材料形成。
在实施例中， 公共电极在对应于子像素区、 扫描线和 /或数据线的区域中 从其底表面至第一厚度的部分可以采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料形成； 公共电极在对应于扫描线和 /或数据线的 区域中从第一厚度至第二厚度的部分可以采用钼、 钼铣合金、 铝、 铝钕合金、 钛和铜中的至少一种材料形成。 在实施例中， 子像素区内可以设置有栅电极、 栅极绝缘层、 有源层、 源 电极和漏电极、 像素电极以及钝化层， 其中扫描线可以与栅电极电连接， 数 据线可以与源电极电连接， 像素电极可以与漏电极电连接， 公共电极可以延 伸为覆盖扫描线和 /或数据线。
在实施例中， 有机薄膜层可以设置在源、 漏电极与像素电极之间， 有机 薄膜层可以采用含有感光材料的树脂材料形成。
在实施例中， 有源层可以采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化 铟镓锡中的至少一种材料形成； 或者， 有源层可以采用非晶硅材料形成。
在实施例中， 公共电极可以设置在钝化层上， 公共电极在对应于子像素 区的区域内呈狭缝状分布； 或者， 像素电极可以设置在钝化层上， 像素电极 在对应于子像素区的区域内呈狭缝状分布。
在实施例中， 第一厚度可以在 550 ~ 100θΑ 的范围内， 第二厚度可以在 300 ~ 500人的范围内。
根据本发明的另一个方面， 提供一种显示装置， 包括上述阵列基板。 根据本发明的另一个方面， 提供一种阵列基板的制备方法， 该方法包括： 形成多条交叉设置的扫描线和数据线的步骤， 其中扫描线和数据线将阵列基 板划分为呈网格分布的非像素区以及由非像素区包围形成的多个子像素区； 以及在子像素区、扫描线和 /或数据线的上方形成包括公共电极的图形的步骤， 其中公共电极的对应于子像素区的区域具有第一厚度， 公共电极的对应于扫 描线和 /或数据线的区域具有第二厚度， 第一厚度小于第二厚度。
在实施例中， 形成包括公共电极的图形可以包括以下步骤：
步骤 S11 ): 形成导电膜层；
步骤 S12 ): 在导电膜层上形成光刻胶层；
步骤 S13 ): 采用双色调掩模板对光刻胶层进行曝光、 显影， 该双色调掩 模板设置有完全保留区、 部分保留区和完全去除区， 光刻胶层的对应于完全 保留区的光刻胶被完全保留， 对应于部分保留区的光刻胶被部分保留， 对应 于完全去除区的光刻胶被完全去除；
步骤 S14 ): 对完成步骤 S13 ) 的导电膜层进行刻蚀， 在对应于子像素区 的区域中形成公共电极的狭缝；
步骤 S15 ): 对完成步骤 S14 ) 的光刻胶层进行灰化处理， 灰化掉光刻胶 层中被部分保留的光刻胶； 步骤 S16 ): 对完成步骤 S15 ) 的导电膜层进行刻蚀， 使子像素区内的导 电膜层的厚度减小， 同时形成公共电极的对应于扫描线和 /或数据线的区域的 图形；
步骤 S 17 ): 将剩余的光刻胶剥离。
在实施例中， 在步骤 S11 )中： 可以采用氧化铟镓辞、 氧化铟辞、 氧化铟 锡、 氧化铟镓锡中的至少一种材料， 通过沉积、 溅射或热蒸发的方法形成导 电膜层， 其中导电膜层的厚度可以等于第二厚度；
或者， 在导电膜层包括第一导电膜层和第二导电膜层的情形下， 先采用 氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料， 通过沉 积、 溅射或热蒸发的方法形成第一导电膜层； 接着， 采用钼、 相4尼合金、 铝、 铝钕合金、 钛和铜中的至少一种材料， 通过溅射或热蒸发的方法在第一导电 膜层上形成第二导电膜层， 其中第一导电膜层的厚度等于第一厚度， 第二导 电膜层的厚度等于第二厚度与第一厚度之差。
在步骤 S16 )中： 经过刻蚀， 子像素区内的第二导电膜层被完全去除并使 子像素区内的第一导电膜层被完全暴露。
在实施例中， 在步骤 S13 )中： 双色调掩模板的对应于公共电极的狭缝的 区域设置为完全去除区， 对应于子像素区内除了所述狭缝之外的其他部分的 区域设置为部分保留区， 对应于所述扫描线和 /或所述数据线的区域设置为完 全保留区。
根据本发明的实施例， 通过将公共电极设置为具有对应于扫描线和 /或数 据线的区域的厚度大于对应于子像素区的区域的厚度的结构， 相应地， 采用 灰化工艺实现公共电极这种厚度不等的结构的制备， 能够增强公共电极的导 电能力， 使得公共电极在整个显示面板上的电压分布更均匀、 更稳定， 提高 了画面显示质量， 提升显示装置的品质等级。 附图说明
图 1A为示出现有技术中的阵列基板的平面示意图；
图 1B为示出图 1A中的公共电极的平面示意图；
图 2为示出阵列基板中的子像素区和非像素区的平面示意图；
图 3A为示出根据本发明第一实施例的阵列基板的平面示意图； 图 3B为示出沿图 3A中的线 A-A剖取的剖视图； 图 4为示出图 3A中的公共电极的平面示意图； 以及
图 5A-5D、图 5F和图 6A-6F为分别示出图 3A中的阵列基板的制备流程 图的平面示意图和沿图 3A中的线 A-A剖取的剖视图；
其中：
图 5A为形成包括栅电极的图形的平面示意图；
图 6A为图 5A所对应的剖视图；
图 5B为形成包括栅极绝缘层和有源层的图形的平面示意图；
图 6B为图 5B所对应的剖视图；
图 5C为形成包括源电极和漏电极的图形的平面示意图；
图 6C为图 5C所对应的剖视图；
图 5D为形成包括像素电极的图形的平面示意图；
图 6D为图 5D所对应的剖视图；
图 6E为形成包括钝化层的图形的剖视图；
图 5F为形成包括公共电极的图形的平面示意图；
图 6F为图 5F所对应的剖视图。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结合附图和具 体实施方式对本发明阵列基板、 制备方法以及显示装置作进一步详细描述。 第一实施例：
如图 2所示， 本实施例提供了一种阵列基板， 该阵列基板包括呈网格分 布的非像素区 2以及由非像素区 2包围形成的多个子像素区 1 , 非像素区 2 内设置有多条交叉设置的扫描线 12和数据线 16。公共电极 20可以设置在子 像素区 1和非像素区 2中。公共电极 20的对应于子像素区 1的区域可以具有 第一厚度， 公共电极 20的对应于扫描线 12和 /或数据线 16的区域可以具有 第二厚度， 第一厚度可以小于第二厚度。 也就是， 在本实施例中， 公共电极 20的对应于扫描线的区域的厚度可以大于公共电极 20的对应于子像素区 1 的区域的厚度，或者，公共电极 20的对应于数据线的区域的厚度可以大于公 共电极 20的对应于子像素区 1的区域的厚度； 或者， 公共电极 20的对应于 扫描线和数据线两者的区域的厚度可以均大于公共电极 20 的对应于子像素 区 1的区域的厚度。
在本实施例中， 如图 3A、 3B所示， 在子像素区 1内可以设置有栅电极 11、 栅极绝缘层 13、 有源层 14、 处于同一层的源电极 17和漏电极 18、 像素 电极 15、 钝化层 19以及公共电极 20。 扫描线 12可以与栅电极 11电连接， 数据线 16可以与源电极 17电连接， 公共电极 20可以设置在钝化层 19上。 在本实施例中， 如图 4所示， 公共电极 20延伸至覆盖扫描线 12与数据线 16 的区域，且公共电极 20的对应于扫描线 12和数据线 16的区域的厚度均大于 公共电极 20的对应于子像素区 1的区域的厚度（图 4中以颜色深浅示出公共 电极 20在子像素区 1和非像素区 2中的厚度差异，深颜色区域的厚度大于浅 颜色区域的厚度）。
公共电极 20可以采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中 的至少一种材料形成。 在公共电极 20中， 第一厚度可以在 550 ~ 100θΑ的范 围内， 第二厚度可以在 300 ~ 50θΑ的范围内。 公共电极 20在对应于子像素 区 1的区域内呈狭缝状分布。
另夕卜，栅电极 11、 源电极 17和漏电极 18可以均采用钼、相4尼合金、铝、 铝钕合金、钛和铜中的至少一种材料形成。栅极绝缘层 13可以采用硅氧化物、 硅氮化物、 铪氧化物、 硅氮氧化物、 铝氧化物中的至少一种材料形成。 有源 层 14可以采用非晶硅材料形成。 钝化层 19可以采用硅氧化物、 硅氮化物、 铪氧化物、 铝氧化物中的至少两种材料形成。
在阐述具体制备方法之前， 应该理解， 在本发明的实施例中， 构图工艺 可以只包括光刻工艺， 或者可以包括光刻工艺以及刻蚀步骤， 同时还可以包 括打印、 喷墨等其他用于形成预定图形的工艺； 光刻工艺是指包括成膜、 曝 光、 显影等工艺过程的利用光刻胶、 掩模板、 曝光机等形成图形的工艺。 可 以根据本发明实施例中所形成的结构而选择相应的构图工艺。 这里， 光刻胶 以正性光刻胶为例， 但是本发明的实施例不限于此。
上述阵列基板的制备方法可以包括： 形成多条交叉设置的扫描线和数据 线的步骤， 其中扫描线和数据线将阵列基板划分为呈网格分布的非像素区以 及由非像素区包围形成的多个子像素区； 在子像素区、扫描线和 /或数据线的 上方形成包括公共电极的图形的步骤， 其中公共电极的对应于子像素区的区 域具有第一厚度， 公共电极的对应于扫描线和 /或数据线的区域具有第二厚 度， 第一厚度可以小于第二厚度。 在本实施例中， 如图 5A-5D、 图 5F和图 6A-6F所示， 该阵列基板的制 备方法可以包括：
步骤 S1 ): 在基板上形成包括栅电极的图形。
在该步骤中， 在基板 10上形成金属薄膜（即栅电极金属薄膜）， 通过一 次构图工艺在基板 10上形成包括栅电极 11和扫描线 12的图形，如图 5A和 图 6A所示。 形成金属薄膜可以采用沉积法、 溅射法或热蒸发法。 在构图工 艺中， 可以先在金属薄膜上形成一层光刻胶， 然后可以采用掩模板对光刻胶 进行曝光、 显影、 刻蚀和剥离， 以形成包括栅电极 11和扫描线 12的图形。
在该步骤中， 还可以同时在基板的对应于非像素区的区域（一般在基板 的边沿） 中形成公共电极连接线， 公共电极连接线留待与随后形成的公共电 极电连接， 公共电极连接线的结构和制备方法与现有技术相同， 这里不再详 述。
这里， 为能更清楚地示出本实施例中的阵列基板在制备过程中的剖面结 构， 剖面图 5A和平面图 6A设置为不同的比例； 同时， 为便于了解薄膜晶体 管的各层结构以及各层之间的位置关系， 平面图 5A中的各层设置为具有一 定透明度， 以下各平面图与各剖面图与此类似。
步骤 S2 ): 在完成步骤 S1 )的基板上形成包括栅极绝缘层和有源层的图 形。
在该步骤中： 在完成步骤 S1 ) 的基板 10上依次形成栅极绝缘层薄膜和 有源层薄膜，通过一次构图工艺形成包括有源层 14的图形。形成栅极绝缘层 薄膜可以采用化学气相沉积（筒称 CVD )法， 栅极绝缘层 13设置为覆盖已 完成步骤 S1 )的整个基板。 在构图工艺中， 先在有源层薄膜上形成一层光刻 胶， 采用掩模板对光刻胶进行曝光、 显影、 刻蚀、 剥离， 以形成包括有源层 14的图形， 如图 5B和图 6B所示。
在本实施例中，有源层 14可以采用非晶硅材料形成。 这里， 由于栅极绝 缘层 13覆盖于整个基板 10之上， 并且栅极绝缘层一般采用透明材料 (硅氧 化物、 硅氮化物、 铪氧化物、 硅氮氧化物、 铝氧化物中的至少一种材料）形 成， 所以栅极绝缘层对平面图的观察不会造成妨碍， 因此在图 5B的平面示 意图中没有示出栅极绝缘层 13, 以便能更好地示出栅电极 11、 扫描线 12与 有源层 14的相对位置关系。
步骤 S3 ): 在完成步骤 S2 ) 的基板上形成包括源电极和漏电极的图形。 在该步骤中： 在完成步骤 S2 ) 的基板 10上形成金属薄膜（即形成源电 极和漏电极的金属薄膜）， 通过一次构图工艺形成包括源电极 17、 漏电极 18 和数据线 16的图形， 其中源电极 17和漏电极 18位于有源层 14的上方且关 于栅电极 11在相对两侧。形成金属薄膜可以采用沉积法、溅射法或热蒸发法。 在构图工艺中， 可以先在金属薄膜上形成一层光刻胶， 然后采用掩模板对光 刻胶进行曝光、 显影、 刻蚀、 剥离， 以形成包括源电极 17、 漏电极 18和数 据线 16的图形， 如图 5C和图 6C所示。
步骤 S4 ): 在完成步骤 S3 ) 的基板上形成包括像素电极的图形。
在该步骤中： 在完成步骤 S3 ) 的基板 10上形成像素电极薄膜， 通过一 次构图工艺形成包括像素电极 15 的图形。 形成像素电极薄膜可以采用沉积 法、 溅射法或热蒸发法。 在构图工艺中， 可以先在像素电极薄膜上形成一层 光刻胶， 然后采用掩模板对光刻胶进行曝光、 显影、 刻蚀、 剥离， 以形成包 括像素电极 15的图形， 漏电极 18可以与像素电极 15直接电连接， 如图 5D 和图 6D所示。
步骤 S5 ): 在完成步骤 S4 ) 的基板上形成包括钝化层的图形， 如图 6E 所示。
在本步骤中，钝化层 19覆盖于整个基板 10之上。类似于栅极绝缘层 13, 钝化层 19一般采用透明材料（诸如， 硅氧化物、硅氮化物、铪氧化物或铝氧 化物）形成， 所以对平面图的观察不会造成妨碍， 因此钝化层没有在相应的 平面示意图中示出。
步骤 S6 ): 在完成步骤 S5 ) 的基板上形成包括公共电极的图形。
在该步骤中： 在完成步骤 S5 ) 的基板 10上形成公共电极薄膜， 通过一 次构图工艺在钝化层 19上形成包括公共电极 20的图形。 形成公共电极薄膜 可以采用沉积法、 溅射法或热蒸发法。 在构图工艺中， 可以先在公共电极薄 膜上形成一层光刻胶， 然后采用双色调掩模板（诸如半色调掩模板（half tone mask )或灰色调掩模板（gray tone mask ) )对光刻胶进行曝光、 显影、 刻蚀、 剥离， 以形成包括公共电极 20的图形， 如图 5F和图 6F所示。
此外，在阵列基板的非像素区中，钝化层 19在对应于公共电极连接线的 位置开设有过孔，公共电极 20可以通过该过孔与公共电极连接线电连接。如 前所述，公共电极连接线可以与栅电极 11以及扫描线 12同时形成在基板 10 上， 在本步骤中， 只需保证公共电极连接线与公共电极 20电连接即可。 具体地， 在完成步骤 S4 ) 的基板 10上形成钝化层薄膜， 通过一次构图 工艺形成钝化层 19图形， 钝化层 19图形覆盖源电极 17、 漏电极 18和像素 电极 15的部分。
形成钝化层薄膜可以采用沉积法、 溅射法或热蒸发法。 在构图工艺中， 可以先在钝化层薄膜上涂敷一层光刻胶，然后采用掩模板对光刻胶进行曝光、 显影、 刻蚀、 剥离， 以形成包括钝化层 19的图形。
由于形成薄膜晶体管的除了公共电极以外的其他层（即形成子像素区 1 内的栅电极 11、 栅极绝缘层 13、 有源层 14、 源电极 17、 漏电极 18、 像素电 极 15、 钝化层 19 ) 的制备工艺与现有技术中相同， 因此这里不再详述。 步骤 S611 ): 在钝化层上形成导电膜层。
在该步骤中， 可以采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡 中的至少一种材料，通过沉积、溅射或热蒸发的方法在钝化层 19上形成一层 导电膜层， 其中导电膜层的厚度可以等于所述第二厚度。
步骤 S612 ): 在导电膜层上形成光刻胶。
在本实施例中， 光刻胶可以采用正性光刻胶或负性光刻胶， 通过涂覆方 式在导电膜层上形成一层光刻胶。
步骤 S613 ): 采用双色调掩模板对光刻胶进行曝光、 显影， 该双色调掩 模板设置有完全保留区、 部分保留区和完全去除区， 光刻胶的对应于完全保 留区的区域被完全保留， 光刻胶的对应于部分保留区的区域被部分保留， 光 刻胶的对应于完全去除区的区域被完全去除。
双色调掩模板的对应于公共电极的狭缝的区域可以设置为狭缝状的完全 去除区， 对应于子像素区 1中除了狭缝之外的其他部分的区域可以设置为部 分保留区， 对应于扫描线和 /或数据线的区域可以设置为完全保留区。
经过曝光、 显影步骤， 光刻胶的对应于双色调掩模板的完全去除区的区 域可以被完全去除。 如果光刻胶采用正性光刻胶， 则在曝光过程中被光照射 到的部分正性光刻胶通过感光化学反应， 在显影液中易于被溶解， 从而被去 除。 相反地， 如果光刻胶采用负性光刻胶， 则在曝光过程中被光照射到的部 分负性光刻胶通过感光化学反应，在显影液中不易于被溶解，从而得以保留。
步骤 S614 ): 对完成步骤 S613 )的导电膜层进行刻蚀， 以在子像素区内 的导电膜层中形成狭缝， 该狭缝也成为最终形成的公共电极中的狭缝。 在该步骤中， 刻蚀可以采用湿法刻蚀工艺。 经过刻蚀步骤， 与公共电极 的狭缝相对应的导电膜层被完全去除， 从而在子像素区 1中形成公共电极的 狭缝。
步骤 S615 ): 对完成步骤 S614 )的光刻胶进行灰化处理， 灰化掉被部分 保留的光刻胶。
在该步骤中， 子像素区 1中对应于双色调掩模板的部分保留区的区域的 光刻胶被进一步完全去除， 使得子像素区 1内的导电膜层被完全暴露。
步骤 S616 ): 对完成步骤 S615 )的导电膜层进行刻蚀， 该刻蚀使子像素 区内的导电膜层的厚度减小， 同时形成公共电极的对应于扫描线和 /或数据线 的区域的图形。
在该步骤中， 刻蚀可以采用湿法刻蚀工艺， 经过刻蚀步骤， 对应于子像 素区 1的导电膜层变薄， 从而具有第一厚度； 而对应于扫描线 12和 /或数据 线 16的区域的导电膜层被完全保留，具有第二厚度，第二厚度大于第一厚度， 从而形成公共电极 20的完整图形。
步骤 S617 ): 将剩余的光刻胶剥离。
在该步骤中， 将剩余的光刻胶完全去除， 即将对应于扫描线和 /或数据线 的区域的光刻胶完全去除，以暴露出对应于扫描线和 /或数据线的区域的导电 膜层。
至此， 阵列基板制备完成。
在本实施例中， 通过双色调掩模板在子像素区 1和非像素区 2中形成了 厚度不等的公共电极， 在公共电极较厚的部分， 对应的电导率较大， 电阻率 较小， 相应的电阻较小； 在公共电极较薄的部分， 对应的电导率较小， 电阻 率较大， 相应的电阻较大。 因此， 能够均衡公共电极在子像素区 1和非像素 区 2的电压分布，使得公共电极 20提供的电压在整个显示区内的分布更均匀、 更稳定。
在上述阵列基板中，处于下层的电极为板状的像素电极，像素电极与 TFT 的漏电极电连接， 而处于上层的电极为狭缝状的公共电极。 通过狭缝电极边 缘与板状电极层之间产生的电场、 以及狭缝电极之间产生的电场共同形成多 维电场， 使液晶盒内的所有液晶分子都能够发生偏转， 从而实现图像显示。 第二实施例： 本实施例与第一实施例的区别在于， 在本实施例中， 阵列基板中的公共 电极 20可以由两种不同的材料形成，即公共电极 20在对应于扫描线和 /或数 据线的区域相对于子像素区 1中的公共电极突出的部分可以采用电导率更高 的材料形成。
具体地， 公共电极 20在对应于子像素区 1、 扫描线和 /或数据线的区域 中从其底表面至第一厚度的部分可以采用氧化铟镓辞、氧化铟辞、氧化铟锡、 氧化铟镓锡中的至少一种材料形成； 公共电极 20在对应于扫描线和 /或数据 线的区域中从第一厚度至第二厚度的部分可以采用钼、 钼铣合金、 铝、 铝钕 合金、 钛和铜中的至少一种材料形成。
相应地， 本实施例的阵列基板的制备方法可以具体包括如下步骤： 步骤 S600 ): 形成阵列基板的除了公共电极以外的其他层。
在该步骤中， 该阵列基板的最上面的一层为钝化层。
步骤 S611 ): 在钝化层上形成导电膜层。
在该步骤中， 导电膜层可以包括第一导电膜层和第二导电膜层， 可以先 采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料， 通 过溅射或热蒸发的方法在钝化层上形成第一导电膜层； 接着， 采用钼、 钼铌 合金、 铝、 铝钕合金、 钛和铜中的至少一种材料， 通过溅射或热蒸发的方法 在第一导电膜层上形成第二导电膜层； 其中第一导电膜层的厚度可以等于第 一厚度， 第二导电膜层的厚度可以等于第二厚度与第一厚度之差。 第一厚度 的范围可以为 550 ~ 100θΑ, 第二厚度的范围可以为 300 ~ 50θΑ。
步骤 S612 ): 在导电膜层上形成光刻胶。
步骤 S613 ): 采用双色调掩模板对光刻胶进行曝光、 显影， 该双色调掩 模板设置有完全保留区、 部分保留区和完全去除区， 光刻胶对应于完全保留 区的区域被完全保留， 对应于部分保留区的区域被部分保留， 对应于完全去 除区的区域被完全去除。
双色调掩模板的对应于公共电极的狭缝的区域设置为狭缝状的完全去除 区， 对应于子像素区 1内除了狭缝之外的其他部分的区域为部分保留区， 对 应于扫描线和 /或数据线的区域设置为完全保留区。
经过曝光、 显影步骤， 对应于公共电极中的狭缝的光刻胶可以被完全去 除。
步骤 S614 ): 对完成步骤 S613 )的导电膜层进行刻蚀， 在子像素区内的 导电膜层中形成狭缝。
在该步骤中， 刻蚀可以采用湿法刻蚀工艺， 经过刻蚀步骤， 对应于公共 电极中的狭缝的导电膜层被完全去除， 从而形成公共电极的狭缝。
步骤 S615 ): 对完成步骤 S614 )的光刻胶进行灰化处理， 灰化掉被部分 保留的光刻胶。
在该步骤中， 子像素区 1中对应于双色调掩模板的部分保留区的区域的 光刻胶被进一步完全去除， 使得子像素区 1内的第二导电膜层被完全暴露。
步骤 S616 ): 对完成步骤 S615 ) 的导电膜层进行刻蚀。
在该步骤中， 刻蚀可以采用湿法刻蚀工艺， 经过刻蚀步骤， 子像素区 1 内的第二导电膜层被完全去除， 使第一导电膜层被完全暴露， 从而形成公共 电极 20对应于子像素区 1的部分图形，该部分公共电极具有第一厚度； 而在 对应于扫描线 12和 /或数据线 16的区域的第二导电膜层被完全保留，该部分 公共电极（包括第一导电膜层和第二导电膜层）具有第二厚度， 第二厚度大 于第一厚度， 从而形成公共电极 20的完整图形。
步骤 S617 ): 将剩余的光刻胶剥离。
在该步骤中， 将剩余的光刻胶完全去除， 即将对应于扫描线和 /或数据线 的区域的光刻胶完全去除，并暴露出对应于扫描线和 /或数据线的区域的第二 导电膜层。
至此， 阵列基板制备完成。
本实施例中阵列基板的其他结构与第一实施例中的阵列基板的结构相 同， 制备方法的其他步骤与第一实施例中的阵列基板的制备方法相同， 这里 不再赘述。 第三实施例：
本实施例与第一和第二实施例的区别在于， 在本实施例的阵列基板中， 有机薄膜层可以进一步设置在源电极和漏电极与像素电极之间。
有机薄膜层可以采用含有感光材料的树脂材料形成， 有机薄膜层的厚度 可以为 2-4 μ ιη (厚度大于钝化层的厚度）。 有机薄膜层可以形成在源电极和 漏电极上， 并在对应于漏电极的区域开设有过孔， 漏电极可以通过该过孔与 像素电极电连接。
相应地， 本实施例的阵列基板的制备方法为： 栅电极沉积→采用普通掩 模板通过一次构图工艺形成栅电极→栅极绝缘层沉积→有源层沉积→采用普 通掩模板通过一次构图工艺形成有源层→金属薄膜沉积→采用普通掩模板通 过一次构图工艺形成源电极和漏电极→有机薄膜层沉积→采用普通掩模板通 过一次构图工艺形成有机薄膜层图形→像素电极沉积→采用普通掩模板通过 一次构图工艺形成像素电极→钝化层沉积→采用普通掩模板通过一次构图工 艺形成钝化层→公共电极沉积→采用半色调掩模板或灰色调掩模板通过一次 构图工艺形成公共电极。
本实施例中阵列基板的其他结构与第一或第二实施例中的阵列基板的结 构相同， 制备方法的其他步骤与第一或第二实施例中的阵列基板的制备方法 相同， 这里不再赘述。
在本实施例的阵列基板中， 由于有机薄膜层设置在源、 漏电极与像素电 极之间， 因此， 能够进一步减小阵列基板中的耦合电容， 减弱耦合电容对公 共电极的影响， 保证公共电极上的电压分布更均匀、 更稳定， 从而使得显示 装置能获得更好的画面显示质量。 第四实施例：
本实施例与第一至第三实施例的区别在于， 本实施例的阵列基板中的有 源层采用金属氧化物半导体形成。
在本实施例中， 有源层可以采用氧化铟镓辞（IGZO )、 氧化铟辞、 氧化 铟锡、 氧化铟镓锡中的至少一种材料形成。
在本实施例中， 由于有源层采用金属氧化物半导体形成， 使得源电极与 漏电极之间的电子迁移率增加， 因此能更好地改善源电极与漏电极之间的电 子迁移率。
本实施例中的阵列基板的其他结构与第一至第三实施例中任一个阵列基 板的结构相同， 制备方法的其他步骤与第一至第三实施例中任一个阵列基板 的制备方法相同， 这里不再赘述。
应该理解是， 尽管在第一至第四实施例中像素电极形成为板状并且公共 电极形成为狭缝状，但是本发明不限于此。备选地，像素电极可以为狭缝状， 公共电极可以为板状， 只要保证处于上方的电极为狭缝状， 处于下方的电极 为板状即可。
本发明的实施例还提供了一种显示装置，其包括上述任意一种阵列基板。 显示装置可以为： 液晶面板、 电子纸、 OLED面板、 手机、 平板电脑、 电视 机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或 部件。
在第一至第四实施例中， 仅以在底栅型薄膜晶体管阵列基板中公共电极 的对应于非像素区的区域的厚度（具体是， 对应于扫描线和 /或数据线的区域 的厚度） 大于公共电极的对应于子像素区的区域的厚度的结构为示例， 对阵 列基板的结构和制备方法进行了详细说明， 但是， 应该理解的是， 上述公共 电极在非像素区和子像素区具有不同厚度的结构同样适用于顶栅型薄膜晶体 管阵列基板， 在设计与生产过程中只需做适应性调整即可。
在第一至第四实施例的阵列基板中， 通过将公共电极设置为对应于非像 素区的扫描线和 /或数据线的区域的厚度大于对应于子像素区的区域的厚度 的结构， 相应地， 采用灰化工艺实现公共电极这种厚度不等的结构的制备， 能够增强公共电极的导电能力， 使得公共电极在整个液晶显示面板上的电压 分布更均匀、 更稳定， 提高了画面显示质量， 提升显示装置的品质等级。
可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而采用的示 例性实施方式， 然而本发明并不局限于此。 对于本领域内的普通技术人员而 言， 在不脱离本发明的精神和实质的情况下， 可以做出各种变型和改进， 这 些变型和改进也视为本发明的保护范围。

Claims

权利要求书
1. 一种阵列基板，该阵列基板包括呈网格分布的非像素区以及由所述非 像素区包围形成的多个子像素区 , 所述非像素区内设置有多条交叉设置的扫 描线和数据线，
其中公共电极设置在所述子像素区和所述非像素区中， 所述公共电极的 对应于所述子像素区的区域具有第一厚度， 所述公共电极的对应于所述扫描 线和 /或所述数据线的区域具有第二厚度， 所述第一厚度小于所述第二厚度。
2.根据权利要求 1所述的阵列基板，其中所述公共电极采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料形成。
3.根据权利要求 1所述的阵列基板，其中所述公共电极在对应于所述子 像素区、所述扫描线和 /或所述数据线的区域中从其底表面至所述第一厚度的 部分采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料 形成；所述公共电极在对应于所述扫描线和 /或所述数据线的区域中从所述第 一厚度至所述第二厚度的部分采用钼、 钼铌合金、 铝、 铝钕合金、 钛和铜中 的至少一种材料形成。
4.根据权利要求 1-3中任一项所述的阵列基板， 其中所述子像素区内设 置有栅电极、 栅极绝缘层、 有源层、 源电极、 漏电极、 像素电极以及钝化层， 所述扫描线与所述栅电极电连接， 所述数据线与所述源电极电连接， 所述像 素电极与所述漏电极电连接，所述公共电极延伸至覆盖所述扫描线和 /或所述 数据线。
5.根据权利要求 1-3中任一项所述的阵列基板， 其中有机薄膜层设置在 所述源电极、 所述漏电极与所述像素电极之间， 所述有机薄膜层采用含有感 光材料的树脂材料形成。
6.根据权利要求 4所述的阵列基板， 其中所述有源层采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料形成； 或者， 所述有源 层采用非晶硅材料形成。
7.根据权利要求 4所述的阵列基板，其中所述公共电极设置在所述钝化 层上， 所述公共电极在对应于所述子像素区的区域内呈狭缝状分布；
或者， 所述像素电极设置在所述钝化层上， 所述像素电极在对应于所述 子像素区的区域内呈狭缝状分布。
8. 根据权利要求 1-3 中任一项所述的阵列基板， 其中所述第一厚度在 550 ~ ΙΟΟθΑ的范围内， 所述第二厚度在 300 ~ 500A的范围内。
9.一种显示装置， 包括权利要求 1-8中任一项所述的阵列基板。
10. 一种阵列基板的制备方法， 包括：
形成多条交叉设置的扫描线和数据线的步骤， 所述扫描线和数据线将所 述阵列基板划分为呈网格分布的非像素区以及由所述非像素区包围形成的多 个子像素区；
在所述子像素区和所述非像素区中形成包括公共电极的图形的步骤， 所 述公共电极的对应于所述子像素区的区域具有第一厚度， 所述公共电极的对 应于所述扫描线和 /或所述数据线的区域具有第二厚度，所述第一厚度小于所 述第二厚度。
11.根据权利要求 10所述的制备方法，其中形成包括公共电极的图形包 括以下步骤：
步骤 S11 ): 形成导电膜层；
步骤 S12 ): 在所述导电膜层上形成光刻胶；
步骤 S13 ): 采用双色调掩模板对所述光刻胶进行曝光、 显影， 所述双色 调掩模板设置有完全保留区、 部分保留区和完全去除区， 所述光刻胶的对应 于所述完全保留区的区域被完全保留， 对应于所述部分保留区的区域被部分 保留， 对应于所述完全去除区的区域被完全去除；
步骤 S14 ): 对完成步骤 S13 )的导电膜层进行刻蚀， 在对应于所述子像 素区的区域中形成所述公共电极的狭缝；
步骤 S15 ): 对完成步骤 S14 )的光刻胶进行灰化处理， 灰化掉被部分保 留的光刻胶；
步骤 S16 ): 对完成步骤 S15 )的导电膜层进行刻蚀， 使所述子像素区内 的导电膜层的厚度减小， 同时形成所述公共电极的对应于扫描线和 /或数据线 的区域的图形；
步骤 S 17 ): 将剩余的光刻胶剥离。
12.根据权利要求 11所述的制备方法， 其中在所述步骤 S11 ) 中： 采用 氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料， 通过沉 积、 溅射或热蒸发的方法形成导电膜层， 其中所述导电膜层的厚度等于所述 第二厚度。
13.根据权利要求 11所述的制备方法， 其中在所述步骤 S11 ) 中： 在所 述导电膜层包括第一导电膜层和第二导电膜层的情形下，先采用氧化铟镓辞、 氧化铟辞、 氧化铟锡、 氧化铟镓锡中的至少一种材料， 通过沉积、 溅射或热 蒸发的方法形成第一导电膜层； 接着， 采用钼、 钼铣合金、 铝、 铝钕合金、 钛和铜中的至少一种材料， 通过溅射或热蒸发的方法在所述第一导电膜层上 形成第二导电膜层， 其中所述第一导电膜层的厚度等于所述第一厚度， 所述 第二导电膜层的厚度等于所述第二厚度与所述第一厚度之差。
14.根据权利要求 13所述的制备方法， 其中在所述步骤 S16 ) 中： 经过 所述刻蚀， 所述子像素区内的所述第二导电膜层被完全去除并使所述子像素 区内的所述第一导电膜层被完全暴露。
15. 根据权利要求 10-14 中任一项所述的制备方法， 其中在所述步骤 S13 ) 中： 所述双色调掩模板的对应于所述公共电极的狭缝的区域设置为完 全去除区， 对应于所述子像素区内除了所述狭缝之外的其他部分的区域设置 为部分保留区， 对应于所述扫描线和 /或所述数据线的区域设置为完全保留 区。
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