WO2014184839A1 - Dispositif semiconducteur au carbure de silicium - Google Patents

Dispositif semiconducteur au carbure de silicium Download PDF

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WO2014184839A1
WO2014184839A1 PCT/JP2013/063265 JP2013063265W WO2014184839A1 WO 2014184839 A1 WO2014184839 A1 WO 2014184839A1 JP 2013063265 W JP2013063265 W JP 2013063265W WO 2014184839 A1 WO2014184839 A1 WO 2014184839A1
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region
impurity concentration
type
silicon carbide
semiconductor device
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PCT/JP2013/063265
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English (en)
Japanese (ja)
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宏行 松島
泰之 沖野
龍太 土屋
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株式会社日立製作所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H01L29/66909—Vertical transistors, e.g. tecnetrons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors

Definitions

  • the present invention relates to a silicon carbide semiconductor device in which a semiconductor device structure is formed on a SiC (silicon carbide) substrate, and more particularly to a technique effective when applied to a JTE (Junction Termination Extension) structure of a silicon carbide semiconductor device.
  • a SiC silicon carbide
  • junction FET junction field effect transistor
  • the junction FET using the SiC substrate has a feature that the on-resistance can be further reduced at the same breakdown voltage when compared with the junction FET using the Si (silicon) substrate. This is due to the fact that the dielectric breakdown strength of SiC is about 10 times that of Si, so that the width of the depletion layer is about 1/10, and the epitaxial layer constituting the drift layer can be made thin.
  • the breakdown voltage of the junction FET is determined by the thickness and impurity concentration of the epitaxial layer constituting the drift layer.
  • the electric field is concentrated at the end of the active region where the junction FET is formed, dielectric breakdown occurs at a value smaller than the designed breakdown voltage unless a structure for relaxing the electric field is provided. Since the maximum electric field of the junction FET using the SiC substrate is about 10 times as high as that of the junction FET using the Si substrate, it is important to provide such a structure for relaxing the electric field.
  • JTE Joint ⁇ ⁇ TerminationJExtension
  • FLR Field Limiting Ring
  • Patent Document 1 adjusts the spread of the depletion layer by forming a plurality of p-type termination regions concentrically in an n-type drift layer around the active region and providing an impurity concentration gradient in these p-type termination regions. The desired breakdown voltage is obtained. Further, an n-type semiconductor region having a higher impurity concentration than that of the n-type drift layer is formed in the surface portion of the junction portion between adjacent termination regions, and the peak electric field at the surface portion of the junction portion is reduced by the n-type semiconductor region. I am letting.
  • a surface portion of a p-type ring region formed in an n-type drift layer outside an active region is a high-concentration ring region having a high p-type impurity concentration, and a portion deeper than the high-concentration ring region is a p-type impurity.
  • the FLR structure having a low-concentration ring region with a low concentration suppresses a decrease in breakdown voltage.
  • FIG. 13 is a cross-sectional view of an essential part showing a two-stage JTE structure of a silicon carbide semiconductor device examined by the present inventors.
  • symbol AR is an active region in which a junction FET (not shown) is formed
  • TR is a termination region located around the active region AR
  • 1 is an n + -type SiC serving as a drain region of the junction FET.
  • the substrate, 2 is an n ⁇ type drift layer, 6 is a p + type gate junction region, and 17 is a gate electrode.
  • a depletion layer expands in the first p ⁇ type termination region 41 having a low impurity concentration, and is completely depleted at a certain voltage.
  • the electric field strength has a peak at the end until the first p ⁇ -type termination region 41 is completely depleted, but thereafter, the depletion layer spreads in the second p ⁇ -type termination region 40 having a high impurity concentration.
  • the peak of the electric field strength moves from the end of the first p ⁇ -type termination region 41 to the end of the second p ⁇ -type termination region 40, and the avalanche breakdown occurs when this electric field strength peak reaches the dielectric breakdown strength. .
  • the 1p - peak electric field intensity at the end of the mold termination region 41 is first 1p just before reaching the dielectric breakdown strength - by type termination region 41 is completely depleted, the electric field intensity The voltage at which the peak moves to the end of the second p ⁇ type termination region 40 increases. For this reason, the voltage at which the peak of the electric field strength at the end of the second p ⁇ -type termination region 40 reaches the dielectric breakdown strength increases, and a high breakdown voltage silicon carbide semiconductor device is obtained.
  • the surface of the first p ⁇ -type termination region 41 and the surface of the second p ⁇ -type termination region 40 are covered with the silicon oxide film 11 that is an insulating material, the charge accumulated in the silicon oxide film 11 increases. At this time, the surface of the first p ⁇ type termination region 41 is depleted by the increased charge, and the first p ⁇ type termination region 41 is completely depleted at a low voltage. As a result, the voltage at which the peak of the electric field strength at the end of the second p ⁇ -type termination region 40 reaches the dielectric breakdown strength is lowered, and the breakdown voltage of the silicon carbide semiconductor device is lowered.
  • the n-type semiconductor region having a high impurity concentration formed in the surface portion of the junction portion of the termination region depletes the surface of the first p ⁇ -type termination region 41. Therefore, the reduction in breakdown voltage due to the charge of the silicon oxide film 11 is promoted.
  • the impurity concentration in the high-concentration ring region is 2 ⁇ 10 19 atom / cm 3 and the impurity concentration in the low-concentration region is 2 ⁇ 10 18 atom / cm 3. Concentration.
  • the JTE structure it is necessary to completely deplete the termination region in order to realize a high breakdown voltage.
  • the depletion does not occur at a high impurity concentration as in the FLR structure, a desired high breakdown voltage can be obtained. I can't.
  • An object of the present invention is to provide a silicon carbide semiconductor device capable of obtaining a stable high breakdown voltage even when the charge of an insulating film covering a termination region varies.
  • One aspect of the silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate, and a first conductivity type drift layer made of silicon carbide epitaxially grown on a main surface of the silicon carbide substrate, A silicon carbide semiconductor device in which a semiconductor device structure is formed on the main surface of the silicon carbide substrate, In plan view, the first semiconductor region of the second conductivity type formed in the drift layer of the second region adjacent to the first region in which the semiconductor device structure is formed; and in plan view, from the first semiconductor region And a second semiconductor region of a second conductivity type formed in the drift layer of the second region located on the first region side, The first semiconductor region is formed on a surface side of the drift layer, is formed in a first high impurity concentration region into which a second conductivity type impurity is introduced, and a lower portion of the first high impurity concentration region.
  • the second semiconductor region is formed on the surface side of the drift layer, and includes a second high impurity concentration region into which a second conductivity type impurity having a concentration higher than that of the first high impurity concentration region is introduced, and the second high impurity concentration region.
  • Each surface of the first and second semiconductor regions is covered with an insulating film.
  • FIG. 1 is a main part plan view showing a silicon carbide semiconductor device of a first embodiment.
  • FIG. 2 is a sectional view taken along line AA in FIG. 1.
  • 10 is a graph showing a typical example of an impurity concentration profile in a first p ⁇ type termination region.
  • 10 is a graph showing an ion implantation concentration profile of impurities for forming a second p ⁇ type termination region.
  • 10 is a graph showing a typical example of an impurity concentration profile of a second p ⁇ type termination region.
  • 3 is a graph showing a relationship between an impurity concentration peak in a first p ⁇ -type termination region and a withstand voltage.
  • FIG. 3 is a main-portion cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device of the first embodiment.
  • FIG. FIG. 8 is a main part cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device continued from FIG. 7.
  • FIG. 9 is a main part cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device continued from FIG. 8.
  • FIG. 10 is a main part cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device following FIG. 9.
  • FIG. 7 is a main part sectional view showing a silicon carbide semiconductor device of a second embodiment.
  • FIG. 7 is a main part sectional view showing a silicon carbide semiconductor device of a third embodiment. It is principal part sectional drawing which shows the 2 step
  • ⁇ ” and + ⁇ represent the relative concentrations of impurities of n-type or p-type conductivity. For example, in the case of n-type impurities, “n ⁇ ”, “n”, “ The impurity concentration increases in the order of “n + ”.
  • FIG. 1 is a schematic plan view showing the silicon carbide semiconductor device of the first embodiment
  • FIG. 2 is a cross-sectional view taken along line AA of FIG.
  • the silicon carbide semiconductor device of the first embodiment includes an active region (first region) AR located at the center of n + -type SiC substrate 1 and a termination located around active region AR. And a region (second region) TR.
  • the termination region TR includes a second p ⁇ -type termination region (second semiconductor region) 7 and a first p ⁇ -type termination region for relaxing an electric field concentrated on an end of an active region AR where a junction FET (described later) is formed.
  • a (first semiconductor region) 8 and an n + -type ring region (third semiconductor region) 9 are provided so as to surround the active region AR.
  • the silicon carbide semiconductor device includes two termination regions (second p ⁇ type termination region 7 and first p ⁇ type termination region) in which the impurity concentration decreases in order from the end of active region AR toward the outside. 8) having a two-stage JTE (Junction Termination Extension) structure.
  • JTE Joint Termination Extension
  • an n ⁇ type drift layer 2 having a lower impurity concentration than that of the n + type SiC substrate 1 is formed on the main surface of the n + type SiC substrate 1 that becomes the drain region of the junction FET.
  • the impurity (nitrogen) concentration of n + type SiC substrate 1 is in the range of 1 ⁇ 10 18 to 1 ⁇ 10 21 atom / cm 3
  • the impurity (nitrogen) concentration of n ⁇ type drift layer 2 is 1 ⁇ 10 15. It is in the range of ⁇ 1 ⁇ 10 16 atom / cm 3 .
  • the thickness of the n ⁇ type drift layer 2 is in the range of 25 to 35 ⁇ m.
  • a plurality of n + -type source regions 3 of the junction FET are formed at a predetermined interval on the surface of the n ⁇ -type drift layer 2 in the active region AR. These n + -type source regions 3 extend in a stripe shape along the first direction (direction perpendicular to the paper surface) of the main surface of n + -type SiC substrate 1.
  • the impurity (nitrogen) concentration of the n + -type source region is higher than the impurity concentration of the n + -type SiC substrate 1 and is in the range of 1 ⁇ 10 18 to 1 ⁇ 10 21 atom / cm 3 .
  • a trench 4 is opened in the n ⁇ -type drift layer 2 between adjacent n + -type source regions 3, and a silicon oxide film 11 covering the surface of the n ⁇ -type drift layer 2 is formed inside the trench 4. Some are embedded.
  • a p + type gate region 5 of the junction FET is formed on the bottom and side walls of the trench 4. Further, n in the active region AR - -type drift layer 2, the p + -type gate junction region 6 which is electrically connected to the p + -type gate region 5 is formed.
  • the impurity (aluminum) concentration of the p + type gate region 5 and the p + type gate junction region 6 is in the range of 1 ⁇ 10 18 to 1 ⁇ 10 21 atom / cm 3 .
  • a contact layer 10 made of a nickel silicide film is formed on the surface of each of the n + -type source region 3, the p + -type gate junction region 6 and the n + -type ring region 9.
  • the contact layer 10 formed on the surface of the n + -type source region 3 is electrically connected to the source electrode 16 through the contact hole 12 formed in the silicon oxide film 11.
  • the contact layer 10 formed on the surface of the p + type gate junction region 6 is electrically connected to the gate electrode 17 through the contact hole 13 formed in the silicon oxide film 11, and the n + type ring region 9.
  • the contact layer 10 formed on the surface is electrically connected to the ring wiring 18 through the contact hole 14 formed in the silicon oxide film 11.
  • the source electrode 16, the gate electrode 17, and the ring wiring 18 are made of the same layer metal film mainly composed of aluminum.
  • a surface protective film 30 made of a polyimide resin film is formed on the uppermost portion of the main surface of the n + -type SiC substrate 1.
  • an opening 31 is formed in the surface protection film 30 in the active region AR, and the source electrode 16 exposed at the bottom of the opening 31 constitutes a source pad.
  • another opening is formed in the surface protective film 30, and the gate electrode 17 exposed at the bottom of this opening constitutes a gate pad.
  • a drain electrode 19 made of a nickel silicide film is formed on the back surface of the n + -type SiC substrate 1.
  • the junction FET of the first embodiment, n + -type source pad and gate pads provided on the main surface of the SiC substrate 1, a drain electrode provided on the back surface side of the n + -type SiC substrate 1 19 has a three-terminal structure.
  • the operation of the junction FET according to the first embodiment is basically the same as that of the conventional vertical junction FET, and is from the p + type gate region 5 to the channel (n ⁇ type drift below the n + type source region 3).
  • the width of the depletion layer extending to layer 2) By controlling the width of the depletion layer extending to layer 2), the current flowing between the source and drain is switched on and off. That is, in the off state, a negative voltage is applied to the gate (p + -type gate region 5), and a depletion layer is extended from the gate to the channel so that carriers (electrons) do not flow between the source and drain. In the ON state, the depletion layer is reduced by applying a positive voltage to the gate and the drain, and carriers (electrons) flow from the source to the drain.
  • the first p ⁇ type termination region 8 is an n ⁇ type.
  • the depth from the surface of the drift layer 2 is set to be in the range of 0.5 to 2.0 ⁇ m.
  • the first p ⁇ -type termination region 8 is a region (charge compensation region 8a, first high impurity concentration region) from the surface of the n ⁇ -type drift layer 2 to a depth of about 0 to 0.5 ⁇ m.
  • the impurity (aluminum) concentration is higher than the impurity (aluminum) concentration in a region deeper than this region (the charge relaxation region 8b, the first low impurity concentration region).
  • n - -type charge compensation region 8a having a high impurity concentration formed in the vicinity of the surface of the drift layer 2, n - due to the charges accumulated in the silicon oxide film 11 covering the surface of the type drift layer 2, the 1p -
  • the surface of the mold termination region 8 has a function of suppressing depletion.
  • the total amount of impurities in the first p ⁇ -type termination region 8 is kept constant by the charge relaxation region 8b.
  • the charge relaxation region 8b is formed when the electric field intensity at the end of the second p ⁇ type termination region 7 becomes maximum after the first p ⁇ type termination region 8 is completely depleted as the voltage increases. It also plays a role in reducing the electric field strength.
  • the peak position of the impurity concentration in the charge compensation region 8a is set in the range of 0 to 0.2 ⁇ m or less from the surface of the n ⁇ -type drift layer 2, and the impurity peak concentration is 3.0 ⁇ 10 17 to 4.5. It is set in the range of ⁇ 10 17 atom / cm 3 . As shown in FIG. 6, the impurity peak concentration range is 4.5 ⁇ 10 17 atom / cm 3 when the charge amount of the silicon oxide film 11 is 1.0 ⁇ 10 12 / cm 2.
  • the simulation shows a high withstand voltage when the impurity peak concentration is 3.0 ⁇ 10 17 atom / cm 3 or more Determined from the results.
  • the impurity concentration of the electric field relaxation layer 8b is set in the range of 1.0 ⁇ 10 17 to 2.0 ⁇ 10 17 atom / cm 3 . At this time, the impurity concentration ratio between the charge compensation region 8a and the electric field relaxation layer 8b is 0.30 to 0.45.
  • the second p ⁇ type termination region 7 is formed so as not to be deeper than the first p ⁇ type termination region 8 when the depth from the surface of the n ⁇ type drift layer 2 is in the range of 0.5 to 2.0 ⁇ m. ing.
  • FIG. 4 shows an ion implantation concentration profile of impurities for forming the second p ⁇ -type termination region 7.
  • the impurity concentration of the second p ⁇ -type termination region 7 has a substantially uniform peak concentration between 1.0 ⁇ 10 17 and 2.0 ⁇ 10 17 atoms / cm 3 .
  • the second p ⁇ -type termination region 7 is implanted with an impurity for forming the first p ⁇ -type termination region 8 and an impurity for forming the second p ⁇ -type termination region 7. Therefore, the 2p - type termination region 7, the 1p - similar to the type termination region 8, n - the vicinity of the surface of the type drift layer 2 constitute a high impurity concentration of the charge compensation region (second high impurity concentration regions) 7a The lower layer constitutes a charge relaxation region (second low impurity concentration region) 7b having a low impurity concentration.
  • a typical example of the impurity concentration profile of the second p ⁇ -type termination region 7 is shown in FIG.
  • the peak position of the impurity concentration in the charge compensation region 7a is set in a range of 0 to 0.2 ⁇ m or less from the surface of the n ⁇ type drift layer 2, and the impurity peak concentration is 4.0 ⁇ 10 17 to 6.5. It is set in the range of ⁇ 10 17 atom / cm 3 .
  • the impurity concentration of the electric field relaxation layer 7b is set in the range of 2.0 ⁇ 10 17 to 4.0 ⁇ 10 17 atom / cm 3 . At this time, the impurity concentration ratio between the charge compensation region 7a and the electric field relaxation layer 7b is 0.50 to 0.65.
  • a difference in impurity concentration between the charge compensation region 8a and the electric field relaxation layer 8b in the first p ⁇ type termination region 8 and a difference in impurity concentration between the charge compensation region 7a and the electric field relaxation layer 7b in the second p ⁇ type termination region 7 are obtained.
  • the impurity concentration difference in the second p ⁇ -type termination region 7 is larger.
  • the depth of the n + -type ring region 9 formed outside the first p ⁇ -type termination region 8 is set in the range of 0.5 to 2.0 ⁇ m from the surface of the n ⁇ -type drift layer 2.
  • the impurity (nitrogen) concentration in the n + -type ring region 9 is set in the range of 1.0 ⁇ 10 19 to 1.0 ⁇ 10 21 atom / cm 3 .
  • the first p ⁇ type termination region 8 Since complete depletion can be delayed, a silicon carbide semiconductor device capable of obtaining a stable high breakdown voltage can be realized.
  • an n + -type SiC substrate 1 made of 4H—SiC doped with an n-type impurity (nitrogen) is prepared, and its Si surface is the main surface.
  • an n ⁇ type drift layer 2 made of SiC is formed on the main surface of the n + type SiC substrate 1 by using an epitaxial growth method.
  • a silicon oxide film 20 is deposited on the n ⁇ -type drift layer 2 by plasma CVD, and then dry using a photoresist film (not shown) as a mask.
  • the silicon oxide film 20 is patterned by etching.
  • the film thickness of the silicon oxide film 20 is in the range of 1 to 3 ⁇ m.
  • a p-type impurity (aluminum) is ion-implanted into the n ⁇ -type drift layer 2 in the termination region TR, whereby the first p ⁇ -type termination is performed.
  • Region 8 is formed.
  • the ion implantation of the p-type impurity is performed by multi-stage implantation with different acceleration voltages, and the charge compensation region 8a is formed in the shallow region of the n ⁇ -type drift layer 2 and the electric field relaxation layer 8b is formed in the deep region.
  • the silicon oxide film 21 deposited on the n ⁇ type drift layer 2 is patterned by the same method as described above.
  • a second p ⁇ type termination region 7 is formed by ion-implanting p type impurities (aluminum) into a part of the first p ⁇ type termination region 8 using the silicon oxide film 21 as a mask.
  • the impurity concentration of the charge compensation region 8a and the impurity concentration of the electric field relaxation layer 8b formed in advance are Due to the difference, a high impurity concentration charge compensation region 7a is formed in the shallow region of the second p ⁇ type termination region 7 (near the surface of the n ⁇ type drift layer 2), and a low impurity concentration electric field relaxation is formed in the deep region. Layer 7b is formed.
  • the silicon oxide film 22 deposited on the n ⁇ type drift layer 2 is patterned by the same method as described above.
  • p + -type gate junction region 6 is formed by ion-implanting p-type impurities (aluminum) into a part of n ⁇ -type drift layer 2 in active region AR using silicon oxide film 22 as a mask.
  • n + -type source region 3 is formed by ion-implanting n-type impurities (nitrogen) into n ⁇ -type drift layer 2 of active region AR using silicon oxide film 23 as a mask.
  • n-type impurities are ion-implanted also into the n ⁇ -type drift layer 2 in the termination region TR to form an n + -type ring region 9 that functions as a channel stopper.
  • the silicon oxide film 24 deposited on the n ⁇ type drift layer 2 is patterned by the same method as described above. Subsequently, by using the silicon oxide film 24 as a mask, the n + type source region 3 and the n ⁇ type drift layer 2 therebelow are dry-etched to form a plurality of grooves 4 in the n ⁇ type drift layer 2 in the active region AR. Form.
  • p-type impurities (aluminum) are ion-implanted into the trench 4 using the silicon oxide film 24 as a mask.
  • the p-type impurity is implanted by combining the vertical ion implantation method and the oblique ion implantation method so that the p-type impurity is implanted into the bottom and the side wall of the trench 4.
  • p + -type gate region 5 is formed at the bottom and side wall of trench 4.
  • the n + -type SiC substrate 1 is annealed, so that the n-type impurity (nitrogen) and p-type impurities (nitrogen) implanted into the n ⁇ -type drift layer 2 in the steps so far are used.
  • Aluminum is activated.
  • the annealing temperature of the n + -type SiC substrate 1 is set to about 1700 to 1800 ° C.
  • the main surface side of the n + -type SiC substrate 1 and the back The side is covered with a carbon film 25.
  • the silicon oxide film 11 deposited using the plasma CVD method is buried in the groove 4, and then the silicon oxide film 11 is etched back. And flatten the surface. Subsequently, the silicon oxide film 11 is dry-etched using the photoresist film as a mask, thereby exposing the respective surfaces of the n + type source region 3, the p + type gate junction region 6 and the n + type ring region 9. Holes 12, 13, and 14 are formed.
  • a contact layer 10 made of a nickel silicide film is formed.
  • a nickel film is deposited on the silicon oxide film 11 by using a sputtering method, and then the n + type SiC substrate 1 is annealed to thereby form the n + type source region 3.
  • the unreacted nickel film is removed.
  • a drain electrode 19 made of a nickel silicide film is formed on the back surface of the n + -type SiC substrate 1 by a similar method.
  • this metal film is formed by dry etching using a photoresist film as a mask. Is patterned.
  • the source electrode 16 electrically connected to the contact layer 10 on the surface of the n + -type source region 3
  • the gate electrode 17 electrically connected to the contact layer 10 on the surface of the p + -type gate junction region 6
  • a ring wiring 18 electrically connected to the contact layer 10 on the surface of the n + -type ring region 9 is formed.
  • a surface protective film 30 made of a polyimide resin film is formed on the uppermost part of the main surface of the n + -type SiC substrate 1, and then an opening 31 is formed in the surface protective film 30 above the source electrode 16. And the silicon carbide semiconductor device of the first embodiment shown in FIG. 2 is completed.
  • FIG. 11 is a main part cross-sectional view showing the silicon carbide semiconductor device of the second embodiment.
  • the difference between the second embodiment and the first embodiment is that the n ⁇ type drift layer 2 outside the first p ⁇ type termination region 8 (on the side away from the active region AR) is different. This is because the p + -type ring region (third semiconductor region) 32 is formed.
  • the p + -type ring region 32 has the same depth from the surface of the n ⁇ -type drift layer 2 and the impurity concentration as that of the second p ⁇ -type termination region 7. That is, the p + -type ring region 32 is formed at the same time in the ion implantation step (step shown in FIG. 8A) for forming the second p ⁇ -type termination region 7.
  • one p + -type ring region 32 is formed outside the first p ⁇ -type termination region 8, but two or more p + -type ring regions 32 may be formed.
  • the silicon carbide semiconductor device capable of obtaining a more stable high breakdown voltage can be realized.
  • FIG. 12 is a cross-sectional view of main parts showing the silicon carbide semiconductor device of the second embodiment. As shown in FIG. 12, the difference between the third embodiment and the first and second embodiments is that three or more p ⁇ type termination regions are formed in the n ⁇ type drift layer 2 of the termination region TR. It is in.
  • the 2p - type n of the inner termination region 7 (the side closer to the active region AR) - the type drift layer 2, the 2p - type termination higher impurity concentration than the region 7 a 3p - A mold termination region (fourth semiconductor region) 33 is formed. Also, the 1p - -type drift layer 2, the 1p - - outer n type termination region 8 first 4p impurity concentration lower than type termination region 8 - -type termination region 34 is formed.
  • the fourth p ⁇ type termination region 34 relaxes the electric field at the end of the first p ⁇ type termination region 8, and the third p ⁇ type termination region 33 relaxes the electric field after the second p ⁇ type termination region 7 is completely depleted. Act as a region.
  • the impurity on the surface side (charge compensation region 8a) of the n ⁇ type drift layer 2 is used only in the ion implantation step when forming the first p ⁇ type termination region 8.
  • the concentration may be increased and the impurity concentration in the lower portion (charge relaxation region 8a) may be decreased.
  • the 1p - second 2p is formed inside the mold termination region 8 - -type termination region 7 is also formed with a charge relaxation region 7b and the charge compensation region 7a is, first 3p is further formed on the inside -
  • the charge termination region 33 is also formed with a charge compensation region 33a and a charge relaxation region 33b. Further, the impurity concentration difference between the charge compensation region and the charge relaxation region becomes smaller as the inner p ⁇ -type termination region.
  • the third embodiment an example in which four p ⁇ -type termination regions are formed in the n ⁇ -type drift layer 2 is shown, but five or more p ⁇ -type termination regions may be formed.
  • the condition is that the impurity concentration is lowered from the outer p ⁇ -type termination region toward the inner p ⁇ -type termination region.
  • the third embodiment it is possible to realize a silicon carbide semiconductor device that can obtain a more stable high breakdown voltage than in the first embodiment.
  • the silicon carbide semiconductor device of the fourth embodiment is replaced with a semiconductor device in this active region AR instead of the junction FET which is a semiconductor device structure formed in the active region AR of the silicon carbide semiconductor device of the first to third embodiments.
  • a metal-oxide semiconductor junction field effect transistor MOSFET
  • IGBT insulated gate bipolar transistor
  • SBD Schottky diode
  • JBS junction barrier Schottky diode
  • a silicon carbide semiconductor device capable of obtaining a stable high breakdown voltage can be realized as in the silicon carbide semiconductor devices of the first to third embodiments.
  • the present invention is not limited to a semiconductor device in which a junction FET is formed on a silicon carbide substrate, but a power semiconductor such as a metal-oxide semiconductor junction field effect transistor, an insulated gate bipolar transistor, a Schottky diode, or a junction barrier Schottky diode. It can be applied in general.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif semiconducteur au carbure de silicium dans lequel une deuxième région de terminaison de type P (7), réalisée sur une couche flottante de type N (2) plus loin vers une région active (AR) que l'est une première région de terminaison de type P (8), présente une concentration d'impuretés plus élevée que ladite première région de terminaison de type P (8). De même, dans lesdites première région de terminaison de type P (8) et deuxième région de terminaison de type P (7), les régions de compensation de charge (8a, 7a) formés sur le côté de la surface supérieure de la couche flottante de type N (2) présentent des concentrations d'impuretés supérieures à celle des régions de relaxation de charge (8b, 7b) qui sont plus profondes que lesdites régions de compensation de charge (8a, 7a). Ainsi, même si la charge d'un film d'oxyde de silicium (11) qui couvre la couche flottante de type N (2) dans une région terminale (TR) varie, un appauvrissement complet de la première région de terminaison de type P (8) peut être retardé, ce qui permet d'obtenir une tension de tenue stable élevée.
PCT/JP2013/063265 2013-05-13 2013-05-13 Dispositif semiconducteur au carbure de silicium WO2014184839A1 (fr)

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Publication number Priority date Publication date Assignee Title
RU172837U1 (ru) * 2017-04-05 2017-07-26 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Диод с барьером шоттки на основе карбида кремния
WO2019159237A1 (fr) * 2018-02-13 2019-08-22 新電元工業株式会社 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
CN114300530A (zh) * 2022-03-09 2022-04-08 芯众享(成都)微电子有限公司 一种碳化硅功率器件结终端结构及其制备方法

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JPH09162422A (ja) * 1995-12-08 1997-06-20 Hitachi Ltd プレーナ型半導体装置
WO1998002924A2 (fr) * 1996-07-16 1998-01-22 Abb Research Ltd. DISPOSITIF A SEMI-CONDUCTEURS EN SiC COMPORTANT UNE JONCTION pn AVEC UN BORD ABSORBANT LA TENSION
JP2007173705A (ja) * 2005-12-26 2007-07-05 Toyota Central Res & Dev Lab Inc 窒化物半導体装置
WO2011141981A1 (fr) * 2010-05-10 2011-11-17 株式会社日立製作所 Dispositif à semi-conducteur

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Publication number Priority date Publication date Assignee Title
JPH09162422A (ja) * 1995-12-08 1997-06-20 Hitachi Ltd プレーナ型半導体装置
WO1998002924A2 (fr) * 1996-07-16 1998-01-22 Abb Research Ltd. DISPOSITIF A SEMI-CONDUCTEURS EN SiC COMPORTANT UNE JONCTION pn AVEC UN BORD ABSORBANT LA TENSION
JP2007173705A (ja) * 2005-12-26 2007-07-05 Toyota Central Res & Dev Lab Inc 窒化物半導体装置
WO2011141981A1 (fr) * 2010-05-10 2011-11-17 株式会社日立製作所 Dispositif à semi-conducteur

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU172837U1 (ru) * 2017-04-05 2017-07-26 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Диод с барьером шоттки на основе карбида кремния
WO2019159237A1 (fr) * 2018-02-13 2019-08-22 新電元工業株式会社 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
JPWO2019159237A1 (ja) * 2018-02-13 2021-01-07 新電元工業株式会社 半導体装置及び半導体装置の製造方法
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CN114300530A (zh) * 2022-03-09 2022-04-08 芯众享(成都)微电子有限公司 一种碳化硅功率器件结终端结构及其制备方法

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