WO2014163099A3 - 再構成可能な論理デバイス - Google Patents

再構成可能な論理デバイス Download PDF

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Publication number
WO2014163099A3
WO2014163099A3 PCT/JP2014/059703 JP2014059703W WO2014163099A3 WO 2014163099 A3 WO2014163099 A3 WO 2014163099A3 JP 2014059703 W JP2014059703 W JP 2014059703W WO 2014163099 A3 WO2014163099 A3 WO 2014163099A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
reconfigurable logic
data input
configuration
data output
Prior art date
Application number
PCT/JP2014/059703
Other languages
English (en)
French (fr)
Other versions
WO2014163099A2 (ja
Inventor
佐藤　正幸
幸志 佐藤
満徳 勝
勲 志水
Original Assignee
太陽誘電株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 太陽誘電株式会社 filed Critical 太陽誘電株式会社
Priority to TW103112408A priority Critical patent/TWI636667B/zh
Priority to US14/781,880 priority patent/US9425800B2/en
Priority to JP2015510111A priority patent/JPWO2014163099A1/ja
Priority to CN201480018307.2A priority patent/CN105191139B/zh
Publication of WO2014163099A2 publication Critical patent/WO2014163099A2/ja
Publication of WO2014163099A3 publication Critical patent/WO2014163099A3/ja

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories

Abstract

【課題】面積の小さくかつ再構成性の高い再構成可能な論理デバイスを提供できる。 【解決手段】複数のマルチルックアップテーブルユニットを有し、構成データ情報に応じて複数の論理回路が構成される再構成可能論理デバイスであって、それぞれのマルチルックアップテーブルユニットは、構成データを格納する構成メモリと、データ入力線と、データ出力線と、前記構成データに応答して選択的に前記データ入力線からのデータ入力と、前記データ出力線への前記データ出力とを結合させ、及び／又は、前記構成データに応答して前記データ入力に関して論理演算したデータを、前記データ出力線へデータ出力する再構成可能論理マルチプレクサと、を備え、前記データ入力線および前記データ出力線により近接する前記マルチルックアップテーブルが接続される、再構成可能論理デバイス。
PCT/JP2014/059703 2013-04-02 2014-04-02 再構成可能な論理デバイス WO2014163099A2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW103112408A TWI636667B (zh) 2013-04-02 2014-04-02 可再構成之邏輯元件
US14/781,880 US9425800B2 (en) 2013-04-02 2014-04-02 Reconfigurable logic device
JP2015510111A JPWO2014163099A1 (ja) 2013-04-02 2014-04-02 再構成可能な論理デバイス
CN201480018307.2A CN105191139B (zh) 2013-04-02 2014-04-02 可重构逻辑器件

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013076506 2013-04-02
JP2013-076506 2013-04-02

Publications (2)

Publication Number Publication Date
WO2014163099A2 WO2014163099A2 (ja) 2014-10-09
WO2014163099A3 true WO2014163099A3 (ja) 2014-11-27

Family

ID=51659278

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/059703 WO2014163099A2 (ja) 2013-04-02 2014-04-02 再構成可能な論理デバイス

Country Status (5)

Country Link
US (1) US9425800B2 (ja)
JP (1) JPWO2014163099A1 (ja)
CN (1) CN105191139B (ja)
TW (1) TWI636667B (ja)
WO (1) WO2014163099A2 (ja)

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CN107078740A (zh) * 2014-10-22 2017-08-18 太阳诱电株式会社 可重构设备
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
JP6405262B2 (ja) * 2015-02-18 2018-10-17 太陽誘電株式会社 再構成可能な論理デバイス
US10963001B1 (en) * 2017-04-18 2021-03-30 Amazon Technologies, Inc. Client configurable hardware logic and corresponding hardware clock metadata
JP6895061B2 (ja) * 2017-04-28 2021-06-30 オムロン株式会社 処理装置及び生成装置
CN108170203B (zh) * 2018-02-02 2020-06-16 清华大学 用于可重构处理系统的查表算子及其配置方法
US10541010B2 (en) * 2018-03-19 2020-01-21 Micron Technology, Inc. Memory device with configurable input/output interface
WO2021060059A1 (ja) * 2019-09-27 2021-04-01 太陽誘電株式会社 生成装置、生成方法およびプログラム

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JP2003198361A (ja) * 2001-12-28 2003-07-11 Fujitsu Ltd プログラマブル論理デバイス
JP2006313999A (ja) * 2005-05-09 2006-11-16 Renesas Technology Corp 半導体装置
JP2009194676A (ja) * 2008-02-15 2009-08-27 Hiroshima Industrial Promotion Organization プログラマブル論理デバイスおよびその構築方法およびその使用方法
JP2010239325A (ja) * 2009-03-30 2010-10-21 Hiroshima Ichi 半導体装置

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US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
WO1999038071A1 (en) * 1998-01-26 1999-07-29 Chameleon Systems, Inc. Reconfigurable logic for table lookup
US6150838A (en) 1999-02-25 2000-11-21 Xilinx, Inc. FPGA configurable logic block with multi-purpose logic/memory circuit
DE60228083D1 (de) * 2001-05-16 2008-09-18 Nxp Bv Rekonfigurierbare logik-vorrichtung
EP1324495B1 (en) 2001-12-28 2011-03-30 Fujitsu Semiconductor Limited Programmable logic device with ferrroelectric configuration memories
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CN1295879C (zh) * 2002-03-18 2007-01-17 皇家飞利浦电子股份有限公司 在可重构逻辑中宽多路复用器的实现
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JP2003198361A (ja) * 2001-12-28 2003-07-11 Fujitsu Ltd プログラマブル論理デバイス
JP2006313999A (ja) * 2005-05-09 2006-11-16 Renesas Technology Corp 半導体装置
JP2009194676A (ja) * 2008-02-15 2009-08-27 Hiroshima Industrial Promotion Organization プログラマブル論理デバイスおよびその構築方法およびその使用方法
JP2010239325A (ja) * 2009-03-30 2010-10-21 Hiroshima Ichi 半導体装置

Also Published As

Publication number Publication date
TW201503590A (zh) 2015-01-16
US9425800B2 (en) 2016-08-23
WO2014163099A2 (ja) 2014-10-09
JPWO2014163099A1 (ja) 2017-02-16
US20160036447A1 (en) 2016-02-04
CN105191139A (zh) 2015-12-23
TWI636667B (zh) 2018-09-21
CN105191139B (zh) 2018-12-07

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