WO2014158200A1 - Dispositif semi-conducteur à courant de fuite réduit et son procédé de fabrication - Google Patents

Dispositif semi-conducteur à courant de fuite réduit et son procédé de fabrication Download PDF

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Publication number
WO2014158200A1
WO2014158200A1 PCT/US2013/039160 US2013039160W WO2014158200A1 WO 2014158200 A1 WO2014158200 A1 WO 2014158200A1 US 2013039160 W US2013039160 W US 2013039160W WO 2014158200 A1 WO2014158200 A1 WO 2014158200A1
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Prior art keywords
voltage
logic
circuit
output
voltage supply
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PCT/US2013/039160
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English (en)
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Gajendra Prasad SINGH
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Cold Brick Semiconductor, Inc.
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Priority claimed from US13/850,269 external-priority patent/US9025404B1/en
Application filed by Cold Brick Semiconductor, Inc. filed Critical Cold Brick Semiconductor, Inc.
Publication of WO2014158200A1 publication Critical patent/WO2014158200A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the disclosure relates generally to the field of semiconductor devices and in particular to a semiconductor device with reduced leakage current and a method of designing these reduced leakage current semiconductor devices.
  • ICs Semiconductor Integrated Chips
  • computers and consumer electronics used in everyday lives, large servers and machines that control many parts of human lives everyday.
  • ICs are used in critical defense machines, machine that control the flow of information, the Internet, other communication networks and various communication mechanisms, etc.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS technology has made remarkable and significant progress in last couple of decades. As predicted by Gordon Moore in 1965 (known as Moore's Law), CMOS manufacturing technology has progressed to a new NODE every 2 years wherein CMOS transistor geometry is shrunk drastically such that a given IC is shrunk to almost half size in less than 2 years when re-designed and manufactured in next generation process. This improvement results in lowering the cost of manufacturing ICs and/or increasing the total amount of work that can be done by an IC.
  • ICs manufactured using the newer technology are cheaper, more powerful and consume less energy. This trend has continued for many decades and is expected to continue for many years in future.
  • An example of the improvement is that, not long ago, a supercomputer required a entire building of space, required a dedicated mini power plant to power and run air conditioner to cool all of the parts of the supercomputer and cost millions of dollars.
  • ICs have become so miniaturized in size, have low power requirements and very low costs that ICS are now used in inexpensive toys and provide very sophisticated control, monitoring, audio visual or robotics functions etc.
  • current ICs are so reliable that they are integrated into critical devices such as pacemaker. They are so critical that entire country's defense infrastructure depends on them.
  • the features, improvements and advantages of CMOS process technology has proven to be a gift to human kind and is expected to continue to be so for long time.
  • a CMOS device generally includes an N-type Metal Oxide Semiconductor (NMOS) transistor/device and/or a P-type Metal Oxide Semiconductor (PMOS) transistor/device (each of which is known as a MOS device or MOS transistor.)
  • NMOS N-type Metal Oxide Semiconductor
  • PMOS P-type Metal Oxide Semiconductor
  • the NMOS and PMOS devices both work as voltage current switches or as voltage dependent current sources. When appropriate voltage is applied at a control node, the switch is ON and current flows between two terminals of the switch (the conducting switch) and when another voltage is applied at the control node the switch is OFF and no current flows between the two terminals of the switch (the nonconducting switch).
  • Any MOS transistor has 4-terminals that include a "gate”, a "source”, a "drain” and a "body.”
  • NMOS negative voltage on the gate terminal with respect to the source terminal
  • PMOS negative voltage
  • the PMOS device acts as an OFF switch and no current flows from the source terminal to the drain terminal or from drain terminal to the source terminal.
  • the "body" node in both NMOS and PMOS devices acts as a reservoir of mobile charges and helps these devices act as switches.
  • CMOS transistors With their switch like behaviors, CMOS transistors (NMOS and PMOS) are best suited for digital technology and more than 95% ICs in the world are designed using digital technology.
  • digital technology all functions and computations are translated to only two states - "Zero"(0) and "One"(l), also called binary states. All logic functions, therefore, are constructed using binary states or binary logic.
  • Logic gates that translate functions in binary logic are called Boolean functions or Boolean gates. These binary or Boolean gates are connected physically by wires to form a complete one-bit function or a multi-bit function. All computing functions are therefore converted to binary or Boolean functions using mathematics that follows Boolean algebra or binary algebra (algebra with base 2).
  • a Boolean gate or Boolean function is implemented using CMOS transistors that are connected to each other through conducting wires.
  • Each CMOS transistor works as switch that behaves as a voltage controlled current source.
  • There are two types of CMOS transistors including a PMOS type transistor and an NMOS transistor.
  • the static energy/power used by an IC has become a significant portion of total power consumed by the IC.
  • the static power can be as much as almost half of the total power consumed by the IC.
  • dynamic power can be reduced by reducing the activity of nodes through development of efficient computation algorithms, static or leakage power is hard to reduce and/or get rid of since the static or leakage power (from the static or leakage current) is inherent to the design of the MOS devices themselves.
  • Figure 1 shows a general structure of a CMOS logic gate or CMOS logic function in existing CMOS Boolean technologies that includes a "pull up circuit” 101 and a “pull down circuit” 102 with each circuit made of MOS transistors connected together to perform part of the Boolean computation to provide the complete desired Boolean computation for the gate.
  • These pull up and pull down circuits are connected to "Supply 1" 105 and “Supply 2" 106, respectively.
  • Supply 1 and Supply 2 are the necessary voltage source and voltage sink nodes for currents to flow.
  • “Supplyl” 105 and “Supply2” also provide the voltage level references for logic” 1" or Logic “high” and logic “0” or logic “low” for the functional gate, its internal nodes, input ports (103) and output ports (104).
  • CMOS Boolean gates can be connected together to form a more complex function with many inputs and many outputs.
  • Many "inputs" of one or multiple loads can be connected to one output of a CMOS gate.
  • Connection between CMOS gates depends on overall required logic function of the integrated CMOS gates.
  • This general structure of a CMOS Boolean gate and CMOS Boolean function has been in existence and use for many decades in semiconductor designs. As described above, modern CMOS technology has an undesired component "the leakage current” that consumes power in any IC all the time unless special methods and structures are adopted to reduce or eliminate this current component.
  • microprocessors of a clock period. Combining the two statics - that a node transitions in less than 15 clock cycles out of 100 clock cycles (maximum of 15%) and that within the clock cycle that it does transition, the transition current itself flows for less than 10% time of that clock period), it can be concluded that, a node spends almost 98%-99% time waiting to do useful work (a transition activity) while it spends less than 2% time in actually doing useful work (making a transition).
  • a leakage current or static current 204 of the node is always present in all nodes. This is not a new phenomenon.
  • These statistics and electrical behavior (of transition current being there only for a small percentage of time duration while leakage current is always present for any given node) have always been present in all ICs using CMOS technology.
  • the leakage current though always present, has been a very small percentage of the transition current and of the total current until recently.
  • leakage current is a large percentage of transition and total current.
  • the need to reduce or eliminate leakage current is more critical with modern ICs than it was in the past.
  • dynamic or active power consumption of ICs is proportional to the number of transitions made by all nodes in that IC.
  • the chip consumes less dynamic or active power.
  • IC designers use the concept of clock gating, for the less active node in an IC, to force the "clock" to NOT transition. Unfortunately, the leakage or static current still flows through all nodes whether transitioning or not.
  • FIG 4 illustrates general structures of current technologies that are used in the industry for leakage reduction.
  • leakage current reduction is accomplished using a special signal called “Sleep” or “Standby” or something equivalent.
  • This signal may be used in conjunction with low leakage MOS devices (PMOS 122 and NMOS 123 in Figure 4) in series with the main pull up and pull down paths and in series with the main computation circuit 121 to reduce leakage when the whole functional block may be inactive or less functional and not doing its full useful function.
  • This specially configured sleep signal is generated using a specialized functional block(s) (a sleep monitoring block). The sleep signal represents a time period when a functional unit, many functional unit or the complete chip is guaranteed to be inactive or non-functional.
  • Sleep signals and associated MOS devices need to be generated and designed for each sub-block, block or multiple of BLOCKs that needs to be switched OFF, independently.
  • special architectural features are designed to recognize such opportunities and generate these "sleep" or "standby” signals.
  • a footer NMOS transistor 123 and a header PMOS transistor 122 is placed in series with the "Pull down circuit” and “Pull up circuit” respectively.
  • the gate terminals of these footer and header transistors are connected to special "sleep" or “standby” signals from sleep/standby pin(s) 126, 127.
  • the NMOS and PMOS devices 122, 123 used for the footer and header are special "Low Leakage" transistors available from all semiconductor foundries. Once an appropriate logic level is asserted on sleep signals
  • the footer and header devices 122, 123 used in series of main functional pull down and pull up paths and the main computation logic block 121 unfortunately slow down the main functionality of the large logic block 121.
  • leakage current and speed of operation are proportional to each other so that increasing the speed of the footer and header devices 122, 123 also increases the leakage current thereby mitigating the very effect these technologies are designed to create.
  • the speed of a circuit that uses the mechanism in Figure 4 tends to be substantially slower.
  • header and footer devices 122, 123 can only be used with large functional blocks and, in general, the larger the block size, the smaller the probability to find appropriate opportunity to assert the sleep mode on the block. This means that the header and footer devices 122, 123 can only be used with large functional blocks and, in general, the larger the block size, the smaller the probability to find appropriate opportunity to assert the sleep mode on the block. This means that the header and footer devices 122, 123 can only be used with large functional blocks and, in general, the larger the block size, the smaller the probability to find appropriate opportunity to assert the sleep mode on the block. This means that the
  • Figure 5 show that a functional unit or chip (IC) is in sleep mode (162) in between active mode (161) in time.
  • IC functional unit or chip
  • the opportunities to put a block in sleep mode are small which means small leakage current reductions.
  • This figure represents statistical behavior of functional blocks (that it is difficult to find opportunities to put a block in standby or sleep mode). This also makes sense from design philosophy point of view.
  • a functional-block in an IC is designed and implemented to do useful work, not to be idle.
  • FIG. 6 illustrates a device that uses sleep signals "SBB” and "SB” with a chain of inverters 141. These are sleep signal for this structure. These sleep signals cause virtual supply rails 146, 147, 149 and 150 to be disconnected from the static (and actual IC) supply rails 148 and 151. This disconnection causes virtual supplies and hence sources of inverters connected to the appropriate supplies to drift to a different voltage than the static supply rails 148 and 151.
  • Figure 1 illustrates the general structure of a CMOS logic gate or CMOS logic function using existing CMOS Boolean technologies
  • Figure 2 illustrates circuit behavior in an active mode and standby mode
  • Figure 3 illustrates circuit behavior in a given clock cycle
  • Figure 4 illustrates an existing technique for leakage reduction
  • Figure 5 shows that a functional unit or chip is in sleep mode in between active mode in time
  • Figure 6 illustrates an existing leakage reduction technique that uses sleep signals "SBB” and "SB” to a chain of inverters
  • Figure 7 illustrates a CMOS inverter
  • Figures 8A1-8C illustrate schematic and cross section, respectively, of a NMOS device, a PMOS and an INVERTER;
  • Figures 9A-D illustrate four different states of an NMOS device
  • Figure 10 illustrates a normal IC development (design and implementation) process
  • FIG. 11 A illustrates an inverter with functionality divided in multiple sub blocks
  • Figure 11B illustrates voltage swings at interfaces between standard Boolean gates
  • Figure 12 illustrates functional sub-blocks of an inverter (or any functional gate) using the reduced leakage current LOGIC (RLCL) technology
  • Figure 13 A illustrates a voltage translator functionality inserted in the path of signal propagation from one logic function to another logic function
  • Figure 13B illustrates Voltage translator circuit embedded in logic gates and voltage swing at interface between the logic blocks
  • Figure 14A is a general functional block diagram of each gate of a reduced leakage current device or a reduced leakage current logic gate
  • Figure 14B-D are 3 different embodiments of implementation of the reduced leakage current device of Figure 14A
  • Figure 15 illustrates an INVERTER with reduced leakage current
  • Figure 16 illustrates a NAND2 gate with reduced leakage current
  • Figure 16 illustrates another embodiment of inverter with the reduced leakage current
  • Figure 17 illustrates a detailed block diagram level implementation of the general circuit illustrated in Figure 14A;
  • Figure 18 is transistor level implementation of a NAND2 gate with reduced leakage current devices according to Figure 17;
  • Figure 19A illustrates another variation in block diagram level implementation of reduced leakage current
  • Figures 19B illustrate a transistor level implementation of an INVERTER circuit with reduced leakage current devices according to scheme in Figure 19 A;
  • Figures 19C illustrates a transistor level implementation of a NAND2 circuit with reduced leakage current devices according to Figure 19 A;
  • Figure 19D illustrates schematic of a LOW Leakage INVERTER used in Figures 19B- C;
  • Figure 20A illustrates a block diagram level implementation of another circuit scheme of the reduced leakage current device
  • Figure 20B illustrates block diagram level implementation of still another circuit scheme of the reduced leakage current device (a variation of Figure 20A);
  • Figure 21 illustrates a MOS transistor level implementation of a NAND2 functionality using the circuit in Figure 20;
  • Figure 22 illustrates another block diagram level implementation of the reduced leakage current device
  • Figure 23 illustrates a MOS transistor level implementation of an inverter function according to the circuit diagram shown in Figure 22;
  • Figure 24 illustrates an implementation of a NAND2 functionality using UN and UP devices
  • Figures 25A-D illustrates examples of implementations of the UN and UP devices, respectively, on semiconductor wafers in semiconductor foundry
  • Figure 26 illustrates the general structure of a standard CMOS memory
  • Figure 27 illustrates more detailed connectivity and functional structure of standard CMOS SRAM memory implementation
  • Figure 28 illustrates details of a single bit cell of the RAM with the details of Word Line driver in a standard SRAM implementation
  • Figure 29 illustrates the leakage current paths related to memory bit cell in typical SRAM designs
  • Figure 30A illustrates the general structure of a memory with reduced leakage current devices
  • Figure 30B illustrates an implementation of an SRAM in which the reduced leakage current inverter is used for the wordline driver. Details of a standard SRAM bit cell are also shown;
  • Figures 31 A and 3 IB illustrate two example of a dynamic functional logic block in standard CMOS technology
  • Figures 32A and 32B illustrate the circuit design of dynamic circuits using reduced leakage current circuits and RLCL technology
  • Figure 33 illustrates implementation of a reduced leakage current dynamic functional gate
  • Figures 34A and 34B illustrate an alternative implementation of a dynamic buffer that is a reduced leakage current dynamic functional gate.
  • Figure 35A-B are flow chart level description of method and functioning of reduced leakage current devices
  • the disclosure is particularly applicable to a CMOS device with leakage current reduction and method of manufacture and it is in this context that the disclosure will be described. It will be appreciated, however, that the leakage power reduction technique illustrated and described below has greater utility since it can be applied to other types of semiconductor devices and may be implemented in other ways that are within the scope of the disclosure.
  • the leakage current reduction and method of manufacture uses the concept of applying negative DETERMINISTIC gate voltage to MOS transistors to reduce leakage current.
  • CMOS gate level a new concept is introduced that is automatic, self monitored, and fully contained at the CMOS gate level. This means that each logic gate monitors and reduces its leakage current when not switching itself. Furthermore, no external control signal is required to monitor or control the leakage current of a logic gate or a logic block.
  • This library is similar to the standard cell CMOS cell library that is widely used in industry currently but provides a very important and needed feature of significantly reduced leakage power. Since all required apparatus and methods to deterministically apply negative gate voltage selectively to leaky MOS transistors are self contained within the logic cell gate, this technology is widely applicable and easily adoptable in all semiconductor ICs. This is a
  • the CMOS gate is divided into its separate native functions and the device incorporates new functional units to reduce leakage current. These functions have been separated in such a way that the Logic gate still appears almost identical to the classical CMOS logic gate to RTL, manufacturing rules and constraints and EDA tools. Only a very small modification is required to the implementation methodology to incorporate this technology. All features of a classical and prevalent CMOS logic gate are practically preserved at the boundary of the new CMOS Logic gate with reduced leakage current so that the reduced leakage current device is easily adoptable in all CMOS ICs.
  • CMOS gate Yet another concept introduced in this invention is related to the electrical and speed performance of CMOS gate. It should be recognized that in a CMOS IC, where Boolean gates are connected to each other, the transition of an output from LOGIC ZERO to LOGIC ONE or vice versa doesn't require an output signal (which is input to another CMOS Boolean gate) to fully transition from one Supply Rail to another Supply rail. Due to embedded characteristic of a CMOS gate, input of a gate is at LOGIC HIGH if it is slightly HIGHER than the "INPUT HIGH THRESHOLD" of that CMOS gate. Similarly the input is LOGIC LOW if it is slightly LOWER than the "INPUT LOW THRESHOLD" of that CMOS gate.
  • the MOS device that performs electrical charging and discharging function at high speed should also provide the LOGIC VOLTAGE LEVEL translation from INPUT TO OUTPUT.
  • the electrical charging/discharging (or voltage translation) functions are separated from LOGIC translation functions wherever these voltage translation functions wherever appropriate.
  • Figure 7 shows schematic of the most basic CMOS Boolean logic function - an inverter.
  • the inverter has a PMOS device 223 and a NMOS device 224 that are connected together.
  • the PMOS device or transistor (223) is connected, at its drain, to an NMOS device or transistor 224 and, at its source, to Supplyl (vdd) (221).
  • the NMOS device or transistor 224 is connected, at its drain, to the PMOS device 223 and at its source to Supply2 (vss) (222) as shown in Figure 7.
  • the gates of both the PMOS and NMOS devices 223, 224 are connected to an input node “In” (225) and the drains of the PMOS and NMOS devices are connected to an output node “Out” 226.
  • Nodes “In” (225) and “Out” (226) are the input and output, respectively, of the inverter.
  • Supply 2 works as a current sink and is typically at ZERO volts.
  • the flow of current from the output node to Vss causes the voltage at output node to be approximately equal to ZERO volts which is "LOGIC ZERO" or "LOGIC LOW".
  • the NMOS device is turned OFF and PMOS device is turned ON which causes current to flow from "Supply 1" or “Vdd” to output node “Out” (226) which charges the output node “Out” to voltage approximately equal to "Vdd” which is "LOGIC HIGH” or "LOGIC ONE".
  • inverter appears to be a very simple device with a very simple operation, many assumptions, electrical activities and functionalities of various nodes in the inverter (as in all Boolean CMOS gates) are hidden and are taken for granted by electrical designers.
  • the hidden behavior, activities, properties and functionalities of inverter (or of any CMOS logic gate) and its internal nodes are used and modified to reduce leakage in CMOS circuits. These hidden behaviors, activities, properties and functionalities are discussed in later sections.
  • Figures 8A1-C illustrates a schematic and cross sections of a NMOS device and a PMOS device and a cross section of an inverter, respectively.
  • the features exhibited by an inverter are exhibited by all CMOS Boolean gates.
  • CMOS Boolean gate structure When designing any alternatives to this classical CMOS Boolean gate structure, one needs to preserve these subtle and hidden features, behaviors and properties of the CMOS Boolean gates that provide substantial practical benefits in a real practical CMOS IC.
  • the reduced leakage current technology exploits the multi functional ability of the connectivity and presence of NMOS and PMOS devices in a CMOS structure to reduce leakage significantly.
  • Figure 8A1 illustrates a schematic of PMOS device that has a source/drain terminal 276, a P-substrate terminal 277, a drain/source terminal 278 and a gate terminal 279.
  • Figure 8A2 illustrates cross section of the PMOS device in which the PMOS device is fabricated on a N-substrate or an N-well.
  • the PMOS has two doped P+ diffusions 286, 289 that are implanted in a N-substrate or N-well 287. These two function as the source or drain ports 283, 284 of the PMOS device and these two are interchangeable in circuit usage.
  • a non conducting Silicon oxide 282 is formed aligned with the ends of source and drain implants as shown.
  • a conducting Poly Silicon gate 281 is deposited aligned with the non conducting oxide 282.
  • the source and drain nodes (289, 286) are metalized to provide conducting source/drain nodes 280, 283.
  • a highly doped N+ implant 1286 is formed in substrate 287 and the metallization is done on top of this implant to form a conducting substrate node 284.
  • Figure 8B 1 illustrates a schematic of an NMOS device that has four terminals - a source/drain 272, a P substrate 273, a drain/source 274 and a gate 275.
  • Figure 8B2 illustrates the cross section of a the NMOS device that is fabricated on a P substrate or an P+ well.
  • the NMOS device has 4 nodes.
  • Two heavily doped N+ diffusions (299, 296) are implanted in a lightly doped P-type substrate 297 (also called P-substrate). These two function as the source or drain ports of the NMOS device. These two are interchangeable in circuit usage and any of these two (299, 292) can function as source or drain ports.
  • a non conducting Silicon oxide 292 is formed aligned with the ends of source and drain implants as shown.
  • a conducting Poly Silicon gate 291 is deposited aligned with the non conducting oxide 292.
  • Source and drain nodes (299, 296) are metalized to provide conducting source/drain nodes 290, 293.
  • a highly doped P+ implant 1296 is formed in substrate 297 and the metallization is done on top of this implant to form a conducting substrate node 294.
  • a substrate node 256 of the NMOS device When used together in an inverter as shown in Figure 8C, a substrate node 256 of the NMOS device is connected to a supply node 255 with lowest voltage called VSS or GND (generally at ZERO Volts).
  • VSS or GND generally at ZERO Volts.
  • One of the source/drain nodes (260 or 262) of the NMOS device is also connected to the same supply node with the lowest voltage and this node becomes the source node of the NMOS, while the other node becomes drain node of the NMOS as shown in Figure 8C.
  • a substrate node 266 is connected to a supply node 250 with highest voltage called VDD or VCC (which has different voltage value in different technologies).
  • a source node 265 of the PMOS device is also typically connected to the same supply node VDD or VCC.
  • the drain nodes of NMOS 262 and PMOS 263 are connected together as shown in Figure 8C to form an output port 253 of the inverter.
  • the gate nodes 251, 254 of NMOS and PMOS are connected together to form an input port 252 of the inverter.
  • FIGS 9A-D illustrates four different states of an NMOS device.
  • the MOS conduction and leakage mechanisms can be understood from functioning of an NMOS device.
  • an NMOS device has its substrate and source node tied to 0 Volt (VSS or GND) which is the supply node with lowest voltage (323).
  • the NMOS device is now configured and capable to draw electrons from VSS to form a conducting channel due to this connection (323). If the voltage on a Gate node 322 is lower than a fixed voltage called Threshold voltage (Vt) compared to voltage at source (322) (that is Vss), the conducting channel is not formed underneath the gate (325) and the NMOS device is theoretically OFF.
  • Vt Threshold voltage
  • Gate node 322 is driven to a voltage greater than Vt (332) and the drain node is still at same voltage as the source (0V in this case) as shown in Figure 9B, electrons are drawn from substrate underneath the Gate due to Electric field through the gate oxide (336) and form an uniform conduction channel (335). Though this channel is formed and ready to conduct there is still no current between source and drain nodes because there is no voltage gradient between drain and source.
  • Figure 9C shows the next stage. To make the NMOS conduct, the voltage on drain node (341) is raised above the voltage on source node 343 as shown in Figure 9C. Now the NMOS transistor is ON and conducting current from drain to source terminals. As the voltage on drain terminal increases above source terminal, the current in NMOS transistors increases till it saturates. Once saturated the NMOS has reached its maximum current for a given gate-source voltage and the current can increase no more.
  • Figure 9D shows the OFF transistor from Figure 9A but in a practical condition (where
  • Gate voltage Vg is less than Vt and drain voltage is Vdd or other high voltage).
  • the gate voltage is lower than Vt (352) and the NMOS device should be OFF but a practical device exhibits non-ideal behavior.
  • mobile charges electrospray in this case
  • the drain voltage is greater than voltage on the source node, current flows between source and drain nodes causing leakage current.
  • the leakage current is larger at larger drain-source voltage. Similarly the leakage current is larger at higher temperature.
  • the operation of the PMOS device is similar to the NMOS device except that the channel formed in PMOS is that of positive mobile charges (called holes), the voltage on substrate and source is VDD and the gate voltage is negative as compared to source voltage for the PMOS to conduct.
  • leakage mechanism is similar in that thermal mobile charges form unwanted conduction channel and cause the PMOS transistor to leak current.
  • FIG 10 illustrates a normal IC development (design and implementation) process.
  • EDA Electronic Design Automation
  • Three independent user inputs are mixed and iterated by Electronic Design Automation (EDA) tools 388 to produce a physical database in graphical format that is converted by the manufacturing house ("semiconductor foundry” or "Foundry") into a physical IC that finally gets used in a system board to perform a specific electronic function.
  • Specific description of functionality and connectivity is generated by a system design engineering team based on system requirement 381 provided to IC design engineers.
  • the IC design engineers translate these requirements and connectivity into known Register Transfer Logic (RTL) (383) for the intended IC.
  • RTL is software like description of IC's functionality and connectivity, written in a Hardware Description Language (or HDL).
  • the RTL is mapped to a Physical IP Library (384) to produce an intermediate format called netlist that describes connectivity of basic functional blocks from Physical IP library (384) to form the complete designed functionality of the IC.
  • Physical Intellectual Property (IP) Library consists of basic functional blocks that can be connected together to form a hardware function. As mentioned, most ICs are CMOS based. Hence most Physical IP Library used in the industry is also CMOS based.
  • This physical database is then processed by software tools and (mostly robotics) machines of the foundry to produce the physical silicon integrated chips (IC) 390 that gets used in a system board (382).
  • IC integrated chips
  • RTL 383
  • Physical IP library 384
  • manufacturing rules and constraints 392
  • EDA tools and Implementation methodology 387
  • the RTL (383) depends on the requirement from the customer or the system. Though an RTL designer can request changes in functionality and connectivity from system
  • RTL is also generally a rigid and inflexible to a large extent for a given IC. Any major change in RTL is avoided in practice. It is important to know that generally an IC is owned by the company or team that owns RTL. Therefore, any quality improvements or reduction/elimination in shortcomings or limitations are therefore addressed in implementation methodology (387), Physical IP Library (384) and EDA tools (388). Among the three, use of Physical IP Library to eliminate issues or make improvements is preferred because of lower cost of making changes in a Physical library. Also because changes in Physical IP Library are contained within the library and very little or no effects are caused on any other part of the IC construction process.
  • the reduced leakage current device and method of manufacture is a circuit technology that can be implemented to form a Physical IP library. Furthermore, no effects are caused on RTL, EDA tools or manufacturing rules and constraints. In addition, very little (almost negligible) effect is caused on "Implementation methodology.”
  • the reduced leakage current device and method of manufacture also may be used with and is compatible with most leakage reduction technologies that are based on architectural or manufacturing features. It reduces leakage significantly even in ICs that already use one or other leakage reduction technologies. Because of these advantages, the reduced leakage current device and method of manufacture can be easily implemented in all CMOS ICs.
  • inverter of Figure 7 is very simple in construction and functionality at a high level, but it has many hidden features, functionalities, activities and properties. For purpose of this invention, these are revealed and analyzed below:
  • Vdd works as current source. All nodes inside the logic gate derive current from
  • Vdd Vdd.
  • Vss node works as a current sink. All current from the logic gate are sinked to Vss.
  • Vdd is a representation of "LOGIC HIGH” or “LOGIC ONE”” and Vss is a representation to "LOGIC ZERO” or "LOGIC LOW". This means any node that is approximately equal to Vdd in voltage is at "LOGIC 1" or "LOGIC HIGH” and any node that is approximately equal to Vss is at "LOGIC 0" or “LOGIC LOW". It must be noted that equality of Vss to "LOGIC 0" (or "0") and equality of Vdd to "LOGIC
  • Vdd and Vss are also the reference voltage for input (“In”) and output (“Out") nodes.
  • the input is driven to Vdd or Vss (or approximate voltage levels) and output transitions to the same voltages (approximately equal to Vdd and Vss).
  • This means output node of a Boolean gate can be connected to the input node of another Boolean gate with any conductor without any interface elements in between.
  • Pull up or Pull down circuit is ACTIVE thereby pulling the output to LOGIC ONE or LOGIC ZERO.
  • Active or transition current does not flow from Supply 1 (Vdd) to Supply 2 (Vss) except for the limited duration when the output of the gate transitions from one logic value to another. This means that the output of a Boolean gate always transitions to a voltage equal to Vdd or Vss in steady state (some error in this equality occurs due to leakage current or noise).
  • a PMOS device pulls positive charges from Supply 1 or Vdd to form a channel when it switches ON to conduct current. Similarly the NMOS device pulls negative charges from Supply 2 or Vss to form a channel when it switches ON.
  • the N-substrate or N-well where a PMOS device is located on a silicon wafer connects to the highest voltage which is generally Supply 1 or Vdd and the P-substrate or P-well where NMOS devices is located on the silicon wafer connects to the lowest voltage on the IC which is generally Supply 2 or Vss.
  • the source terminals of PMOS and NMOS devices are also connected to the same nodes Vdd and Vss in general in most CMOS ICs.
  • Inputs of a MOS gate are non-conducting. This means that no static current flows between the input of a "load” CMOS gate and output of a “driver” CMOS gate in steady state. Only stored mobile charges are pulled or provided by the "driver” gate to the "load” inputs. This means any number of "load” CMOS gate can be connected to output of a CMOS gate without loss of accuracy as long as enough time is available for making the transition of load inputs. In practice the number of loads is limited to achieve good speed of transition.
  • the CMOS INVERTER of Figure 7 can therefore be seen as a circuit block consisting of a group of functional blocks connected together as shown in Figure 11 A. These functional blocks are input receiver (5113), output driver (5114), logic computer (5111) and noise filter (5112). Power supplies "Supply 1" or “Vdd” 5115 and “Supply 2" or “Vss” 5116 provide the current source and sink functionalities along with being reference for compute, compare, noise and other necessary functions.
  • Figure 11 B shows voltage transition of signals connecting multiple Logic functions in standard CMOS process.
  • a set of output and inputs signals or wires 5121, 5123, 5124 transition between supply-rails "Vdd” and “Vss", the same supply rails that the logic function gates 5122, and 5128 are connected to.
  • Uniformity of supply rails for connecting transistors and reference for input and output signal swing provides ease and simplicity of operation and implementation. However, this uniformity becomes a limitation and causes high leakage in high speed MOS transistors in standard CMOS logic circuits.
  • Figure 12 illustrates general construction and functionalities of an inverter (or any other logic function gate) using leakage reduction technology of this invention.
  • New sub blocks have been added to the sub-blocks of Figure 11 A to accomplish reduction in leakage current.
  • the new functionality sub-blocks are "Voltage translator” 5082, "Current control decision circuit” 5086 and "Current Control circuit” 5085.
  • Other functional sub-blocks of Figure 11 A of standard CMOS INVERTER or any standard CMOS functional gate
  • FIG 11A perform all the necessary standard functions of CMOS gate described earlier, namely Logic computer (5081), Noise filter (5087), output Driver (5083) and Input receiver (5084).
  • Two new supply rails are added “Vddsp” and “Vsssp” making the number of supply rails to be 4 (as compared to 2 in a standard CMOS Boolean logic gate).
  • Supplyl (5090) and Supply2 (5091) are two “voltage high” supply rails (Vddsp and Vdd) and Supply3 (5092) and Supply4 (5093) are two “voltage low” supply rails (Vss and Vsssp).
  • the quad supply rails consisting of dual "Voltage High” and dual “Voltage Low” (5090, 5091 and 5092, 5093, respectively) are used to provide voltage references for generating DETERMINISTIC negative gate voltages to MOS devices and do other necessary functions required by the logic function gate.
  • CMOS circuits can be commercially viable only when its performance and behavior can be predicted deterministically in all conditions of environment, manufacturing, and material properties. Since voltage supply on different terminals of a MOS transistors affects behavior and performance significantly, mostly, a CMOS circuit technology is not of use commercially if deterministic voltages cannot be applied to all terminals of MOS transistors.
  • CMOS circuits constructed with this technology provide leakage reduction always, when not switching without help of external control signals.
  • the "Voltage translator” block 5082 in Figure 12 does voltage translation of input and/or output signals from one supply rail to another supply rail. For example, it can be implemented to apply Vddsp on gate of a PMOS transistor whose source is connected to Vdd supply rail when the PMOS is supposed to be OFF, thus causing negative gate-source voltage to PMOS transistor(s), assuming Vddsp was a higher voltage than Vdd.
  • this functional block can translate input signal or output signal from one supply rail to another. Furthermore it can translate an internal gate, source or drain signals from Vdd to Vddsp or vice versa or from Vss to Vsssp or vice versa.
  • This functionality is in addition to the functionality of a standard CMOS logic gate of computing output voltage to be LOGIC HIGH or LOGIC LOW as a function of combination of inputs and the logic function implementation.
  • the "Current Control Circuit” 5085 provides control of leakage current when the output is not switching in addition to control of current for switching the output depending on the inputs and logic functions.
  • “Current control decision circuit” 5086 monitors the behavior of the “Current Control Circuit” 5085 by monitoring how and when the "current control circuit” 5085 should be in operating condition for reduced leakage current, or operating condition for high switching current. It should be noted that such monitoring may have to be applied separately for all PMOS and NMOS transistors in the functional gate or they can all be driven by a single control or a combination of the two.
  • number of supply rails can be changed from 4 to 3. Any of the 4 supply rails can be eliminated depending on whether leakage reduction is to be realized in both PMOS and NMOS or both Pull up and Pull down or only in Pull up or Pull down (or only in PMOS or NMOS).
  • one, multiple or all functions of Figure 12 can be implemented by one, two or many MOS transistors. Also, one, multiple or all functions may be sub-divided in multiple blocks. Furthermore, two or multiple functional blocks can be merged together for purposes of implementations.
  • FIG 13 A illustrates the concept of voltage translation and use of voltage translation for leakage reduction as per this invention.
  • a "voltage translator” 5161 is inserted in the signal propagation path from one Logic function gate 5160 to another Logic function gate 5162.
  • This voltage translator block will translate the voltage on output signals 5156 driven by "standard logic function gate” 5160 from “Vdd” to "Vddsp ("Vdd+ ⁇ ") and from “Vss" to "Vsssp" ("Vss- ⁇ 2") in addition to allowing the transition between Vddsp and Vsssp.
  • Embodiment with "Voltage translator" as shown in FIGURE 13 A will achieve leakage reduction at cost of more delay in the signal propagation path. While this could be an acceptable solution to some applications, it may pose unacceptable restriction for some other applications.
  • the "Voltage Translator” blocks are merged with the "Logic function gate”.
  • “Logic function gates” have built in “Voltage translator” functionality. This would allow voltage translation function to be merged with Logic computer and other necessary logical and electrical functionality of a Boolean function gate and achieve high speed along with the leakage reduction.
  • Figure 13B shows signal flow between blocks that have CMOS Boolean gate functionality merged with Voltage translation functionality. As shown the output signals and input signals transition between Vddsp and Vsssp.
  • "Logic function gate with Voltage translation” 5170 and 5171 are connected to all supply rails Vdd, Vddsp, Vss and Vsssp.
  • these can be connected to any 3 supply rails if leakage reduction was desired only in PMOS or NMOS.
  • the input/output signals in such case will transition between Vddsp and Vss or between Vdd and Vsssp depending on presence of the supply rails and depending on the requirements.
  • Figure 13 A shows only a limited possible implementation of general scheme illustrated in Figure 12.
  • Figure 12 illustrates general construction and connectivity of a Logic function gate with reduced leakage technology of this invention.
  • each reduced leakage functional gate 5221 comprises of four main functional units: a "Logic computer, Noise filter, Input receiver & output driver unit” 5220, a “Voltage translator unit” 5217, a “Current control Circuit” 5218 and a “Current control decision Circuit” 5219.
  • Each functional gate may have one or more inputs 5215 and one or more outputs 5216 that may be connected to one or more or all of these units (5220, 5217, 5218, and 5219).
  • Vddsp Supplyl
  • Vdd Supply2
  • Vss Supply3
  • Vsssp Supply4
  • Vddsp Vdd + ⁇
  • Vdd the voltage on Supply2
  • ⁇ In currently available leading edge 28nm process technology ⁇ is expected to be in range of 50 MILI VOLT to 100 MILI VOLT and in future 20nm process technology ⁇ is expected to be lower voltage. Similarly, the voltage on Supply3 (Vss) 5213 is higher than voltage on Supply4 (Vsssp) by a value ⁇ 2 where ⁇ 2 is determined after careful analysis of leakage, speed and other design considerations by the implementation team at the time of IC implementation. Similar to ⁇ , ⁇ 2 can be in range of 30 MILI VOLT to 200 MILI VOLT (mv) (one MILI VOLT is equal to 1/1000 of one VOLT).
  • CMOS process technology ⁇ is expected to be in range of 200 MILI VOLT. In currently available leading edge 28nm process technology ⁇ is expected to be in range of 50 MILI VOLT to 100 MILI VOLT and in future 20nm process technology ⁇ is expected to be lower voltage.
  • ⁇ and ⁇ 2 may or may not be equal and there is no pre-determined limitation on values of ⁇ and ⁇ 2. This voltage relationship is true for all notations where 4 supply rails (Supply 1, Supply2, Supply3, Supply4, Vddsp, Vdd, Vss and Vsssp) are drawn or mentioned in this description or diagrams. This voltage relationship is also true for embodiments where only 3 supply rails may be implemented. Values of ⁇ and ⁇ 2 mentioned here are only representative. Their range or values may be different if the IC implementation team would want to implement.
  • a family of logic function gates implemented with the RLCL technology may be known as "Reduced Leakage CMOS Logic” or "RLCL" family of logic gates and a library of these gates may be known as RLCL library.
  • RLCL Reduced Leakage CMOS Logic
  • a library of these gates may be known as RLCL library.
  • the standard Cell library in RLCL logic family consists of many cells with many and various Boolean functionality and drive strength with added advantage of substantially reduced leakage current. The mechanism to reduce leakage is contained within each basic cell.
  • RLCL logic gates behave and perform mostly in the same way as a normal CMOS Boolean logic gates that are already in use in the industry.
  • Figure 14B, Figure 14C and Figure 14D show 3 different variations of implementation of reduced leakage current device of Figure 14A. All of these implementations require 4 or 3 supply rails as described above.
  • each of 4 functionality "Logic computer, Noise filter, input receiver and output drive”, “Voltage Translator”, “Current control circuit” and “current control decision circuit” are comprised of both High Speed and Low Leakage CMOS components.
  • each of three blocks "Logic computer, Noise filter, input receiver and output drive”, “Voltage Translator” and “Current control circuit” are divided in two separate sections connected to each other and also connected to "current control decision circuit” wherein all circuit blocks in “Circuit section 1" 25204 are comprised of "HIGH SPEED” CMOS components while all circuit blocks in “Circuit section 2" 25205 are comprised of LOW LEAKAGE CMOS components while “Current control decision circuit” 25206 are comprised of LOW LEAKAGE CMOS components.
  • the "Current control decision circuit" 25206 of Figure 14C is replaced by a "Current control decision circuit comprised of both HIGH SPEED and LOW LEAKAGE CMOS components". In yet another embodiment, not shown in Figures, the "Current control decision circuit” 25206 of Figure 14C is replaced by a "Current control decision circuit comprised of only HIGH SPEED and CMOS components".
  • FIG. 14D Yet another embodiment and variation of implementation of reduced leakage current device of Figure 14A is represented in Figure 14D where "Logic computer, Noise Filter, input receiver & Output driver”, 'Current control circuit”, “Voltage translator”, and '"Current control decision circuit” are merged together and are comprised of a mix and a combination of HIGH SPEED, LOW LEAKAGE and Uni Directional CMOS components.
  • HIGH SPEED CMOS transistors can be large CMOS transistors of any type or low Vt, standard Vt, intrinsic CMOS transistors.
  • a LOW LEAKAGE CMOS transistor can be a small transistor of any type or High Vt, High voltage (thick oxide) CMOS transistors.
  • Uni-directional CMOS transistors are special CMOS transistors as proposed in this invention.
  • a Unidirectional PMOS transistor "UP" conducts current only from first diffusion node to second but never conducts current from second diffusion node to first.
  • CMOS transistor "UN" also conducts current only from first diffusion node to second but never conducts current from second diffusion node to first. Except for this nature of uni-directional current flow "uni directional" CMOS transistors behave similar to standard CMOS transistors.
  • Figure 15 illustrates a reduced leakage current inverter 5240 that has MOS transistors. Transistor symbols are defined here that apply to all relevant symbols of MOS transistor relevant in this invention.
  • PMOS transistor Symbol with "HS” written under it means a HIGH SPEED PMOS Transistor (PMOS-HS)
  • NMOS transistor symbol with "HS” written under it means a HIGH SPEED NMOS Transistor (NMOS-HS)
  • PMOS transistor Symbol with "LL” written under it means a LOW LEAKAGE PMOS Transistor (PMOS-LL)
  • NMOS transistor symbol with LL written under it means a LOW LEAKAGE NMOS Transistor (NMOS-LL).
  • Any logic gate symbol with "HS” written in its body or under the symbol means the LOGIC gate consisting of HIGH SPEED MOS transistors.
  • Any logic gate symbol with "LL” written in its body or under the symbol means the LOGIC gate consisting of LOW LEAKAGE MOS transistors.
  • the PMOS-HS is a high speed (HS) PMOS transistor and NMOS-HS transistor is a high speed NMOS transistor.
  • the PMOS-LL transistor is a Low Leakage PMOS transistor and NMOS-LL transistor is Low Leakage NMOS transistor. All modern semiconductor manufacturing houses (Semiconductor foundries) have these transistors as standard product offerings. Their use for various purposes is a standard practice in modern IC implementations including in some of the typical circuits described earlier.
  • high Speed MOS PMOS or NMOS
  • the low leakage transistor can be High Threshold
  • High Vt High Voltage or Thick Oxide or Double Oxide transistor.
  • Many known and well established manufacturing technologies are used to create High Speed and Low Leakage MOS transistors by Semiconductor foundries. As a general rule, a Low Leakage MOS transistor is a slow speed MOS transistor and conversely a High Speed MOS transistor is a High Leakage MOS transistor. Regardless of the manufacturing technologies used in semiconductor this leakage and speed relationship is true. This relationship is driven by the very science (Physics) that govern all behavior of MOS transistors and is a well known and practiced in
  • inverter 5240 may have a PMOS-HS transistor (5241) and NMOS-HS transistor (5243) that are connected to each other (at their respective source and drains as shown) and to Supply2 (Vdd) line 5248 (the source of the PMOS transistor) and a Supply3 (Vss) line 5249 (the source of the NMOS transistor), respectively. These two MOS transistor are also connected to an input port 5245 and an output port 5246 of the inverter as shown in Figure 15. This connection is similar to a classical CMOS inverter prevalent in Industry.
  • the inverter of Figure 15 may also have a PMOS-LL transistor (5242) and NMOS- LL transistor (5244) that are connected to each other (at their respective source and drains as shown), to the input port 5245 and to the output port 5246 as shown. Additionally, the PMOS- LL transistor and NMOS-LL transistor are connected to a Supplyl (Vddsp) line 5247 and a Supply4 (Vsssp) line 5250, respectively.
  • Vddsp Supplyl
  • Vsssp Supply4
  • the PMOS-HS (5241) is a high speed (HS) PMOS transistor and NMOS-HS transistor
  • the PMOS-LL transistor (5242) is Low Leakage PMOS transistor and NMOS-LL transistor (5244) is Low Leakage NMOS transistor.
  • RLCL technology the advantages of Low Leakage and High Speed MOS transistors are combined together along with the circuit design technology of connectivity to mitigate or eliminate the shortcomings of speed and leakage.
  • the Input Port (5245) is driven to Logic High (to a voltage of Vddsp, and not to Vdd as will be clear from following paragraphs)
  • the High Speed NMOS transistor 5243 and Low Leakage NMOS transistor 5244 are turned ON.
  • the High Speed (but also high leakage) NMOS (5243) pulls down the output node 5246 with high speed assisted by Low Leakage but slow NMOS transistor (5244).
  • the High Leakage (High Speed) NMOS 5243 pulls the output node 5246 down only to a voltage at Supply3 (Vss), but the Low Leakage NMOS transistor 5244 pulls the output port 5246 down to Supply4 (Vsssp) which is at a voltage ⁇ 2 lower than Vss.
  • the High Speed PMOS transistor 5241 and Low Leakage PMOS transistor 5242 are turned ON.
  • the High Speed (but also High Leakage) PMOS (5241) pulls up the output node 5246 with high speed, assisted by Low Leakage (but slow) PMOS transistor 5244.
  • the High Speed (but also High Leakage) PMOS 5243 pulls the output node UP only to voltage at Supply2 (Vdd), while the Low Leakage PMOS transistor 5242 pulls the output port 5246 up to Supply 1 (Vddsp) which is at a voltage ⁇ higher than Vdd.
  • the output node thus swings from Vddsp to Vsssp and from Vsssp to Vddsp because of this special circuit arrangement.
  • the output of this functional gate is connected to inputs of other CMOS function gates so that the inputs of all logic function gates connected to the output of this INVERTER will therefore transition from Vddsp to Vsssp and from Vsssp to Vddsp. Since, the input of this inverter is also driven by output of a similar CMOS gate with this exactly same voltage transition behavior, the input of this INVERTER will transition from Vddsp to Vsssp and from Vsssp to Vddsp.
  • the input (5245) transitions between Vddsp and Vsssp.
  • the Input port (5245) is held at Vddsp or Vsssp.
  • the gate-source voltage of High speed (and hence high leakage) PMOS transistor 5241 is negative because the source of this transistor is connected to Vdd (Supply 2).
  • the negative gate-source voltage reduces the leakage current in this PMOS transistor significantly as per the leakage behavior explained earlier.
  • the Gate-source Voltage of Low Leakage PMOS transistor 5242 is ZERO as in prevalent standard CMOS logic function gate.
  • PMOS 5242 is a Low Leakage PMOS transistor by default and definition as provided by the semiconductor foundry, hence the leakage current in this transistor is very small by definition. Also, the PULL UP speed of this function gate is achieved by PULL UP current of PMOS 5241, therefore the size of LOW Leakage PMOS 5242 is small. Overall, because of small size and being a LOW LEAKAGE PMOS by definition, the leakage in PMOS 5242 is very small.
  • the gate-source voltage of High speed (and hence high leakage) NMOS transistor 5243 is negative because the source of this transistor is connected to a Vss (Supply 3) thus drastically reducing the leakage current in this NMOS transistor.
  • the Gate-source Voltage of Low Leakage NMOS transistor 5244 is ZERO as in prevalent standard CMOS logic function gate. But NMOS 5244 is a Low Leakage NMOS transistor by default and definition as provided by the semiconductor foundry, hence the leakage current in this transistor is very small.
  • the PULL DOWN speed of this function gate is achieved by PULL DOWN current in NMOS 5244, therefore the size of LOW Leakage NMOS 5244 is small. Overall, because of small size and being a LOW LEAKAGE NMOS by definition, the leakage in PMOS 5242 is very small.
  • Low Leakage PMOS 5242 and Low Leakage NMOS 5244 transistors are chosen by various standard design considerations such as leakage current, noise margin and speed etc..
  • the function of leakage reduction is caused by the voltage translation of the output port (5246) signal which is input to other logic function gates that results in negative voltage for the large and High Leakage (but high speed) MOS transistors (which are the main functional and speed provider for the logic function gate) thereby reducing leakage currents in these main transistors.
  • Low Leakage PMOS and NMOS transistors 5242 and 5244 provide assistance to the High Speed PMOS and NMOS transistors 5241 and 5243 respectively during output transitions. More importantly these LOW Leakage PMOS and NMOS transistors 5242 and 5244 pull the output node of the function gate to Vddsp and Vsssp respectively. Also these Low Leakage PMOS and NMOS transistors 5242 and 5244 do not hinder the logic and voltage operation of the logic functional gate in any way.
  • the circuit presented in Figure 15 has all 4 functions of Figure 14A (5217, 5218, 5219 and 5220) embedded in these 4 transistors (5241, 5242, 5243 and 5244).
  • the "Logic computer, Noise Filter, Input Receiver & Output Driver” (5220) function is performed by all PMOS and NMOS transistors combined.
  • the "Voltage translator” function is performed by Low Leakage PMOS transistor 5242 and Low Leakage NMOS transistor 5244 along with their special connectivity to power supplies Vddsp and Vsssp respectively.
  • the "Current control Circuit" 5218 function is performed by the special connectivity of High Speed PMOS and NMOS transistors 5241 and 5243 to Supply2 (Vdd) and Supply3 (Vss) respectively and by Low Leakage PMOS and NMOS transistors 5242 and 5244.
  • Vdd Supply2
  • Vss Supply3
  • Low Leakage PMOS and NMOS transistors 5242 and 5244 Low Leakage PMOS and NMOS transistors 5242 and 5244.
  • Vddsp or Vsssp Low Leakage PMOS and NMOS transistors 5242 and 5244 respectively.
  • the leakage current is controlled and significantly reduced in High Speed PMOS and NMOS transistors 5241 and 5343 due to negative gate-source voltage.
  • the leakage currents in "Low Leakage” PMOS and NMOS transistors 5242 and 5244 are small by definition. It must be noted that the input voltage swing differential from Vdd and Vss is achieved by the voltage translation function in the logic cell that drives the input of this Logic functions cell and has same or compatible voltage translation mechanism for its output port.
  • the "Current control decision Circuit” 5218 function is performed implicitly by the negative gate-source voltage biasing provided by the way power supply, inputs and outputs of logic cells are connected together.
  • Vddsp, Vdd, Vss and Vsssp are 4 separate power supply rails. These rails are generated for the whole IC or one or multiple blocks by one or multiple voltage regulator or other supply generator(s) that is either embedded in the same IC chip or is externally located. Generator ICs of such multiple supply rails are available as standard products in semiconductor industry. Multiple power supplies generated internally or externally in any IC is standard practice in semiconductor design and usage industry. Many supply generator ICs are available as standard products that can fulfill the requirements. Intellectual Property (IP) blocks with this functionality are available to be embedded inside an IC that can provide such power rails with or without minor modifications.
  • IP Intellectual Property
  • This embodiment is therefore buildable, but requires important chance in MOS transistor behavior through change in semiconductor process technology to function.
  • This new (to be designed) MOS transistor would need to conduct current only in one direction (from drain to source for NMOS and source to drain for PMOS) and block current in other direction, in order for the INVERTER of Figure 15 to function with substantially reduced Leakage Current but without short circuit current.
  • Multiple viable process technologies may be used to design and manufacture such MOS transistors. But Development of such MOS transistor technology may take time and effort by the semiconductor industry before it can be commercially available readily. Viable process change to implement such special functionality transistors is detailed in later sections ( Figures 22-25).
  • this invention uses alternative methods and design to overcome the current shortcomings of the circuit presented in Figure 15, so that RLCL technology can be used with currently available MOS transistors in presently functioning semiconductor fabrication foundries. These methods have been explained in following sections.
  • FIG 16 illustrates alternative MOS transistor level implementation of the reduced leakage current inverter.
  • Supplyl Vddsp
  • Supply2 Vdd
  • Supply3 Vss
  • Supply4 Vsssp
  • Vddsp Supplyl
  • Vddd Supply2
  • Vddd Supply3
  • Vsssp Supply4
  • Vsssp Supply4
  • the main inverter function is performed by High Speed PMOS 5271 and High Speed NMOS 5272.
  • an input port 5270 is driven by another RLCL circuit gate or compatible circuit component and transitions between Vddsp and Vsssp.
  • Port "out" 5280 is the output of this RLCL inverter.
  • the RLCL inverter gate further consists of a CMOS inverter 5291 that further consists of Low
  • the RLCL inverter further consists of a second CMOS inverter 5292 that further consists of Low Leakage PMOS 5278 and Low Leakage NMOS 5279.
  • the input of Inverter 5291 is connected to the output port 5280 and its output 5281 is connected to the input of Inverter 5292 and to the gate of Low Leakage PMOS transistor 5273 and to the gate of Low Leakage NMOS transistor 5275.
  • the output 5282 of Inverter 5292 is connected to the gates of High Speed PMOS 5274 and High speed NMOS 5276.
  • the inverters 5291 and 5292 provide the functionality of "current control decision circuits" of Figure 14A.
  • the source node of High Speed PMOS 5274 is connected to Supply2 (Vdd), and source node of Low Leakage PMOS 5273 is connected to Supplyl (Vddsp).
  • the drain nodes of both of these PMOS transistors 5273 and 5274 are connected together and also to the source node of High Speed PMOS 5271.
  • the sources of High speed NMOS 5276 and Low Leakage NMOS 5275 are connected to Supply3 (Vss) and Supply4 (Vsssp) respectively.
  • the drain nodes of the two NMOS transistors 5275 and 5276 are connected together and also to the source node of High Speed NMOS transistor 5272.
  • the drain nodes of High speed PMOS transistor 5271 and High Speed NMOS transistor 5272 are connected together and also to the output port 5280.
  • the output port 5280 is the output of this
  • the new RLCL INVERTER looks much larger and elaborate in size, the actual implementation is very comparable to the INVERTER in Figure 15 because the sizes of all Low Leakage MOS transistors are very small. In an actual layout implementation, these small transistors are located in auxiliary cell areas that would otherwise have been wasted in a normal CMOS INVERTER implementation. Therefore the layout areas of RLCL function gates in RLCL library are comparable to the layout areas of equivalent NORMAL CMOS gate in a NORMAL CMOS library. After implementation the overall size of CMOS IC is NOT impacted significantly even with this transistor level complexity of an RLCL function gate.
  • the INVERTER of Figure 16 represents the most basic but complete, fully functional and self sufficient cell of the RLCL technology, RLCL circuit and RLCL library.
  • CMOS functional gate As in case of a NORMAL CMOS functional gate, only supply ports, input ports and output port(s) are visible and used by tools for chip implementation. Complex connectivity within the function gate is neither visible not used during chip (IC) implementation in RLCL technology as well as standard CMOS technology. This means RLCL logic gates are comparable to standard CMOS in ease of use in an IC.
  • Input port 5270 transitions from Vddsp to Vsssp and from Vsssp to Vddsp and is driven by another RLCL circuit or RLCL compatible circuit component. This is exactly same as described for the inverter in Figure 15.
  • a LOGIC LOW (Vsssp) at node 5282 causes High Speed NMOS 5276 to be OFF with its gate node driven to Vsssp.
  • Low Leakage PMOS transistor 5273 is OFF since its gate node is driven by node 5281 (which is at voltage Vddsp).
  • the High Speed PMOS transistor 5274 is ON since its gate node is driven by node 5282 (which is at Vsssp). This causes the voltage on node 5294 to be Vdd (not Vddsp) which is also the source node for High Speed PMOS transistor 5271. Since the INPUT port is LOGIC HIGH at voltage Vddsp, the PMOS transistor 5271 has its gate node at higher voltage than the source voltage.
  • the RLCL inverter of Figure 16 has its pull down path deterministically driven to be Vsssp and significantly small leakage current in PULL UP path.
  • High Speed NMOS 5276 has ZERO gate-source voltage and not a negative gate-source voltage. Therefore, potentially it may have leakage current (since it is a high leakage MOS transistor). But the High Speed NMOS 5276 doesn't have high leakage current. Since the source node of High Speed NMOS 5276 is at voltage Vsssp and the drain node is at voltage Vss, the voltage differential between drain and source terminals is only ⁇ 2.
  • this differential voltage ( ⁇ 2) is an order of magnitude smaller than the normal voltage on Vdd
  • the drain source voltage of this High Speed OFF NMOS (5276) is an order of magnitude lower than the OFF MOS transistor in a normal CMOS logic circuit.
  • the Leakage current of this OFF NMOS 5276 is substantially smaller than an OFF NMOS of a normal CMOS function gate.
  • RLCL inverter of Figure 16 has substantially reduced leakage current as compared to a NORMAL CMOS circuit in this steady state. Also it has substantially small short circuit current unlike the RLCL inverter of Figure 15.
  • All other OFF MOS transistors are LOW LEAKAGE and small MOS transistors in size and hence they have substantially low leakage currents by definition.
  • a LOGIC HIGH (Vddsp) at node 5282 causes High Speed PMOS 5274 to be OFF with its gate node driven to Vddsp.
  • Low Leakage NMOS transistor 5275 is OFF since its gate node is driven by node 5281 (which is at voltage Vsssp).
  • the High Speed NMOS transistor 5276 is ON since its gate node is driven by node 5282 (which is at Vddsp). This causes the voltage on node 5293 to be Vss (not Vsssp) which is also the source node for High Speed NMOS transistor 5272.
  • the NMOS transistor 5272 Since the INPUT port is LOGIC LOW at voltage Vsssp, the NMOS transistor 5272 has its gate node at lower voltage than the source voltage (which is Vss). This is a negative gate-source voltage for High Speed NMOS 5272, which not only causes the pull down path from output port 5280 to be cut off from supply lines Vsssp and Vss but also significantly reduces the leakage in High Speed NMOS 5272. In this way the RLCL inverter of Figure 16 has its pull up path deterministically driven to be Vddsp and significantly small leakage current in PULL DOWN path.
  • the High Speed PMOS 5274 doesn't have high leakage current. Since the source node of High Speed PMOS 5274 is at voltage Vddsp and the drain node is at voltage Vdd, the voltage differential between drain and source terminals is only ⁇ . In practice this differential voltage ( ⁇ ) is almost an order of magnitude smaller than the normal voltage differential of Vdd. Thus the drain source voltage of this High Speed OFF PMOS (5274) is an order of magnitude smaller than the OFF MOS transistor in a normal CMOS logic circuit.
  • the Leakage current of this OFF PMOS 5274 is substantially smaller than an OFF NMOS of a normal CMOS function gate.
  • RLCL inverter of Figure 16 has substantially smaller leakage current as compared to a normal CMOS circuit in this steady state. Also it has substantially smaller short circuit current unlike the RLCL inverter of Figure 15. All other OFF MOS transistors are LOW LEAKAGE and small MOS transistors and hence they have substantially low leakage currents by definition.
  • Input port 5270 When Input port 5270 is at LOGIC LOW (at voltage Vsssp), the output port 5280 is charged to Vddsp through ON PMOS transistors 5273 and 5271.
  • the High Speed NMOS transistor 5276 is ON.
  • Node 5293 is discharged to Vss.
  • the HIGH Speed NMOS transistor 5272 is OFF. In this state this inverter is ready for a transition in the output whenever input changes. This steady state can be present for long time but the inverter has substantially reduced leakage current in this steady state as explained earlier. It must be noticed that again that node 5293 is at Vss in this state.
  • High Speed NMOS transistor 5272 turns ON (from OFF) and High speed PMOS transistor (5271) turns OFF (from ON). Since node 5293 was already discharged to Vss, the output port 5280 starts discharging to Vss by PULL DOWN current through High Speed NMOS transistors 5272 and 5276 as soon as input transitions HIGH. High Speed PMOS 5271 turns OFF as High Speed NMOS 5272 turns ON. OFF PMOS transistor 5271 cuts OFF the pull up current path of output port. The output port discharge continues through High Speed NMOS transistors 5272 and 5276.
  • High Speed NMOS transistor 5276 turns OFF the output port has already made transition to LOGIC LOW. This behavior is guaranteed because the event of switching OFF of High Speed NMOS 5276 starts only after the output port 5280 has already transitioned to LOGIC LOW. Also there is ample time difference between the events of output port 5280 making transition to LOGIC LOW and High Speed NMOS transistor 5276 switching OFF. In effect, the speed of transition to LOGIC LOW at output port of this gate is caused by PULL DOWN current through high Speed NMOS transistors 5272 and 5276.
  • High Speed NMOS transistor 5276 After High Speed NMOS transistor 5276 is turned OFF, the discharge current through Low Leakage NMOS transistor 5275 and High Speed NMOS transistor 5272 discharges output port 5280 to lower voltage Vsssp and keeps it there in steady state till the input(s) change again to cause the output transition in opposite direction.
  • Input port 5270 When Input port 5270 is at LOGIC HIGH (at voltage Vddsp) in steady state, the output port is discharged to Vsssp through ON NMOS transistors 5272 and 5275.
  • the High Speed PMOS transistor 5274 is ON charging the node 5294 to Vdd.
  • High Speed PMOS transistor 5271 turns ON (from OFF) and High speed NMOS transistor (5272) turns OFF (from ON). Since node 5294 was already charged to Vdd, the output port 5280 starts charging to Vdd by PULL UP current through High Speed PMOS transistors 5271 and 5274 as soon as input transitions LOW. High Speed NMOS 5272 turns
  • Vddsp This Logic transition at node 5281 causes the logic transition on the output of inverter 5292 from LOGIC LOW to LOGIC HIGH, pulling the node 5282 up to Vddsp.
  • LOGIC HIGH (Vddsp) at node 5282 turns OFF PMOS 5274 thus eliminating the short between Vdd and Vddsp.
  • High Speed PMOS transistor 5274 turns OFF the output port has already made transition to LOGIC HIGH. This behavior is guaranteed because the event of switching OFF of High Speed PMOS 5274 starts only after the output port 5280 has already crossed the threshold of the transition to LOGIC HIGH. Again, there is ample time difference between the events of output port 5280 making transition to LOGIC HIGH and High Speed PMOS transistor 5274 switching OFF.
  • An RLCL logic gate thus uses high speed MOS transistors to achieve high speed performance, low leakage MOS transistors to maintain voltage at the output port, voltage translation of the output port through its connectivity and design, low leakage MOS transistors to recognize transition behavior and provide necessary control signals to various portions of design that help logic transition and leakage reduction and deterministic voltage supply rails along with active circuit design methods and connections to achieve leakage reduction through negative gate-source voltage and substantially reduced source drain voltage in transistors that have tendency of high leakage current in a standard CMOS design. Additionally all these features and functionalities are contained within a basic cell in this technology. These basic individual cells are fully compatible with each other with the same simplicity and ease as that of a normal CMOS circuit cells (or logic gates) currently used in semiconductor industry.
  • a designer has the freedom to adjust voltage differences between Vdd and Vddsp and Vss and Vsssp ( ⁇ and ⁇ 2), choice of MOS transistor for Low Leakage and High Speed MOS devices to adjust and achieve desired speed, leakage, area and power of the IC. These choices are similar to the choices that an engineer needs to make in using a non-RLCL (or normal CMOS) circuit gates.
  • ⁇ and ⁇ 2 can be in range of 20 mili Volts (mV) to 200 mili Volt (mv) or little more depending on the fabrication process node chosen for the IC being implemented.
  • High Speed NMOS and PMOS transistor sizes will be chosen according to the required drive strength and speed as is commonly done in a normal CMOS circuit design.
  • Sizes of Low Leakage MOS transistors are expected to be minimum allowed by the process geometry or slightly higher to eliminate any coupling noise issues. However, for various leakage and speed tradeoff the ratio of sizes of different transistors can be varied, using normal engineering expertise, common in semiconductor industry.
  • RLCL circuits that use output port to generate various control signals can be divided in standard sub-blocks or sections of functionality as shown in Figure 16.
  • Basic construction blocks as shown in Figure 14A can be recognized in the transistor level implementation of the INVERTER of Figure 16.
  • blocks 5295 and block 5296 and components inside these blocks together correspond to "Current Control Circuit” 5218 of Figure 14 A.
  • block 5298 from Figure 16 and components within this block correspond to "Current control decision circuit” (5219) of Figure 14A.
  • Figure 17 illustrates a block diagram level implementation of the circuit in Figure 14A and general construction of one embodiment of RLCL function gates.
  • the "current control decision circuit” 5415 is connected to the output port 5241 of the logic function gate.
  • Any basic functional gates in RLCL technology (or RLCL circuit blocks) have one output port and one or many Input ports as shown in Figure 17.
  • Any functional gate with more than one output ports are constructed by combining two or more basic logic gates. This same property exists in a standard and normal CMOS circuit gates currently used in industry.
  • Figure 17 represents a general and expanded block level construction of a logic gate using RLCL technology where "current control decision circuit" uses output port of the functional gate for its recognition, monitoring and control functionalities.
  • RLCL circuits are ones that do not use output port to generate control signals for monitoring and controlling switching and leakage behavior of the circuit. These are discussed later.
  • "Pull up logic computation circuit” 5412 is connected to “Pull up current control Circuit” 5411, output port 5421 and “Pull down logic computation Circuit” 5413.
  • "Pull down logic computation circuit” 5413 is connected to input(s) 5420, “Pull Down current control Circuit” 5414, output port 5421 and “Pull up logic computation Circuit” 5412.
  • the "Pull up current control circuit” 5411 is connected to Supply rails "Supplyl” (Vddsp) 5416 and Supply2 (Vdd) 5417 and to the "Current control decision circuit” 5415 and "Pull up logic computation circuit” 5412.
  • “Pull down current control circuit” 5414 is connected to Supply rails “Supply3" (Vss) 5418 and Supply4 (Vsssp) 5419 and to the "Current control decision circuit” 5415 and "Pull down logic computation circuit” 5413.
  • the "Current Control Decision Circuit” 5415 is connected to "Pull up current control circuit” 5411, “Pull Down current control circuit” 5414, output port 5421 and power supply rails Supplyl 5416, Supply2 5417, Supply3 5418 and Supply4 5419. Any of the functional blocks 5411, 5412, 5413, 5414 and 5415 may be connected to all Supply rails Supplyl 5416, Supply2 5417, Supply3 5418, Supply4 5419 or any one or multiple of them.
  • Figure 17 represents a block level construction of any RLCL logic function gate.
  • Figure 16 is transistor level implementation of the simplest RLCL logic function gate- an INVERTER according to the circuit scheme presented in more abstract form in Figure 17.
  • "Pull up logic computation circuit” 5412 of Figure 17 is represented by a single PMOS transistor 5271 in Figure 16.
  • the "Pull down logic computation circuit” 5413 of Figure 17 is represented by a single NMOS transistor 5272 in Figure 16.
  • “Pull Down current control circuit” 5414 in Figure 17 is represented by block 5295 in Figure 16.
  • the "Pull up current control circuit” 5411 of Figure 17 is represented by block 5296 in Figure 16.
  • Current control decision circuit” 5415 of Figure 17 is represented by block 5298 in Figure 16.
  • Figure 18 shows transistor level implementation of a NAND2 function gate with RLCL technology using the general scheme shown in Figure 17.
  • NAND2 is a 2 input NAND function defined in a NORMAL BOOLEAN Logic Function such that its it has two LOGIC INPUTS and its output is at LOGIC LOW only when both inputs are at LOGIC HIGH. Otherwise output is at LOGIC HIGH in all other conditions and combination of INPUT states.
  • "Pull up current control circuit" 5501, "Pull down current control circuit” 5504 and “current control decision circuit” 5505 in Figure 18 are same as in RLCL INVERTER of Figure 16.
  • the "Pull up logic computation circuit" 5502 and “Pull down logic computation circuit” 5503 are different from the RLCL INVERTER shown in Figure 16, because of change in functionality.
  • high speed logic transition on output 5510 of the NAND2 in figure 18 is facilitated by current through High Speed MOS transistors and output is held at steady state at Vddsp or Vsssp by Low Leakage MOS transistors.
  • the NAND2 is a 2 input Boolean NAND function where NAND is "NOT OF AND" defined by a Boolean binary function such that the output is at LOGIC LOW only when both INPUT ports are at LOGIC HIGH.
  • NAND is "NOT OF AND” defined by a Boolean binary function such that the output is at LOGIC LOW only when both INPUT ports are at LOGIC HIGH.
  • INPUT_2 (In_2) both at LOGIC LOW) the output is at LOGIC HIGH.
  • node 5510 is input to the Low Leakage inverter 5551 consisting of Low Leakage PMOS and NMOS transistors 5529 and 5530, its out output node 5541 is LOGIC HIGH at Vddsp.
  • Node 5541 is also the input for Low Leakage inverter 5552 consisting of Low Leakage PMOS and NMOS transistors 5531 and 5532 respectively, the output of this inverter node 5542 is LOGIC LOW at Vsssp.
  • node 5541 drives the gate nodes of Low Leakage PMOS 5521 and Low Leakage NMOS 5527.
  • Node 5542 drives gate nodes of High Speed PMOS 5522 and High Speed NMOS 5528.
  • High Speed PMOS transistor 5522 is ON and Low Leakage PMOS transistor 5521 is OFF. Because of this, the middle node 5561 is charged to Vdd (not Vddsp). Node 5561 is also the source node for High speed PMOS transistors 5523 and 5524.
  • the gate nodes of High Speed PMOS transistors 5524 and 5523 are at Vddsp since they are connected to input ports In_l and In_2. Thus these two high speed PMOS transistors 5524 and 5523 have negative gate source voltage which means they have substantially reduced leakage current when they are OFF in this steady state.
  • ON High Speed PMOS transistor 5522 in this state also means that this gate is ready for an output transition to LOGIC HIGH quickly whenever appropriate input transitions occur.
  • the Pull down path from output to Vss/Vsssp is cut OFF because one or both of the NMOS transistors 5525 and 5526 are OFF.
  • high speed NMOS 5528 is ON and Low Leakage NMOS 5527 is OFF.
  • the internal node 5562 that is also the source node for High Speed NMOS 5526 is at Voltage Vss (not Vsssp).
  • This means one or both of High Speed NMOS transistors 5525 and 5526 have negative gate -source voltage because the gate node is driven by input ports to Vsssp.
  • the PULL DOWN path in this state has significantly reduced leakage current.
  • the short circuit current between Low Leakage PMOS transistor 5521 and High Speed PMOS transistor 5522 is very small because the OFF High Speed PMOS transistor 5522 has ZERO gate-source voltage but only a very small ⁇ source-drain voltage across the High Speed PMOS 5522.
  • the Pull down current Path starts turning OFF because High Speed NMOS transistors 5525 and/or 5526 start turning OFF.
  • output node 5541 transitions to LOGIC LOW and output node 5542 of inverter 5552 transitions to logic HIGH. Transitions of these two nodes cause Low Leakage PMOS 5521 to turn ON and High Speed PMOS 5522 to turn OFF. This pulls the output port 5510 and middle node 5561 to Vddsp.
  • the High Speed PMOS transistor 5522 turns OFF but only after the LOGIC transition of output node 5510 is completed because only after the LOGIC transition of output port 5510, nodes 5541 and 5542 make the LOGIC transitions.
  • the output node 5510 transitions from LOGIC LOW to LOGIC HIGH through High Speed PMOS transistors path 5522 and 5523 and/or 5524 but in steady state is held at LOGIC HIGH at voltage Vddsp by the Low Leakage Pull UP path consisting of Low Leakage transistor 5521 in series with High Speed PMOS transistors 5523 and 5524.
  • High Speed PMOS transistors cause high speed transition to the output port when appropriate.
  • Input and output ports behave in the same way as a normal CMOS NAND2 gate Achieves fast transition by use of High Speed CMOS transistors. This is a desired requirement of modern ICs in the industry
  • the circuits shown in Figure 16 and Figure 18 are two basic examples of RLCL logic function gates. They represent construction and functioning of all basic cells that can constitute the library of RLCL logic function gates. By replacing the High Speed PMOS and NMOS devices in "Pull up logic computation Circuit” and “Pull Down logic computation Circuit” in both Figure 16 and Figure 18, any Boolean Function equivalent to a normal CMOS Logic gate, can be constructed. More complex Logic function cells with more than one output in RLCL library are constructed by combining multiple basic logic gates, which is same as in normal CMOS logic Cell library. All cells in RLCL logic library operate with High Speed at transition time and with substantially reduced leakage current in steady state. In another words, RLCL circuit cells have significantly reduced leakage current without significant loss in speed. These two features together make this technology a compelling offering for implementation in modern ICs.
  • Figure 19A shows another embodiment of implementation of the general circuit scheme of Figure 14 A.
  • Figure 19A is a variation in circuit level implementation from one shown in Figure 17.
  • Figure 14A various sub-blocks of circuit functionalities represented in Figure 14A can be merged together or divided into two or multiple subsections.
  • Figure 19A shows a variant embodiment where the functional sub blocks of Figure 14A are divided into multiple subsections.
  • FIG. 19 A various blocks of Figure 14A (general construction of RLCL functional gate) has been sub-divided and merged.
  • the voltage translation circuits have been merged with other functions in block 15431 and 15432.
  • Current control decision circuit 15415 is connected to Pull up current control circuit 1, 15411 and Pull down current control circuit 1, 15414 in this embodiment.
  • Four supply rails 15416, 15417, 15418 and 15419 are used in this embodiment as in other embodiments of RLC circuits. Again one or two supply rails can be omitted depending on requirements of an application. For example, while using in address decoder of SRAM, Supplyl or Supply 2 may be omitted. Other connections of various sub- blocks of this embodiment are as shown in Figure 19
  • Figures 19B and 19C illustrate transistor level implementations of an RLCL
  • FIG 19B shows transistor level implementation of RLCL inverter as per this embodiment (as shown in Figure 19A).
  • Pull up current control circuit is divided in two parts.
  • the first part 15601 is the high speed Pull up Current Control Circuit that consists of a single High Speed PMOS transistor 15621. Its gate is connected to the output of "Current control
  • the first part 15602 is the High Speed Logic computation circuit that consists of a single High Speed PMOS transistor 15624 whose gate is connected to the input port "In" 15608, source node is connected to the drain of High Speed PMOS 15621 and the drain node is connected to the output port "Out" 15609.
  • the second part of Pull up logic computation circuit is merged with other functionalities in block 15606 that is implemented with a single Low Leakage PMOS transistor 15631 as already described in this paragraph.
  • "Pull Down Logic Computation Circuit” is also split in two parts, the first part 15603 is High Speed Pull Down Logic computation circuit implemented by a single High
  • Speed NMOS transistor 15625 whose drain node is connected to the output port "Out” 15609, gate node is connected to the Input port “in” 15608 and the source node is connected to the drain node of High Speed NMOS transistor 15627.
  • Second part of the "Pull down Logic Computation Circuit” is the Low Leakage Pull Down Logic Computation Circuit that is merged with other functionalities in block 15607 that consists of a single Low Leakage NMOS transistor 15632.
  • the drain node of this NMOS transistor 15632 is connected to the output port "out” 15609, source node is connected to Supply4 (Vsssp) and gate node is connected to the input port "In” 15608.
  • “Pull Down Current Control Circuit” is also split in two parts - a high speed Pull Down Current control Circuit 15604 and a Low leakage Pull down Current Control Circuit 15607 that is also merged with other functionalities.
  • the High Speed Pull Down current control circuit 15604 consists of a single High Speed NMOS transistor 15627 whose gate is connected to output of 'Current control decision circuit" 15605, node 15639.
  • the second part of "Pull down Current Control Circuit” is the Low Leakage Pull down Current control Circuit” 15607 whose functionality is merged with other functionalities of the gate. Its connectivity has already been described earlier in this same paragraph.
  • Current Control decision circuit 15605 consists of two Low Leakage CMOS inverters 15628 and 15629.
  • Both of these INVERTERS are simple CMOS inverters consisting of Low Leakage PMOS and Low Leakage NMOS transistors as shown in Figure 19D.
  • Input of this block 15605 is the input to first Low Leakage INVERTER 15628 connected to the output Port "out" 15609.
  • Output 15639 of this block is connected to the gates of High Speed PMOS and NMOS transistors 15621 and 15627.
  • the input port "In” 15608 is driven by another RLCL functional gate or a compatible circuit and transitions from Vddsp to Vsssp and from Vsssp to Vddsp.
  • the Input "In” is LOGIC HIGH at Vddsp
  • Low Leakage NMOS transistor 15632 is ON and the output port of the inverter 15609 is discharged to Vsssp (LOGIC LOW) through this Low Leakage NMOS transistor 15632.
  • Low Leakage PMOS 15631 is OFF with ZERO gate-source voltage and Low Leakage NMOS 15632 is ON discharging and holding the output port "out" 15609 to LOGIC LOW at Vsssp.
  • Leakage in Low Leakage PMOS transistor is significantly small by definition.
  • Leakage in high Speed PMOS 15624 is significantly small because of negative gate- source voltage which, as explained earlier, reduces the leakage of a High Speed MOS transistor significantly.
  • the leakage in High Speed NMOS transistor 15627 is significantly smaller because of very small source drain voltage ( ⁇ 2), as in case of other embodiments of Figure 16 and Figure 18.
  • High Speed PULL UP path from output port 15609 to Supply2 (Vdd) through High Speed PMOS transistors 15624 and 15621 is also OFF because of OFF PMOS 15621 with ZERO gate-source voltage and ⁇ as its source- drain voltage.
  • Low Leakage NMOS 15632 is OFF with ZERO gate-source voltage and Low Leakage PMOS 15631 is ON charging and holding the output port "out" 15609 to LOGIC HIGH at Vddsp.
  • Leakage current in Low Leakage NMOS transistor 15632 is significantly small by definition.
  • Leakage in high Speed NMOS 15625 is significantly small because of negative gate-source voltage.
  • Negative gate source voltage reduces the leakage of a High Speed MOS transistor significantly.
  • the leakage in High Speed PMOS transistor 15621 is significantly small because of very small source drain voltage ( ⁇ ), as in case of other embodiments of Figure 16 and Figure 18.
  • the RLCL inverter designed with the scheme as presented in Figure 19 A has significantly small leakage current in steady state.
  • Figure 19C shows transistor level implementation of another (more complex) RLCL functional gate, NAND2, according to the scheme presented in Figure 19 A.
  • NAND2 function gate provides the functionality of a Boolean 2 input NAND gate.
  • NAND2 Boolean function is defined such that it has 2 inputs and one output. The output is at LOGIC LOW only when both inputs of this Boolean logic gate are at LOGIC HIGH. In all other combinations of INPUTS, the output is LOGIC HIGH.
  • the "Pull up logic computation circuit” is divided in two circuit blocks 5602 and 5606 each consisting of High Speed and Low Leakage PMOS transistors respectively. Circuit block 5606 in this implementation performs double function of "pull up logic computation” and "voltage translation circuit”. Similarly, the "Pull down logic computation circuit” 5 is divided into two sub-blocks 5603 and 5607 in this implementation each consisting of High Speed and Low Leakage NMOS transistors respectively. Block 5607 again performs double functions of "pull down logic computation” and "voltage translation circuit".
  • Blocks 5607 and 5607 also perform additional task of holding output port to LOGIC LOW at Vsssp and LOGIC HIGH at Vddsp after the output has made the transition appropriately (according to Boolean function rule for NAND2 as defined earlier).
  • the "current control decision circuit" 5605 in this implementation works in exactly same way as in the INVERTER of Figure 19B. In this implementation, the Low Leakage MOS circuit and High Speed MOS circuits compute exactly same logic for the functional gate separately but in exactly same way.
  • the "pull up logic compute circuit” block 5606 and “Pull down logic compute circuit” block 5607 are connected to Supplyl (Vddsp) and Supply4 (Vsssp) respectively while the Pull UP logic computation circuit 5602 and Pull Down Logic computation Circuit 5603 are connected to Vdd and Vss supplies, respectively through other MOS transistors.
  • NAND2 Boolean functionality is performed by High Speed PMOS transistors 5623 and 5624, High speed NMOS transistors 5625 and 5626 and Low Leakage PMOS transistors 5630, 5631 and LOW Leakage NMOS transistors 5632 and 5633.
  • High Speed PMOS transistors 5623 and 5624 have negative gate-source voltages and hence have substantially reduced leakage current from Vdd to output port or Vss or Vsssp.
  • Leakage current through LOW Leakage and small MOS transistors 5630, 5631, 5632 and 5633 is substantially small by definition as explained earlier.
  • the output port 5609 is pulled to LOGIC HIGH at Vddsp by one or both of the Low Leakage PMOS transistors 5630 and 5631.
  • One or both of Low Leakage NMOS transistors 5632 and 5633 are OFF and one or both of High Speed NMOS transistors 5625 and 5626 are OFF.
  • current pull-down paths from output port 5609 to Vss or to Vsssp are cut OFF.
  • the output node 5639 of "current control decision circuit" 5605 is LOGIC HIGH at voltage Vddsp which means High Speed PMOS 5621 is OFF and High Speed NMOS transistor 5604 is ON which pulls down node 5635 to Vss.
  • one or both of the High Speed NMOS transistors 5625 and 5626 have negative gate-source voltage thus reducing the leakage currents through them substantially.
  • High Speed PMOS transistors 5623 and 5624 are ON. Since output port 5609 is pulled to LOGIC HIGH to voltage Vddsp, node 5634 also gets charged to Vddsp through one or both ON High Speed PMOS transistors 5623 and 5624. This node then becomes source node for High Speed PMOS transistor 5621 whose gate is also at Voltage Vddsp. But since the source-drain voltage of this PMOS transistor is only ⁇ , the leakage of this PMOS will be substantially LOW because of small drain-source voltage. As explained earlier Low Leakage PMOS and NMOS transistors 5630, 5631, 5632 and 5633 are small in size and of low leakage by definition. Hence the leakage of entire circuit function is substantially smaller than a normal CMOS circuit when the in this steady state.
  • the output port is at LOGIC LOW (Vsssp)
  • output of "Current control decision Circuit” 5605 is LOGIC LOW at voltage Vsssp
  • the High Speed PMOS 5621 is ON and High Speed NMOS 5627 is OFF.
  • High Speed NMOS 5626 turns OFF and High Speed PMOS 5624 turns ON. Since High Speed PMOS 5621 is also ON, current from Vdd starts charging the output node 5609 through ON High Speed PMOS transistors 5621 and 5624.
  • Low Leakage NMOS 5633 turns OFF and Low Leakage PMOS 5630 turns ON. This ON Low Leakage PMOS transistor starts charging the output port 5609 to Vddsp.
  • the output port makes transition from LOGIC LOW to LOGIC HIGH in exactly the same way when both the Inputs In_l and In_2 transition from LOGIC HIGH to LOGIC LOW, except in this case, both High Speed PMOS transistors 5624 and 5623 participate in charging of the output. Similarly both Low Leakage PMOS transistors 5630 and 5631 participate in charging of the output to Vddsp and holding the output to the voltage Vddsp in steady state after transition at output port is completed.
  • Output port 5609 hence starts discharging quickly through the high speed Pull down path consisting of High Speed NMOS transistors 5625, 5626 and 5627. Simultaneously, Low Leakage NMOS transistors 5632 and 5633 are also turned ON and conduction path for pull down current from output port 5609 to Vsssp is completed thus discharging the output port to Vsssp.
  • output discharge through High Speed NMOS transistors 5625, 5626 and 5627 that are appropriately sized for speed is much faster.
  • Low leakage NMOS transistors 5632 and 5633 gradually pull the output port 5609 to voltage Vsssp thus bringing the functional gate to its steady state of output being LOGIC LOW and holding the output in this state till the transition occurs again because of appropriate changes in input signals.
  • Low Leakage PMOS transistor 5641 and Low Leakage NMOS transistor 5642 are represented symbolically by a Low Leakage inverter 5640.
  • Two of these inverters make up "current control decision circuit” 5605 in Figure 19C and 15605 in Figure 19B.
  • this schematic representation is exactly same as the schematic representation of "current control decision circuit” in Figure 19B. It can be easily understood that sizing of transistors in "current control decision circuit” will be chosen appropriately by design engineers in actual implementation according to speed, noise and other performance and implementation parameter requirements.
  • Figure 19D shows transistor level implementation and connectivity of Low Leakage INVERTERS 15628 and 15629 of Figure 19B and 5628 and 5629 of Figure 19C.
  • the low Leakage INVERTER of Figure 19D, 5640 consists of the Low Leakage PMOS 5641 whose source is connected to Vddsp, drain is connected to the output port and the drain of Low Leakage NMOS 6542 and Gate is connected to the Input port and also to the gate of Low Leakage NMOS 5642, and Low Leakage NMOS 5642 whose source is connected to Vsssp.
  • More complex and sophisticated comparator circuits can be used to construct the "current control decision circuit” in variations of this design. Additionally, timing delay through “current control decision circuit” can be changed by many various methods including sizing, more stages, use of slower or faster MOS transistors, explicit or implicit loading of nets or MOS ports etc. This delay tuning will help in controlling the ratio of current to Vdd/Vss and Vddsp/Vsssp, duration of participation of high speed transistors in transitioning the output. The sizing and ratio of sizes of High Speed and Low Leakage MOS transistors is determined in actual implementation by design engineer based n various IC implementation requirements of performance, noise, reliability, leakage, speed etc.
  • Figure 20A illustrates yet another variation of general implementation of the general RLCL scheme presented in Figure 14 A.
  • Figure 20 A represents design of RLCL function gates exactly like the ones in Figure 17 except connectivity of some of the sub-blocks have been reshuffled.
  • the "current control decision circuit” is connected to output port of the cell (Out) 5707 in same way as in Figure 17. Additionally it may be connected to "Pull up logic computation and current control circuit” 5701 "Pull up current control circuit” 5702, “Pull down current control circuit” 5703, “Pull down logic computation & current control circuit” 5704. In transistor level implementation each of these blocks can be sub-divided into multiple blocks or merged together with other blocks of form any combination of merge and divide to provide the fundamental functionality as described in Figure 14 A. As compared to Figure 17, connectivity of various sub-blocks to each other and supply rails has small changes, but the number of supply rails is same as in Figure 17 with exactly same voltage relationship.
  • Figure 20B shows yet another variation in connectivity and design of sub-blocks as compared to Figure 20A.
  • Figure 20B is similar to Figure 20A except some of the sub-blocks have been split in two parts. This functionality sub-division is similar to the functionality subdivision illustrated in Figure 19B. Again, this variation of Figure 20A and 19B is just another implementation of the general RLCL circuit scheme presented in Figure 14A.
  • Figure 21 shows MOS transistor level implementation of RLCL NAND2 functional gate according to embodiments presented in Figure 20B. MOS implementation according to circuit scheme shown in Figure 20 A is similar.
  • MOS transistor level implementation of Figure 20B is very similar to one shown and described in Figure 19C with exception of swapping of some of the sub-blocks connectivity in the circuit. All parts consisting of Low Leakage transistors are exactly same as in Figure 19C and also function in exactly same way as in Figure 19C. All other parts of circuits consisting of High speed transistors also function in mostly same way as in Figure 19C with small difference. This difference is in the way how, "pull up current control circuit" 5802 and “pull down current control circuit” 5803 and nodes connected to these sub-blocks behave during transitions.
  • Steady state behavior of this implementation is same as the RLCL NAND2 gate described in Figure 19C.
  • all High Speed transistors are OFF.
  • Leakage currents in all high Speed transistors are substantially smaller than a CMOS implementation because of negative gate-source voltage or because of very small source-drain voltage on High Speed MOS transistors that are OFF.
  • Output of the functional gate is held at Vddsp or Vsssp by LOW Leakage PMOS or NMOS transistors in blocks 5806 and 5807 depending on the LOGIC at Input ports In_l and In_2.
  • High Speed MOS transistors are active and provide High switching current to achieve high speed transitions and after the output has transitioned the High Speed MOS path (PULL up or PULL DOWN as appropriate) turns OFF as controlled by the 'Current control decision Circuit" 5805. This operation is exactly same as in other variations of RLCL circuit implementation described before.
  • output port (Out) 5809 has made transition from LOGIC LOW to LOGIC HIGH
  • output node 5839 of "Current Control Decision Circuit” 5809 transitions to LOGIC HIGH at Vddsp as previously described in reference to other embodiments of RLCL functional gates. This causes the High Speed PMOS transistor 5823 to turn OFF and High Speed NMOS transistor 5824 to turn ON.
  • the output 5809 is then pulled UP to Vddsp by PULL UP path consisting of Low Leakage PMOS transistors 5830 and/or 5831.
  • High speed PMOS 5823 turns ON. This makes node 5840 discharge to a voltage that is a PMOS threshold voltage above the voltage at output port 5809 at this exact moment (and eventually to a voltage equal to Vsssp due to leakage if the output port 5809 doesn't switch again for long time). This is due to natural electrical behavior of a PMOS transistor. This results in charge sharing between output node 5809 and node 5840. This charge sharing creates small kink in the output node thereby slowing down the discharge of output node 5809 slightly or causing small bump in the output node that jumps up slightly before discharging to Vsssp completely.
  • Output port 5809 is pulled down to Vsssp b cxsm n in Low Leakage PoH do n path through NMOS tran i t rs 3 ⁇ 432 and 5833. It should be noted that this doesn't cause any LOGIC glitch in the output port 5809 since the output has transitioned to LOGIC LOW successfully before this charge sharing action. Similarly, when output port 5809 is pulled UP to LOGIC HIGH and node 5839 is also PULLED high to LOGIC HIGH, High speed NMOS 5824 turns ON (while High Speed PMOS 5823 turns OFF).
  • node 5841 charge to a voltage that is a NMOS threshold voltage below the voltage at output port 5809 at this exact moment (This node 5841 eventually charges to a voltage equal to Vddsp due to leakage if the output port 5809 doesn't switch again for long time). This is due to natural electrical behavior of a MOS transistor. This results in charge sharing between output node 5809 and node 5841. This charge sharing creates small kink in the output node thereby slowing down the charging of output node 5809 slightly or causing small dip in the instantaneous voltage of the output node that dips slightly before charging to Vddsp completely.
  • Output port 5809 is pulled up to Vddsp by currem m Lo Leakage Pull o path mrough P OS iraris stor : 5830 and/or 5831. It should be noted that this doesn't cause any LOGIC glitch in the output port 5809 since the output has transitioned to LOGIC HIGH successfully before this charge sharing action takes place.
  • the connectivity described in this implementation reduces effect of ground bounce in source nodes of High Speed PMOS transistors when the output switches from LOGIC LOW to LOGIC HIGH (Vsssp to Vddsp) thereby increasing the speed of transition. Therefore this implementation can be advantageous for Speed.
  • Figure 22 illustrates yet another implementation of the RLCL circuit technology presented in Figure 14A.
  • This is a simpler schematic implementation of RLCL circuits of Figure 14A where all functionalities of sub-blocks of Figure 14A are merged into a "Pull up logic computation and voltage translation with current control and current control decision circuits" 5901 and "Pull down logic computation and voltage translation with current control and current control decision circuit” 5902.
  • the four supply rails Supply 1, Supply2, Supply3 and Supply4 are exactly same as described with reference to Figure 14A and in other embodiments of RLCL circuit implementations. All basic logic functions are formed with one or multiple input ports and one output port as in other implementations. Similarly, more complex functional circuits or cells are formed by combining multiple basic functional gates (cells).
  • Figure 23 illustrates a MOS transistor level implementation of an RLCL INVERTER function according to the scheme shown in Figure 22.
  • This transistor level implementation is same as the implementation in Figure 15 with some small modification, but the functioning of this structure is exactly same as explained earlier in detail for Figure 15.
  • input port "In” transitions from LOGIC LOW at Vsssp to LOGIC HIGH at Vddsp the High Speed NMOS UN device 5942 and Low Leakage NMOS transistor 5944 are ON.
  • the High Speed UN NMOS device 5942 pulls the output port 5929 down to Vss with High Speed and Low Leakage NMOS device 5944 pulls the output port 5929 down to Vsssp and keeps it there till the next transition Similarly, hen input port "In" transitions from LOGIC HIGH at Vddsp to LOGIC LOW at Vsssp the High Speed PMOS UP device 5923 and Low Leakage PMOS transistor 5943 are ON.
  • the High Speed UP PMOS device 5923 pulls the output port 5929 UP to Vdd with High Speed and Low Leakage PMOS device 5943 pulls the output port 5929 UP to Vddsp and keeps it there till the next transition.
  • This UP device is turned on in the same way as a standard PMOS transistor (when gate is at lower voltage than source by more than the PMOS threshold voltage. There is never a current flow from drain to source in this device.
  • the UN device is a Unidirectional High Speed NMOS transistor that conducts current only in one direction - drain to source when it is ON and conducts no current when it is OFF. This UN device is turned on in the same way as a standard NMOS transistor (when its gate node is more than an NMOS threshold above the source node). There is never a current flow from source to drain in this special High Speed NMOS device.
  • the inverter in Figure 23 functions exactly the same way as the INVERTER shown in Figure 15 whose functionality to fulfill high speed and low leakage characteristics of RLCL technology is explained earlier.
  • INVERTER of Figure 15 there is a shortcoming in the implementation of INVERTER of Figure 15 that there is a short circuit current between Vdd and Vddsp when the input port "In" is at LOGIC LOW.
  • the INVERTER of Figure 15 has a short circuit current between Vss and Vsssp when the input port "In” is at LOGIC HIGH.
  • the shortcoming of the short circuit currents in INVERTER of Figure 15 is eliminated in the INVERTER of Figure 23 by use of these special MOS devices UP and UN.
  • the output port 5929 is pulled down to Vsssp by the Low Leakage NMOS 5944.
  • this NMOS transistor doesn't conduct current from Vss to Vsssp because of its uni-directional current conduction property.
  • the UN NMOS 5924 helps in transitioning the output to LOGIC LOW by allowing high current from output port 5929 to Vss during transition of output port from LOGIC HIGH to LOGIC LOW. Once the output has reached Vss quickly it gets pulled further DOWN by Low Leakage PMOS 5943 to Vsssp. The drain node of UN NMOS 5941 being pulled below Vss makes the current ZERO in UN NMOS 5941.
  • Figure 24 illustrates an implementation of a RLCL NAND2 functionality using UN and UP devices as per the circuit scheme of Figure 22.
  • This implementation functions in the same way as the INVERTER of Figure 23 except it performs a NAND2 logic function while reducing the leakage of the functional gate by negative gate-source biasing as per the general scheme of the circuit block diagram proposed in Figure 14A.
  • Figures 25A-B illustrates examples of implementations of the UN and UP devices, respectively, in semiconductor foundries.
  • Figure 25 A shows an implementation of the UN device using a diode junction in series with the drain of the NMOS transistor. This diode is shown schematically by 6001 in Figure 25 A. On silicon, this diode is formed within the drain of the NMOS transistor by formation of a P+ diffusion 6010 in the N+ diffusion of the drain as shown. Rest of the structures and formation of UN NMOS device is exactly same as standard NMOS devices formed by the foundry currently.
  • FIG. 25B An alternative implementation of special NMOS transistor UN is shown in Figure 25B.
  • an NPN BJT transistor 6021 is in series with the drain terminal of the NMOS transistor.
  • the implementation on silicon of this NPN transistor is as shown by 6030.
  • An N+ diffusion is formed within P+ diffusion 6031 which in turn is formed within N+ drain 6032 of NMOS transistor.
  • UP PMOS transistors will be formed in the similar way as shown in Figure 25 C and Figure 25D.
  • a diode 16001 is attached to the drain terminal of PMOS device.
  • On silicon such a device can be formed by forming N+ diffusion inside the P+ drain diffusion of the MOS transistor as shown in the Figure 25C.
  • An alternate method is to form a PNP transistor 16021 in the drain terminal of the PMOS device instead of a diode as show in Figure 25D by forming a P+ diffusion within a N+ diffusion which is further formed by N+ diffusion in the P+ diffusion of the drain of PMOS device.
  • the diode or NPN/PNP transistors so connected to the drain of NMOS or PMOS transistors prevent current from flowing from the source to the drain for UN NMOS and prevent current flowing from drain to the source for a PMOS device.
  • the source node for UP PMOS device is defined as the diffusion terminal connected to the Vdd (or Vddsp or another equivalent HIGH voltage supply node).
  • the source node for UN NMOS device is defined as the diffusion terminal connected to the Vss node (or Vsssp or another equivalent LOW voltage supply node.
  • a change in terminal voltage on source/drain doesn't change the designation of source/drain.
  • RLCL circuit technology can be used for reduction of leakage current and active current and for improving performance in memory structures such as SRAM (Static random access memory), DRAM (Dynamic Random Access Memory), Flash memory etc.
  • SRAM Static random access memory
  • DRAM Dynamic Random Access Memory
  • Flash memory etc.
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • Flash Memory Flash Memory
  • Figure 26 shows the block level functional and structural block diagram of a memory block. It consists of four sub-blocks including an "Address decoder” 6101, a "Control block” 6102, a "Sense Amp and IO” block 6103 and an "Array of memory bit cells” 6104. Small variations may exist in implementations that divide these blocks further in sub-blocks but at a high level Figure 26 represents structural and functional partitioning followed by most memory implementations.
  • Memory bit Array (6104) occupies most of the area in a memory implementation and is also the most important part of the memory implementation. This array is made up of many mostly identical memory bit cells, with slight variations for edge cells. Edge cells are memory bit cells that form peripheral part of "memory bit array" 6104. The number of memory bit cells in an IC is typically very large (can be in millions). An array of thousands of memory bit cells in same memory structure is common. Memory bit cells are commonly designed and provided by a manufacturing house (semiconductor foundry) because they are very small in size and special processing steps are performed by the manufacturers to keep their sizes small. Need for low cost and high performance presents conflicting requirements on design of a memory bit cell which tend to reduce the memory bit cell size and demand more performance
  • CMOS ICs in general, speed and size of a circuit component are inversely proportional to each other. Significant resources, time and efforts are spent on design and manufacturing of memory bit cell throughout the semiconductor industry, every year. Small and high performance memory bit cell provides significant business advantage to any semiconductor manufacturing house over their competitors. Hence, having a smaller, faster or both memory bit cell can be of high commercial value. Because of this reason, in modern times the Research and Development efforts for design and manufacturing of memory bit cells is mostly lead and conducted by semiconductor manufacturing companies.
  • a memory bit and memory array store data for computation within system or ASIC or any IC which is essential part of semiconductor IC and system functionality. All other blocks shown in Figure 26 exist to facilitate writing into and reading from this array 6104. Most IC designers take and use the memory bit cells provided by the manufacturer (Semiconductor foundry) and assemble them in appropriate array size as per their requirements. All other blocks "Address decoder” 6101, "control block” 6102, "Sense Amp &IO” 6103 are designed by IC design engineers based on the memory bit cell size and characteristics provided by the manufacturing house (Semiconductor foundry).
  • DRAM Dynamic Random Access Memory
  • SRAM static Random Access Memory
  • Flash memory Flash memory
  • a DRAM memory bit cell is a capacitor with a MOS switch for access to the charge on this capacitor. Charge is stored on a capacitor and read through the MOS switch. Each read destroys the charge of the memory bit cell and the charge needs to be restored by active circuit tricks for the memory bit before it can be read again. DRAM memory bit cell also looses charge due to leakage and the whole memory array needs to be refreshed periodically to compensate for the loss of charge due to leakage. In a refresh cycle, every memory bit cell is read.
  • Read LOGIC value is written back to the same memory bit cell immediately thus restoring the charge on memory bit cell to its healthy state. This is done for every memory bit cell in the array.
  • An SRAM bit cells consists of multiple MOS devices and retains charge forever as long as the memory block is connected to a power supply so that it does not require any refreshing.
  • the DRAM bit cell is typically much smaller in size as compared to SRAM bit cell.
  • DRAM memory ICs or DRAM memory blocks are much cheaper for a given cost (in dollars or area) as compared to SRAM ICs or SRAM blocks.
  • Flash memory bits are special memory structures that retain charge stored within special PolySilicon structures even after the power supply is disconnected. Thus Flash memory is a non- volatile memory.
  • SRAM is the fastest memory in CMOS, followed by DRAM and Flash memories. This is also the sequence for cost of memory per bit or memory ICs/blocks of same number of bits.
  • a group of memory cells are read and written simultaneously in the memory array 6104.
  • the memory array 6104 is, therefore organized in number of rows and columns. A whole row of memory bit cells is written and read simultaneously.
  • a "word line” connects all memory bit cells in a row together and controls the accesses to them for read and write operations.
  • a "bit line” connects all memory cells in a column together so as to provide a conduction path from bit cells to external circuitry through "Sense amp and 10" block 6103 for read and write operations..
  • bitlines may consist of one wire (single ended bitline) or two wires (differential bitline). Differential bitlines (two wires for every bitline) is a common practice.
  • Timing and electrical behavior for reading and writing the memory bit array is managed by the address decoder, control block and sense amp and IO block. These blocks are designed in such a way that an array of given memory bit cells is accessed for read and write, reliably, deterministically and with speed that memory is supposed to work at.
  • FIG. 27 illustrates more detailed connectivity and functional structure of SRAM memory implementation. As stated earlier this structure is applicable to all other types of memories also.
  • SRAM has four major blocks “address decoder” 6201, “control block” 6202, “Sense Amp and IO block” 6203 and "Memory bit cell array” 6204.
  • a simple and most commonly used design of a memory bit cell called 6T-bit cell (with 6 MOS transistors in one memory bit cell) 6223 is also shown in Figure 27.
  • a set of wordlines 6211 each connect all cells of one row.
  • Differential bitlines 6212 are also shown in this example.
  • One differential bit-line wires connect all cells of a column of memory bit cells together.
  • the wordlines are driven by address decoder block 6201 that further consists of address decoder and address driver gates 6221. Both bitlines 6212 and Wordlines 6211 are used for read and write operations.
  • bitlines are driven by bitline driver which is part of a larger functional sub-block "Pre-charge, column MUX, Sense Amp & bit line driver 6222.
  • bitlines are driven by the memory bit cell of the row being read. Complex timing and electrical behaviors are exhibited during memory read and write operations. A sophisticated timing and electrical behavior control mechanism is built by IC designers in address decoder, control block and Sense Amp & 10 blocks to accomplish reliable read and write operations.
  • Figure 28 illustrates a single bit cell of the RAM using reduced leakage current technology.
  • a detailed structure of a 6T SRAM memory bit cell 6301 is shown. It consists of a pair of back-to-back connected inverters connected to each other to form a bi-stable storage unit 6302.
  • a bi-stable structure is one that can hold both logic ZERO and LOGIC ONE states indefinitely unless a changing agent forces the state to change
  • These two inverters are formed by PMOS transistors 6311, 6312 and NMOS transistors 6313, 6314 as shown in Figure 28.
  • a pair of pass transistors consist of NMOS transistors 6315, 6316 that connect the storage unit 6302 to differential bit lines 6331 and 6332 respectively and also to wordline 6330.
  • An additional inverter 6303 made of PMOS transistor 6321 and NMOS transistor 6322 is part of the address decode and wordline driver functionality shown in Figure 27. This inverter is sized to drive the long and resistive word line wire of the memory array.
  • Bit lines 6331 and 6332 are differential and form one logical bitline for read and write of the column in which this particular memory bit cell is placed.
  • memory bit (storage unit) 6302 is a bistable storage unit for this memory bit cell.
  • Nodes 6333 and 6334 work as nodes where LOGIC value are preserved indefinitely until changed by an external agent/event as long as power supply Vdd and Vss are alive or ON. If node 6333 is driven to LOGIC HIGH, the inverter consisting of PMOS 6312 and NMOS 6314 drives a LOGIC LOW at node 6334, that in-turn drives a LOGIC HIGH at node 6333 through inverter made of PMOS 6311 and NMOS 6313.
  • bitlines 6331 and 6332 are pre-charged (pulled UP) to Vdd by the "Pre-charge, sense Amp & Bit line driver” unit 6304. Then the wordline 6330 is driven to LOGIC HIGH at voltage Vdd by the wordline driver 6303. Pre-charge action is terminated before switching ON the wordline. Bitlines 6331 and
  • bitline 6331 will remain pre-charged to Vdd while bitline 6332 starts discharging to Vss through Pull down path inside the memory bit cell formed by NMOS transistors 6316 and 6314, after Word Line is Pulled UP to Vdd.
  • a difference in voltage develops between the two bitlines which is correctly interpreted by the special circuit block called SENSE AMP in "Pre-charge, sense Amp & Bit line driver" 6304 block.
  • bitline 6331 is discharged by the pull down path inside the memory bit cell formed by NMOS transistors 6315 and 6313 while bitline 6332 remains pre-charged to Vdd. Again this voltage differential between the two wires of differential bit lines is senses correctly by the Sense Amp structure within block 6304.
  • differential "bitline driver" of block 6304 drives bitline 6331 and 6332 to appropriate differential LOGIC values and voltages when wordline 6330 is ON. Since the memory bit cell transistors are small and weak their LOGIC VALUES are forcefully overwritten by strong bitline drivers of block 6304.
  • NMOS transistors 6313, 6314 and pass transistors (also NMOS transistors) 6315 and 6316 need to provide high current during read operation.
  • high current requires large sizes of these NMOS transistors, which makes a memory bit cell large.
  • Large pass transistors 6315 and 6316 also increase load on the bitlines, which is connected to many bit cells in a column, thereby reducing the gain from increasing sizes of these transistors.
  • a larger pass transistors pair 6115 and 6116 also means larger capacitance on the word line 6330 which is connected to many cells within a row, which makes the word line also slower.
  • the speed of memory read and write is also negatively impacted by leakage currents in the pass transistors 6315 and 6316 of the memory bit cells.
  • the memory bit cell to be read has LOGIC LOW to be read on left hand side bitline 6331 (means the right hand side bitline 6332 would stay pre-charged to LOGIC HIGH) while the LOGIC VALUE stored on left hand side storage nodes (that is connected to the left side bitline 6331 with NMOS pass transistors that are OFF) of ALL memory bit cells in that column is LOGIC HIGH.
  • bitline 6331 and 6332 For example if the memory bit cell to be read had LOGIC LOW to be placed at bitline 6331 and LOGIC HIGH at bitline 6332 and if all other cells in the column were such that the leakage through their pass transistors would charge bitline 6331 and discharge bitline 6332, then this will mean that to develop a required differential between the two bitlines 6331 and 6332 will take more time as compared to the situation if the pass transistors were not leaking.
  • a larger differential voltage between bitlines means a more reliable read of the data.
  • Sense Amp circuits that detect the differential voltage between bitlines need certain minimum voltage to function reliably. In modern process technologies, this differential can be in range of 20mv -to- 70mv or higher. Larger differential voltage in bit lines provides faster speed of SENSE AMPLIFIERS.
  • RLCL circuit technology helps improve speeds of read and write operations by reducing leakage through the pass transistors 6315 and 6316 that are OFF and/or also by enhancing current in the pass transistors that are ON.
  • Leakage current in the memory is becoming worse in cost and speed parameters through generations as manufacturing technology progresses to newer generations.
  • This leakage power (or static power) is a big concern in modern ICs.
  • RLCL circuit technology reduces the leakage (static) power of the memory. In addition it also improves performance of the memory. This is achieved without needing changes in memory bit cell.
  • This feature (of reducing leakage power and improving performance of the memory without need to modify the memory bit cell) of RLCL circuit technology is of significant commercial advantage for IC implementation since the costly process of designing/modifying memory bit cell is completely bypassed.
  • leakage is present in all blocks Address decode 6101, Control Block 6102, Sense Amp & IO 6103 and Memory bit array 6104.
  • the leakage current in memory array 6104 is the most significant portion of overall leakage current in the memory.
  • all blocks except the memory array 6104 and Sense Amplifier circuits inside block 6103 are normal CMOS logic gates.
  • address decoder block 6101 will contain logic function and timing circuits with RLCL technology.
  • Sense Amplifier in the "Sense Amp & 10" block 6103 is replaced by RLCL sense Amplifier using RLCL technology and circuit techniques.
  • RLCL circuit technology leakage current in "Address decoder” 6101, Control block 6102 and "Sense Amp and IO” block 6103 is significantly reduced.
  • the memory bit used in the memory array can be same as the one provided by the manufacturing house (semiconductor foundry), because developing new memory bit cell may be a very expensive process. Even without changing the memory bit cell in the memory bit array, the leakage of "memory bit cell array" 6104 is reduced significantly using RLCL circuit technology
  • Figure 29 illustrates the leakage paths in a normal bit cell of a SRAM memory.
  • the schematic of Figure 28 is reproduced in Figure 29 with an emphasis of showing leakage currents in the memory bit cell.
  • Four current leakage paths are shown that originate or terminate leakage current in a memory bit cell.
  • word line 6430 is driven to Vss by the address decoder and word line driver (not shown in Figure 29)
  • this row is not selected for reading or writing operation and all the bit cells in this ROW are supposed to be inaccessible.
  • the Pass transistors 6415 and 6516 are OFF but are leaking. The amount of leakage current depends on the type and design of the Pass transistor NMOS and exact voltages on various nodes.
  • bitline 6431 is NOT being discharged and is in pre-charge state (Vdd) which also means bitline 6432 is being discharged by the bitcell that is being read (The bit cell being read is not shown in this Figure).
  • Vdd pre-charge state
  • one current leakage path 6441 exists from Vdd through pre-charged bitline (and the MOS transistor(s) pre-charging the bitline 6431 to Vdd), OFF NMOS 6415 and ON NMOS 6413.
  • node 6433 is at voltage Vss
  • the NMOS pass transistor 6415 has maximum drain- source voltage and ZERO gate-source voltage and hence high leakage current through it.
  • Another leakage current path 6442 exists from Vdd to Vss within the memory bit cell itself through OFF PMOS 6411 and ON NMOS 6413.
  • the PMOS of memory bit cell is very small in width and of larger gate length than normal gate length. Hence, this leakage current in OFF PMOS 6411 is relatively smaller than any of the OFF NMOS in the memory bit cell. Since node 6433 is at Vss and node 6434 is at Vdd, NMOS transistor 6414 is OFF.
  • yet another leakage current path 6443 exists within the memory bit cell from Vdd to Vss through ON PMOS 6412 and OFF NMOS 6414.
  • This NMOS 6414 has high drain-source voltage.
  • This NMOS is also much larger in comparison to both PMOS 6411 and 6412 Hence, leakage current through this NMOS transistor is much larger than the leakage current through any of the OFF PMOS transistors in the memory bit cell.
  • Yet another leakage current path 6444 exists from Vdd of the memory bit through on PMOS 6412 and OFF NMOS transistor 6416 to the discharging bitline 6432 (and hence to the NMOS of the bit cell that is being read and is discharging this bitline 6432).
  • Leakage current through pass transistors of the memory cell 6415 and 6416 are significant part of total leakage current in the memory array. Since, there is large number of memory in most modern CMOS ICS, the leakage current in memory is large percentage of the total leakage current of the IC even through the leakage in one memory cell is substantially lower than most of the CMOS logic gates.
  • Figure 30A illustrates a SRAM block implementation with RLCL technology.
  • Figure 30A is exactly same structure as in Figure 26 except that "Address decoder” has been replaced by “RLCL Address decoder”, sub-block "Sense Amp and 10" has been replaced by “RLCL Sense Amp and IO” and "Control block” has been replaced by 'RLCL Control Block”.
  • these blocks are exactly same as a normal CMOS SRAM memory of Figure 26 but the normal CMOS logic gates and circuits have been replaced by the RLCL logic gates and RLCL circuit.
  • RLCL logic gates and circuits are designed with one of the embodiments and circuit topologies described in Figure 14A and explained in more detailed from Figure 14A to Figure 25D. As mentioned earlier, the SRAM bit cell remains same as in Figure 26.
  • RLCL logic gates and RLCL circuit topologies used within sub-blocks "RLCL Address decoder” 16101, "RLCL Control block” 16102 and “RLCL Sense Amp & IO” 16103 result in substantially reduced leakage currents in these circuit structures. Additionally, RLCL circuit technology results in substantially reduced leakage current in "memory array” 16104 also.
  • Figure 30B shows circuit topology and design to achieve leakage current reduction in memory array.
  • word line driver Instead of a normal CMOS inverter, an RLCL INVERTER has been used as word line driver.
  • RLCL INVERTER One of the embodiments of RLCL INVERTER as explained earlier can be used for the purpose. Choice of type of RLCL inverter will depend on speed, noise margin and active power consumption requirements.
  • 6505 has been used to represent the RLCL INVERTER. Rest of the address decoder sub-block will be constructed using RLCL circuits.
  • 6504 is part of the wordline driver which is part of the address decoder section presented in Figures 26 and 27 and Figure 30A.
  • Output of this RLCL inverter is the wordline 6530 that transitions from Vddsp to Vsssp (that are at "Vdd+ ⁇ " and "Vss-Av2" respectively) as discussed earlier in the functionality of RLCL INVERTERS.
  • NMOS pass transistors With RLCL technology the memory bit cell read and write works in the same way as in a normal CMOS memory.
  • NMOS pass transistors When the wordline 6530 transitions to Vddsp, NMOS pass transistors are ON and discharge one of the two bit lines 6531 and 6532 depending on whether node 6533 is at LOGIC LOW or node 6534 is at LOGIC LOW.
  • ⁇ can be ZERO or positive (in range of 30mv - 200mv). If ⁇ is ZERO the read and write current through NMOS pass transistors 6515 and 6515 is same as in normal CMOS memory design. However, if ⁇ is positive, NMOS pass transistors 6515 and 6516 get higher gate- source voltage than the normal CMOS memory implementation of Figure 28.
  • leakage through pass NMOS transistors in the bit cells of ROWs in the memory that are supposed to be inactive (not accessed), is a major cause of degradation in memory read speed and degradation of reliability of read operation.
  • This leakage current also forces the memory structures to have less number of ROWs in the memory structure than the case if the leakage current in these pass transistors is significantly lower or ZERO.
  • Each memory block that is constructed needs to have its accompanying "Address Decoder", 'Control Block” and "Sense Amp and IO" sub-blocks.
  • these sub-blocks are only overheads (for speed, area and functionality that are unnecessary extra cost and power consumption). This means when a large memory block of the chip needs to be divided into smaller sub-block the total overheads are higher than if one large memory block was constructed instead.
  • RLCL circuit topology allows larger SRAM memory blocks to be designed, implemented and manufactured thereby reducing the overhead of "address decoder", "control block” and 'Sense Amp and IO” blocks.
  • RLCL technology allows design and implementation of larger memory blocks that are better in area, speed and power consumption. This is in addition to reduction in leakage power by reduction of leakage in all components and circuits in the memory block. It is important to note that no changes in "memory bit cell" are required for these improvements to take place, which makes RLCL technology easily adoptable in implementing memories in ICs.
  • RLCL technology Use, advantages and importance of RLCL technology explained in preceding sections are not limited to SRAM memory. DRAM, Flash memory and other CMOS based memory technology would realize similar speed, cost and power improvements by use of RLCL technology.
  • DRAM bit cell will not require any modifications.
  • the address decoder, control block, sense amp and 10 sections are modified using RLCL circuit technology to eliminate leakage in these sections as well as in memory array.
  • improved performance, improved area (that is lower area which means lower cost) and lower power consumption are realized using RLCL circuit technology.
  • Flash memory can use RLCL technology in the same way as in SRAM blocks and be better in area, performance, cost and power consumption.
  • RLCL Circuit technology is also usable in CMOS dynamic circuits.
  • Dynamic circuit blocks are special CMOS circuit topologies used for design and implementation of very high performance circuits in ICs. Dynamic CMOS circuits provide very high speed in calculating Boolean logic functions by speculatively computing one of the LOGIC states in advance and by reducing capacitance in propagation paths. This circuit technology in classical CMOS implementation is becoming extinct as semiconductor progress to modern smaller geometry CMOS because of Leakage current in MOS transistors.
  • Figures 31 A shows commonly used circuit structure of a CMOS dynamic Boolean logic block.
  • a dynamic Boolean logic block consists of small number of PMOS transistors (typically two) to PULL UP node 6620 to Vdd and a clock gated pull down network to PULL DOWN node 6620 to Vss.
  • An inverter 6615 is connected between node 6620 and output node “Out" (6614). The output node 6614 is connected to gate node of holding
  • PMOS 6613 is a signal generated through special timing circuits (Design and use of such timing circuits is common in IC design Industry) from global “Clock” signal.
  • the pre- charge signal switches ON PMOS 6612 at time when the PULL down current path through NMOS 6618 and "Pull Down Network” 6616 is OFF.
  • the dynamic circuit evaluates its input and computes output accordingly in “evaluate” phase when Both "Pre-charge” and "Clock” nodes are driven to logic HIGH (Vdd). "Pre-charge” and "Clock” are input signals to this block.
  • Pre- charge signal goes from Vdd to Vss little later than Clock and goes from Vss to Vdd little earlier than the 'Clock" signal.
  • Such behavior is easy to derive and is a common practice by engineers designing dynamic circuits. It is not uncommon to use "Clock” input signal also as “Pre-charge” signal.
  • "Pre-charge” signal can be generated separately from clock or from another source such that it provides functionality to PULL UP node 6620 by switching ON PMOS 6612 when the PULL DOWN current path through NMOS 6618 and "Pull down Network” 6616 is OFF.
  • Figure 3 IB shows the simplest logic function designed as a dynamic circuit where the "Pull Down Network” 6616 consists of a single NMOS transistor 6621 connected to only one input signal “In” (6622). Usually, though, dynamic circuit blocks use more complex pull down network to implement complex Boolean logic function.
  • the dynamic CMOS circuits shown in Figures 31 A and 3 IB have significant speed advantage over static CMOS circuits because logic computation involves only NMOS that present much smaller capacitive loads on signal propagation paths and have much larger drive currents. Dynamic circuits generally consume more active power due to high activity on nodes.
  • node 6620 When “clock” is driven high and also "Pre- charge” signal is already Vdd or driven to Vdd before “Clock” signal, node 6620 will be discharged to Vss if the "Pull Down Network” 6616 is conducting. If not- node 6620 is held at Vdd by PMOS transistor 6613. This is called “evaluation” phase for dynamic circuits.
  • the "Pull Down Network” 6616 conducts depending on the logic function computation designed in this network and the state of input signals. It must be noted that the PMOS transistor 6613 and the "Pull Down Network” 6616 must be appropriately sized such that when the Pull Down path is conducting, node 6620 is driven to Vss by overpowering the conduction of PMOS 6613.
  • the output of dynamic logic function of Figure 31 A is driven to LOGIC LOW in every clock cycle by pre-charging node 6620 to Vdd thus applying a LOGIC ZERO or LOGIC LOW at the output port 6614 of the gate speculatively.
  • the dynamic logic gate as shown in Figure 31 A only computes a LOGIC HIGH or LOGIC ONE at output port 6614 as function of its input ports 6617.
  • Logic ZERO or LOGIC LOW at output is driven by default through the pre- charge functionality.
  • the PMOS 6613 can be made stronger such that even in worst adverse process, voltage, temperature or noise conditions (Noise on input signals or noise on power supply rails) the output node 6620 is not discharged enough due to leakage or noise to cause LOGIC change or Noise pulse in output node 6614. But this means that when node 6620 actually needs to get discharged due to valid inputs and correct LOGIC function, the pull down path consisting of "Pull Down Network" 6616 and NMOS 6618 will have to fight a stronger PMOS 6613 which degrades the speed of the dynamic gate. This degradation defeats the very purpose of adopting dynamic circuit gate in the first place. As stated earlier, dynamic circuits consume more power because of high activity at various nodes. If they don't provide substantial speed improvement, they become impractical for commercial ICs.
  • leakage current is one of the biggest problems for dynamic circuits as explained in previous paragraph - big enough to make them extinct in modern technologies.
  • RLCL technology reduces leakage drastically thereby eliminating the problem of functional failure preserving the speed advantage of dynamic circuits, thus making them useful and practical even in modern technologies.
  • Figure 32 shows general scheme of connectivity for dynamic circuits using RLCL circuit technology or RLCL dynamic circuits.
  • Figure 33 shows implementation of the simplest RLCL dynamic functional gate.
  • CMOS dynamic circuits of Figure 31(a) is modified to make RLCL dynamic circuit as shown in Figure 32A.
  • Four power supply rails are used instead of two as in all RLCL circuit schemes.
  • Inverter 6615 of Figure 31(a) is replaced by RLCL inverter 6710 in Figure 32 A.
  • RLCL inverter 6710 is the Reduced Leakage INVERTER using RLCL circuit technology as per Figure 14A for static CMOS gates as explained in this invention and is implemented using one of the RLCL embodiments as illustrated in many figures from Figure 14A to Figure 25.
  • PMOS transistors 6702 and 6701 are connected to power supply rail Vddsp.
  • Pull Down Network 6703 consists of preferably “High Speed” NMOS transistors though it can consist of any type of NMOS transistors. Input ports 6711 of the dynamic gate are also inputs to the "Pull Down Network” 6703 and are driven by similar dynamic circuits or compatible circuits such that these nodes transition between supply rails Vddsp and Vsssp. Five new circuit components are added - Low Leakage NMOS transistors 6706 and 6713 and Low Leakage INVERTERS 6707 and 6708 and preferably High Speed NMOS 6705
  • "Low Leakage” inverters 6707 and 6708 which, as shown in Figure 32B, are normal CMOS Boolean INVERTER using "LOW LEAKAGE” PMOS and NMOS transistors connected to supply rails Vddsp and Vsssp. Gate of Low Leakage NMOS transistor 6713 is driven by "clock" input. Inverter 6707 is designed such that its input switching threshold is lower than half way between Vddsp and Vsssp. In practice, the extent of this threshold manipulation will be determined on many normal design considerations of dynamic circuits commonly known to CMOS design engineers and commonly prevalent in semiconductor industry.
  • inverter 6707 is connected to gate of NMOS 6706 and input of inverter 6708.
  • Output of inverter 6708 is connected to the gate of NMOS 6705 which is in series of NMOS 6704 and "Pull Down Circuit” 6703, that constitute the Pull Down path from node 6720.
  • Figure 32B shows schematic representation of LOW Leakage Inverter used in Figure 32A and is self explanatory.
  • Figure 32A is only a sample configuration of dynamic circuit using RLCL technology. Other configurations, connectivity and choice of MOS transistors are possible using same general concept explained here and without deviating from these concepts.
  • Figure 33 shows implementation of a simple function gate (a buffer) using RLCL dynamic circuit topology of Figure 32A. Functioning of RLCL technology in dynamic circuit is explained using functioning of this simple dynamic circuit.
  • NMOS 6805 has substantially reduced leakage because of negative gate-source voltage of NMOS 6804.
  • Pull down path consisting of Low Leakage NMOS transistors 6806 and 6813 is OFF by definition because of use of Low Leakage transistors.
  • Low Leakage inverter 6808 After node 6820 switches to LOGIC LOW, the output of Low Leakage inverter 6808 also switches to LOGIC LOW to Vsssp and causes the High Speed NMOS transistor 6805 to switch OFF.
  • Node 6820 is PULLED DOWN to Vsssp and held there through PULL DOWN path consisting of Low Leakage NMOS transistors 6806 and 6813.
  • High Speed NMOS transistors 6803, 6804 and 6805 have ZERO gate-source voltage and ⁇ 2 (very small compared to Vdd) drain-source voltage.
  • Low Leakage PMOS transistors 6801 and 6802 are OFF with ZERO gate-source voltage. The leakage current in this gate after transition is very small because of negative gate-source voltage to OFF High Speed MOS transistors or OFF Low leakage transistors.
  • PULL DOWN PATH consisting of Low Leakage NMOS 6806 and Low Leakage NMOS 6813 from node 6820 to Vsssp is also OFF because output of INVERTER 6807 is LOGIC LOW (Vsssp) which keeps Low Leakage NMOS 6806 OFF.
  • Leakage current in PULL DOWN path consisting of Low Leakage NMOS 6806 and 6813 is very low by definition because of the path consisting of Low Leakage NMOS transistors.
  • node 6820 is easily held at Vddsp by PMOS 6701. Now, the holding PMOS transistor 6801 can be weak and is still able to hold node 6820 to Vddsp. Noise and malfunctioning issues are eliminated because of elimination of leakage current in High Speed Pull Down path.
  • dynamic circuit can be designed using RLCL technology to retain their speed and area advantage in modern process technology over static circuits and can be used to design high speed circuits.
  • PMOS 6802 and 6801 are not required to be “Low Leakage” PMOS transistors but preferably they are so, since the Pull Down path consisting of "Pull Down Network” 6703 and NMOS 6705 has substantially reduced leakage current because of "Negative" gate source voltage on NMOS transistors used in the "Pull Down Network” as explained.
  • FIG. 34A illustrates an alternative implementation of a dynamic buffer with RLCL technology.
  • the two NMOS transistors 6804 and 6805 of Figure 33 are replaced by one NMOS transistor 6905 and a 2 INPUT Low Leakage AND gate 6904.
  • Clock input now is connected as input of AND gate 6904, output of which drives the gate node of (preferably) High Speed NMOS 6905.
  • the High Sped PULL DOWN path consists of only two (preferably) High Speed NMOS transistors 6903 and 6905 (instead of 3 NMOS transistors in Figure 33).
  • Figure 34B is schematic of the Low Leakage 2 input AND gate used in Figure 34A and is self explanatory.
  • RLCL dynamic buffers illustrate in Figures 33 and 34A use the same fundamentals of asserting negative gate-source voltage on High Speed (and hence High leakage) transistors.
  • the fundamental concepts of RLCL technology as represented at high level in Figure 14A and in more details in Figure 14A to Figure 35D, are used in dynamic circuits to reduced leakage current in dynamic circuits and make them viable in modern semiconductor ICs.
  • Figure 35A and Figure 35B illustrate the overall functioning of RLCL devices in form of algorithm and flow charts.
  • RLCL device is in reduced leakage state in steady state condition but ready to transition the output in opposite direction.
  • high current flows in transition paths consisting of HIGH SPEED MOS devices.
  • High Speed and High Leakage devices change state to low leakage mode using negative gate-source voltage or very small drain source voltage and the circuit enters the reduced leakage steady state condition in opposite direction waiting for output to transition again when input signals change appropriately.
  • an RLCL circuit is waiting in reduced leakage steady state when output is LOGIC ZERO as indicate by state 7501 and 8001. In this state the circuit can wait indefinitely in reduced leakage current state.
  • High speed current flows from Vdd and Vddsp or from one of them to output, charging the output towards LOGIC ONE.
  • High Speed MOS transistors change state to reduced leakage state either because of active circuit is switching off the High speed MOS components or the MOS components are designed with specific property of uni directional current.
  • the output is further pulled to up to Vddsp (still LOGIC ONE) by low leakage CMOS components.
  • Vddsp still LOGIC ONE
  • the circuit block enters the steady state with reduced leakage current but ready to switch the output to LOGIC ZERO at high speed if the input changes again.
  • This state is shown by state 7521 and 8021.
  • high speed MOS components conduct large discharge current from output to Vdd and Vddsp or one of them.
  • High Speed MOS components change state to reduced leakage state either because of active circuit is switching off the High speed MOS components or the MOS components are designed with specific property of uni directional current.
  • the output is further pulled down to Vsssp (still LOGIC ZERO) by low leakage CMOS components.
  • RLCL logic gate is now back to reduced leakage current state ready for transition in opposite direction of state 7501 and 8001.
  • Figures 35A and 35B are similar except Figure 34A indicates use of High Speed MOS components that can enter into LOW LEAKGE state automatically because of operating condition while Figure 35B indicates use of active circuit to actively enforce such behavior in High Speed MOS components.

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Abstract

L'invention concerne un dispositif semi-conducteur à courant de fuite réduit et un procédé de fabrication de ces dispositifs semi-conducteurs à courant de fuite réduit. Les dispositifs semi-conducteurs à courant de fuite réduit peuvent être utilisés aussi bien dans les circuits statiques que dans les circuits dynamiques. Les dispositifs semi-conducteurs à courant de fuite réduits réduisent le courant de fuite dans le dispositif quand le nœud n'est pas en transition, ce qui se produit plus de 95 % du temps.
PCT/US2013/039160 2013-03-25 2013-05-01 Dispositif semi-conducteur à courant de fuite réduit et son procédé de fabrication WO2014158200A1 (fr)

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US13/850,269 US9025404B1 (en) 2011-10-27 2013-03-25 Semiconductor device with reduced leakage current and method for manufacture of the same
US13/850,271 US9361950B1 (en) 2011-10-27 2013-03-25 Semiconductor device with reduced leakage current and method for manufacture of the same
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