WO2014153821A1 - 显示驱动电路及其驱动方法、显示装置 - Google Patents

显示驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2014153821A1
WO2014153821A1 PCT/CN2013/075915 CN2013075915W WO2014153821A1 WO 2014153821 A1 WO2014153821 A1 WO 2014153821A1 CN 2013075915 W CN2013075915 W CN 2013075915W WO 2014153821 A1 WO2014153821 A1 WO 2014153821A1
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WIPO (PCT)
Prior art keywords
signal
gate line
circuit
output enable
shielding
Prior art date
Application number
PCT/CN2013/075915
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English (en)
French (fr)
Inventor
吴行吉
李承珉
许益祯
张亮
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP13863667.5A priority Critical patent/EP2983161A4/en
Priority to JP2016504446A priority patent/JP2016512903A/ja
Priority to US14/368,144 priority patent/US9286821B2/en
Priority to KR1020147019388A priority patent/KR101579396B1/ko
Publication of WO2014153821A1 publication Critical patent/WO2014153821A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display driving circuit, a driving method thereof, and a display device. Background technique
  • the display device drives a panel operation by outputting a specific control signal through a timing controller (Timing Controler), and the timing controller usually includes the following signals: a frame start signal (STV), a gate line clock signal (CPV), first Output enable signal (0E1, Output Enable), gate line voltage chamfering signal (0E2), data read in and output signal (TP), pixel polarity control signal (POL), data enable signal (DE, Da ta Enab Le ).
  • STV frame start signal
  • CPV gate line clock signal
  • E1 first Output enable signal
  • TP data read in and output signal
  • POL pixel polarity control signal
  • DE Da ta Enab Le
  • the signals STV, CPV, 0E1 and 0E2 jointly control and drive the gate lines of the array substrate of the display device; wherein the rising edge of the CPV signal triggers driving the respective gate lines, and sequentially triggers the gate line driving signals of the respective gate lines through the shift register
  • the 0E1 signal is used to separate the gate line drive signals of adjacent rows to avoid crosstalk.
  • FIG. 1 is a schematic diagram of a display driving circuit of the prior art.
  • the gate line driving circuit triggers the gate line driving signal according to the gate line clock signal, and according to the first output enable signal.
  • the gate line driving signals of the adjacent rows are separated, and then the separated gate line driving signals are output to the gate lines.
  • 2 is a schematic diagram showing the relationship between the first output enable signal and the gate line driving signal in the prior art. As shown in FIG.
  • the corresponding gate line driving signal is triggered to a high level;
  • a rising edge of the output enable signal 0E1 pulls the corresponding gate line drive signal low to turn off the gate line drive signal, such as the Gatel signal or the Gate2 signal.
  • the prior art has the disadvantage that the first output enable signal cannot be used to shield the gate line driving signal according to a specific situation.
  • the frame flicker condition needs to be caused.
  • the frame data is masked off.
  • the prior art can only input the gate line driving signal of the adjacent row according to the first output enable signal 0E1. Line separation, it is impossible to trigger the generation of the mask signal according to the specific situation, the first output enable signal is shielded according to the mask signal, the corresponding gate line drive signal is turned off, and the data that may cause the display abnormality cannot be eliminated. Summary of the invention
  • the present disclosure provides a display driving circuit and a driving method thereof, and a display device for solving the problem that the prior art cannot shield the first output enable signal according to the mask signal, thereby removing data that may cause display abnormality.
  • a display driving circuit comprising: a gate line driving circuit for separating gate line driving signals of adjacent rows according to a first output enable signal;
  • the shielding signal generating circuit triggers the generation of the shielding signal when the gate driving signal needs to be turned off;
  • the first input end of the gate line shielding circuit inputs the first output enable signal, the second input end inputs the shielding signal, and the output end is connected to the gate line driving circuit, the gate line
  • the shielding circuit is configured to shield the first output enable signal according to the shielding signal, thereby turning off the gate line driving signal.
  • the gate line shielding circuit includes: a first transistor, a second transistor, a first resistor, a second resistor, and a third resistor, wherein
  • the first transistor of the first transistor receives the first output enable signal, the source of the first transistor is connected to a power source, and the drain of the first transistor is connected to the first resistor One end;
  • the gate of the second transistor receives the mask signal as the second input terminal, the source of the second transistor is connected to a power source, and the drain of the second transistor is connected to one end of the third resistor and The output terminal;
  • the other end of the first resistor is connected to one end of the second resistor and the other end of the third resistor;
  • the other end of the second resistor is grounded.
  • the mask signal is triggered by a timing controller.
  • a display device including the display drive circuit of the present invention is provided.
  • a driving method for driving a display driving circuit according to the present invention wherein the gate line driving signals of the adjacent rows are separated according to the first output enable signal, further comprising:
  • the mask signal generating circuit triggers the generation of the mask signal
  • the gate line masking circuit When the gate line masking circuit detects the masking signal, the first output enable signal is masked, thereby turning off the gate line driving signal.
  • the first output enable signal is pulled to a high level.
  • the present disclosure provides a display driving circuit, a driving method thereof, and a display device, which directly shields a first output enable signal according to a mask signal, thereby turning off a gate line driving signal, and shielding data on a corresponding gate line.
  • the first output enable signal can be used to avoid the occurrence of abnormal display conditions, and the circuit cost and circuit space can be saved, and the structure is simple and easy to implement.
  • FIG. 1 is a schematic diagram of a display driving circuit of the prior art
  • FIG. 2 is a schematic diagram showing the relationship between a first output enable signal and a gate line drive signal in the prior art
  • FIG. 3 is a circuit diagram of a display driving circuit according to an embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a gate line shielding circuit according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a driving method according to an embodiment of the present invention.
  • Figure 6 is a signal waveform diagram of a mask signal, a first output enable signal, and a gate line drive signal in accordance with an embodiment of the present invention.
  • Example 1 3 is a circuit diagram of a display driving circuit according to an embodiment of the present invention. As shown in FIG. 3, the display driving circuit of the embodiment of the present invention includes:
  • the mask signal generating circuit 200 when the gate driving signal needs to be turned off, triggering to generate the masking signal TR;
  • the gate line shielding circuit 300 inputs a first output enable signal 0E1 at a first input end of the gate line mask circuit 300, a mask signal TR at a second input end thereof, and a gate line drive circuit 100 connected to the output terminal.
  • the gate line mask circuit 300 shields the first output enable signal 0E1 according to the mask signal TR, thereby turning off the gate line drive signal.
  • the signal output from the output of the gate line mask circuit 300 is 0E1' and The waveform of an output enable signal OE1 is the same, that is, the signal 0E1 outputted by the output of the gate line mask circuit 300 follows the first output enable signal OE1, and the gate line mask circuit 300 does not affect the first output enable signal OE1.
  • An output enable signal 0E1 operates normally and is input to the gate line driving circuit 100, and the gate line driving circuit 100 separates and outputs the gate line driving signal to control the corresponding gate to operate normally.
  • the trigger signal TR When the trigger signal TR is triggered, that is, when the mask signal TR is at a high level, the signal 0E1 outputted from the output terminal of the gate line masking circuit 300 is kept at a high level, and the first output enable signal 0E1 is shielded. During the duration of the TR, all of the first output enable signals 0E1 are masked, thereby shielding the gate line drive signals, so that all gates are stopped.
  • the display driving circuit of the embodiment of the invention directly shields the gate line driving signal by the first output enable signal according to the shielding signal, and performs shutdown control on the corresponding gate line, thereby saving circuit cost and circuit space, and having a simple structure. Easy to implement.
  • the mask signal generating circuit 200 can detect an abnormal signal according to a specific requirement, for example, a flicker problem caused by POL inversion, and the timing controller can find the frame data of the blinking at the POL inversion timing, trigger the generation of the mask signal, and then
  • the masking signal controls the first output enable signal to turn off the corresponding gate line driving signal, and the frame data causing the display abnormality is removed, or the pin may be
  • the gate drive signal of a specific row in one frame is detected, and the data of a specific row in which the signal is abnormal is found to be culled.
  • a display driving circuit according to an embodiment of the present invention
  • Fig. 4 is a circuit diagram showing a gate line shielding circuit of an embodiment of the present invention.
  • the gate line shielding circuit 300 includes: a first transistor T1, a second transistor ⁇ 2, a first resistor R1, a second resistor R2, and a third resistor R3, wherein
  • the gate of the first transistor T1 receives the first output enable signal 0E1 as a first input terminal, the source of the first transistor T1 is connected to the power supply VDD, and the drain of the first transistor T1 is connected to one end of the first resistor R1;
  • the gate of the second transistor T2 receives the shield signal TR as a second input terminal, the source of the second transistor T2 is connected to the power supply VDD, and the drain of the second transistor T2 is connected to one end of the third resistor R3 and serves as an output terminal, and outputs a signal 0E1. ,;
  • the other end of the first resistor R1 is connected to one end of the second resistor R2 and the other end of the third resistor R3;
  • the other end of the second resistor R2 is grounded.
  • the manner in which the resistor is disposed is not limited.
  • the first resistor may be formed by several resistors in series or in parallel, and the above embodiment is only one of the preferred ones.
  • the second transistor T2 When the masking signal TR is at a high level, the second transistor T2 is turned on, the drain voltage of the second transistor T2 is pulled up to the power supply voltage, and the signal 0E1 outputted by the output terminal of the gate line masking circuit 300 is at a high level.
  • the first output enable signal 0E1 is completely shielded, further shielding the gate line driving signal, and stopping driving for all the gate lines;
  • the second transistor T2 When the masking signal TR is low, the second transistor T2 is turned off, and the first transistor T1 is turned on or off according to the first output enable signal OE1, so that the signal 0E1' outputted by the output of the gate line masking circuit 300 is first
  • the waveform of the output enable signal 0E1 is the same, specifically: when the first output enable signal 0E1 is at a high level, the first transistor T1 is turned on, and the voltage of the output signal 0E1 of the output terminal is pulled high to the high level.
  • Shielding gate line driving signal separating gate line driving signals of adjacent rows; when first output enable signal 0E1 is low level, first The transistor T1 is turned off, and the voltage of the signal 0 ⁇ outputted from the output terminal is pulled down to the ground, that is, the low level. At this time, the gate line driving signal is not shielded, and the corresponding gate line is driven. Since the first output enable signal OE1 is an electrical signal of the same interval generated according to the clock signal, when the first output enable signal OE1 is at a high level, the gate line driving signal at this time is shielded, thereby causing the gate line driving signal to be generated.
  • the first output enable signal is corresponding to the interval, thereby separating the gate line driving signals of the adjacent rows to avoid crosstalk; the signal outputted by the gate line shielding circuit 300 is ⁇ 1, according to the first output enable signal 0E1. , control the gate line drive circuit of its back end to work normally.
  • the mask signal is triggered by a timing controller.
  • the mask signal TR is generated by the timing controller, and the mask signal TR is utilized.
  • the output enable signal 0E1 turns off the gate drive signal, eliminating the POL inversion, which may result in flickering frame data.
  • the present invention also provides a display device comprising the display drive circuit of the present invention.
  • the display driving circuit of the present invention By using the display driving circuit of the present invention on the display device, the first output enable signal and the gate line driving circuit can be shielded by the gate line driving signal, thereby controlling the corresponding gate line, and the data which may cause the display abnormality is removed, the display
  • the drive circuit has a simple structure and is easy to install on a display device.
  • FIG. 5 is a flowchart of a driving method according to an embodiment of the present invention. As shown in FIG. 5, a driving method for driving a display driving circuit according to Embodiment 1 of the present invention is provided according to Embodiment 3 of the present invention, according to a first output.
  • the signal can separate the gate line driving signals of adjacent rows, and the method further includes the following processing:
  • step S101 when it is necessary to turn off the gate driving signal, the mask signal generating circuit triggers the generation of the masking signal
  • step S102 when the gate line masking circuit detects the mask signal, the first output enable signal is masked, thereby turning off the gate line drive signal.
  • the first output enable signal is pulled high.
  • Figure 6 is a signal waveform diagram of a mask signal, a first output enable signal, and a gate line drive signal in accordance with an embodiment of the present invention.
  • Ga tel, Ga te2, Ga te 3, Ga te4 or Ga te5 are gate line driving signals, respectively, when the masking signal is high level in the turn-on interval of the gate line driving signals Ga te3 and Ga te4, Pulling the first output enable signal to a high level, the first output enable signal is shielded, and the gate line drive signals Ga te3 and Ga te4 of the corresponding gate line drive circuit are set to a low level, the gate line drive signal Ga Te 3 and Ga te4 are shielded; when the mask signal is low, the first output enable signal returns to the normal output waveform, and the gate line drive signals of adjacent rows are separated, and the respective gate line drive signals of the gate line drive circuit also work normally.
  • step S101 of the driving method of Embodiment 3 of the present invention when it is necessary to turn off the gate line driving signal, the mask signal generating circuit triggers generation of the masking signal.
  • the frame data is affected, which causes the frame flicker to occur; the frame data is transmitted through the multi-row grid lines of the display device;
  • the data of the corresponding row lines can be eliminated by turning off the gate line driving signal, thereby avoiding the occurrence of frame flicker; therefore, when the POL is reversed, the gate line driving signal needs to be turned off; Shielding the signal, shielding the first output enable signal, turning off the corresponding gate line driving signal, and culling data that may cause frame flicker; otherwise, the masking signal is not triggered, the first output enable signal is normally sent, and the gate line driving signal works normally.
  • the POL inversion is controlled by the timing controller, and therefore, the masking signal TR can be triggered by the timing controller for the case of POL inversion.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明涉及显示技术。公开一种显示驱动电路，包括：栅线驱动电路，用于根据第一输出使能信号，分隔相邻行的栅线驱动信号；屏蔽信号产生电路，当需要关断栅极驱动信号时，触发产生屏蔽信号；栅线屏蔽电路，栅线屏蔽电路的第一输入端输入第一输出使能信号，第二输入端输入所述屏蔽信号，输出端连接所述栅线驱动电路，栅线屏蔽电路用于根据屏蔽信号屏蔽第一输出使能信号，从而关闭栅线驱动信号。本发明实施例的显示驱动电路及其驱动方法、显示装置，直接根据屏蔽信号对第一输出使能信号进行屏蔽，从而对栅线驱动信号进行关断，对相应栅线上的数据进行屏蔽，能够利用第一输出使能信号避免显示异常情况的出现，而且还可以节省电路成本和电路空间。

Description

显示驱动电路及其驱动方法、 显示装置 技术领域
本发明涉及显示技术领域， 尤其涉及一种显示驱动电路及其驱动 方法、 显示装置。 背景技术
显示装置通过时序控制器（Timing Contro l ler )输出特定的控制 信号来驱动面板（panel )工作， 时序控制器通常包含以下信号： 帧开 始信号（STV ),栅线时钟信号（CPV ), 第一输出使能信号（0E1 , Output Enable ), 栅线电压削角信号 （ 0E2 ), 数据读入与输出信号 （TP ), 像 素极性控制信号 （POL ), 数据使能信号 （DE , Da ta Enab le )。 其中信 号 STV、 CPV、 0E1和 0E2联合控制并驱动显示装置的阵列基板的栅线； 其中 CPV信号的上升沿触发驱动各个栅线， 通过移位寄存器， 依次触 发各条栅线的栅线驱动信号； 0E1 信号用于分隔相邻行的栅线驱动信 号， 以避免串扰的发生。
图 1是现有技术的显示驱动电路示意图， 如图 1所示， 在现有技 术的显示驱动电路中， 栅线驱动电路根据栅线时钟信号触发栅线驱动 信号， 根据第一输出使能信号分隔相邻行的栅线驱动信号， 然后输出 经过分隔的栅线驱动信号至栅线。 图 2是现有技术的第一输出使能信 号和栅线驱动信号的关系示意图， 如图 2 所示， 在栅线时钟信号 CPV 的上升沿，触发相应栅线驱动信号至高电平； 在第一输出使能信号 0E1 的上升沿， 把相应的栅线驱动信号拉低至低电平， 关断栅线驱动信号， 例如 Gatel信号或者 Gate2信号。 可见， 在第一输出使能信号 0E1的 高电平区域， 相邻行的栅线驱动信号为低电平， 被屏蔽， 形成了多个 栅线驱动信号间的间隔， 在该间隔区域内， 相应栅极被强制关闭， 以 此避免了相邻栅极在驱动时的串扰现象。
但是， 现有技术的缺点在于， 无法利用第一输出使能信号根据特 定情况对栅线驱动信号进行屏蔽， 例如对于解决消除残像技术的 POL 反转带来的闪烁问题， 需要把导致帧闪烁情况的帧数据屏蔽掉。 而现 有技术仅仅能根据第一输出使能信号 0E1 对相邻行的栅线驱动信号进 行分隔， 无法做到根据特定情况触发产生屏蔽信号， 根据屏蔽信号对 第一输出使能信号进行屏蔽， 关断相应栅线驱动信号， 进而无法把可 能导致显示异常的数据进行剔除。 发明内容
本公开提供一种显示驱动电路及其驱动方法、 显示装置， 用于解 决现有技术不能根据屏蔽信号对第一输出使能信号进行屏蔽， 进而把 可能导致显示异常的数据进行剔除的问题。
按照本发明的一个方面， 提供一种显示驱动电路， 包括： 栅线驱动电路， 用于根据第一输出使能信号， 分隔相邻行的栅线 驱动信号；
屏蔽信号产生电路， 当需要关断栅极驱动信号时， 触发产生屏蔽 信号；
栅线屏蔽电路， 所述栅线屏蔽电路的第一输入端输入所述第一输 出使能信号， 第二输入端输入所述屏蔽信号， 输出端连接所述栅线驱 动电路， 所述栅线屏蔽电路用于根据所述屏蔽信号屏蔽所述第一输出 使能信号， 从而关闭栅线驱动信号。
可选择地， 在本发明实施例的显示驱动电路中， 所述栅线屏蔽电 路包括： 第一晶体管、 第二晶体管、 第一电阻、 第二电阻、 第三电阻， 其中，
所述第一晶体管的栅极作为所述第一输入端接收所述第一输出使 能信号， 所述第一晶体管的源极连接电源， 所述第一晶体管的漏极连 接所述第一电阻的一端；
所述第二晶体管的栅极作为所述第二输入端接收所述屏蔽信号， 所述第二晶体管的源极连接电源， 所述第二晶体管的漏极连接所述第 三电阻的一端并且作为所述输出端；
所述第一电阻的另一端连接所述第二电阻的一端和所述第三电阻 的另一端；
所述第二电阻的另一端接地。
可选择地， 在本发明实施例的显示驱动电路中， 所述屏蔽信号由 时序控制器触发产生。 按照本发明的另一方面， 提供一种显示装置， 包括本发明所述的 显示驱动电路。
按照本发明的另一方面， 提供一种驱动如本发明所述的显示驱动 电路的驱动方法， 根据第一输出使能信号分隔相邻行的栅线驱动信号， 还包括：
当需要关断栅极驱动信号时， 屏蔽信号产生电路触发产生屏蔽信 号；
当栅线屏蔽电路检测到所述屏蔽信号 , 则第一输出使能信号被屏 蔽， 从而关闭栅线驱动信号。
可选择地， 根据本发明实施例的驱动方法， 当所述屏蔽信号的电 压为高电平， 则把所述第一输出使能信号拉至高电平。
本公开提供一种显示驱动电路及其驱动方法、 显示装置， 直接根 据屏蔽信号对第一输出使能信号进行屏蔽， 从而对栅线驱动信号进行 关断， 对相应栅线上的数据进行屏蔽， 能够利用第一输出使能信号避 免显示异常情况的出现， 而且还可以节省电路成本和电路空间， 结构 简单、 易于实现。 附图说明
图 1是现有技术的显示驱动电路示意图；
图 2是现有技术的第一输出使能信号和栅线驱动信号的关系示意 图；
图 3是本发明实施例的显示驱动电路的电路图；
图 4是本发明实施例的栅线屏蔽电路的电路图；
图 5是本发明实施例的驱动方法的流程图；
图 6是本发明实施例的屏蔽信号、 第一输出使能信号和栅线驱动 信号的信号波形图。
具体实施方式
为了更好地理解本发明， 下面结合附图与具体实施方式对本发明 作进一步描述。
实施例 1: 图 3是本发明实施例的显示驱动电路的电路图， 如图 3所示， 本 发明实施例的显示驱动电路包括：
栅线驱动电路 1 00 , 用于根据第一输出使能信号 0E 1 , 分隔相邻行 的栅线驱动信号；
还包括：
屏蔽信号产生电路 200 , 当需要关断栅极驱动信号时，触发产生屏 蔽信号 TR;
栅线屏蔽电路 300 ,在栅线屏蔽电路 300的第一输入端输入第一输 出使能信号 0E1 , 在其第二输入端输入屏蔽信号 TR , 输出端连接栅线 驱动电路 1 00。 栅线屏蔽电路 300根据屏蔽信号 TR屏蔽第一输出使能 信号 0E1 , 从而关闭栅线驱动信号。
通过把第一输出使能信号 0E 1输入栅线屏蔽电路 300 ,在没有触发 产生屏蔽信号 TR时， 即屏蔽信号 TR为低电平时， 栅线屏蔽电路 300 的输出端输出的信号 0E1 ' 与第一输出使能信号 0E1的波形相同， 即栅 线屏蔽电路 300的输出端输出的信号 0E1，跟随第一输出使能信号 0E1 , 栅线屏蔽电路 300不对第一输出使能信号 0E1产生影响， 第一输出使 能信号 0E1 正常工作并输入至栅线驱动电路 1 00 , 栅线驱动电路 1 00 分隔并输出栅线驱动信号， 控制相应的栅极正常工作。
在触发产生屏蔽信号 TR时， 即屏蔽信号 TR为高电平时， 栅线屏 蔽电路 300的输出端输出的信号 0E1， 保持为高电平，对第一输出使能 信号 0E1进行屏蔽， 在屏蔽信号 TR的持续时间内， 对所有第一输出使 能信号 0E1 都进行屏蔽， 进而屏蔽栅线驱动信号， 使所有栅极都停止 驱动。
通过本发明实施例的显示驱动电路， 直接根据屏蔽信号使第一输 出使能信号对栅线驱动信号进行屏蔽， 对相应栅线进行关断控制， 可 以节省电路成本和电路空间， 而且结构简单、 易于实现。 屏蔽信号产 生电路 200可以根据具体需求检测异常信号， 例如针对 POL反转带来 的闪烁问题， 通过时序控制器可以将 POL反转时刻带来闪烁的帧数据 找出， 触发产生屏蔽信号， 然后根据屏蔽信号控制第一输出使能信号 把相应栅线驱动信号关断， 把导致显示异常的帧数据剔除， 也可以针 对一帧中特定行的栅极驱动信号进行检测， 找出信号发生异常的特定 行的数据进行剔除。
可替换地， 按照本发明实施例的显示驱动电路， 图 4 示出本发明 实施例的栅线屏蔽电路的电路图。 如图 4所示， 栅线屏蔽电路 300包 括： 第一晶体管 Tl、 第二晶体管 Τ2、 第一电阻 Rl、 第二电阻 R2、 第 三电阻 R3 , 其中，
第一晶体管 T1 的栅极作为第一输入端接收第一输出使能信号 0E1 , 第一晶体管 T1的源极连接电源 VDD, 第一晶体管 T1的漏极连接 第一电阻 R1的一端；
第二晶体管 T2的栅极作为第二输入端接收屏蔽信号 TR,第二晶体 管 T2的源极连接电源 VDD, 第二晶体管 T2的漏极连接第三电阻 R3的 一端并且作为输出端， 输出信号 0E1，；
第一电阻 R1的另一端连接第二电阻 R2的一端和第三电阻 R3的另 一端；
第二电阻 R2的另一端接地。
在上述实施例中， 对所述电阻的设置方式不做限定， 比如第一电 阻可以由几个电阻串联或并联等效形成， 上述实施例只是其中优选的 一种。
以上电路是本发明实施例的栅线屏蔽电路的具体实现电路， 其原 理可描述如下：
当屏蔽信号 TR为高电平时， 第二晶体管 T2导通， 第二晶体管 T2 的漏极电压被拉高至电源电压， 栅线屏蔽电路 300 的输出端输出的信 号 0E1， 为高电平， 把第一输出使能信号 0E1全部屏蔽， 进一步屏蔽了 栅线驱动信号， 对所有栅线都停止驱动；
当屏蔽信号 TR为低电平时， 第二晶体管 T2关断， 第一晶体管 T1 根据第一输出使能信号 0E1打开或者关断， 使栅线屏蔽电路 300的输 出端输出的信号 0E1 ' 与第一输出使能信号 0E1的波形相同， 具体为： 当第一输出使能信号 0E1为高电平时， 第一晶体管 T1导通， 输出端输 出的信号 0E1， 的电压被拉高至高电平， 此时屏蔽栅线驱动信号， 分隔 相邻行的栅线驱动信号； 当第一输出使能信号 0E1 为低电平时， 第一 晶体管 Tl关断， 输出端输出的信号 0ΕΓ 的电压被拉低至地， 即低电 平， 此时不屏蔽栅线驱动信号， 对相应的栅线进行驱动。 由于第一输 出使能信号 0E1是根据时钟信号产生的相同间隔的电信号， 在第一输 出使能信号 0E1是高电平时， 屏蔽此时的栅线驱动信号， 从而使栅线 驱动信号产生与第一输出使能信号相对应的间隔， 从而把相邻行的栅 线驱动信号分隔开来，避免了串扰；栅线屏蔽电路 300输出的信号 0Ε1， 根据第一输出使能信号 0E1 正常工作， 控制其后端的栅线驱动电路正 常工作。
可替换地， 本发明实施例所述的显示驱动电路， 所述屏蔽信号由 时序控制器触发产生。
对于消除残像技术的 POL反转带来的闪烁问题， 由于 POL反转是 由时序控制器控制的， 因此， 当 POL反转时， 由时序控制器触发产生 屏蔽信号 TR,屏蔽信号 TR利用第一输出使能信号 0E1把栅极驱动信号 关闭， 剔除了 POL反转时， 可能导致闪烁的帧数据。
实施例 2:
本发明还提供一种显示装置， 包括本发明的显示驱动电路。
通过在显示装置上使用本发明的显示驱动电路， 可以利用第一输 出使能信号和栅线驱动电路， 屏蔽栅线驱动信号， 从而控制相应栅线， 把可能导致显示异常的数据剔除， 该显示驱动电路结构简单、 在显示 装置上易于安装。
实施例 3:
图 5是本发明实施例的驱动方法的流程图， 如图 5所示， 本发明 实施例 3提供的一种驱动如本发明实施例 1 中的显示驱动电路的驱动 方法， 根据第一输出使能信号分隔相邻行的栅线驱动信号， 该方法还 包括下列处理：
在步骤 S101中， 当需要关断栅极驱动信号时， 屏蔽信号产生电路 触发产生屏蔽信号；
在步骤 S102中， 当栅线屏蔽电路检测到屏蔽信号时， 第一输出使 能信号被屏蔽， 从而关断栅线驱动信号。
可替换地， 在本发明实施例的驱动方法中， 当屏蔽信号的电压为 高电平时， 把第一输出使能信号拉至高电平。
图 6是本发明实施例的屏蔽信号、 第一输出使能信号和栅线驱动 信号的信号波形图。 如图 6 所示， Ga tel、 Ga te2、 Ga te 3、 Ga te4 或 Ga te5分别是栅线驱动信号，当在栅线驱动信号 Ga te3和 Ga te4的开启 间隔内屏蔽信号为高电平时， 把第一输出使能信号拉至高电平， 第一 输出使能信号被屏蔽， 相对应的栅线驱动电路的栅线驱动信号 Ga te3 和 Ga te4被置为低电平， 栅线驱动信号 Ga te 3和 Ga te4被屏蔽； 当屏 蔽信号为低电平时， 第一输出使能信号恢复正常输出波形， 分隔相邻 行的栅线驱动信号， 栅线驱动电路的各个栅线驱动信号也正常工作， 例如， 栅线驱动信号 Ga tel、 Ga te2或 Ga te5。
在本发明实施例 3的驱动方法的步骤 S101中， 当需要关断栅线驱 动信号时， 屏蔽信号产生电路触发产生屏蔽信号。
例如， 对于消除残像技术的 POL反转带来的帧闪烁问题， 在 POL 反转时， 会对帧数据产生影响， 导致帧闪烁情况的发生； 帧数据通过 显示装置的多行栅线进行传输； 可以通过关断栅线驱动信号的方式来 把相应数行栅线上的数据剔除， 从而避免帧闪烁情况的发生； 因此， 在 POL反转时， 就需要关断栅线驱动信号； 通过触发产生屏蔽信号， 屏蔽第一输出使能信号， 关断相应栅线驱动信号， 将可能导致帧闪烁 的数据剔除； 否则， 不触发屏蔽信号， 正常发送第一输出使能信号， 栅线驱动信号正常工作；其中， POL反转是由时序控制器控制的， 因此， 可以由时序控制器针对 POL反转的情况触发产生屏蔽信号 TR。
以上仅为本发明的优选实施例， 当然， 本发明还可以有其他多种 实施例， 在不背离本发明精神及其实质的情况下， 熟悉本领域的技术 人员当可根据本发明做出各种相应的改变和变形， 但这些相应的改变 和变形都应属于本发明所附的权利要求的保护范围。

Claims

权 利 要 求 书
1、 一种显示驱动电路， 包括：
栅线驱动电路， 用于根据第一输出使能信号， 分隔相邻行的栅线 驱动信号；
屏蔽信号产生电路， 当需要关断栅极驱动信号时， 触发产生屏蔽 信号；
栅线屏蔽电路， 所述栅线屏蔽电路的第一输入端输入所述第一输 出使能信号， 第二输入端输入所述屏蔽信号， 输出端连接所述栅线驱 动电路， 所述栅线屏蔽电路用于根据所述屏蔽信号屏蔽所述第一输出 使能信号， 从而关断栅线驱动信号。
2、 根据权利要求 1所述的显示驱动电路， 其中， 所述栅线屏蔽电 路包括： 第一晶体管、 第二晶体管、 第一电阻、 第二电阻、 第三电阻， 其中，
所述第一晶体管的栅极作为所述第一输入端接收所述第一输出使 能信号， 所述第一晶体管的源极连接电源， 所述第一晶体管的漏极连 接所述第一电阻的一端；
所述第二晶体管的栅极作为所述第二输入端接收所述屏蔽信号， 所述第二晶体管的源极连接电源， 所述第二晶体管的漏极连接所述第 三电阻的一端并且作为所述输出端；
所述第一电阻的另一端连接所述第二电阻的一端和所述第三电阻 的另一端；
所述第二电阻的另一端接地。
3、 根据权利要求 1所述的显示驱动电路， 所述屏蔽信号由时序控 制器触发产生。
4、 一种显示装置， 包括如权利要求 1至 3任一项所述的显示驱动 电路。
5、 一种驱动如权利要求 1所述显示驱动电路的驱动方法， 根据第 一输出使能信号分隔相邻行的栅线驱动信号， 还包括：
当需要关断栅极驱动信号时， 屏蔽信号产生电路触发产生屏蔽信 号；
当栅线屏蔽电路检测到所述屏蔽信号， 则第一输出使能信号被屏 蔽， 从而关断栅线驱动信号。
6、 根据权利要求 5所述的驱动方法， 其中， 当所述屏蔽信号的电 压为高电平， 则把所述第一输出使能信号拉至高电平。
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CN103177682B (zh) 2015-05-13
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EP2983161A1 (en) 2016-02-10
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