WO2014086016A1 - Rc-igbt及其制作方法 - Google Patents

Rc-igbt及其制作方法 Download PDF

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Publication number
WO2014086016A1
WO2014086016A1 PCT/CN2012/086018 CN2012086018W WO2014086016A1 WO 2014086016 A1 WO2014086016 A1 WO 2014086016A1 CN 2012086018 W CN2012086018 W CN 2012086018W WO 2014086016 A1 WO2014086016 A1 WO 2014086016A1
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WO
WIPO (PCT)
Prior art keywords
buffer layer
layer
heavily doped
igbt
short
Prior art date
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Ceased
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PCT/CN2012/086018
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English (en)
French (fr)
Inventor
田晓丽
朱阳军
张文亮
吴振兴
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SHANGHAI LIANXING ELECTRONICS Co Ltd
Institute of Microelectronics of CAS
Jiangsu CAS IGBT Technology Co Ltd
Original Assignee
SHANGHAI LIANXING ELECTRONICS Co Ltd
Institute of Microelectronics of CAS
Jiangsu CAS IGBT Technology Co Ltd
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Application filed by SHANGHAI LIANXING ELECTRONICS Co Ltd, Institute of Microelectronics of CAS, Jiangsu CAS IGBT Technology Co Ltd filed Critical SHANGHAI LIANXING ELECTRONICS Co Ltd
Priority to PCT/CN2012/086018 priority Critical patent/WO2014086016A1/zh
Publication of WO2014086016A1 publication Critical patent/WO2014086016A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and more particularly to an RC-IGBT and a method of fabricating the same. Background technique
  • RC-IGBT Reverse Conducting Insulated Gate Bipolar Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • FDD fast recovery diode
  • the structure of the existing RC-IGBT is divided into an RC-IGBT having a buffer layer and an RC-IGBT having no buffer layer.
  • the RC-IGBT without buffer layer has a large on-state voltage drop and conduction loss.
  • the RC-IGBT with a buffer layer can reduce the on-state voltage drop through the buffer layer. And conduction loss.
  • An existing method for fabricating an RC-IGBT having a buffer layer includes:
  • the front surface structure of the device is fabricated on the N-substrate, and then the substrate is thinned to a desired thickness by grinding, etching, etc. from the back surface of the substrate, and the N+ of the back surface is formed by an ion implantation process and an annealing process.
  • the punch layer and the P+ collector region are then photolithographically etched to etch the N+ short circuit region window, and then an ion implantation is performed to form an N+ short circuit region.
  • the buffer layer produced by the above method is too thin, and it is substantially impossible to be larger than 1 micrometer, and the ion doping concentration in the buffer layer is related to the annealing process, so that the ion doping concentration in the buffer layer is not easily controlled within an ideal range. . Therefore, the on-state voltage drop and conduction loss of the buffered RC-IGBT fabricated by the above method are still not satisfactory. Summary of the invention
  • the embodiment of the invention provides an RC-IGBT and a manufacturing method thereof, which solves the problems in the prior art, improves the on-state voltage drop and conduction loss of the RC-IGBT, and improves the performance of the device.
  • the present invention provides the following technical solutions:
  • a method for fabricating an RC-IGBT comprising: providing a heavily doped substrate; forming a buffer layer on a surface of the heavily doped substrate, the buffer layer having a thickness greater than ⁇ , and a peak concentration of Iel4/cm 3 to 3el6 /cm 3 ; thinning the heavily doped substrate.
  • the buffer layer has a thickness of 5 ⁇ to 30 ⁇ .
  • the process for forming the buffer layer is an epitaxial process.
  • the method further includes: forming a light on the surface of the buffer layer a doped layer; a front structure of the RC-IGBT is formed on the lightly doped layer.
  • An RC-IGBT includes: a collector region, the collector region is a heavily doped region; a buffer layer, the buffer layer is located on a surface of the collector region, and the buffer layer has a thickness greater than ⁇ , The peak concentration is Iel4/cm 3 ⁇ 3el6/cm 3 .
  • the RC-IGBT further includes: a lightly doped layer, the lightly doped layer is located on a surface of the buffer layer; a front structure of the RC-IGBT, a front structure of the RC-IGBT is located in the lightly doped a short circuit region, the short circuit region is deep into the surface of the buffer layer, and a back surface of the short circuit region is flush with a back surface of the buffer layer; a collector, the collector is located in the collector region and The back side of the short circuit area.
  • the collector region has a thickness of 0.5 ⁇ m to 1 ⁇ m
  • the lightly doped layer has a thickness of 70 ⁇ m to 300 ⁇ m.
  • An RC-IGBT includes: a short circuit region, the short circuit region is a heavily doped region; a buffer layer, the buffer layer is located on a surface of the short circuit region, and the buffer layer has a thickness greater than ⁇ , and the peak concentration is Iel4/cm 3 ⁇ 3el6/cm 3 .
  • the RC-IGBT further includes: a lightly doped layer, the lightly doped layer is located on a surface of the buffer layer; a front structure of the RC-IGBT, a front structure of the RC-IGBT is located in the lightly doped a collector layer, the collector region is deep into the surface of the buffer layer, and a back surface of the collector region is flush with a back surface of the buffer layer; a collector, the collector is located in the set The back of the electrical and short circuit areas.
  • the short-circuited region has a thickness of 0.5 ⁇ m to 1 ⁇ m
  • the lightly doped layer has a thickness of 70 ⁇ m to 300 ⁇ m.
  • the RC-IGBT provided by the present application is formed by forming a buffer layer on the surface of the heavily doped substrate, and the thickness of the buffer layer is greater than ⁇ , which may be determined according to the withstand voltage requirement of the device, and then The heavily doped substrate is thinned. Since the buffer layer is formed on the surface of the heavily doped substrate, the thickness of the buffer layer is greater than ⁇ , the thickness of the buffer layer is no longer limited by the ion implantation process, that is, the thickness of the buffer layer can be controlled A larger range. Accordingly, the thickness of the buffer layer can be made thicker than in the prior art.
  • the method does not require annealing to activate the buffer layer
  • doping ions it is possible to precisely control the peak concentration of ion doping to be Iel4/cm 3 to 3el6/cm 3 .
  • the on-state voltage drop and conduction loss of the RC-IGBT can be further optimized, and the performance of the RC-IGBT can be improved.
  • FIG. 1 is a schematic flow chart of a method for fabricating an RC-IGBT according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of an RC-IGBT according to an embodiment of the present application
  • Another schematic diagram of the RC-IGBT structure is also provided.
  • the ion concentration is not easy to control.
  • the on-state voltage drop and conduction loss of the RC-IGBT with buffer layer are related to the thickness and quality of the buffer layer.
  • the existing method limits the thickness and quality of the buffer layer, and
  • the on-state voltage drop and conduction loss of the RC-IGBT of the buffer layer are also limited, which does not reach the desired level.
  • an embodiment of the present invention provides a method for fabricating an RC-IGBT, including: providing a heavily doped substrate;
  • a buffer layer on the surface of the heavily doped substrate, the buffer layer having a thickness greater than ⁇ , and a peak concentration of Iel4/cm 3 to 3el6/cm 3 ;
  • the heavily doped substrate is thinned.
  • the thickness of the buffer layer is no longer limited by the ion implantation process, and can be made thicker (greater than ⁇ ⁇ corresponding to the existing Compared with the technology, the thickness of the buffer layer can be controlled within a large range.
  • the method does not require annealing to activate the doping ions in the buffer layer, so that the peak concentration of ion doping can be precisely controlled to be Iel4/cm 3 . ⁇ 3el6/cm 3.
  • the on-state voltage drop and conduction loss of the RC-IGBT can be further optimized to improve the performance of the RC-IGBT.
  • the embodiment of the present application provides a method for fabricating an RC-IGBT, as shown in FIG. 1, comprising: providing a heavily doped substrate.
  • a buffer layer is formed on the surface of the heavily doped substrate, the buffer layer having a thickness greater than ⁇ , and the buffer layer having a peak concentration of Iel4/cm 3 to 3el6/cm 3 .
  • the buffer layer has a thickness of 5 ⁇ m to 30 ⁇ m, and more preferably, the buffer layer has a thickness of 20 ⁇ m.
  • the peak concentration of the buffer layer is from 1.5 el 4 /cm 3 to 2.5 el 6 /cm 3 .
  • the withstand voltage range of the RC-IGBT is not more than 2.5 KV.
  • the thickness of the buffer layer may be other optimal values depending on the withstand voltage of the device.
  • the heavily doped substrate is thinned, and the thickness of the heavily doped substrate after thinning is 0.5 ⁇ m to 1 ⁇ m. Preferably, the thickness of the heavily doped substrate after thinning is 0.8 ⁇ m.
  • the RC-IGBT provided by the present application is formed by forming a buffer layer on the surface of the heavily doped substrate, the buffer layer being thicker, and then thinning the heavily doped substrate. Since the buffer layer is formed on the surface of the heavily doped substrate, the thickness of the buffer layer is no longer limited by the ion implantation process and can be made thicker.
  • the thickness of the buffer layer can be controlled within a larger range than in the prior art.
  • the method does not require annealing to activate the doping ions in the buffer layer, so that the peak concentration of the ion doping can be precisely controlled to be Iel4/cm 3 to 3el6/cm 3 .
  • the on-state voltage drop and conduction loss of the RC-IGBT can be further optimized to improve the performance of the RC-IGBT.
  • Another embodiment of the present application discloses a method of fabricating a RC-IGBT of a P-type substrate, the method comprising:
  • the heavily doped substrate is a P-type heavily doped substrate, and the heavily doped substrate provided by the embodiment is thicker to avoid chipping due to the substrate being too thin in the subsequent fabrication process.
  • the buffer layer has a thickness of 10 ⁇ m.
  • the buffer layer has a peak concentration of Iel4/cm 3 to 3el6/cm 3 , preferably 2el6/cm 3 .
  • This embodiment is a buffer layer formed on the surface of the heavily doped substrate, so the thickness of the buffer layer is no longer limited by the ion implantation process and may be greater than 1 ⁇ m. Accordingly, the thickness of the buffer layer can be made thicker as compared with the prior art. And the method of forming a buffer layer on the surface of the heavily doped substrate by using an epitaxial process does not require annealing to activate dopant ions in the buffer layer, so that the peak concentration of ion doping can be precisely controlled to be Iel4/cm 3 ⁇ 3el6/cm. 3 .
  • the on-state voltage drop and conduction loss of the RC-IGBT can be further optimized to improve the performance of the RC-IGBT.
  • a lightly doped layer is formed on the surface of the buffer layer, and a front structure of the RC-IGBT is formed on the lightly doped layer.
  • a lightly doped layer is formed on the surface of the buffer layer by using an epitaxial process, the lightly doped layer is an N-type lightly doped layer, and the lightly doped layer has a thickness of 70 ⁇ m to 300 ⁇ m, preferably 150 ⁇ m. It should be noted that the thickness of the lightly doped layer may also be selected as other optimal values according to different voltage withstand requirements of the device.
  • the process of forming the front structure of the RC-IGBT on the lightly doped layer includes:
  • first gate dielectric layer on the surface of the lightly doped layer by a thermal oxidation process
  • the material of the first gate dielectric layer may be silicon dioxide.
  • a polysilicon layer is formed on a surface of the first gate dielectric layer.
  • a polysilicon layer is formed on a surface of the first gate dielectric layer by a process such as CVD, LPCVD or HDP.
  • Etching the polysilicon layer and the first gate dielectric layer to form a planar gate, and exposing lightly doped The impurity layer, the planar gate is a polysilicon planar gate.
  • a well region is formed in the surface of the lightly doped layer by an ion implantation process and an annealing process, and the well region is a P-type lightly doped well region.
  • a source region is formed in the well region by using an ion implantation process and an annealing process using a photoresist having a source region pattern as a mask, and the source region is an N-type heavily doped source region.
  • a second gate dielectric layer is formed on the planar gate surface and sidewalls by an oxidation process or a deposition process, and an oxide layer is formed on the surface of the lightly doped layer.
  • a photolithography process and an etching process are used to remove the oxide layer on the surface of the lightly doped layer to expose the source region, and further etch away part of the source region to expose a portion of the well region, the surface of the well region, the source region and the second gate dielectric layer
  • a source is formed thereon, and the source is in electrical contact with the well region and the source region to complete fabrication of the front surface structure of the RC-IGBT.
  • the source may also be passivated.
  • the heavily doped substrate is thinned by a chemical mechanical polishing process, and the thickness of the heavily doped substrate after thinning is
  • the heavily doped substrate can also be thinned using a mechanical or chemical etching process.
  • a short-circuit region window is formed in the heavily doped substrate to expose the buffer layer and form a short-circuit region in the buffer layer.
  • a photoresist layer is formed on the back surface of the heavily doped substrate, and the photoresist layer is exposed by using a mask having a short-circuit area window pattern, and a short-circuit area window is formed on the photoresist layer.
  • a pattern using a developing process, removing the photoresist at the short-circuit area window pattern, forming a short-circuit area window pattern on the photoresist layer, using a photoresist layer having a short-circuit area window pattern as a mask,
  • the doped substrate is etched to form a short-circuit region window, and the buffer layer is exposed.
  • the heavily doped substrate that is not etched is a collector region, and then the photoresist layer having the short-circuit region window pattern is used as a mask.
  • the photoresist layer having the short-circuit region window pattern is used as a mask.
  • the photoresist layer is removed, and annealing is performed to activate the doping ions in the short circuit region.
  • the short circuit region is an N-type heavily doped short circuit region.
  • the doping ions of the short circuit region are preferably phosphorus ions.
  • a collector is formed on the surface of the collector region and the surface of the short-circuit region, the collector being in electrical contact with the collector region and the short-circuit region.
  • the front surface structure of the device is first formed on the N-substrate, and then the substrate is thinned to a desired thickness by grinding, etching, or the like from the back surface of the substrate. Then, an N+ buffer layer and a P+ collector region on the back surface are formed by an ion implantation process, and then a N+ short-circuit region window is etched by a photolithography process, and an N+ short-circuit region is formed in the buffer layer by performing an ion implantation.
  • the processes of forming the P+ collector region and the N+ short-circuit region are performed on the basis of the N+ buffer layer, and the processing damage and inevitable crystal defects may cause the N+ buffer layer to prevent the field strength capability from being invalidated. , causing device performance to deteriorate.
  • the embodiment of the present application changes the existing RC-IGBT manufacturing method.
  • the step performed on the buffer layer only forms a process of forming a lightly doped layer and a short-circuit region, and therefore, relative to the present
  • the embodiment of the present application reduces processing damage and crystal defects of the buffer layer, improves the quality of the buffer layer, and further improves the performance of the RC-IGBT.
  • the operation of the back structure includes: the N-substrate needs to be thinned, and then the N+ buffer layer, the P+ collector region, and the N+ short circuit are formed. Zones, when operating on a thinner device basis, the device has a higher fragmentation rate.
  • the operation of the back structure includes: thinning the heavily doped substrate, and then forming a short-circuit area window and a short-circuit area. Compared with the prior art, the operation steps of the back structure are collapsed, Should reduce the fragmentation rate during device fabrication,
  • Another embodiment of the present application discloses a method for fabricating an RC-IGBT of an N-type substrate, the method comprising: providing a heavily doped substrate, the heavily doped substrate being an N-type heavily doped substrate, The heavily doped substrate provided by the embodiment is thicker to avoid the occurrence of debris due to the substrate being too thin during subsequent fabrication.
  • Forming a buffer layer on the surface of the heavily doped substrate by an epitaxial process the buffer layer is an N-type heavily doped buffer layer, and the buffer layer has a thickness greater than ⁇ , preferably, the thickness of the buffer layer It is 15 ⁇ .
  • the buffer layer has a peak concentration of Iel4/cm 3 to 3el6/cm 3 , preferably 1.8 el 4 /cm 3 .
  • This embodiment is a buffer layer formed on the surface of the heavily doped substrate, so the thickness of the buffer layer is no longer limited by the ion implantation process and may be greater than 1 ⁇ m. Correspondingly, the thickness of the buffer layer can be controlled within a larger range than in the prior art. And the method of forming a buffer layer on the surface of the heavily doped substrate by using an epitaxial process does not require annealing to activate dopant ions in the buffer layer, so that the peak concentration of ion doping can be precisely controlled to be Iel4/cm 3 ⁇ 3el6/cm. 3 .
  • a lightly doped layer is formed on the surface of the buffer layer, and a front structure of the RC-IGBT is formed on the lightly doped layer.
  • a lightly doped layer is formed on the surface of the buffer layer by an epitaxial process, the lightly doped layer is an N-type lightly doped layer, and the lightly doped layer has a thickness of 70 ⁇ m to 300 ⁇ m, preferably 150 ⁇ m.
  • a process of forming a front structure of an RC-IGBT on the lightly doped layer includes: forming a trench in the surface of the lightly doped layer by using a photolithography and dry etching process, and forming a first gate dielectric layer on the bottom of the trench and the sidewall surface by a thermal oxidation process.
  • the material of the first gate dielectric layer may be silicon dioxide.
  • Polysilicon is deposited in the trench to form a trench gate, and the trench gate fills the trench.
  • a well region is formed in the surface of the lightly doped layer by an ion implantation process and an annealing process, and the well region is a P-type lightly doped well region.
  • a source region is formed in the well region by an ion implantation process and an annealing process, and the source region is an N-type heavily doped source region.
  • a second gate dielectric layer is formed on the surface of the trench gate by an oxidation process, and an oxide layer is formed on the surface of the lightly doped layer.
  • An oxide layer on the surface of the lightly doped layer is removed by a photolithography process and an etching process to expose a portion of the well region and the source region.
  • a source is formed on the surface of the well region, the source region and the second gate dielectric layer, and the source is in electrical contact with the well region and the source region to complete fabrication of the front surface structure of the RC-IGBT.
  • the source may also be passivated.
  • the heavily doped substrate is thinned by a chemical mechanical polishing process, and the thickness of the heavily doped substrate after thinning is 0.5 ⁇ m to 1 ⁇ m, preferably 0.8 ⁇ m.
  • the heavily doped substrate can also be thinned using a mechanical or chemical etching process.
  • a collector region window is formed in the heavily doped substrate to expose the buffer layer, and a collector region is formed in the buffer layer.
  • the collector region is a ⁇ -type heavily doped region.
  • the dopant ions of the collector region are preferably boron ions.
  • a photoresist layer is formed on the back surface of the heavily doped substrate, and the photoresist layer is exposed by using a mask having a collector window pattern to form a current collection on the photoresist layer.
  • Area window pattern Using a developing process, removing the photoresist at the window pattern of the collector region, forming a collector region window pattern on the photoresist layer, using a photoresist layer having a collector region window pattern as a mask, The heavily doped substrate is etched to form a collector region window, and the buffer layer is exposed. The heavily doped substrate that is not etched is a short-circuit region, and then the photoresist layer having the collector region window pattern is The mask is formed by using an ion implantation process to form a collector region in the buffer layer, removing the photoresist layer, and annealing to activate dopant ions in the collector region.
  • the collector region is a P-type heavily doped collector region.
  • the dopant ions of the collector region are preferably boron ions.
  • a collector is formed on the surface of the collector region and the surface of the short-circuit region, the collector being in electrical contact with the collector region and the short-circuit region.
  • a further embodiment of the present application discloses an RC-IGBT, as shown in FIG. 2, comprising: a collector region 101, the collector region 101 is a heavily doped region, specifically a P-type heavily doped region, and The collector region 101 has a thickness of 0.5 ⁇ m to 1 ⁇ m; a buffer layer 102, and the buffer layer 102 is located on the surface of the collector region 101 and is heavily doped with germanium.
  • the thickness of the buffer layer is greater than ⁇ .
  • the buffer layer 102 has a thickness of 5 ⁇ m to 30 ⁇ m.
  • the buffer layer has a peak concentration of Iel4/cm 3 to 3el6/cm 3 , preferably 1.5 e 14/cm 3 to 2 ⁇ 5 e 16/cm 3 . It should be noted that the thickness and the doping concentration of the buffer layer 102 may also be adjusted according to different levels of the withstand voltage of the device, and are not specifically limited herein.
  • the RC-IGBT further includes: a lightly doped layer 103, the lightly doped layer 103 is located on the surface of the buffer layer 102, and is N-type light Doped, and the lightly doped layer 103 has a thickness of 70 ⁇ m to 300 ⁇ m.
  • the front structure of the RC-IGBT is located on the lightly doped layer 103.
  • a planar gate is taken as an example.
  • the front structure of the RC-IGBT includes: a well region 1031 in the surface of the layer 103, a source region 1032 located in the surface of the well region 1031, and a surface of the source region 1032 and a surface of the well region 1031 are flush with a surface of the lightly doped layer 103; a first gate dielectric layer 1033 on the surface of the lightly doped layer 103, on the surface of the well region 1031, and on the surface of the source region 1032, the first gate dielectric layer 1033 not completely covering the source region 1032 and the well region 1031; a planar gate 1034 on the surface of the first gate dielectric layer 1033, the planar gate 1034 is made of polysilicon; a second gate dielectric layer 1035 covering the surface and sidewalls of the planar gate 1034; a source 1036 on a surface of the second gate dielectric layer 10
  • the source electrode 1036 is a metal electrode, and the source electrode 1036 may be provided with a blunt surface. Layer to protect the source 1036 Effect.
  • the well region 1031 is P-type lightly doped, and the source region 1032 is N-type heavily doped.
  • a short circuit region 104, the short circuit region 104 penetrates into the surface of the buffer layer 102, and the short circuit region
  • the back surface of 104 is flush with the back surface of the buffer layer 102, and the short circuit region is a heavily doped region, specifically N-type heavily doped.
  • the collector 105 is located on the back surface of the collector region 101 and the short-circuit region 104, and the collector 105 is a metal electrode.
  • the buffer layer 102 since the thickness of the buffer layer 102 is greater than 1 ⁇ m, the buffer layer 102 is thicker than the prior art, and the heavily doped is used in the epitaxial process.
  • the method of forming a buffer layer on the surface of the substrate does not require annealing to activate dopant ions in the buffer layer, so that the peak concentration of ion doping can be precisely controlled to be Iel4/cm 3 to 3el6/cm 3 .
  • the on-state voltage drop and conduction loss of the RC-IGBT can be further optimized, and the performance of the RC-IGBT can be improved.
  • FIG. 3 Another embodiment of the present application discloses another RC-IGBT, as shown in FIG. 3, including: a short circuit region 201, the short circuit region 201 is a heavily doped region, specifically an N-type heavily doped region, and The short circuit region 201 has a thickness of 0.5 ⁇ m to 1 ⁇ m; a buffer layer 202, and the buffer layer 202 is located on the surface of the short circuit region 201 and is heavily doped with germanium.
  • the thickness of the buffer layer is greater than ⁇ .
  • the buffer layer 202 has a thickness of 5 ⁇ m to 30 ⁇ m.
  • the buffer layer has a peak concentration of Iel4/cm 3 to 3el6/cm 3 , preferably 1.5 e 14/cm 3 to 2 ⁇ 5 e 16/cm 3 .
  • the RC-IGBT further includes: a lightly doped layer 203, the lightly doped layer 203 is located on the surface of the buffer layer 202, is N-type lightly doped, and the lightly doped layer 203 has a thickness of 70 ⁇ m ⁇ 300 ⁇ .
  • the front surface structure of the RC-IGBT is located on the lightly doped layer 203.
  • a trench gate is taken as an example.
  • the front structure of the RC-IGBT includes: a well region 2031 in the surface of the impurity layer 203, a source region 2032 located in the surface of the well region 2031, and a surface of the source region 2032 and a surface of the well region 2031 are flush; formed in the lightly doped layer 203 a trench, a first gate dielectric layer 2033 at the bottom and sidewalls of the trench; a trench gate 2034 filled in the trench and located on a surface of the first gate dielectric layer 1033, the trench
  • the trench gate 2034 is made of polysilicon; a second gate dielectric layer 2035 overlying the surface of the trench gate 2034; on the surface of the second gate dielectric layer 2035, on the surface of the source region 2032, and on the surface of the well region 2031.
  • the source 2036 is a metal electrode, and the source 2036 may be provided with a passivation layer on the surface to protect the source 2036.
  • the well region 2031 is P-type lightly doped, and the source region
  • the 2032 is N-type heavily doped.
  • the collector region 204, the collector region 204 is deep into the surface of the buffer layer 202, and the back surface of the collector region 204 is flush with the back surface of the buffer layer 202, and the collector region 204 is heavily doped.
  • the region is specifically P-type heavily doped.
  • the collector electrode 205 is located on the back surface of the short circuit region 201 and the collector region 204, and the collector electrode 205 is a metal electrode.
  • the buffer layer 202 since the thickness of the buffer layer 202 is greater than 1 ⁇ m, the buffer layer 202 is thicker than the prior art, and the heavily doped is used in the epitaxial process.
  • the method of forming a buffer layer on the surface of the substrate does not require annealing to activate dopant ions in the buffer layer, so that the peak concentration of ion doping can be precisely controlled to be Iel4/cm 3 to 3el6/cm 3 .
  • the on-state voltage drop and conduction loss of the RC-IGBT can be further optimized, and the performance of the RC-IGBT can be improved.
  • the doping type in the RC-IGBT may be: the collector region is P-type heavily doped, the buffer layer is N-type heavily doped, and the lightly doped layer is N-type Lightly doped, the short circuit region is N-type heavily doped, the well region is P-type lightly doped, and the source region is N-type heavily doped.
  • the front structure of the RC-IGBT in this embodiment of the present application may also be other types of front structures. I will not repeat them here. The subject matter of the embodiments of the present invention is within the scope of protection of the embodiments of the present invention.

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Abstract

一种RC-IGBT及其制作方法，该方法包括：提供一重掺杂衬底，在所述重掺杂衬底表面上形成缓冲层，所述缓冲层的厚度大于1μm，峰值浓度为1e14/cm3~3e16/cm3，减薄所述重掺杂衬底。由于所述缓冲层的厚度可以根据器件的耐压水平做的更厚，而浓度可以做的更加精确，所以可以进一步的优化RC-IGBT的通态压降和导通损耗，改善所述RC-IGBT的性能。

Description

RC-IGBT及其制作方法
技术领域
本发明涉及半导体制造技术领域， 更具体地说， 涉及一种 RC-IGBT及其制 作方法。 背景技术
逆导型绝缘栅双极晶体管 （RC-IGBT, Reverse Conducting -Insulated Gate Bipolar Transistor )是具有国际前瞻性的一种新型绝缘栅双极晶体管 （IGBT, Insulated Gate Bipolar Transistor )器件， 它将传统的与 IGBT芯片反并联封装在 一起的快速恢复二极管（FRD, Fast Recovery Diode )与 IGBT集成在同一芯片 上， 提高了功率密度， 降低了芯片面积、 制造和封装成本， 同时提高了器件的 可靠性。
现有的 RC-IGBT的结构分为具有緩沖层的 RC-IGBT和没有緩沖层的 RC-IGBT两种。
其中， 没有緩沖层的 RC-IGBT的通态压降和导通损耗较大，相对于没有緩 沖层的 RC-IGBT而言，具有緩沖层的 RC-IGBT可以通过緩沖层来降低通态压降 和导通损耗。
现有的具有緩沖层的 RC-IGBT的制作方法 （以 P+集电区的 RC-IGBT为 例）， 包括：
在 N-衬底上制作器件的正面结构， 然后从衬底背面， 用研磨、腐蚀等方法 将衬底减薄至所需的厚度， 再采用离子注入工艺和退火工艺形成背面的 N+緩 沖层和 P+集电区， 接着再采用光刻工艺， 刻蚀出 N+短路区窗口， 再进行一次 离子注入形成 N+短路区。
但是， 通过上述方法制作的緩沖层太薄， 基本不可能大于 1微米， 而且所 述緩沖层内的离子掺杂浓度与退火过程有关，使得緩沖层内的离子掺杂浓度不 易控制在理想范围内。 因此，通过上述方法制作的具有緩沖层的 RC-IGBT的通 态压降和导通损耗仍不理想。 发明内容
本发明实施例提供了一种 RC-IGBT及其制作方法，解决了现有技术中的问 题， 改善了 RC-IGBT的通态压降和导通损耗， 提高了器件的性能。
为实现上述目的， 本发明提供了如下技术方案：
一种 RC-IGBT的制作方法， 包括： 提供一重掺杂衬底； 在所述重掺杂衬 底表面上形成緩沖层， 所述緩沖层的厚度大于 Ιμηι , 峰值浓度为 Iel4/cm3~3el6/cm3; 减薄所述重掺杂衬底。 优选的， 所述緩沖层的厚度为 5μΓη~30μηι。 优选的， 形成緩沖层所采用的工艺为外延工艺，在所述重掺杂衬底表面形 成緩沖层之后， 减薄所述重掺杂衬底之前， 还包括： 在所述緩沖层表面形成轻 掺杂层； 在所述轻掺杂层上形成 RC-IGBT的正面结构。 一种 RC-IGBT, 包括： 集电区， 所述集电区为一重掺杂区； 緩沖层， 所 述緩沖层位于所述集电区的表面上，且所述緩沖层的厚度大于 Ιμηι,峰值浓度 为 Iel4/cm3~3el6/cm3。 优选的， 所述 RC-IGBT还包括： 轻掺杂层， 所述轻掺杂层位于所述緩沖层表面上； RC-IGBT的正面结构， 所述 RC-IGBT的正面结构位于所述轻掺杂层上； 短路区， 所述短路区深入所 述緩沖层表面内， 且所述短路区的背面与所述緩沖层的背面齐平； 集电极， 所 述集电极位于所述集电区和短路区的背面。 优选的， 所述集电区的厚度为 0.5μηι~1μηι, 所述轻掺杂层的厚度为 70μηι~300μηι。 一种 RC-IGBT, 包括： 短路区， 所述短路区为一重掺杂区； 緩沖层， 所述緩沖层位于所述短路区 的表面上， 且所述緩沖层的厚度大于 Ιμηι, 峰值浓度为 Iel4/cm3~3el6/cm3。 优选的， 所述 RC-IGBT还包括： 轻掺杂层， 所述轻掺杂层位于所述緩沖 层表面上； RC-IGBT的正面结构， 所述 RC-IGBT的正面结构位于所述轻掺杂 层上； 集电区， 所述集电区深入所述緩沖层表面内， 且所述集电区的背面与所 述緩沖层的背面齐平； 集电极， 所述集电极位于所述集电区和短路区的背面。 优选的， 所述短路区的厚度为 0.5μηι~1μηι , 所述轻掺杂层的厚度为 70μηι~300μηι。 由上述方案可见， 本申请所提供的 RC-IGBT的制作方法是在重掺杂衬底 表面上形成緩沖层，所述緩沖层的厚度大于 Ιμηι,具体可以根据器件的耐压要 求而定， 再减薄所述重掺杂衬底。 由于是在重掺杂衬底表面上形成的緩沖层， 所述緩沖层的厚度大于 Ιμηι,所以所述緩沖层的厚度不再受离子注入工艺的限 制， 即所述緩沖层的厚度可以控制在一个较大的范围内。 相应的， 与现有技术 相比， 所述緩沖层的厚度可以做的更厚。且该方法不需要退火激活緩沖层内的 掺杂离子， 因此可以精确控制离子掺杂的峰值浓度为 Iel4/cm3~3el6/cm3。 通 过对 RC-IGBT的制作方法和制作工艺的调整，可以进一步的优化 RC-IGBT的 通态压降和导通损耗， 改善所述 RC-IGBT的性能。
附图说明 图 1为本申请实施例提供的一种 RC-IGBT制作方法的流程示意图； 图 2为本申请实施例所提供的一种 RC-IGBT结构示意图； 图 3为本申请实施例所提供的另一种 RC-IGBT结构示意图。
具体实施方式 正如背景技术所述，通过现有方法制作的具有緩沖层的 RC-IGBT的通态压 降和导通损耗仍不理想。 发明人研究发现， 出现这种问题的原因是，现有的具有緩沖层的 RC-IGBT 的制作方法中，是以 N-衬底为基础，再以离子注入工艺在所述 N-衬底背面形成 的緩沖层。 由于受到离子注入工艺及薄片工艺自身的限制， 所述緩沖层的厚度 很难超过 Ιμηι, 并且现有技术在离子注入工艺之后还需要退火以激活緩沖层内 的掺杂离子， 致使緩沖层内的离子浓度不易控制。 而具有緩沖层的 RC-IGBT 的通态压降和导通损耗是与緩沖层的厚度及质量有关系的，现有的方法限制了 緩沖层的厚度及质量，则通过现有方法制作的具有緩沖层的 RC-IGBT的通态压 降和导通损耗也受到了限制， 达不到理想水平。
发明人进一步研究发现， 通过改变现有具有緩沖层的 RC-IGBT的制作工 艺， 则可以使緩沖层的厚度达到 Ιμηι以上， 进而进一步优化 RC-IGBT的通态 压降和导通损耗， 提高器件的性能， 使其进一步满足需求。 基于此， 本发明实施例提供了一种 RC-IGBT的制作方法， 包括： 提供一重掺杂衬底；
在所述重掺杂衬底表面上形成緩沖层，所述緩沖层的厚度大于 Ιμηι,峰值 浓度为 Iel4/cm3~3el6/cm3;
减薄所述重掺杂衬底。
上述方法中， 由于是在重掺杂衬底表面上形成的緩沖层， 所以所述緩沖层 的厚度不再受离子注入工艺的限制， 可以做的较厚（大于 Ιμηι λ 相应的， 与 现有技术相比， 所述緩沖层的厚度可以控制在一个较大的范围内。且该方法不 需要退火激活緩沖层内的掺杂离子，因此可以精确控制离子掺杂的峰值浓度为 Iel4/cm3~3el6/cm3。 通过对 RC-IGBT的制作方法和制作工艺的调整， 可以进 一步的优化 RC-IGBT的通态压降和导通损耗， 改善所述 RC-IGBT的性能。
以上是本申请的核心思想， 下面将结合本发明实施例中的附图，对本发明 实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本 发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普 通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本 发明保护的范围。 在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明 还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不 违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例 的限制。
本申请实施例提供了一种 RC-IGBT的制作方法， 如图 1所示， 包括： 提供一重掺杂衬底。 在所述重掺杂衬底表面上形成緩沖层，所述緩沖层的厚度大于 Ιμηι,所述 緩沖层的峰值浓度为 Iel4/cm3~3el6/cm3。 优选的， 所述緩沖层的厚度为 5μηι~30μηι, 更优选的， 所述緩沖层的厚度为 20μηι。 所述緩沖层的峰值浓度 为 1.5el4/cm3~2.5el6/cm3。 此时， 所述 RC-IGBT的耐压范围不大于 2.5KV, 需要说明的是，根据器件耐压不同，所述緩沖层的厚度也可以为其他的最优值。 减薄所述重掺杂衬底， 减薄后的重掺杂衬底厚度为 0.5μηι~1μηι, 优选的， 减薄后的重掺杂衬底厚度为 0.8μηι。 由上述方案可见， 本申请所提供的 RC-IGBT的制作方法是在重掺杂衬底 表面上形成緩沖层， 所述緩沖层的厚度较厚， 再减薄所述重掺杂衬底。 由于是 在重掺杂衬底表面上形成的緩沖层，所以所述緩沖层的厚度不再受离子注入工 艺的限制， 可以做得较厚。 相应的， 与现有技术相比， 所述緩沖层的厚度可以 控制在一个较大的范围内。且该方法不需要退火激活緩沖层内的掺杂离子， 因 此可以精确控制离子掺杂的峰值浓度为 Iel4/cm3~3el6/cm3。 通过对 RC-IGBT 的制作方法和制作工艺的调整， 可以进一步的优化 RC-IGBT的通态压降和导 通损耗， 改善所述 RC-IGBT的性能。
本申请另一实施例公开了一种 P型衬底的 RC-IGBT的制作方法， 该方法 包括：
提供一重掺杂衬底，所述重掺杂衬底为 P型重掺杂衬底，本实施例提供的 重掺杂衬底较厚， 以避免后续制作过程中由于基底太薄而出现碎片的情况。 采用外延工艺在所述重掺杂衬底表面上形成緩沖层， 所述緩沖层为 N型 重掺杂的緩沖层， 且所述緩沖层的厚度大于 Ιμηι, 优选的， 所述緩沖层的厚度 为 10μηι。 所述緩沖层的峰值浓度为 Iel4/cm3~3el6/cm3, 优选为 2el6/cm3。 本 实施例是在重掺杂衬底表面上形成的緩沖层，所以所述緩沖层的厚度不再受离 子注入工艺的限制， 可以大于 1μηι。 相应的， 与现有技术相比， 由于本实施例 所述緩沖层的厚度可以做的更厚。且采用外延工艺在所述重掺杂衬底表面上形 成緩沖层的方法不需要退火激活緩沖层内的掺杂离子，因此可以精确控制离子 掺杂的峰值浓度为 Iel4/cm3~3el6/cm3。通过对 RC-IGBT的制作方法和制作工 艺的调整， 可以进一步的优化 RC-IGBT 的通态压降和导通损耗， 改善所述 RC-IGBT的性能。 在所述緩沖层表面形成轻掺杂层， 并在所述轻掺杂层上形成 RC-IGBT的 正面结构。 具体的， 采用外延工艺在所述緩沖层表面形成轻掺杂层， 所述轻掺杂层为 N型轻掺杂层， 且所述轻掺杂层的厚度为 70μηι~300μηι, 优选为 150μηι, 需要 说明的是，根据器件耐压要求的不同， 所述轻掺杂层的厚度也可以选取为其他 的最优值。
在所述轻掺杂层上形成 RC-IGBT的正面结构的过程（以正面为平面栅的 RC-IGBT为例）， 包括：
在所述轻掺杂层表面上采用热氧化工艺形成第一栅介质层，所述第一栅介 质层的材料可以为二氧化硅。在所述第一栅介质层表面上形成多晶硅层， 具体 的， 可采用 CVD、 LPCVD或 HDP等工艺在所述第一栅介质层表面上形成多 晶硅层。 对所述多晶硅层和第一栅介质层进行刻蚀， 形成平面栅， 并露出轻掺 杂层， 所述平面栅为多晶硅平面栅。 以所述平面栅为掩模， 采用离子注入工艺 和退火工艺在所述轻掺杂层表面内形成阱区，所述阱区为 P型轻掺杂阱区。 以 具有源区图形的光刻胶为掩模，采用离子注入工艺和退火工艺在所述阱区内形 成源区， 所述源区为 N型重掺杂源区。 采用氧化工艺或者淀积工艺在所述平 面栅表面和侧壁形成第二栅介质层， 同时会在轻掺杂层表面形成氧化层。采用 光刻工艺和刻蚀工艺去掉轻掺杂层表面的氧化层， 露出源区， 进一步刻蚀掉部 分源区， 露出部分阱区， 在所述阱区、 源区和第二栅介质层表面上形成源极， 所述源极与所述阱区和源区电接触， 完成所述 RC-IGBT正面结构的制作。 在完成所述 RC-IGBT正面结构的制作之后， 还可以对所述源极进行钝化 处理。 采用化学机械研磨工艺减薄所述重掺杂衬底，减薄后的重掺杂衬底厚度为
0.5μηι~1μηι, 优选为 0.8μηι。 此外， 还可以采用机械研磨或化学腐蚀工艺减薄 所述重掺杂衬底。
在所述重掺杂衬底内形成短路区窗口， 露出所述緩沖层， 并在所述緩沖层 内形成短路区。
具体的， 在所述重掺杂衬底背面形成光刻胶层， 利用具有短路区窗口图形 的掩膜版对所述光刻胶层进行曝光， 在所述光刻胶层上形成短路区窗口图案， 采用显影工艺，去掉短路区窗口图案处的光刻胶，在所述光刻胶层上形成短路 区窗口图形， 以具有短路区窗口图形的光刻胶层为掩模，对所述重掺杂衬底进 行刻蚀，形成短路区窗口，并露出緩沖层，未被刻蚀掉的重掺杂衬底为集电区， 之后， 以具有短路区窗口图形的光刻胶层为掩模， 采用离子注入工艺， 在所述 緩沖层内形成短路区，去除光刻胶层，并进行退火，激活短路区内的掺杂离子。 所述短路区为 N型重掺杂短路区， 优选的， 所述短路区的掺杂离子优选为磷 离子。
在所述集电区表面和短路区表面形成集电极，所述集电极与所述集电区和 短路区电接触。
需要说明的是，现有的 RC-IGBT的制作方法中，在 N-衬底上先制作器件的 正面结构， 然后从衬底背面用研磨、 腐蚀等方法将衬底减薄至所需的厚度， 再 采用离子注入工艺形成背面的 N+緩沖层和 P+集电区， 接着再采用光刻工艺， 刻蚀出 N+短路区窗口， 再进行一次离子注入在緩沖层内形成 N+短路区。
可见， 在 N+緩沖层形成之后， 形成 P+集电区和 N+短路区的过程都是在 N+ 緩沖层的基础上进行的， 加工损伤和难免的晶体缺陷会造成 N+緩沖层阻止场 强能力的失效， 导致器件性能变坏。
而本申请实施例改变了现有的 RC-IGBT的制作方法，在形成緩沖层之后， 在所述緩沖层基础上进行的步骤只有形成轻掺杂层和短路区的过程， 因此，相 对于现有技术， 本申请实施例减少了緩沖层的加工损伤和晶体缺陷，提高了緩 沖层的质量， 进而提升了所述 RC-IGBT的性能。 此外， 现有技术中， 对于中低压 RC-IGBT, 在形成器件的正面结构之后， 背面结构的操作包括： 需要减薄 N-衬底， 然后再形成 N+緩沖层、 P+集电区和 N+短路区， 在较薄的器件基础上进行操作的时候， 器件的碎片率较高。
而本申请实施例中， 背面结构的操作包括： 减薄重掺杂衬底， 然后再形成 短路区窗口、 短路区。 相较于现有技术而言， 筒化了背面结构的操作步骤， 相 应的降低了器件制作过程中的碎片率,
本申请另一实施例公开了一种 N型衬底的 RC-IGBT的制作方法， 该方法 包括： 提供一重掺杂衬底， 所述重掺杂衬底为 N型重掺杂衬底， 本实施例提供 的重掺杂衬底较厚， 以避免后续制作过程中由于基底太薄而出现碎片的情况。 采用外延工艺在所述重掺杂衬底表面上形成緩沖层， 所述緩沖层为 N型 重掺杂的緩沖层， 且所述緩沖层的厚度大于 Ιμηι, 优选的， 所述緩沖层的厚度 为 15μηι。 所述緩沖层的峰值浓度为 Iel4/cm3~3el6/cm3, 优选为 1.8el4/cm3。 本实施例是在重掺杂衬底表面上形成的緩沖层，所以所述緩沖层的厚度不再受 离子注入工艺的限制， 可以大于 1μηι。 相应的， 与现有技术相比， 所述緩沖层 的厚度可以控制在一个较大的范围内。且采用外延工艺在所述重掺杂衬底表面 上形成緩沖层的方法不需要退火激活緩沖层内的掺杂离子，因此可以精确控制 离子掺杂的峰值浓度为 Iel4/cm3~3el6/cm3。通过对 RC-IGBT的制作方法和制 作工艺的调整， 可以进一步的优化 RC-IGBT的通态压降和导通损耗， 改善所 述 RC-IGBT的性能。 在所述緩沖层表面形成轻掺杂层， 并在所述轻掺杂层上形成 RC-IGBT的 正面结构。 具体的， 采用外延工艺在所述緩沖层表面形成轻掺杂层， 所述轻掺杂层为 N型轻掺杂层， 且所述轻掺杂层的厚度为 70μηι~300μηι, 优选为 150μηι。 在所 述轻掺杂层上形成 RC-IGBT的正面结构的过程 (以正面为沟槽栅的 RC-IGBT 为例）， 包括： 采用光刻和干法刻蚀工艺在所述轻掺杂层表面内形成沟槽，采用热氧化工 艺在所述沟槽底部和侧壁表面形成第一栅介质层，所述第一栅介质层的材料可 以为二氧化硅。 在所述沟槽内淀积多晶硅， 形成沟槽栅， 且所述沟槽栅填满所 述沟槽。采用离子注入工艺和退火工艺在所述轻掺杂层表面内形成阱区， 所述 阱区为 P 型轻掺杂阱区。 采用离子注入工艺和退火工艺在所述阱区内形成源 区， 所述源区为 N型重掺杂源区。 采用氧化工艺在所述沟槽栅表面形成第二 栅介质层， 同时会在轻掺杂层表面形成氧化层。采用光刻工艺和刻蚀工艺去掉 位于所述轻掺杂层表面上的氧化层， 露出部分阱区和源区。 在所述阱区、 源区 和第二栅介质层表面上形成源极， 所述源极与所述阱区和源区电接触， 完成所 述 RC-IGBT正面结构的制作。 在完成所述 RC-IGBT正面结构的制作之后， 还可以对所述源极进行钝化 处理。 采用化学机械研磨工艺减薄所述重掺杂衬底，减薄后的重掺杂衬底厚度为 0.5μηι~1μηι, 优选为 0.8μηι。 此外， 还可以采用机械研磨或化学腐蚀工艺减薄 所述重掺杂衬底。
之后， 在所述重掺杂衬底内形成集电区窗口， 露出所述緩沖层， 并在所述 緩沖层内形成集电区。 所述集电区为 Ρ型重掺杂区， 优选的， 所述集电区的掺 杂离子优选为硼离子。 具体的， 在所述重掺杂衬底背面形成光刻胶层， 利用具有集电区窗口图形 的掩膜版对所述光刻胶层进行曝光， 在所述光刻胶层上形成集电区窗口图案， 采用显影工艺，去掉集电区窗口图案处的光刻胶，在所述光刻胶层上形成集电 区窗口图形， 以具有集电区窗口图形的光刻胶层为掩模，对所述重掺杂衬底进 行刻蚀，形成集电区窗口，并露出緩沖层，未被刻蚀掉的重掺杂衬底为短路区， 之后， 以具有集电区窗口图形的光刻胶层为掩模， 采用离子注入工艺， 在所述 緩沖层内形成集电区，去除光刻胶层，并进行退火，激活集电区内的掺杂离子。 所述集电区为 P型重掺杂集电区，优选的，所述集电区的掺杂离子优选为硼离 子。
在所述集电区表面和短路区表面形成集电极，所述集电极与所述集电区和 短路区电接触。
本申请又一实施例公开了一种 RC-IGBT, 如图 2所示， 包括： 集电区 101 , 所述集电区 101为一重掺杂区， 具体为一 P型重掺杂区， 且 所述集电区 101的厚度为 0.5μηι~1μηι; 緩沖层 102, 所述緩沖层 102位于所述集电区 101的表面上， 为 Ν型重掺 杂。 且所述緩沖层的厚度大于 Ιμηι, 优选的， 所述緩沖层 102 的厚度为 5μηι~30μηι。 所述緩沖层的峰值浓度为 Iel4/cm3~3el6/cm3 , 优选为 1.5 e 14/cm3~2 · 5 e 16/cm3。 需要说明的是，所述緩沖层 102的厚度和掺杂浓度还可以根据器件耐压水 平的不同而调整， 在此不做具体限定。 所述 RC-IGBT, 还包括： 轻掺杂层 103 , 所述轻掺杂层 103位于所述緩沖层 102表面上， 为 N型轻 掺杂， 且所述轻掺杂层 103的厚度为 70μηι~300μηι。
RC-IGBT的正面结构， 所述 RC-IGBT的正面结构位于所述轻掺杂层 103 上， 本实施例以平面栅为例， 所述 RC-IGBT的正面结构包括： 位于所述轻掺杂层 103表面内的阱区 1031 , 位于所述阱区 1031表面内的 源区 1032,且所述源区 1032的表面、 阱区 1031的表面均与所述轻掺杂层 103 的表面齐平； 位于所述轻掺杂层 103表面上、 阱区 1031表面上和源区 1032 表面上的第一栅介质层 1033 , 所述第一栅介质层 1033并未完全覆盖住所述源 区 1032和阱区 1031 ; 位于所述第一栅介质层 1033表面上的平面栅 1034, 所 述平面栅 1034的制作材料优选为多晶硅；包覆在所述平面栅 1034表面和侧壁 的第二栅介质层 1035; 位于所述第二栅介质层 1035表面上、 源区 1032表面 上和阱区 1031表面上的源极 1036, 所述源极 1036为金属电极， 且所述源极 1036表面上还可以设置有钝化层， 以对所述源极 1036起到保护的作用。 所述 RC-IGBT的正面结构中， 所述阱区 1031为 P型轻掺杂， 所述源区 1032为 N型重掺杂。 短路区 104, 所述短路区 104深入所述緩沖层 102表面内， 且所述短路区
104的背面与所述緩沖层 102的背面齐平， 所述短路区为重掺杂区， 具体为 N 型重掺杂。 集电极 105 , 所述集电极 105位于所述集电区 101和短路区 104的背面， 所述集电极 105为金属电极。
本实施例所公开的 RC-IGBT中， 由于所述緩沖层 102的厚度大于 1 μηι , 与现有技术相比， 所述緩沖层 102的厚度较厚，且采用外延工艺在所述重掺杂 衬底表面上形成緩沖层的方法不需要退火激活緩沖层内的掺杂离子，因此可以 精确控制离子掺杂的峰值浓度为 Iel4/cm3~3el6/cm3。通过对 RC-IGBT的制作 方法和制作工艺的调整，可以进一步的优化 RC-IGBT的通态压降和导通损耗， 改善所述 RC-IGBT的性能。
本申请又一实施例公开了另一种 RC-IGBT, 如图 3所示， 包括： 短路区 201 , 所述短路区 201为一重掺杂区， 具体为一 N型重掺杂区， 且 所述短路区 201的厚度为 0.5μηι~1μηι; 緩沖层 202, 所述緩沖层 202位于所述短路区 201的表面上， 为 Ν型重掺 杂。 且所述緩沖层的厚度大于 Ιμηι, 优选的， 所述緩沖层 202 的厚度为 5μηι~30μηι。 所述緩沖层的峰值浓度为 Iel4/cm3~3el6/cm3 , 优选为 1.5 e 14/cm3~2 · 5 e 16/cm3。 所述 RC-IGBT, 还包括： 轻掺杂层 203 , 所述轻掺杂层 203位于所述緩沖层 202表面上， 为 N型轻 掺杂， 且所述轻掺杂层 203的厚度为 70μηι~300μηι。
RC-IGBT的正面结构， 所述 RC-IGBT的正面结构位于所述轻掺杂层 203 上， 本实施例以沟槽栅为例， 所述 RC-IGBT的正面结构包括： 位于所述轻掺杂层 203表面内的阱区 2031 , 位于所述阱区 2031表面内的 源区 2032, 且所述源区 2032的表面、 阱区 2031的表面齐平； 形成在所述轻 掺杂层 203 内的沟槽， 位于所述沟槽底部和侧壁的第一栅介质层 2033; 填充 在所述沟槽内、 且位于所述第一栅介质层 1033表面上的沟槽栅 2034, 所述沟 槽栅 2034的制作材料优选为多晶硅；包覆在所述沟槽栅 2034表面的第二栅介 质层 2035;位于所述第二栅介质层 2035表面上、源区 2032表面上和阱区 2031 表面上的源极 2036, 所述源极 2036为金属电极， 且所述源极 2036表面上还 可以设置有钝化层， 以对所述源极 2036起到保护的作用。 所述 RC-IGBT的正面结构中， 所述阱区 2031为 P型轻掺杂， 所述源区
2032为 N型重掺杂。 集电区 204, 所述集电区 204深入所述緩沖层 202表面内， 且所述集电区 204的背面与所述緩沖层 202的背面齐平， 所述集电区 204为重掺杂区， 具体 为 P型重掺杂。 集电极 205 , 所述集电极 205位于所述短路区 201和集电区 204的背面， 所述集电极 205为金属电极。
本实施例所公开的 RC-IGBT中， 由于所述緩沖层 202的厚度大于 1 μηι , 与现有技术相比， 所述緩沖层 202的厚度较厚，且采用外延工艺在所述重掺杂 衬底表面上形成緩沖层的方法不需要退火激活緩沖层内的掺杂离子，因此可以 精确控制离子掺杂的峰值浓度为 Iel4/cm3~3el6/cm3。通过对 RC-IGBT的制作 方法和制作工艺的调整，可以进一步的优化 RC-IGBT的通态压降和导通损耗， 改善所述 RC-IGBT的性能。 需要说明的是， 所述 RC-IGBT中的掺杂类型可以为： 所述集电区为 P型重掺杂，所述緩沖层为 N型重掺杂，所述轻掺杂层为 N 型轻掺杂， 所述短路区为 N型重掺杂， 所述阱区为 P型轻掺杂， 所述源区为 N型重掺杂。 本申请本实施例中 RC-IGBT的正面结构还可以为其他类型的正面结构， 在此不再赘述。 只要符合本发明实施例的主体思想， 均在本发明实施例的保护 范围之内。
以上所述实施例，仅是本发明的较佳实施例而已， 并非对本发明作任何形 式上的限制。 虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。任何熟 悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭 示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为 等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本发 明的技术实质对以上实施例所做的任何筒单修改、等同变化及修饰， 均仍属于 本发明技术方案保护的范围内。

Claims

权 利 要 求
1、 一种 RC-IGBT的制作方法， 其特征在于， 包括： 提供一重掺杂衬底；
在所述重掺杂衬底表面上形成緩沖层，所述緩沖层的厚度大于 Ιμηι,峰值 浓度为 Iel4/cm3~3el6/cm3; 减薄所述重掺杂衬底。
2、 根据权利要求 1 所述方法， 其特征在于， 所述緩沖层的厚度为 5μΓη~30μηι。
3、 根据权利要求 2所述方法， 其特征在于， 形成緩沖层所采用的工艺为 外延工艺。
4、 根据权利要求 1所述方法， 其特征在于， 在所述重掺杂衬底表面形成 緩沖层之后， 减薄所述重掺杂衬底之前， 还包括： 在所述緩沖层表面形成轻掺杂层；
在所述轻掺杂层上形成 RC-IGBT的正面结构。
5、 根据权利要求 4所述方法， 其特征在于， 形成轻掺杂层所采用的工艺 为外延工艺。
6、 根据权利要求 4 所述方法， 其特征在于， 所述轻掺杂层的厚度为
Figure imgf000019_0001
7、 根据权利要求 1所述方法， 其特征在于， 所述减薄所述重掺杂衬底的 过程， 包括： 采用化学机械研磨工艺减薄所述重掺杂衬底，减薄后的重掺杂衬底厚度为 0·5μΓη~1μηι。
8、 根据权利要求 1所述方法， 其特征在于， 所述减薄所述重掺杂衬底后， 还包括： 在所述重掺杂衬底内形成短路区窗口， 露出所述緩沖层， 并在所述緩沖层 内形成短路区。
9、 根据权利要求 8所述方法， 其特征在于， 在所述重掺杂衬底内形成短 路区窗口， 露出所述緩沖层， 并在所述緩沖层内形成短路区的过程， 包括： 在所述重掺杂衬底背面形成光刻胶层； 利用具有短路区窗口图形的掩膜版对所述光刻胶层进行曝光； 采用显影工艺， 在所述光刻胶层上形成短路区窗口图形； 以具有短路区窗口图形的光刻胶层为掩模， 对所述重掺杂衬底进行刻蚀， 形成短路区窗口， 并露出緩沖层， 未被刻蚀掉的重掺杂衬底为集电区；
以具有短路区窗口图形的光刻胶层为掩模， 采用离子注入工艺，在所述緩 沖层内形成短路区； 去除光刻胶层， 进行退火。
10、 根据权利要求 1所述方法， 其特征在于， 所述减薄所述重掺杂衬底之 后， 还包括： 在所述重掺杂衬底内形成集电区窗口， 露出所述緩沖层， 并在所述緩沖层 内形成集电区。
11、 根据权利要求 10所述方法， 其特征在于， 在所述重掺杂衬底内形成 集电区窗口， 露出所述緩沖层， 并在所述緩沖层内形成集电区的过程， 包括： 在所述重掺杂衬底背面形成光刻胶层； 利用具有集电区窗口图形的掩膜版对所述光刻胶层进行曝光；
采用显影工艺， 在所述光刻胶层上形成集电区窗口图形； 以具有集电区窗口图形的光刻胶层为掩模， 对所述重掺杂衬底进行刻蚀， 形成集电区窗口， 并露出緩沖层， 未被刻蚀掉的重掺杂衬底为短路区；
以具有集电区窗口图形的光刻胶层为掩模， 采用离子注入工艺，在所述緩 沖层内形成集电区；
去除光刻胶层， 进行退火。
12、 根据权利要求 9或 11所述方法， 其特征在于， 还包括： 在所述集电区表面和短路区表面形成集电极。
13、根据权利要求 1所述方法， 其特征在于， 所述重掺杂衬底为 P型重掺 杂， 所述緩沖层为 N型重掺杂， 所述轻掺杂层为 N型轻掺杂， 所述短路区为 N型重掺杂。
14、 根据权利要求 1所述方法， 其特征在于， 所述重掺杂衬底为 N型重 掺杂， 所述緩沖层为 N型重掺杂， 所述轻掺杂层为 N型轻掺杂， 所述短路区 为 N型重掺杂。
15、 一种 RC-IGBT, 其特征在于， 包括： 集电区， 所述集电区为一重掺杂区； 緩沖层， 所述緩沖层位于所述集电区的表面上， 且所述緩沖层的厚度大于 Ιμηι, 峰值浓度为 Iel4/cm3~3el6/cm3。
16、 根据权利要求 15所述 RC-IGBT, 其特征在于， 还包括： 轻掺杂层， 所述轻掺杂层位于所述緩沖层表面上； RC-IGBT的正面结构， 所述 RC-IGBT的正面结构位于所述轻掺杂层上； 短路区， 所述短路区深入所述緩沖层表面内，且所述短路区的背面与所述 緩沖层的背面齐平；
集电极， 所述集电极位于所述集电区和短路区的背面。
17、 根据权利要求 16所述 RC-IGBT, 其特征在于， 所述集电区的厚度为 0.5μηι~1μηι, 所述轻掺杂层的厚度为 70μηι~300μηι。
18、 一种 RC-IGBT, 其特征在于， 包括： 短路区， 所述短路区为一重掺杂区； 緩沖层， 所述緩沖层位于所述短路区的表面上， 且所述緩沖层的厚度大于 Ιμηι, 峰值浓度为 Iel4/cm3~3el6/cm3。
19、 根据权利要求 18所述 RC-IGBT, 其特征在于， 还包括： 轻掺杂层， 所述轻掺杂层位于所述緩沖层表面上；
RC-IGBT的正面结构， 所述 RC-IGBT的正面结构位于所述轻掺杂层上； 集电区， 所述集电区深入所述緩沖层表面内，且所述集电区的背面与所述 緩沖层的背面齐平； 集电极， 所述集电极位于所述集电区和短路区的背面。
20、 根据权利要求 17所述 RC-IGBT, 其特征在于， 所述短路区的厚度为 0.5μηι~1μηι, 所述轻掺杂层的厚度为 70μηι~300μηι。
21、 根据权利要求 15或 18所述 RC-IGBT, 其特征在于， 所述緩沖层的 厚度为 5μηι~30μηι„
22、根据权利要求 16或 19所述 RC-IGBT, 其特征在于， 所述集电区为 P 型重掺杂， 所述短路区为 N型重掺杂， 所述緩沖层为 N型重掺杂， 所述轻掺 杂层为 N型轻掺杂。
PCT/CN2012/086018 2012-12-06 2012-12-06 Rc-igbt及其制作方法 Ceased WO2014086016A1 (zh)

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Publication number Priority date Publication date Assignee Title
JP2004207567A (ja) * 2002-12-26 2004-07-22 Shindengen Electric Mfg Co Ltd 半導体装置の製造方法
US20070290237A1 (en) * 2006-06-16 2007-12-20 Kabushiki Kaisha Toshiba Insulated gate bipolar transistor and method for manufacturing same
CN101877352A (zh) * 2009-04-29 2010-11-03 Abb技术有限公司 反向导通半导体器件
CN102412288A (zh) * 2010-09-21 2012-04-11 株式会社东芝 逆导型绝缘栅双极晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207567A (ja) * 2002-12-26 2004-07-22 Shindengen Electric Mfg Co Ltd 半導体装置の製造方法
US20070290237A1 (en) * 2006-06-16 2007-12-20 Kabushiki Kaisha Toshiba Insulated gate bipolar transistor and method for manufacturing same
CN101877352A (zh) * 2009-04-29 2010-11-03 Abb技术有限公司 反向导通半导体器件
CN102412288A (zh) * 2010-09-21 2012-04-11 株式会社东芝 逆导型绝缘栅双极晶体管

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