WO2014067344A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2014067344A1
WO2014067344A1 PCT/CN2013/082918 CN2013082918W WO2014067344A1 WO 2014067344 A1 WO2014067344 A1 WO 2014067344A1 CN 2013082918 W CN2013082918 W CN 2013082918W WO 2014067344 A1 WO2014067344 A1 WO 2014067344A1
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Prior art keywords
field limiting
limiting ring
ring
semiconductor device
field
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PCT/CN2013/082918
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French (fr)
Chinese (zh)
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王者伟
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无锡华润上华科技有限公司
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Publication of WO2014067344A1 publication Critical patent/WO2014067344A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the invention belongs to the technical field of semiconductors, and in particular to a semiconductor device.
  • High voltage power semiconductor devices such as Trench MOS (trench semiconductor field effect transistor), VDMOS, IGBT, etc., due to its high operating frequency, fast switching speed, high control efficiency, etc., are more and more widely used in the field of power electronics.
  • the blocking capability of high-voltage power semiconductor devices is an important indicator of the development level.
  • the breakdown voltage can be ranged from 25V to 6000V.
  • the semiconductor structure is shallow and the junction edge is curved.
  • the device's withstand voltage capability is reduced, the withstand voltage stability is poor, the safe working area of the device is small, and the device is easily damaged.
  • a field limit ring at the edge of the device is especially suitable for devices with vertical current flow, such as Trench MOS and VDMOS, etc., it has large current handling capability and large current gain.
  • the field limiting ring structure can effectively suppress the electric field concentration caused by the curvature effect of the main junction edge of the device, thereby improving the withstand voltage, and is compatible with the low voltage integrated circuit process, and is convenient for promotion in power integrated circuits and discrete high voltage devices, and is placed in the depletion region.
  • the edge-limited ring can act as a high-voltage detector that drives the protection circuitry in the SPIC, making the SPIC more sensitive.
  • FIG. 1 is a top view of a prior art semiconductor device 10 with a GTE ring 14, a field limiting ring 11, a field limiting ring 12, a field limiting ring 33, and a cut-off ring 15 disposed around the edge of the substrate 16, wherein
  • the width of the GTE ring 14 is 12 ⁇ m
  • the width of the field limiting ring 11, the field limiting ring 12, and the field limiting ring 13 are both 5 ⁇ m
  • the width of the cut ring 15 is 7 ⁇ m
  • the GTE ring 14 and the field ring 11 are
  • the pitch is 24 ⁇ m
  • the spacing between the field limiting ring 11 and the field limiting ring 12 is 17 ⁇ m
  • the spacing between the field limiting ring 12 and the field limiting ring 13 is 18 ⁇ m
  • the spacing between the field limiting ring 13 and the cut-off ring 15 is 18 ⁇ m. It can be seen from the measurement that the breakdown voltage of the semiconductor device obtained by this parameter is 6
  • the technical problem to be solved by the present invention is to provide a semiconductor device which has a high withstand voltage capability.
  • the present invention provides the following technical solutions:
  • a semiconductor device comprising a substrate and a field limiting ring disposed around an edge of the substrate, the field limiting ring comprising a field limiting ring 1, a field limiting ring 2 and a field limiting ring 3, wherein the field limiting ring 2 is located Between the field limiting ring 1 and the field limiting ring 3, wherein the spacing between the field limiting ring 1 and the field limiting ring 2 is 19-21 ⁇ m, and the spacing between the field limiting ring 2 and the field limiting ring 3 is 20 ⁇ 23 ⁇ m.
  • the semiconductor device further includes a GTE ring, the field limiting ring 1 is located between the GTE ring and the field limiting ring 2, and the GTE ring has a width of 12 ⁇ m.
  • the distance between the GTE ring and the field limiting ring is 20-30 ⁇ m.
  • the semiconductor device further includes a cut-off ring, the field limiting ring 3 being located between the cut-off ring and the field limiting ring 2, the cut-off ring having a width of 7 ⁇ m.
  • the distance between the cut-off ring and the field limiting ring 3 is 20-28 ⁇ m.
  • the field limiting ring 1 has a width of 5 ⁇ m.
  • the width of the field limiting ring 2 is 5 ⁇ m.
  • the width of the field limiting ring 3 is 5 ⁇ m.
  • the semiconductor device is a DMOS.
  • the present invention has the beneficial effects of improving the withstand voltage capability of the semiconductor device by changing the spacing between the field limiting ring 1, the field limiting ring 2 and the field limiting ring 3.
  • FIG. 1 is a schematic structural view of a semiconductor device in the prior art
  • FIG. 2 is a schematic structural view of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural view of a semiconductor device according to Embodiment 2 of the present invention.
  • the semiconductor device obtained in the prior art has a poor withstand voltage capability.
  • the inventors have found through a large number of experiments that when the spacing between the field limiting rings is changed to a certain value, the withstand voltage capability of the device can be significantly improved, in particular, the spacing between the field limiting ring 1 and the field limiting ring 2 is increased. The spacing between the field limit ring 2 and the field limit ring 3.
  • embodiments of the present invention provide a semiconductor device to solve the above problems.
  • embodiments of the present invention provide a semiconductor device to solve the above problems.
  • FIG. 2 is a schematic structural view of a semiconductor device according to Embodiment 1 of the present invention.
  • the semiconductor device 20 includes:
  • the substrate in this embodiment may include a semiconductor element such as single crystal, polycrystalline or amorphous silicon or silicon germanium (SiGe), and may also include a mixed semiconductor structure, such as silicon carbide, germanium. Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof; may also be silicon-on-insulator (SOI). Further, the semiconductor substrate may further include other materials such as an epitaxial layer or a buried layer multilayer structure. Although a few examples of materials from which a substrate can be formed are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.
  • a GTE ring 24, a field limiting ring 21, a field limiting ring 22, a field limiting ring 33, and a cut-off ring 25 are disposed around the edge of the substrate 26.
  • the width of the GTE ring 24 is 12 ⁇ m
  • the width of the field limiting ring 21, the field limiting ring 22 and the field limiting ring 23 is 5 ⁇ m
  • the width of the cut ring 25 is 7 ⁇ m
  • the spacing between the field limiting ring 21 and the field limiting ring 22 is 21 ⁇ m
  • the spacing between the field limiting ring 22 and the field limiting ring 23 is 23 ⁇ m
  • the spacing between the field limiting ring 23 and the cut-off ring 25 is 28 ⁇ m. .
  • the breakdown voltage of the semiconductor device 20 is 720 V, which is a large improvement compared with 683 V in the prior art.
  • FIG. 3 is a schematic structural view of a semiconductor device according to Embodiment 2 of the present invention.
  • the semiconductor device 30 includes:
  • the substrate in this embodiment may include a semiconductor element such as single crystal, polycrystalline or amorphous silicon or silicon germanium (SiGe), and may also include a mixed semiconductor structure, such as silicon carbide, germanium. Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof; may also be silicon-on-insulator (SOI). Further, the semiconductor substrate may further include other materials such as an epitaxial layer or a buried layer multilayer structure. Although a few examples of materials from which a substrate can be formed are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.
  • a GTE ring 34, a field limiting ring 31, a field limiting ring 32, a field limiting ring 33, and a cut-off ring 35 are disposed around the edge of the substrate 36.
  • the width of the GTE ring 34 is 12 ⁇ m
  • the width of the field limiting ring 31, the field limiting ring 32 and the field limiting ring 33 are both 5 ⁇ m
  • the width of the cut-off ring 35 is 7 ⁇ m
  • the spacing is 26 ⁇ m
  • the spacing between the field limiting ring 31 and the field limiting ring 32 is 19 ⁇ m
  • the spacing between the field limiting ring 32 and the field limiting ring 33 is 20 ⁇ m
  • the spacing between the field limiting ring 33 and the cutoff ring 35 is 20 ⁇ m. .
  • the breakdown voltage of the semiconductor device 30 is 700 V, which is a large improvement compared with 683 V in the prior art.
  • the present invention improves the withstand voltage capability of the semiconductor device by changing the spacing between the field limiting ring 1, the field limiting ring 2 and the field limiting ring 3.
  • the structure of this field limiting ring is especially suitable for devices with vertical current flow, such as Trench MOS and VDMOS, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device comprises a substrate (26) and field limiting rings (21, 22, 23) disposed around an edge of the substrate (26). The field limiting rings (21, 22, 23) comprises a first field limiting ring (21), a second field limiting ring (22), and a third field limiting ring (23). The second field limiting ring (22) are located between the first field limiting ring (21), and the third field limiting ring (23), and a distance between the second field limiting ring (22) and the third field limiting ring (23) is 20-23μm. By changing the distance between the first field limiting ring (21), the second field limiting ring (22) and the third field limiting ring (23), the voltage resistance capability of the semiconductor device is improved.

Description

半导体器件Semiconductor device
【技术领域】[Technical Field]
本发明属于半导体技术领域，尤其涉及一种半导体器件。  The invention belongs to the technical field of semiconductors, and in particular to a semiconductor device.
【背景技术】【Background technique】
高压功率半导体器件如Trench MOS（沟槽半导体场效应管）、VDMOS、IGBT等，由于其工作频率高、开关速度快、控制效率高等特点，在电力电子领域得到越来越广泛的应用。高压功率半导体器件的阻断能力是衡量发展水平的一个重要标志，依据应用击穿电压的范围可以从25V-6000V，但是由于现代半导体工艺采用平面型终端结构，一般结深较浅、结边缘弯曲，使得器件的耐压能力降低，耐压稳定性差，器件的安全工作区域较小，器件容易被破坏。High voltage power semiconductor devices such as Trench MOS (trench semiconductor field effect transistor), VDMOS, IGBT, etc., due to its high operating frequency, fast switching speed, high control efficiency, etc., are more and more widely used in the field of power electronics. The blocking capability of high-voltage power semiconductor devices is an important indicator of the development level. The breakdown voltage can be ranged from 25V to 6000V. However, due to the modern terminal structure, the semiconductor structure is shallow and the junction edge is curved. The device's withstand voltage capability is reduced, the withstand voltage stability is poor, the safe working area of the device is small, and the device is easily damaged.
为了改善高压半导体器件的耐压需求，通常通过改变外延浓度和厚度来实现不同的耐压需求，但实际生产中发现，当半导体器件的击穿电压提高到680V以后，再降低外延浓度或提高外延厚度，无法提高其击穿电压。In order to improve the withstand voltage requirements of high-voltage semiconductor devices, different withstand voltage requirements are usually achieved by changing the epitaxial concentration and thickness, but in actual production, it is found that when the breakdown voltage of the semiconductor device is increased to 680V, the epitaxial concentration is lowered or the epitaxial thickness is increased. Thickness cannot increase its breakdown voltage.
目前，常用的提高器件耐压能力和稳定性的方法还包括在器件边缘设置场限环（Field Limiting Ring，简称FLR）的方式，这种方法特别适用于电流垂直流向的器件，如Trench MOS和VDMOS等，它具有大的电流处理能力和大的电流增益。场限环结构可有效抑制器件主结边缘曲率效应引起的电场集中，从而提高耐压，并且与低压集成电路工艺兼容，便于在功率集成电路和分立高压器件中推广，另外，放置在耗尽区边缘的场限环可以作为高压探测器，驱动SPIC中的保护电路，使SPIC更加灵敏。At present, commonly used methods to improve the withstand voltage capability and stability of the device include setting a field limit ring at the edge of the device. Ring, referred to as FLR), this method is especially suitable for devices with vertical current flow, such as Trench MOS and VDMOS, etc., it has large current handling capability and large current gain. The field limiting ring structure can effectively suppress the electric field concentration caused by the curvature effect of the main junction edge of the device, thereby improving the withstand voltage, and is compatible with the low voltage integrated circuit process, and is convenient for promotion in power integrated circuits and discrete high voltage devices, and is placed in the depletion region. The edge-limited ring can act as a high-voltage detector that drives the protection circuitry in the SPIC, making the SPIC more sensitive.
图1所示为现有技术中半导体器件10的俯视图，GTE环14、场限环一11、场限环二12、场限环三13以及截止环15环绕设于衬底16的边缘，其中，GTE环14的宽度为12μm，场限环一11、场限环二12和场限环三13的宽度均为5μm，截止环15的宽度为7μm，GTE环14与场限环一11的间距为24μm，场限环一11与场限环二12的间距为17μm，场限环二12与场限环三13的间距为18μm，场限环三13与截止环15的间距为18μm。经测量可知，由该参数所获得的半导体器件的击穿电压为683V，耐压较小。1 is a top view of a prior art semiconductor device 10 with a GTE ring 14, a field limiting ring 11, a field limiting ring 12, a field limiting ring 33, and a cut-off ring 15 disposed around the edge of the substrate 16, wherein The width of the GTE ring 14 is 12 μm, the width of the field limiting ring 11, the field limiting ring 12, and the field limiting ring 13 are both 5 μm, the width of the cut ring 15 is 7 μm, and the GTE ring 14 and the field ring 11 are The pitch is 24 μm, the spacing between the field limiting ring 11 and the field limiting ring 12 is 17 μm, the spacing between the field limiting ring 12 and the field limiting ring 13 is 18 μm, and the spacing between the field limiting ring 13 and the cut-off ring 15 is 18 μm. It can be seen from the measurement that the breakdown voltage of the semiconductor device obtained by this parameter is 683 V, and the withstand voltage is small.
【发明内容】[Summary of the Invention]
本发明解决的技术问题在于提供一种半导体器件，该半导体器件具有较高的耐压能力。The technical problem to be solved by the present invention is to provide a semiconductor device which has a high withstand voltage capability.
为实现上述目的，本发明提供如下技术方案：To achieve the above object, the present invention provides the following technical solutions:
一种半导体器件，包括衬底以及环绕该衬底边缘设置的场限环，所述场限环包括场限环一、场限环二和场限环三，所述场限环二位于所述场限环一和场限环三之间，其中，所述场限环一和场限环二之间的间距为19~21μm，所述场限环二和场限环三之间的间距为20~23μm。A semiconductor device comprising a substrate and a field limiting ring disposed around an edge of the substrate, the field limiting ring comprising a field limiting ring 1, a field limiting ring 2 and a field limiting ring 3, wherein the field limiting ring 2 is located Between the field limiting ring 1 and the field limiting ring 3, wherein the spacing between the field limiting ring 1 and the field limiting ring 2 is 19-21 μm, and the spacing between the field limiting ring 2 and the field limiting ring 3 is 20~23μm.
作为本发明的进一步改进，所述半导体器件还包括GTE环，所述场限环一位于所述GTE环和场限环二之间，所述GTE环的宽度为12μm。As a further improvement of the present invention, the semiconductor device further includes a GTE ring, the field limiting ring 1 is located between the GTE ring and the field limiting ring 2, and the GTE ring has a width of 12 μm.
优选的，所述GTE环与场限环一之间的间距为20~30μm。Preferably, the distance between the GTE ring and the field limiting ring is 20-30 μm.
作为本发明的进一步改进，所述半导体器件还包括截止环，所述场限环三位于所述截止环和场限环二之间，所述截止环的宽度为7μm。As a further improvement of the present invention, the semiconductor device further includes a cut-off ring, the field limiting ring 3 being located between the cut-off ring and the field limiting ring 2, the cut-off ring having a width of 7 μm.
优选的，所述截止环与场限环三之间的间距为20~28μm。Preferably, the distance between the cut-off ring and the field limiting ring 3 is 20-28 μm.
作为本发明的进一步改进，所述场限环一的宽度为5μm。As a further improvement of the present invention, the field limiting ring 1 has a width of 5 μm.
作为本发明的进一步改进，所述场限环二的宽度为5μm。As a further improvement of the present invention, the width of the field limiting ring 2 is 5 μm.
作为本发明的进一步改进，所述场限环三的宽度为5μm。As a further improvement of the present invention, the width of the field limiting ring 3 is 5 μm.
作为本发明的进一步改进，所述半导体器件为DMOS。As a further improvement of the present invention, the semiconductor device is a DMOS.
与现有技术相比，本发明的有益效果在于：通过改变场限环一、场限环二和场限环三之间的间距，以提高半导体器件的耐压能力。Compared with the prior art, the present invention has the beneficial effects of improving the withstand voltage capability of the semiconductor device by changing the spacing between the field limiting ring 1, the field limiting ring 2 and the field limiting ring 3.
【附图说明】[Description of the Drawings]
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings to be used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description are only It is a few embodiments described in the present application, and other drawings can be obtained from those skilled in the art without any creative work.
图1所示为现有技术中半导体器件的结构示意图；1 is a schematic structural view of a semiconductor device in the prior art;
图2所示为本发明实施例一中半导体器件的结构示意图；2 is a schematic structural view of a semiconductor device according to Embodiment 1 of the present invention;
图3所示为本发明实施例二中半导体器件的结构示意图。FIG. 3 is a schematic structural view of a semiconductor device according to Embodiment 2 of the present invention.
【具体实施方式】 【detailed description】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。The above described objects, features and advantages of the present invention will become more apparent from the aspects of the appended claims.
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。In the following description, numerous specific details are set forth in order to provide a full understanding of the present invention, but the invention may be practiced in other ways than those described herein, and those skilled in the art can do without departing from the scope of the invention. The invention is not limited by the specific embodiments disclosed below.
正如背景技术部分所述，现有技术中所获得的半导体器件的耐压能力较差。发明人经过大量的实验发现，将场限环之间的间距改变为一定值的时候，可以显著提高器件的耐压能力，特别是增大场限环一和场限环二之间的间距以及场限环二和场限环三之间的间距。As described in the background section, the semiconductor device obtained in the prior art has a poor withstand voltage capability. The inventors have found through a large number of experiments that when the spacing between the field limiting rings is changed to a certain value, the withstand voltage capability of the device can be significantly improved, in particular, the spacing between the field limiting ring 1 and the field limiting ring 2 is increased. The spacing between the field limit ring 2 and the field limit ring 3.
基于上述原因，本发明实施例提供了一种半导体器件，以解决上述问题，具体描述参见以下实施例。For the above reasons, embodiments of the present invention provide a semiconductor device to solve the above problems. For details, refer to the following embodiments.
实施例一Embodiment 1
图2所示为本发明实施例一中半导体器件的结构示意图。FIG. 2 is a schematic structural view of a semiconductor device according to Embodiment 1 of the present invention.
参图2所示，该半导体器件20包括：As shown in FIG. 2, the semiconductor device 20 includes:
衬底26； Substrate 26;
需要说明的是，本实施例中的衬底可以包括半导体元素，例如单晶、多晶或非晶结构的硅或硅锗（SiGe），也可以包括混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合；也可以是绝缘体上硅（SOI）。此外，半导体衬底还可以包括其它的材料，例如外延层或掩埋层的多层结构。虽然在此描述了可以形成衬底的材料的几个示例，但是可以作为半导体衬底的任何材料均落入本发明的精神和范围。It should be noted that the substrate in this embodiment may include a semiconductor element such as single crystal, polycrystalline or amorphous silicon or silicon germanium (SiGe), and may also include a mixed semiconductor structure, such as silicon carbide, germanium. Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof; may also be silicon-on-insulator (SOI). Further, the semiconductor substrate may further include other materials such as an epitaxial layer or a buried layer multilayer structure. Although a few examples of materials from which a substrate can be formed are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.
环绕于衬底26边缘设置的GTE环24、场限环一21、场限环二22、场限环三23和截止环25。其中，GTE环24的宽度为12μm，场限环一21、场限环二22和场限环三23的宽度均为5μm，截止环25的宽度为7μm，GTE环24与场限环一21的间距为20μm，场限环一21与场限环二22的间距为21μm，场限环二22与场限环三23的间距为23μm，场限环三23与截止环25的间距为28μm。A GTE ring 24, a field limiting ring 21, a field limiting ring 22, a field limiting ring 33, and a cut-off ring 25 are disposed around the edge of the substrate 26. Wherein, the width of the GTE ring 24 is 12 μm, the width of the field limiting ring 21, the field limiting ring 22 and the field limiting ring 23 is 5 μm, the width of the cut ring 25 is 7 μm, and the GTE ring 24 and the field ring 21 The spacing between the field limiting ring 21 and the field limiting ring 22 is 21 μm, the spacing between the field limiting ring 22 and the field limiting ring 23 is 23 μm, and the spacing between the field limiting ring 23 and the cut-off ring 25 is 28 μm. .
经测量可知，半导体器件20的击穿电压为720V，相较于现有技术中的683V，实现了较大的提升。It can be seen from the measurement that the breakdown voltage of the semiconductor device 20 is 720 V, which is a large improvement compared with 683 V in the prior art.
实施例二Embodiment 2
图3所示为本发明实施例二中半导体器件的结构示意图。FIG. 3 is a schematic structural view of a semiconductor device according to Embodiment 2 of the present invention.
参图3所示，该半导体器件30包括：As shown in FIG. 3, the semiconductor device 30 includes:
衬底36； Substrate 36;
需要说明的是，本实施例中的衬底可以包括半导体元素，例如单晶、多晶或非晶结构的硅或硅锗（SiGe），也可以包括混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合；也可以是绝缘体上硅（SOI）。此外，半导体衬底还可以包括其它的材料，例如外延层或掩埋层的多层结构。虽然在此描述了可以形成衬底的材料的几个示例，但是可以作为半导体衬底的任何材料均落入本发明的精神和范围。It should be noted that the substrate in this embodiment may include a semiconductor element such as single crystal, polycrystalline or amorphous silicon or silicon germanium (SiGe), and may also include a mixed semiconductor structure, such as silicon carbide, germanium. Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof; may also be silicon-on-insulator (SOI). Further, the semiconductor substrate may further include other materials such as an epitaxial layer or a buried layer multilayer structure. Although a few examples of materials from which a substrate can be formed are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.
环绕于衬底36边缘设置的GTE环34、场限环一31、场限环二32、场限环三33和截止环35。其中，GTE环34的宽度为12μm，场限环一31、场限环二32和场限环三33的宽度均为5μm，截止环35的宽度为7μm，GTE环34与场限环一31的间距为26μm，场限环一31与场限环二32的间距为19μm，场限环二32与场限环三33的间距为20μm，场限环三33与截止环35的间距为20μm。A GTE ring 34, a field limiting ring 31, a field limiting ring 32, a field limiting ring 33, and a cut-off ring 35 are disposed around the edge of the substrate 36. The width of the GTE ring 34 is 12 μm, the width of the field limiting ring 31, the field limiting ring 32 and the field limiting ring 33 are both 5 μm, the width of the cut-off ring 35 is 7 μm, and the GTE ring 34 and the field limiting ring 31 The spacing is 26 μm, the spacing between the field limiting ring 31 and the field limiting ring 32 is 19 μm, the spacing between the field limiting ring 32 and the field limiting ring 33 is 20 μm, and the spacing between the field limiting ring 33 and the cutoff ring 35 is 20 μm. .
经测量可知，半导体器件30的击穿电压为700V，相较于现有技术中的683V，实现了较大的提升。It can be seen from the measurement that the breakdown voltage of the semiconductor device 30 is 700 V, which is a large improvement compared with 683 V in the prior art.
综上所述，本发明通过改变场限环一、场限环二和场限环三之间的间距，提高了半导体器件的耐压能力。这种场限环的结构特别适用于电流垂直流向的器件，如Trench MOS和VDMOS等In summary, the present invention improves the withstand voltage capability of the semiconductor device by changing the spacing between the field limiting ring 1, the field limiting ring 2 and the field limiting ring 3. The structure of this field limiting ring is especially suitable for devices with vertical current flow, such as Trench MOS and VDMOS, etc.
以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干改进和修饰，这些改进和修饰也落入本发明权利要求的保护范围内。The above description of the embodiments is merely to assist in understanding the method of the present invention and its core idea. It should be noted that those skilled in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the invention.
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but the scope of the invention is to be accorded

Claims (10)

  1. 一种半导体器件，包括衬底以及环绕该衬底边缘设置的场限环，所述场限环包括场限环一、场限环二和场限环三，所述场限环二位于所述场限环一和场限环三之间，其特征在于：所述场限环一和场限环二之间的间距为19~21μm，所述场限环二和场限环三之间的间距为20~23μm。A semiconductor device comprising a substrate and a field limiting ring disposed around an edge of the substrate, the field limiting ring comprising a field limiting ring 1, a field limiting ring 2 and a field limiting ring 3, wherein the field limiting ring 2 is located Between the field limiting ring 1 and the field limiting ring 3, the spacing between the field limiting ring 1 and the field limiting ring 2 is 19-21 μm, and between the field limiting ring 2 and the field limiting ring 3 The pitch is 20~23μm.
  2. 根据权利要求1所述的半导体器件，其特征在于：所述半导体器件还包括GTE环，所述场限环一位于所述GTE环和场限环二之间，所述GTE环的宽度为12μm。The semiconductor device according to claim 1, wherein said semiconductor device further comprises a GTE ring, said field limiting ring being located between said GTE ring and said field limiting ring 2, said GTE ring having a width of 12 μm .
  3. 根据权利要求2所述的半导体器件，其特征在于：所述GTE环与场限环一之间的间距为20~26μm。The semiconductor device according to claim 2, wherein a distance between the GTE ring and the field limiting ring 1 is 20 to 26 μm.
  4. 根据权利要求1所述的半导体器件，其特征在于：所述半导体器件还包括截止环，所述场限环三位于所述截止环和场限环二之间，所述截止环的宽度为7μm。The semiconductor device according to claim 1, wherein said semiconductor device further comprises a cut-off ring, said field limiting ring 3 being located between said cut-off ring and a field limiting ring 2, said cut-off ring having a width of 7 μm .
  5. 根据权利要求4所述的半导体器件，其特征在于：所述截止环与场限环三之间的间距为20~28μm。The semiconductor device according to claim 4, wherein a spacing between the cut-off ring and the field limiting ring 3 is 20 to 28 μm.
  6. 根据权利要求1所述的半导体器件，其特征在于：所述场限环一的宽度为5μm。The semiconductor device according to claim 1, wherein said field limiting ring 1 has a width of 5 μm.
  7. 根据权利要求1所述的半导体器件，其特征在于：所述场限环二的宽度为5μm。The semiconductor device according to claim 1, wherein said field limiting ring 2 has a width of 5 μm.
  8. 根据权利要求1所述的半导体器件，其特征在于：所述场限环三的宽度为5μm。The semiconductor device according to claim 1, wherein said field limiting ring 3 has a width of 5 μm.
  9. 根据权利要求1所述的半导体器件，其特征在于：所述半导体器件为DMOS。The semiconductor device according to claim 1, wherein said semiconductor device is a DMOS.
  10. 根据权利要求9所述的半导体器件，其特征在于：所述半导体器件为VDMOS。The semiconductor device according to claim 9, wherein said semiconductor device is a VDMOS.
PCT/CN2013/082918 2012-10-29 2013-09-04 Semiconductor device WO2014067344A1 (en)

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