CN103794639B - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

Info

Publication number
CN103794639B
CN103794639B CN201210424017.0A CN201210424017A CN103794639B CN 103794639 B CN103794639 B CN 103794639B CN 201210424017 A CN201210424017 A CN 201210424017A CN 103794639 B CN103794639 B CN 103794639B
Authority
CN
China
Prior art keywords
field limiting
limiting ring
ring
μm
semiconductor devices
Prior art date
Application number
CN201210424017.0A
Other languages
Chinese (zh)
Other versions
CN103794639A (en
Inventor
王者伟
Original Assignee
无锡华润上华科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华科技有限公司 filed Critical 无锡华润上华科技有限公司
Priority to CN201210424017.0A priority Critical patent/CN103794639B/en
Publication of CN103794639A publication Critical patent/CN103794639A/en
Application granted granted Critical
Publication of CN103794639B publication Critical patent/CN103794639B/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

The invention discloses a kind of semiconductor devices, the field limiting ring set including substrate and around the edges of substrate, the field limiting ring includes field limiting ring one, field limiting ring two and field limiting ring three, the field limiting ring two is between the field limiting ring one and field limiting ring three, spacing between the field limiting ring one and field limiting ring two is 19 ~ 21 μm, and the spacing between the field limiting ring two and field limiting ring three is 20 ~ 23 μm.The present invention improves the voltage endurance capability of semiconductor devices by changing the spacing between field limiting ring one, field limiting ring two and field limiting ring three.

Description

Semiconductor devices

Technical field

The invention belongs to technical field of semiconductors, more particularly to a kind of semiconductor devices.

Background technology

High voltage power semiconductor device such as Trench MOS(Trench semiconductor FET), VDMOS, IGBT etc., due to The features such as its working frequency is high, switching speed is fast, control efficiency is high, more and more extensive application is obtained in field of power electronics. The blocking ability of high voltage power semiconductor device is an important symbol for weighing development level, according to the model for applying breakdown voltage Enclosing can be from 25V-6000V, but because modern semiconductor processes use plane terminal structure, general junction depth is shallower, knot side Edge is bent so that the voltage endurance capability of device reduces, and pressure-resistant stability is poor, and the area of safety operaton of device is smaller, the easy quilt of device Destroy.

In order to improve the pressure-resistant demand of high-voltage semi-conductor device, generally difference is realized by changing extension concentration and thickness Pressure-resistant demand, but found in actual production, after the breakdown voltage of semiconductor devices brings up to 680V, then to reduce extension dense Degree improves epitaxial thickness, can not improve its breakdown voltage.

At present, the method for conventional raising device voltage endurance capability and stability is additionally included in device edge and sets field limiting ring (Field Limiting Ring, abbreviation FLR)Mode, the device that this method flows vertically to especially suitable for electric current, such as Trench MOS and VDMOS etc., it has big current handling capability and big current gain.Field limiting ring structure can effectively suppress Device it is main knot edge effect caused by electric field concentrate, it is pressure-resistant so as to improve, and with low-voltage ic process compatible, just Promoted in power integrated circuit and discrete high tension apparatus, in addition, height can be used as by being placed on the field limiting ring at depletion region edge Detector is pressed, the protection circuit in SPIC is driven, makes SPIC sensitiveer.

Fig. 1 show the top view of semiconductor devices 10 in the prior art, GTE rings 14, field limiting ring 1, field limiting ring two 12nd, field limiting ring 3 13 and cut-off ring 15 are surround located at the edge of substrate 16, wherein, the width of GTE rings 14 is 12 μm, field limiting ring One 11, the width of field limiting ring 2 12 and field limiting ring 3 13 is 5 μm, and the width of cut-off ring 15 is 7 μm, GTE rings 14 and field limiting ring One 11 spacing is 24 μm, and the spacing of field limiting ring 1 and field limiting ring 2 12 is 17 μm, field limiting ring 2 12 and field limiting ring 3 13 Spacing is 18 μm, and the spacing of field limiting ring 3 13 and cut-off ring 15 is 18 μm.Understood through measurement, the semiconductor obtained by the parameter The breakdown voltage of device is 683V, pressure-resistant smaller.

The content of the invention

Present invention solves the technical problem that be to provide a kind of semiconductor devices, the semiconductor devices has higher pressure-resistant Ability.

To achieve the above object, the present invention provides following technical scheme:

A kind of semiconductor devices, including substrate and the field limiting ring around edges of substrate setting, the field limiting ring include Field limiting ring one, field limiting ring two and field limiting ring three, the field limiting ring two between the field limiting ring one and field limiting ring three, wherein, Spacing between the field limiting ring one and field limiting ring two is 19 ~ 21 μm, and the spacing between the field limiting ring two and field limiting ring three is 20~23μm。

As a further improvement on the present invention, the semiconductor devices also includes GTE rings, and the field limiting ring one is positioned at described Between GTE rings and field limiting ring two, the width of the GTE rings is 12 μm.

Preferably, the spacing between the GTE rings and field limiting ring one is 20 ~ 30 μm.

As a further improvement on the present invention, the semiconductor devices also includes cut-off ring, and the field limiting ring three is located at institute State between cut-off ring and field limiting ring two, the width of the cut-off ring is 7 μm.

Preferably, the spacing between the cut-off ring and field limiting ring three is 20 ~ 28 μm.

As a further improvement on the present invention, the width of the field limiting ring one is 5 μm.

As a further improvement on the present invention, the width of the field limiting ring two is 5 μm.

As a further improvement on the present invention, the width of the field limiting ring three is 5 μm.

As a further improvement on the present invention, the semiconductor devices is DMOS.

Compared with prior art, the beneficial effects of the present invention are:By changing field limiting ring one, field limiting ring two and field limiting ring Spacing between three, to improve the voltage endurance capability of semiconductor devices.

Brief description of the drawings

, below will be to embodiment or existing in order to illustrate more clearly of the embodiment of the present application or technical scheme of the prior art There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this Some embodiments described in application, for those of ordinary skill in the art, on the premise of not paying creative work, Other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 show the structural representation of semiconductor devices in the prior art;

Fig. 2 show the structural representation of semiconductor devices in the embodiment of the present invention one;

Fig. 3 show the structural representation of semiconductor devices in the embodiment of the present invention two.

Embodiment

In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention Embodiment be described in detail.

Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with It is different from other manner described here using other to implement, those skilled in the art can be without prejudice to intension of the present invention In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.

Just as described in the background section, the voltage endurance capability of the semiconductor devices obtained in prior art is poor.Invention People has found by substantial amounts of experiment, when the spacing between field limiting ring is changed into certain value, can significantly improve device Voltage endurance capability, between particularly increasing between spacing and field limiting ring two and the field limiting ring three between field limiting ring one and field limiting ring two Away from.

For these reasons, the embodiments of the invention provide a kind of semiconductor devices, to solve the above problems, specifically describe Referring to following examples.

Embodiment one

Fig. 2 show the structural representation of semiconductor devices in the embodiment of the present invention one.

Join shown in Fig. 2, the semiconductor devices 20 includes:

Substrate 26;

It should be noted that the substrate in the present embodiment can include semiconductor element, such as monocrystalline, polycrystalline or amorphous knot The silicon or SiGe of structure(SiGe), the semiconductor structure mixed, such as carborundum, indium antimonide, lead telluride, arsenic can also be included Indium, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination;It can also be silicon-on-insulator(SOI).In addition, partly lead Body substrate can also include other materials, such as the sandwich construction of epitaxial layer or buried layer.Can be with shape although there is described herein Into several examples of the material of substrate, but the spirit and model of the present invention can be each fallen within as any material of Semiconductor substrate Enclose.

It is surrounded on GTE rings 24, field limiting ring 1, field limiting ring 2 22, field limiting ring 3 23 and the cut-off of the setting of the edge of substrate 26 Ring 25.Wherein, the width of GTE rings 24 is 12 μm, and the width of field limiting ring 1, field limiting ring 2 22 and field limiting ring 3 23 is 5 μm, The width for ending ring 25 is 7 μm, and the spacing of GTE rings 24 and field limiting ring 1 is 20 μm, field limiting ring 1 and field limiting ring 2 22 Spacing is 21 μm, and the spacing of field limiting ring 2 22 and field limiting ring 3 23 is 23 μm, and the spacing of field limiting ring 3 23 and cut-off ring 25 is 28 μ m。

Understand that the breakdown voltage of semiconductor devices 20 is 720V, compared to 683V of the prior art, is realized through measurement Larger lifting.

Embodiment two

Fig. 3 show the structural representation of semiconductor devices in the embodiment of the present invention two.

Join shown in Fig. 3, the semiconductor devices 30 includes:

Substrate 36;

It should be noted that the substrate in the present embodiment can include semiconductor element, such as monocrystalline, polycrystalline or amorphous knot The silicon or SiGe of structure(SiGe), the semiconductor structure mixed, such as carborundum, indium antimonide, lead telluride, arsenic can also be included Indium, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination;It can also be silicon-on-insulator(SOI).In addition, partly lead Body substrate can also include other materials, such as the sandwich construction of epitaxial layer or buried layer.Can be with shape although there is described herein Into several examples of the material of substrate, but the spirit and model of the present invention can be each fallen within as any material of Semiconductor substrate Enclose.

It is surrounded on GTE rings 34, field limiting ring 1, field limiting ring 2 32, field limiting ring 3 33 and the cut-off of the setting of the edge of substrate 36 Ring 35.Wherein, the width of GTE rings 34 is 12 μm, and the width of field limiting ring 1, field limiting ring 2 32 and field limiting ring 3 33 is 5 μm, The width for ending ring 35 is 7 μm, and the spacing of GTE rings 34 and field limiting ring 1 is 26 μm, field limiting ring 1 and field limiting ring 2 32 Spacing is 19 μm, and the spacing of field limiting ring 2 32 and field limiting ring 3 33 is 20 μm, and the spacing of field limiting ring 3 33 and cut-off ring 35 is 20 μ m。

Understand that the breakdown voltage of semiconductor devices 30 is 700V, compared to 683V of the prior art, is realized through measurement Larger lifting.

In summary, the present invention improves half by changing the spacing between field limiting ring one, field limiting ring two and field limiting ring three The voltage endurance capability of conductor device.

The explanation of above example is only intended to help the method and its core concept for understanding the present invention.It should be pointed out that pair For those skilled in the art, under the premise without departing from the principles of the invention, the present invention can also be carried out Some improvement and modification, these are improved and modification is also fallen into the protection domain of the claims in the present invention.

The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention. A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one The most wide scope caused.

Claims (4)

1. a kind of semiconductor devices, including substrate and the field limiting ring around edges of substrate setting, the field limiting ring include field Ring one, field limiting ring two and field limiting ring three are limited, between the field limiting ring one and field limiting ring three, its feature exists the field limiting ring two In:The semiconductor devices also includes cut-off ring, and the field limiting ring three is between the cut-off ring and field limiting ring two, GTE rings Width be 12 μm, the width of field limiting ring one, field limiting ring two and field limiting ring three is 5 μm, end ring width be 7 μm, GTE rings Spacing with field limiting ring one is 20 μm, and the spacing of field limiting ring one and field limiting ring two is 21 μm, between field limiting ring two and field limiting ring three Away from for 23 μm, field limiting ring three is 28 μm with the spacing for ending ring.
2. semiconductor devices according to claim 1, it is characterised in that:The semiconductor devices is DMOS.
3. a kind of semiconductor devices, including substrate and the field limiting ring around edges of substrate setting, the field limiting ring include field Ring one, field limiting ring two and field limiting ring three are limited, between the field limiting ring one and field limiting ring three, its feature exists the field limiting ring two In:The semiconductor devices also includes cut-off ring, and the field limiting ring three is between the cut-off ring and field limiting ring two, GTE rings Width be 12 μm, the width of field limiting ring one, field limiting ring two and field limiting ring three is 5 μm, end ring width be 7 μm, GTE rings Spacing with field limiting ring one is 26 μm, and the spacing of field limiting ring one and field limiting ring two is 19 μm, between field limiting ring two and field limiting ring three Away from for 20 μm, field limiting ring three is 20 μm with the spacing for ending ring.
4. semiconductor devices according to claim 3, it is characterised in that:The semiconductor devices is DMOS.
CN201210424017.0A 2012-10-29 2012-10-29 Semiconductor devices CN103794639B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210424017.0A CN103794639B (en) 2012-10-29 2012-10-29 Semiconductor devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210424017.0A CN103794639B (en) 2012-10-29 2012-10-29 Semiconductor devices
PCT/CN2013/082918 WO2014067344A1 (en) 2012-10-29 2013-09-04 Semiconductor device

Publications (2)

Publication Number Publication Date
CN103794639A CN103794639A (en) 2014-05-14
CN103794639B true CN103794639B (en) 2018-01-16

Family

ID=50626435

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210424017.0A CN103794639B (en) 2012-10-29 2012-10-29 Semiconductor devices

Country Status (2)

Country Link
CN (1) CN103794639B (en)
WO (1) WO2014067344A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106340534A (en) * 2015-07-09 2017-01-18 北大方正集团有限公司 Field limit loop and junction terminal expansion complex pressure dividing structure and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102479807A (en) * 2010-11-26 2012-05-30 三菱电机株式会社 Silicon carbide semiconductor device and manufacturing method therefor
CN102569388A (en) * 2010-12-23 2012-07-11 无锡华润上华半导体有限公司 Semiconductor device and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7541660B2 (en) * 2006-04-20 2009-06-02 Infineon Technologies Austria Ag Power semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102479807A (en) * 2010-11-26 2012-05-30 三菱电机株式会社 Silicon carbide semiconductor device and manufacturing method therefor
CN102569388A (en) * 2010-12-23 2012-07-11 无锡华润上华半导体有限公司 Semiconductor device and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
功率MOSFET击穿特性研究;刘驰;《中国优秀硕士学位论文全文数据库》;20121015;第57-64页 *

Also Published As

Publication number Publication date
WO2014067344A1 (en) 2014-05-08
CN103794639A (en) 2014-05-14

Similar Documents

Publication Publication Date Title
CN106158800B (en) Semiconductor devices
JP5017865B2 (en) Semiconductor device
US9818852B2 (en) Semiconductor device and semiconductor device manufacturing method
US8598658B2 (en) High voltage LDMOS device
CN102569354B (en) Insulated gate bipolar transistor and manufacturing method thereof
US9231083B2 (en) High breakdown voltage LDMOS device
CN106601809A (en) Gallium-nitride field effect transistor and manufacturing method therefor
CN103258847B (en) Reverse block (RB)-insulated gate bipolar transistor (IGBT) device provided with double-faced field stop with buried layers
CN101771039B (en) BCD device and manufacturing method thereof
CN103872099B (en) Semiconductor Device with Step-Shaped Edge Termination, and Method for Manufacturing a Semiconductor Device
US20120003803A1 (en) Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance
CN103035641B (en) Semiconductor device
Li et al. Design and simulation of 5–20-kV GaN enhancement-mode vertical superjunction HEMT
CN102683402B (en) A kind of planar gate charge storage type IGBT
US9324787B2 (en) Semiconductor device
CN102983171B (en) The vertical structure without knot surrounding-gate MOSFET device and manufacture method thereof
JP2015207784A (en) Power semiconductor element and method of manufacturing the same
GB2497259A (en) Butted SOI junction isolation structures and devices and method of fabrication
SG170670A1 (en) Method of fabricating a silicon tunneling field effect transistor (tfet) with high drive current
US9614071B2 (en) Semiconductor device
JP6189045B2 (en) Manufacturing method of semiconductor device
JP6224242B2 (en) Silicon carbide semiconductor device
CN102194818B (en) P-type epitaxial layer-based binary coded decimal (BCD) integrated device and manufacturing method thereof
CN102779840A (en) Insulated gate bipolar translator (IGBT) with terminal deep energy level impurity layer
CN103928527B (en) A kind of junction termination structures of horizontal high voltage power semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
GR01 Patent grant
GR01 Patent grant