CN102569388A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN102569388A
CN102569388A CN201010603278XA CN201010603278A CN102569388A CN 102569388 A CN102569388 A CN 102569388A CN 201010603278X A CN201010603278X A CN 201010603278XA CN 201010603278 A CN201010603278 A CN 201010603278A CN 102569388 A CN102569388 A CN 102569388A
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Prior art keywords
limiting ring
groove
isolated groove
semiconductor device
field limiting
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CN201010603278XA
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CN102569388B (en
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卞铮
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CSMC Technologies Corp
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CSMC Technologies Corp
Wuxi CSMC Semiconductor Co Ltd
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Priority to CN201010603278.XA priority Critical patent/CN102569388B/en
Priority to PCT/CN2011/083110 priority patent/WO2012083784A1/en
Priority to JP2013545021A priority patent/JP6103712B2/en
Publication of CN102569388A publication Critical patent/CN102569388A/en
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Publication of CN102569388B publication Critical patent/CN102569388B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, an active region, field limit rings and isolating grooves, wherein the active region is positioned in the surface of the substrate; the field limit rings are positioned outside the active region; the isolating grooves are positioned among the field limit rings; and in adjacent isolating grooves, at least two isolating grooves are electrically connected with each other through a connecting channel. In the embodiment of the invention, the etching step of the field limit rings is eliminated, and the production cost is reduced; and at least every two isolating grooves in adjacent isolating grooves are connected, and the width of a single field limit ring depletion region in the prior art is increased from the width of one isolating groove to the sum of the widths of interconnected isolating grooves and the widths of the field limit rings among the isolating grooves, so that the voltage dividing effect of the field limit rings is enhanced, and the voltage endurance capability of a chip is further enhanced.

Description

Semiconductor device and manufacturing approach thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of semiconductor device and manufacturing approach thereof.
Background technology
High-voltage power semiconductor device such as Trench MOS (trench semiconductor FET), VDMOS, IGBT etc. are because characteristics such as its operating frequency is high, switching speed is fast, control efficiency height obtain application more and more widely in field of power electronics.The blocking ability of high-voltage power semiconductor device is an important symbol weighing development level; Can be according to the scope of using puncture voltage from 25V-6000V, still because modern semiconductors process using plane terminal structure, generally more shallow, the knot curved edge of junction depth; Make the voltage endurance capability of device reduce; Withstand voltage poor stability, the area of safety operaton of device is less, and device is destroyed easily.Therefore, in order to improve the voltage endurance of device, the cooperation except between each parameter of device inside; The more important thing is that the PN junction that the surface is stopped carries out proper process; To improve the Electric Field Distribution of device edge, weaken the centrality of surface field, improve the voltage endurance capability and the stability of device.
At present; The method of raising device withstand voltage ability commonly used and stability is included in device edge field limiting ring (Field Limiting Ring is set; Abbreviation FLR) mode; This method is specially adapted to the device that current vertical flows to, and like Trench MOS and VDMOS etc., it has big current handling capability and big current gain.Field limiting ring structure effectively suppression device master is tied the electric field that the edge curvature effect causes and is concentrated; Thereby improve withstand voltage, and with the low-voltage ic process compatible, be convenient in power integrated circuit and discrete high tension apparatus, promote; In addition; The field limiting ring that is placed on the depletion region edge can be used as high voltage detector, drives the protective circuit among the SPIC, makes SPIC sensitive more.
The mode that forms field limiting ring in the prior art mainly contains two kinds, is example with the chip of Trench MOS device configuration, below in conjunction with accompanying drawing dual mode is described.
The field limiting ring that the mode of employing prior art one forms is as depicted in figs. 1 and 2; Adopt the vertical view of the chip that this mode forms as shown in Figure 1; Fig. 2 is the profile of chip; This mode is to adopt the mode of injecting separately to form field limiting ring 104 at chip edge, and the dividing potential drop through field limiting ring 104 is to improve the voltage endurance capability of chip.
As shown in Figure 2; The forming process of field limiting ring 104 is, after the main knot 102 and the groove 103 of active area form, and spin coating photoresist on the surface of substrate 101; Be mask with the photoresist layer 105 with field limiting ring pattern afterwards, the mode that adopts ion to inject forms field limiting ring 104.That is to say that this method needs one independent lithography step to construct the injection zone of field limiting ring, owing to increased lithography step one time, and then increased production cost.
Field limiting ring such as Fig. 3 and shown in Figure 4 that the mode of employing prior art two forms; Fig. 3 is the vertical view of chip; Fig. 4 is the profile of chip, and from the consideration of cost, the mode that the commercial FET of part low pressure adopts trench isolations to inject is constructed field limiting ring; Can omit lithography step one, reduce production costs.
As shown in Figure 4, the forming process of field limiting ring 205 is that elder generation is formed with the groove 202 and the isolated groove 204 that is used to isolate field limiting ring in source region in the surface of substrate 201, adopt the mode of ion injection afterwards, is formed with the main knot 203 and the field limiting ring 205 in source region simultaneously.The field limiting ring that this mode forms, though reduced production cost, in practical application, than prior art one, the dividing potential drop effect of the field limiting ring that this mode forms is relatively poor, the voltage endurance capability of chip is limited.
Summary of the invention
The embodiment of the invention provides a kind of semiconductor device and manufacturing approach thereof, has both omitted the lithography step of field limiting ring, has reduced production cost, has improved the dividing potential drop effect of field limiting ring again, has improved the voltage endurance capability of chip.
For realizing above-mentioned purpose, the embodiment of the invention provides following technical scheme:
A kind of semiconductor device comprises:
Substrate;
Be positioned at the active area of said substrate surface;
Field limiting ring is positioned at outside the said active area;
Isolated groove, between said field limiting ring, in the adjacent isolated groove, the said isolated groove of twice is electrical connected through interface channel at least.
Preferably, said interface channel is a link slot.
Preferably, said active area has groove, and the groove of said link slot, isolated groove and said active area forms in same step lithography step.
Preferably, said link slot, isolated groove are identical with the dopant states of the groove of said active area.
Preferably, said semiconductor device also comprises:
Be positioned at said suprabasil dielectric layer, and be positioned at the metal level on the said dielectric layer, wherein, said dielectric layer has through hole, is filled with metal in the said through hole, to connect said metal level.
Preferably, said interface channel is the metal in said metal level and the said through hole.
Preferably, said semiconductor device is a groove MOS device, and the main knot of said field limiting ring and said groove MOS device forms in same implantation step, and the dopant states of said field limiting ring is identical with the dopant states of said groove MOS device active area master knot.
The embodiment of the invention also discloses a kind of manufacturing approach of semiconductor device, comprising:
Substrate is provided;
In said substrate surface, be formed with source region groove and multiple tracks isolated groove simultaneously, wherein, every at least twice isolated groove links to each other through interface channel in the adjacent isolated groove, and said interface channel is a link slot;
In said substrate surface, be formed with the main knot in source region simultaneously and be positioned at the multiple tracks field limiting ring between isolated groove.
Preferably, the mode that adopts ion to inject forms the main knot and the field limiting ring of said active area simultaneously in said substrate surface.
The embodiment of the invention also discloses a kind of manufacturing approach of semiconductor device, comprising:
Substrate is provided;
In said substrate surface, be formed with field limiting ring and the isolated groove between field limiting ring outside source region, the active area;
In said substrate, form dielectric layer, on said dielectric layer, form the through hole that extends to isolated groove;
In said through hole, fill metal;
On said dielectric layer, form metal level, the metal of filling in the said through hole forms the interface channel that is connected adjacent isolated groove with said metal level.
Compared with prior art, technique scheme has the following advantages:
The passing through of the semiconductor device that the embodiment of the invention provides forms multiple tracks field limiting ring and active area master knot in same implantation step, omitted the lithography step that forms field limiting ring, reduced production cost; And through every at least twice isolated groove in the adjacent isolated groove is linked to each other; Make the induced potential of the field limiting ring between the isolated groove that is positioned at interconnection identical with the isolated groove current potential of interconnection; Thereby shielded the effect of the field limiting ring between the isolated groove that interconnects; Also just be equivalent to the width of single field limiting ring depletion region in the prior art is increased to by the width of an isolated groove summation of the width of the isolated groove width of interconnection and field limiting ring therebetween; Just that the field limiting ring between the isolated groove of interconnection is shared transverse area is expanded and is the depletion region of previous field limiting ring; Thereby increased the dividing potential drop effect of previous field limiting ring, further improved the voltage endurance capability of chip.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 is the vertical view of semiconductor device in the prior art one;
Fig. 2 is the profile of semiconductor device in the prior art one;
Fig. 3 is the vertical view of semiconductor device in the prior art two;
Fig. 4 is the profile of semiconductor device in the prior art two;
Fig. 5 is the profile of the embodiment of the invention one disclosed semiconductor device;
Fig. 6 is the vertical view of the embodiment of the invention two disclosed semiconductor device;
Fig. 7 is the stereogram of the embodiment of the invention two disclosed semiconductor device;
Fig. 8-Figure 14 is the profile of the embodiment of the invention three disclosed method, semi-conductor device manufacturing methods;
Figure 15 is the profile of the embodiment of the invention four disclosed semiconductor device.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention; But the present invention can also adopt other to be different from alternate manner described here and implement; Those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed specific embodiment.
Secondly, the present invention combines sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is example, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Said as the background technology part; Form the extra lithography step that increased by a time of mode of field limiting ring in the prior art one; Increased production cost,, reduced production cost though prior art two has been omitted lithography step one; But cause the dividing potential drop weak effect of field limiting ring, the voltage endurance capability of chip is poor.
The inventor discovers that the basic reason that forms the problems referred to above is the field limiting ring that the mode that adopts trench isolations to inject in the prior art two forms; The width of depletion region of each field limiting ring is the width of isolated groove, because the width of isolated groove is narrow, causes each field limiting ring all can't reach the corresponding best dividing potential drop effect of its doping content; Promptly in galvanization, each field limiting ring is not when reaching its best dividing potential drop effect, and the depletion layer of device has just expanded to next field limiting ring; Because in the width regions scope of field limiting ring, current potential is identical, so the width regions of field limiting ring can not exhaust; That is to say; Total depletion widths of field limiting ring only is the summation of isolated groove width in the prior art two, thereby has reduced the dividing potential drop efficient of field limiting ring, and then causes the voltage endurance capability of whole chip relatively poor.
But; Expand the depletion region of field limiting ring if adopt the mode that increases the isolated groove width; Again because the width of isolated groove receives the restriction of follow-up grid region material (like polysilicon) fill process (being generally film deposition art); The problem of the reliability aspect that bring in the filling space of the material for fear of the grid region (like polysilicon); Thereby the Breadth Maximum that has limited isolated groove generally can not be greater than about 1.2 times of the polysilicon membrane thickness in the film deposition art; But because the restriction of film deposition art, the Breadth Maximum of isolated groove generally speaking remains not enough for the depletion widths of field limiting ring, and therefore to expand the mode of the depletion region of field limiting ring also be infeasible through increasing the isolated groove width.
For these reasons, the embodiment of the invention provides a kind of new semiconductor device structure and manufacturing approach thereof, to address the above problem, specifically describes referring to following examples.
Embodiment one
The embodiment of the invention one provides a kind of semiconductor device, and its structure is as shown in Figure 5, and Fig. 5 is the profile of this semiconductor device, below in conjunction with Fig. 5 the structure of this semiconductor device is elaborated.
This semiconductor device comprises:
Substrate 301;
Need to prove; Substrate in the present embodiment can comprise semiconductor element; The for example silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe); The semiconductor structure that also can comprise mixing, for example carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination; It also can be silicon-on-insulator (SOI).In addition, the semiconductor-based end, can also comprise other material, for example the sandwich construction of epitaxial loayer or buried layer.Though in these several examples of having described the material that can form substrate, any material that can be used as the semiconductor-based end all falls into the spirit and scope of the present invention.
Be positioned at the multiple tracks isolated groove of active area, multiple tracks field limiting ring and the opposite field limit interannular on said substrate 301 surfaces; Said active area has groove 302; And every at least twice isolated groove links to each other through interface channel 306 in the adjacent isolated groove, and the induced potential that is arranged in the field limiting ring (shown in the field limiting ring 305 of Fig. 5) between isolated groove (shown in Fig. 5 isolated groove 304) is identical with the isolated groove current potential of interconnection.
Wherein, said interface channel 306 can have multiple mode, and like link slot or metal etc., concrete connected mode is elaborated in the subsequent implementation example, and present embodiment repeats no more.
It is emphasized that; The process that forms field limiting ring in the present embodiment does; Earlier at groove that is formed with the source region in the surface of substrate 301 302 and the isolated groove (shown in Fig. 5 isolated groove 304) that is used for isolating field limiting ring; The mode that adopts ion to inject afterwards is formed with main knot 303 in source region and field limiting ring (shown in the field limiting ring among Fig. 5 305) simultaneously.
Because the multiple tracks field limiting ring in the present embodiment is tied 303 with the active area master and formed simultaneously, so present embodiment omitted the lithography step of formation field limiting ring than prior art one, reduced production cost.Accordingly, the field limiting ring 305 of present embodiment has the identical dopant states of main knot with active area 303.
Field limiting ring action principle in the present embodiment is, when the main reversed bias voltage rising of tying strengthens the fringe field of semiconductor device, when fringe field reaches critical electric field; The main knot of device just punch-through can occur, yet, add after the field limiting ring; When the avalanche voltage puncture does not take place in device master knot as yet; Main knot depletion region has just expanded to the loops position of field limiting ring, though the depletion region of PN junction and field limiting ring break-through, so the depletion layer of the loops of main knot and field limiting ring is connected each other; Near field limiting ring, just respond to the loops electric field that has produced field limiting ring; Because the loops electric field of field limiting ring is identical with main knot direction of an electric field, two mutual superpositions of electric field form pressure drop, are equivalent to just weaken the electrical potential difference that main knot bore; When applied voltage continues to rise, then to bear by field limiting ring, the increase of main knot electric field will be controlled.
In other words, the effect of field limiting ring just is equivalent to increase at the edge of planar power device the voltage divider of a voltage, and applied voltage is distributed in the longer distance, thereby has stoped the puncture that causes device master knot owing to applied voltage is too high.
The mechanism of action based on field limiting ring can be known; The width of field limiting ring depletion region can influence the dividing potential drop efficient of field limiting ring; The width of the depletion region of single field limiting ring is specially in the present embodiment; The summation of the transverse width of the isolated groove of one group of interconnection and the transverse width of the field limiting ring of the isolated groove centre that is positioned at the interconnection of this group, and the width of the depletion region of the single field limiting ring in the prior art two is the transverse width of single isolated groove.
Because the isolated groove of present embodiment and the groove of active area form simultaneously, field limiting ring and active area master knot form simultaneously, have omitted the lithography step of structure field limiting ring, have saved production cost.Pass through in the present embodiment every at least twice isolated groove in the adjacent isolated groove is linked to each other; Make the induced potential of the field limiting ring between the isolated groove that is positioned at interconnection identical with the isolated groove current potential of interconnection; Thereby shielded the effect of the field limiting ring between the isolated groove that interconnects; Also just be equivalent to the width of field limiting ring depletion region in the prior art is increased to by the width of an isolated groove summation of the width of the isolated groove width of interconnection and field limiting ring therebetween; The transverse area that field limiting ring between the isolated groove of interconnection is shared is expanded and is the depletion region of previous field limiting ring; Thereby increased the dividing potential drop effect of previous field limiting ring, further improved the voltage endurance capability of chip.
Need to prove; Do not limit the quantity of field limiting ring and isolated groove in the present embodiment and several isolated groove interconnection are arranged; Can link to each other in twos, also can per three isolated grooves link to each other etc., many factors that concrete structure also need combine to influence puncture voltage and dividing potential drop efficient in the device are considered simultaneously; (surface charge of bipolar device is many more generally speaking like what of the surface charge of semiconductor device; Puncture voltage is low more), the doping content (substrate doping is low more, and puncture voltage is high more) of substrate, junction depth (junction depth increases, and puncture voltage also increases) and substrate thickness etc.
Embodiment two
The structure of the disclosed semiconductor device of present embodiment and a last embodiment are similar; But different with a last embodiment is; Present embodiment carries out refinement to this semiconductor device on the basis of a last embodiment, a kind of concrete mode that every at least twice isolated groove is linked to each other through interface channel has been described.
This implements disclosed semiconductor device such as Fig. 6 and shown in Figure 7, and Fig. 6 is the vertical view of this semiconductor device, and Fig. 7 is the stereogram of this semiconductor device.
Below be connected to example in twos with isolated groove 401 structure of this semiconductor device described; Like Fig. 6 and shown in Figure 7; The isolated groove that links to each other is in position adjacent; And have link slot 403 between any two, that is to say, the link slot 403 in the present embodiment is similar with interface channel described in the embodiment one.
Link slot 403 in the present embodiment forms in same lithography step with the groove 404 of isolated groove 401 and active area, so the dopant states of the groove 404 of said link slot 403, isolated groove 401 and active area is identical.
Wherein, dopant states comprises described in the present embodiment: doping content and dopant species, and the dopant states of the groove 404 of link slot 403, isolated groove 401 and active area is identical, and dopant ion, doping content that is to say the three etc. is identical.
Concrete, substrate described in the present embodiment comprises epitaxial loayer, said isolated groove, link slot and field limiting ring and active area are arranged in the epi-layer surface.And; The main packing material of the isolated groove in the present embodiment, link slot and active area groove can be polysilicon; Certainly, before filling polysilicon, also be included in trench wall heat growth one deck isolating oxide layer, this processing step can carry out with the grid oxygen technology of making in the cellular region simultaneously.
In addition; If the semiconductor device in the present embodiment is a groove MOS device; The active area master knot of said field limiting ring and said groove MOS device forms in same injection process, and the dopant states of said field limiting ring is identical with the dopant states of said groove MOS device active area master knot.Certainly, the semiconductor device in the present embodiment also can be the MOS device that the current vertical of other kind flows to, and like the VDMOS device etc., gives unnecessary details no longer one by one here.
The semiconductor device of present embodiment through the link slot that is provided with between adjacent isolated groove, has increased the width of depletion region of single field limiting ring; Realized the zero potential transition of terminal electric field; And link slot and isolated groove form simultaneously, need not increase any operation, when reducing production costs; Strengthen the dividing potential drop performance of field limiting ring, improved the voltage endurance capability of chip.
Need to prove; Number and the spacing between link slot to the link slot between the isolated groove that has annexation in the present embodiment are not done concrete qualification, and concrete setting also need combine many-sided conditions such as dopant states, junction depth, substrate thickness to take all factors into consideration.
Embodiment three
Corresponding with the semiconductor device structure of a last embodiment, present embodiment discloses a kind of manufacturing approach of semiconductor device, like Fig. 8-shown in Figure 14, may further comprise the steps:
Substrate 501 is provided;
Said substrate comprises epitaxial loayer, and said epitaxial loayer can be and adopts CVD technology once the N type of property growth or P type epitaxial loayer on substrate, and the thickness of epitaxial loayer can be confirmed according to the concrete application requirements of device.Substrate in the present embodiment can be silicon substrate.
In said substrate surface, be formed with source region groove and multiple tracks isolated groove simultaneously, wherein, every at least twice isolated groove links to each other through interface channel in the adjacent isolated groove, and said interface channel is a link slot;
Concrete; Can adopt the mode of dry etching or wet etching in said substrate surface, to be formed with source region groove, isolated groove and link slot in the present embodiment; Be example with the dry etching mode below, the process that is formed with source region groove, isolated groove and link slot in the present embodiment be described in detail in conjunction with accompanying drawing.
Referring to Fig. 8, the deposit layer of oxide layer is as etching barrier layer 502 on substrate 501 surfaces, and said etching barrier layer 502 can adopt the mode of LPCVD to form said etching barrier layer 502 for the silicon dioxide layer with TEOS (tetraethoxysilane) preparation;
Spin coating photoresist layer 503 on said etching barrier layer 502 surfaces in order to guarantee exposure accuracy, also can form anti-reflecting layer, to reduce unnecessary reflection between photoresist layer and said substrate surface; Adopt mask that photoresist layer 503 is made public afterwards with active area groove, isolated groove and link slot figure; On said photoresist layer 503 surfaces, be formed with the pattern (not shown) of source region groove, isolated groove and link slot; Be mask with photoresist layer afterwards with active area groove, isolated groove and link slot pattern; Can adopt the method for dry etching or wet etching; On said etching barrier layer 502, be formed with source region groove, isolated groove and link slot figure, as shown in Figure 9;
Shown in figure 10; Be hard mask with etching barrier layer 502 afterwards with active area groove, isolated groove and link slot figure; Adopt dry etching or other corroding method; In the surface of substrate 501, be formed with source region groove, isolated groove and link slot figure opening, adopt the method for wet-chemical cleaning to remove photoresist layer 503 and etching barrier layer 502 afterwards;
Referring to Figure 11; Inner surface growth layer of oxide layer (not shown) at active area groove, isolated groove and link slot figure opening; Afterwards at said substrate 501 surface coverage grid region materials, in said active area groove, isolated groove and link slot figure opening, to fill the grid region material;
Can adopt modes such as CVD, PECVD (plasma chemical vapor deposition), HDP (high-density plasma chemical vapor deposition) or PVD in active area groove, isolated groove and link slot figure opening, to fill the grid region material, the polysilicon that said grid region material can be polysilicon (can in subsequent technique, mix again) or has certain doping content in the present embodiment.
Afterwards,, remove the outer grid region material of active area groove, isolated groove and link slot figure opening, be formed with groove grid region 504, isolated groove 505 and the link slot (not shown) in source region referring to Figure 12;
Can adopt chemical mechanical milling tech to remove the outer grid region material of groove grid region, isolated groove and link slot figure opening of active area in the present embodiment; Substrate surface is flushed; Perhaps be utilized in the stop layer of the silicon dioxide film of substrate surface growth as etching; Adopt back carving technology to remove grid region material, make figure open surfaces and the flush of said substrate of groove grid region, isolated groove and the link slot of active area, to guarantee the smooth of said substrate surface on the silicon dioxide film surface; Utilize wet etching method or additive method afterwards again, remove silicon dioxide film.
In said substrate surface, be formed with the main knot in source region simultaneously and be positioned at the multiple tracks field limiting ring between isolated groove.
Shown in Figure 13 and 14, the mode that can adopt ion to inject in the present embodiment forms said active area master simultaneously and ties 506 and be positioned at the multiple tracks field limiting ring 507 between isolated groove in said substrate surface.
Detailed process can for, carrying out before ion injects, one deck thin oxide layer of can on the surface of substrate 501, grow is as injection oxide layer (not shown); Carrying out ion afterwards again and inject, is example with N type MOSFET, injects p type impurity; Dopant ion is a boron, and doping content is E13cm-3.Wherein, the effect of injecting oxide layer is to carry out the process that ion injects, and reduces the ion implantation damage that the surface of active area receives and prevent foreign atom or ion spreads out from the silicon of substrate; Said injection oxide layer can adopt CVD or thermal oxidation technology to form.
Referring to Figure 14, after the injection of accomplishing active area master knot and field limiting ring, push away the diffusion of trap technology and activate the dopant material that injects through high temperature.High temperature pushes away the ion that trap technology can make the dopant material of injection and passes the silicon crystal of substrate; In substrate, form the junction depth (being diffusion process) of expectation; Make the ion of injection and the silicon atom bonding of lattice afterwards, this process has activated the injection ion, has formed active area master knot and field limiting ring.
The trap technology that pushes away high temperature in the present embodiment can adopt 1000 ℃-1150 ℃ high temperature; But start from special consideration under some situation; Also can use other temperature outside this temperature range; Therefore in practical application, the control of actual temp and time can be decided the requirement of active area master knot and field limiting ring according to concrete device, and the embodiment of the invention is not done concrete restriction.
Can select afterwards to keep or remove and inject oxide layer, wherein remove the injection oxide layer and can adopt methods such as wet-chemical cleaning, repeat no more here.
" in the substrate surface " described in the present embodiment is meant that this zone belongs to the part of substrate by the zone of substrate surface to the certain depth that extends below; Said " on the substrate surface " is meant that this zone does not belong to the part of substrate by the upwardly extending zone of substrate surface.
Embodiment four
Structure according to the semiconductor device of the embodiment of the invention four is shown in figure 15, and Figure 15 is the profile of this semiconductor device, and this semiconductor device comprises:
Substrate 601;
Be positioned at the multiple tracks isolated groove 603 of active area, multiple tracks field limiting ring 602 and the opposite field limit interannular of said substrate surface, said active area has groove 604;
Also comprise in addition; Be positioned at said substrate 601 lip-deep dielectric layers 605; And be positioned at the metal level 606 on the said dielectric layer 605; Wherein said dielectric layer 605 has the through hole 607 that is communicated with said isolated groove 603 and said metal level 606, is filled with metal in the said through hole 607, can be tungsten, copper etc.
Dielectric layer can be interlayer dielectric layer described in the present embodiment, also can be before-metal medium layer etc., the kind of dielectric layer is not done concrete qualification here.
Metal level 606 shown in the present embodiment is equivalent to embodiment one described interface channel, and metal level 606 is positioned at the through hole of the dielectric layer 605 of isolated groove 603 tops through connection, makes in the adjacent isolated groove every at least twice isolated groove current potential identical.
The through hole that is arranged in the dielectric layer of isolated groove top in the present embodiment can form at same lithography step with the through hole of the dielectric layer that is positioned at the active area top; Metal in the said through hole can form in same depositing step with the metal plug of active area; The metal level 606 that is arranged in the isolated groove top can form at same lithography step with the metal level of active area top, so the semiconductor device in the present embodiment can not increase lithography step or cost in manufacture process.
Need to prove; Through hole in the present embodiment can only be got through dielectric layer; Also can squeeze into certain depth in the isolated groove surface; The latter can guarantee that the metal that is injected in the through hole better couples together isolated groove and metal level, but specifically adopts which kind of through hole, and present embodiment is not done concrete qualification.
Through metal layer material adjacent isolated groove is connected in the present embodiment; Can make the isolated groove current potential of interconnection identical equally; And the induced potential that is positioned at the field limiting ring between the isolated groove of interconnection is also identical with the isolated groove current potential of interconnection; And then the zero potential transition of realization terminal electric field, expand the width of single field limiting ring depletion region, thereby improve the dividing potential drop effect of field limiting ring and the voltage endurance capability of chip.
Embodiment five
Corresponding with the disclosed semiconductor device structure of a last embodiment, present embodiment discloses a kind of manufacturing approach of semiconductor device, may further comprise the steps:
Substrate is provided;
In said substrate surface, be formed with the multiple tracks isolated groove of source region, multiple tracks field limiting ring and opposite field limit interannular;
In said substrate, form dielectric layer, on said dielectric layer, form the through hole that extends to isolated groove, dielectric layer can be interlayer dielectric layer described in the present embodiment, also can be before-metal medium layer etc., the kind of dielectric layer is not done concrete qualification here;
As above an embodiment is said; The through hole that is arranged in the dielectric layer of isolated groove top can form at same lithography step with the through hole of the dielectric layer that is positioned at the active area top; Be specially; Spin coating photoresist layer on said dielectric layer adopts the mask with said via hole image that said photoresist layer is made public, and on said photoresist layer, forms the pattern with said through hole; Be mask with photoresist layer afterwards, adopt etching technics in said dielectric layer, to form said through hole with this through-hole pattern.
In said through hole, fill metal;
With the tungsten be the example explanation this in through hole, fill the step of metal.This step can form in same depositing step with the tungsten plug of active area, can adopt PVD technology.Detailed process can be, and earlier at said dielectric layer surface deposition skim Titanium, the titanium liner has served as tungsten is limited in the adhesive in the through hole on the bottom and sidewall of through hole; At the upper surface deposit skim titanium nitride of titanium, titanium nitride has served as the diffusion impervious layer of tungsten afterwards; Can adopt the upper surface depositing metal tungsten of the method for chemical vapor deposition afterwards, with the opening of filling vias at titanium nitride; Afterwards, can adopt the method for cmp to remove the outer tungsten of via openings, make dielectric layer keep smooth.
On said dielectric layer, form metal level, to form the interface channel that connects adjacent isolated groove.
The metal level of the said through hole of connection in this step and the metal level of active area form in same lithography step; Concrete steps can do, deposited metal on said dielectric layer surface, and this metal level can be the sandwich metal structure; Adopt photoetching and etching technics that said metal level is etched into desired structure afterwards; Promptly, adjacent isolated groove is coupled together, to form said interface channel through the contacting of tungsten in metal level and the through hole.
In the present embodiment; When forming the photoetching of through hole and forming the photoetching of metal level; Its mask should be made according to the structure of the semiconductor device of present embodiment accordingly; Wherein form the figure that should comprise the through hole that connects adjacent isolated groove on the mask of through hole, form the figure that should comprise isolated groove place metal level on the mask of metal level, to guarantee the correct connection of isolated groove.
The above embodiment only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims (10)

1. a semiconductor device is characterized in that, comprising:
Substrate;
Be positioned at the active area of said substrate surface;
Field limiting ring is positioned at outside the said active area;
Isolated groove, between said field limiting ring, in the adjacent isolated groove, the said isolated groove of twice is electrical connected through interface channel at least.
2. semiconductor device according to claim 1 is characterized in that, said interface channel is a link slot.
3. semiconductor device according to claim 2 is characterized in that said active area has groove, and the groove of said link slot, isolated groove and said active area forms in same step lithography step.
4. semiconductor device according to claim 3 is characterized in that, said link slot, isolated groove are identical with the dopant states of the groove of said active area.
5. semiconductor device according to claim 1 is characterized in that, said semiconductor device also comprises:
Be positioned at said suprabasil dielectric layer, and be positioned at the metal level on the said dielectric layer, wherein, said dielectric layer has through hole, is filled with metal in the said through hole, to connect said metal level.
6. semiconductor device according to claim 5 is characterized in that, said interface channel is the metal in said metal level and the said through hole.
7. according to each described semiconductor device of claim 1-6; It is characterized in that; Said semiconductor device is a groove MOS device; The main knot of said field limiting ring and said groove MOS device forms in same implantation step, and the dopant states of said field limiting ring is identical with the dopant states of said groove MOS device active area master knot.
8. the manufacturing approach of a semiconductor device is characterized in that, comprising:
Substrate is provided;
In said substrate surface, be formed with source region groove and multiple tracks isolated groove simultaneously, wherein, every at least twice isolated groove links to each other through interface channel in the adjacent isolated groove, and said interface channel is a link slot;
In said substrate surface, be formed with the main knot in source region simultaneously and be positioned at the multiple tracks field limiting ring between isolated groove.
9. method according to claim 8 is characterized in that, the mode that adopts ion to inject forms the main knot and the field limiting ring of said active area simultaneously in said substrate surface.
10. the manufacturing approach of a semiconductor device is characterized in that, comprising:
Substrate is provided;
In said substrate surface, be formed with field limiting ring and the isolated groove between field limiting ring outside source region, the active area;
In said substrate, form dielectric layer, on said dielectric layer, form the through hole that extends to isolated groove;
In said through hole, fill metal;
On said dielectric layer, form metal level, the metal of filling in the said through hole forms the interface channel that is connected adjacent isolated groove with said metal level.
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Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd.

Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China

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Patentee before: Wuxi CSMC Semiconductor Co., Ltd.