CN102569160B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN102569160B CN102569160B CN201010599115.9A CN201010599115A CN102569160B CN 102569160 B CN102569160 B CN 102569160B CN 201010599115 A CN201010599115 A CN 201010599115A CN 102569160 B CN102569160 B CN 102569160B
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Abstract
The invention discloses a method for manufacturing a semiconductor device, which comprises the steps as follows: a substrate is provided and includes an STI shallow trench; ions are injected into the side wall and the bottom of the STI shallow trench, so as to improve the lattice structure of the substrate material where the ions are arranged; and an STI shallow trench isolation area is formed on the surface of the substrate. In the embodiment of the invention, the ions are injected into the side wall and the bottom of the STI shallow trench, the lattice structure of the substrate material where the ions are arranged is destroyed through the ion impact on lattice, and the change of the lattice structure of the substrate material means the change of a stress receptor, so that the stress generated between the substrate material and the STI shallow trench isolation area is reduced, that is, the STI stress effect is improved, and the performance of the semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly, relate to a kind of manufacturing method of semiconductor device.
Background technology
Along with the development of semiconductor technology, process is more and more less, also more and more higher to the performance requirement of semiconductor device.Along with the reduction of process, the STI stress effect of shallow trench isolation region is also more and more obvious.STI stress effect can make the ion concentration of narrow channel device too high, thus causes the leakage current of device excessive, and then reduces the performance of device.
Adopt in prior art and layout is optimized, and increase the stress that the modes such as annealing steps discharge STI, but along with the size of device constantly reduces, the effect of these methods is unsatisfactory, STI stress effect still clearly, the performance of device is not better improved, and therefore, needs the method finding and more effectively improve STI stress effect at present badly.
Summary of the invention
Embodiments provide a kind of manufacturing method of semiconductor device, the main manufacturing process describing shallow trench isolation region, by improving the manufacturing process of STI, thus improves STI stress effect, thus improves the performance of semiconductor device.
For achieving the above object, following technical scheme is embodiments provided:
A kind of manufacturing method of semiconductor device, comprising:
There is provided substrate, described substrate comprises STI shallow trench;
At sidewall and the bottom injection ion of described STI shallow trench, to improve the lattice structure of the base material injecting ion place;
Described substrate surface is formed STI shallow trench isolation region.
Preferably, the ion injected in sidewall and the bottom of described STI shallow trench is quadrivalent ion.
Preferably, described quadrivalent ion is silicon ion.
Preferably, the dosage injecting ion at the sidewall of described STI shallow trench and bottom is 1E13cm2 substantially.
Preferably, the implant angle injecting ion at the sidewall of described STI shallow trench and bottom is 20 °-40 °.
Preferably, be substantially 30 ° at the sidewall of described STI shallow trench and the implant angle of bottom injection ion.
Preferably, the process described substrate surface forming STI shallow trench isolation region comprises:
The sidewall and bottom of described STI shallow trench form cushion oxide layer;
STI packed layer is formed in described cushion oxide layer He on described substrate surface;
Remove the outer unnecessary STI packed layer material of described STI shallow trench, form STI shallow trench isolation region.
Preferably, thermal oxidation method is adopted to form described cushion oxide layer.
Preferably, the mode of low-pressure chemical vapor phase deposition or high-density plasma chemical vapor deposition is adopted to form described STI packed layer.
Preferably, the mode of employing cmp removes the STI packed layer outside STI shallow trench, forms STI shallow trench isolation region.
Compared with prior art, technique scheme has the following advantages:
The manufacturing method of semiconductor device that the embodiment of the present invention provides, by injecting ion at the sidewall of STI shallow trench and bottom, thus pass through the shock of ion pair lattice, destroy the lattice structure of the base material injecting ion place, because the lattice structure of base material is destroyed, make the stress direction that produces between base material and STI shallow trench isolation region no longer concentrated, but by irregular dispersion, thus reduce stress, because the lattice structure of stress receptor changes, namely the factor producing stress is fundamentally changed, eliminate STI stress Producing reason, thus reduce STI stress effect, improve the performance of semiconductor device.
And, the method of the embodiment of the present invention is owing to being the improvement carried out in the manufacturing process of STI shallow trench isolation region, very little with the correlation of layout, it also reduce the dependence to layout, and, owing to just having done low dose of ion implantation at the sidewall of STI shallow trench and bottom, therefore also very little on the impact of other electrical parameter of semiconductor device.
Accompanying drawing explanation
Shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawing indicates identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on purport of the present invention is shown.
The flow chart of Fig. 1 manufacturing method of semiconductor device disclosed in the embodiment of the present invention one;
The profile of Fig. 2-Fig. 7 each step of manufacturing method of semiconductor device disclosed in the embodiment of the present invention two.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Just as described in the background section, along with dimensions of semiconductor devices is more and more less, discharge the mode effect of STI stress in prior art and not obvious.Based on the problems referred to above, inventor studies discovery, the reason producing stress is the existence of STI shallow trench isolation region, substrate defines multiple insulate on Si island, due to the difference of the material of filling in STI shallow trench and periphery material, makes both contact-making surfaces to produce stress, and due to the existence of STI stress, will inevitably electron mobility be affected, and then cause the ion concentration of narrow channel device too high, make leakage current excessive.Therefore, to fundamentally less STI stress effect, best bet is from stress Producing reason, and destroy the basis that stress produces, STI stress will reduce naturally.
Embodiment one
For these reasons, the embodiment of the invention discloses a kind of manufacturing method of semiconductor device, mainly for the manufacturing process of STI shallow trench isolation region,
The flow chart of the method as shown in Figure 1, comprises the following steps:
Step S1: substrate is provided, described substrate comprises STI shallow trench;
Step S2: at sidewall and the bottom injection ion of described STI shallow trench, to improve the lattice structure of the base material injecting ion place;
Step S3: form STI shallow trench isolation region on described substrate surface.
The embodiment of the present invention is by injecting ion at the sidewall of described STI shallow trench and bottom, by the shock of ion pair lattice, destroy the lattice structure of the base material injecting ion place, due to the change of base material lattice structure, namely the acceptor of stress changes, thus reduce the stress produced between base material and STI shallow trench isolation region, namely improve STI stress effect, improve the performance of semiconductor device.
Wherein, the acceptor of described stress refers to the both sides met with stresses, here basidigitale material and STI shallow trench packing material, and the side changed is base material.
Embodiment two
The profile of each step of manufacturing method of semiconductor device disclosed in the present embodiment is as shown in Fig. 2-Fig. 7, and the present embodiment has been described in detail each step on the basis of a upper embodiment, is described in detail to the method below in conjunction with accompanying drawing.
The method comprises the following steps:
Step S1: as shown in Figures 2 and 3, provides substrate, and described substrate comprises STI shallow trench;
Described substrate also comprises body layer 101, epitaxial loayer 102 in addition, described epitaxial loayer can comprise well region 103, STI shallow trench can be positioned at the active area of device, also well region 103 surface can be positioned at, also epitaxial loayer 102 surface can be positioned at, the present embodiment is only positioned at well region 103 surface for STI shallow trench and is described, but the present embodiment is not specifically limited the position of STI shallow trench and effect.
It should be noted that, substrate in the present embodiment can comprise semiconductor element, the silicon of such as monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe), also the semiconductor structure of mixing can be comprised, such as carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination; Also can be silicon-on-insulator (SOI).In addition, semiconductor base can also comprise other material, the sandwich construction of such as epitaxial loayer or buried layer.Although there is described herein several examples of the material that can form substrate, all the spirit and scope of the present invention can be fallen into as any material of semiconductor base.
Epitaxial loayer 102 in the present embodiment can be the epitaxial loayer adopting the once property growth in body layer 101 of CVD technique, well region 103 can be N-type well region or P type trap zone, and the thickness of epitaxial loayer and the doping type of well region, doping content etc. can require to determine according to the embody rule of device.Body layer 101 in the present embodiment can be silicon substrate.
Wherein, form the process of STI shallow trench as shown in Figures 2 and 3, can adopt mode or the CVD technique of thermal oxidation, form one deck isolating oxide layer 104 on the surface at described well region 103, the thickness of this isolating oxide layer 104 is about
well region or active area can be protected in subsequent technique from chemical spot.
Can adopt the mode of low-pressure chemical vapor phase deposition afterwards, form etching barrier layer 105 on the surface at described isolating oxide layer 104, described etching barrier layer 105 can be silicon nitride or silicon oxynitride or the mixed layer of the two.
At described etching barrier layer 105 spin coating photoresist layer 107 on the surface, in order to ensure exposure accuracy, also can form anti-reflecting layer 106 between photoresist layer 107 and etching barrier layer 105, to reduce unnecessary reflection; The mask plate with STI shallow trench figure is adopted to expose photoresist layer 107 afterwards, STI shallow trench pattern 108 is formed on the surface at described photoresist layer 107, afterwards there is the photoresist layer of STI shallow trench pattern for mask, the mode of dry etching or wet etching is adopted to form STI shallow trench 109 in described well region 103 surface, as shown in Figure 3.
Wherein, the sidewall of STI shallow trench 109 tilts, and bottom surface is round and smooth, contributes to like this improving the quality of follow-up fill process and the electrology characteristic of isolation structure.
After the etching completing STI shallow trench 109, remove photoresist, and carry out wet-cleaned in a series of chemical reagent, to ensure the clean of semiconductor device surface.After completing cleaning, the detection of the features such as the gash depth of STI shallow trench, characteristic size and defect need be carried out, to ensure the quality of device.
Above-described " in well region 103 surface " refers to that this region belongs to a part for well region 103 by the region of well region 103 surface to the certain depth of downward-extension; Described " well region 103 on the surface " refers to by region upwards, well region 103 surface, and this region does not belong to well region 103 itself.
Step S2: at sidewall and the bottom injection ion of described STI shallow trench 109, to improve the lattice structure of the base material injecting ion place, inject the distribution in ion district 110 as shown in Figure 4;
Wherein, in order to silicon that is better and substrate is had an effect, the ion that this step is injected at trenched side-wall and bottom is quadrivalent ion, and consider cost factor, described quadrivalent ion is preferably silicon ion, because silicon materials cost is lower, can save production cost.
In order to ion is injected in the better sidewall at STI shallow trench 109 and bottom, also in order to eliminate the channeling effect produced in ion implantation process, inclination certain angle can be adopted to carry out ion implantation, implant angle is between 20 °-40 °, preferred implant angle is 30 °, and the silicon ion dosage of injection is 1E13cm substantially
2, implantation dosage can have a little fluctuation within the scope of this, does not affect the effect of the embodiment of the present invention.Meanwhile, the control that injection of tilting can also be suitable is injected the degree of depth and is unlikely to excessive, and then reduces the impact on other electric property of semiconductor device.
This step is by injecting ion at the sidewall of STI shallow trench and bottom, by the shock of ion pair lattice, destroy the lattice structure of the base material injecting ion place, make the stress direction that produces between base material and STI shallow trench isolation region no longer concentrated, but by irregular dispersion, thus reduce stress, because the lattice structure of stress receptor changes, namely the factor producing stress is fundamentally changed, eliminate STI stress Producing reason, thus reduce STI stress effect, improve the performance of semiconductor device.
And, this step is the improvement carried out in the manufacturing process of STI shallow trench isolation region, very little with the correlation of layout, it also reduce the dependence to layout, and, owing to just having done low dose of ion implantation at the sidewall of STI shallow trench and bottom, therefore also very little on the impact of other electrical parameter of semiconductor device.
Step S3: form STI shallow trench isolation region on described substrate surface.
See Fig. 5, the sidewall and bottom of described STI shallow trench 109 form cushion oxide layer 111;
It should be noted that, the method for thermal oxidation or CVD can be adopted to form described cushion oxide layer 111, and the thickness of described cushion oxide layer 111 is about
cushion oxide layer 111 can improve the interfacial characteristics between base material (silicon) and STI shallow trench filler.
As shown in Figure 6, in described cushion oxide layer 111 He on described substrate surface, STI packed layer 112 is formed;
This step can adopt the mode of low-pressure chemical vapor phase deposition or high-density plasma chemical vapor deposition to form described STI packed layer 112, and wherein, STI packed layer material can be silica.
As shown in Figure 7, remove the outer unnecessary STI packed layer material of described STI shallow trench 109, form STI shallow trench isolation region 113.
Chemical mechanical milling tech can be adopted in the present embodiment to remove the unnecessary STI packed layer material of STI shallow trench 109, STI shallow trench surface is flushed, because well region is coated with the materials such as silicon nitride on the surface as etching barrier layer, can overmastication be prevented, after completing grinding, check the thickness of isolating oxide layer, particle and defect etc.
After cmp, utilizing wet etching method or additive method, remove the silicon nitride etc. of etching barrier layer, simultaneously in order to bring impurity to subsequent technique, also needing to remove the isolating oxide layer 104 outside STI shallow trench isolation region 113.
The above embodiment is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. a manufacturing method of semiconductor device, is characterized in that, comprising:
There is provided substrate, described substrate comprises STI shallow trench;
At sidewall and the bottom injection ion of described STI shallow trench, to improve the lattice structure of the base material injecting ion place;
Described substrate surface is formed STI shallow trench isolation region;
The dosage injecting ion at the sidewall of described STI shallow trench and bottom is 1E13cm
2.
2. method according to claim 1, is characterized in that, the ion injected in sidewall and the bottom of described STI shallow trench is quadrivalent ion.
3. method according to claim 2, is characterized in that, described quadrivalent ion is silicon ion.
4. method according to claim 1, is characterized in that, is 20 °-40 ° at the sidewall of described STI shallow trench and the implant angle of bottom injection ion.
5. method according to claim 4, is characterized in that, is substantially 30 ° at the sidewall of described STI shallow trench and the implant angle of bottom injection ion.
6. method according to claim 5, is characterized in that, the process that described substrate surface is formed STI shallow trench isolation region comprises:
The sidewall and bottom of described STI shallow trench form cushion oxide layer;
STI packed layer is formed in described cushion oxide layer He on described substrate surface;
Remove the outer unnecessary STI packed layer material of described STI shallow trench, form STI shallow trench isolation region.
7. method according to claim 6, is characterized in that, adopts thermal oxidation method to form described cushion oxide layer.
8. method according to claim 7, is characterized in that, adopts the mode of low-pressure chemical vapor phase deposition or high-density plasma chemical vapor deposition to form described STI packed layer.
9. method according to claim 8, is characterized in that, the mode of employing cmp removes the STI packed layer outside STI shallow trench, forms STI shallow trench isolation region.
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| CN104347471A (en) * | 2013-07-29 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| CN105206520B (en) * | 2014-06-25 | 2018-02-02 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of floating boom |
| CN109037144A (en) * | 2018-08-01 | 2018-12-18 | 武汉新芯集成电路制造有限公司 | The method for improving diffusion length effect and making MOS transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143624A (en) * | 1998-10-14 | 2000-11-07 | Advanced Micro Devices, Inc. | Shallow trench isolation formation with spacer-assisted ion implantation |
| US6150235A (en) * | 2000-01-24 | 2000-11-21 | Worldwide Semiconductor Manufacturing Corp. | Method of forming shallow trench isolation structures |
| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| CN101436565A (en) * | 2007-11-13 | 2009-05-20 | 上海华虹Nec电子有限公司 | Method for preparing shallow plow groove isolation |
| CN101887866A (en) * | 2009-05-12 | 2010-11-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow trench isolation structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100428768B1 (en) * | 2001-08-29 | 2004-04-30 | 삼성전자주식회사 | Sti type semiconductor device and method of forming the same |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143624A (en) * | 1998-10-14 | 2000-11-07 | Advanced Micro Devices, Inc. | Shallow trench isolation formation with spacer-assisted ion implantation |
| US6150235A (en) * | 2000-01-24 | 2000-11-21 | Worldwide Semiconductor Manufacturing Corp. | Method of forming shallow trench isolation structures |
| CN1722410A (en) * | 2004-07-12 | 2006-01-18 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| CN101436565A (en) * | 2007-11-13 | 2009-05-20 | 上海华虹Nec电子有限公司 | Method for preparing shallow plow groove isolation |
| CN101887866A (en) * | 2009-05-12 | 2010-11-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow trench isolation structure |
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Effective date of registration: 20171130 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |