WO2014065031A1 - バランサ回路およびこれを用いたバッテリユニット - Google Patents
バランサ回路およびこれを用いたバッテリユニット Download PDFInfo
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- WO2014065031A1 WO2014065031A1 PCT/JP2013/074299 JP2013074299W WO2014065031A1 WO 2014065031 A1 WO2014065031 A1 WO 2014065031A1 JP 2013074299 W JP2013074299 W JP 2013074299W WO 2014065031 A1 WO2014065031 A1 WO 2014065031A1
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- state
- balancer circuit
- capacitive element
- balance
- voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/4207—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells for several batteries or cells simultaneously or sequentially
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
- H02J7/0016—Circuits for equalisation of charge between batteries using shunting, discharge or bypass circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M2010/4271—Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Definitions
- the present invention relates to a balancer circuit that corrects a balance state between secondary batteries and a battery unit using the balancer circuit.
- large-scale power storage systems using storage batteries have been developed.
- the development of large-scale power storage systems is carried out for the purpose of, for example, peak shifts due to recent tight power demand, means as a backup power source in an emergency, or stable use of unstable environmental energy such as solar power generation. ing.
- a battery pack is configured by using a plurality of single cells in which medium-sized single cells of about 10 Ah to 20 Ah are combined in series or in parallel, and this battery pack is used in a power storage system.
- FIG. 5 shows a configuration example of a battery unit provided with such a balancer circuit.
- the battery unit 101 shown in FIG. 5 includes a battery pack 102 in which the single cells (121 to 123) are connected in series, and a balancer circuit 103 that corrects the balance state (voltage balance state) between the single cells. Yes.
- the balancer circuit 103 includes an oscillator 131, a switch unit 132, and capacitive elements (133a, 133b).
- the switch unit 132 is configured to switch the connection state of both ends of the capacitive element 133a between the states including the state connected to both ends of the unit cell 123 and the state connected to both ends of the unit cell 122. ing. Further, the switch unit 132 is configured to switch the connection state of both ends of the capacitive element 133b between the states including the state connected to both ends of the unit cell 122 and the state connected to both ends of the unit cell 121. Has been.
- the balancer circuit 103 executes a switching operation for repeatedly performing the switching. Due to this switching operation, the electric charge is transferred through the capacitive elements (133a, 133b) so that the voltage variation of the single cells (121 to 123) is reduced, and the balance state between the single cells is corrected.
- the power consumption of the balancer circuit as described above increases as the operation increases (especially as the switching operation cycle is shorter).
- the power consumption of the balancer circuit becomes large, the self-discharge in the battery unit is accelerated correspondingly, and the function as a storage battery deteriorates.
- the balancer circuit has a function of detecting the balance state between the single cells.
- the present invention corrects the balance state between the secondary batteries by executing a switching operation, and can detect the balance state, and a battery including the balancer circuit The purpose is to provide units.
- the balancer circuit according to the present invention is connected to a battery pack in which a plurality of secondary batteries are connected in series, and the connection state of the capacitive element and both ends of the capacitive element is connected to both ends of any of the secondary batteries.
- a switch unit that switches between each state including a state that is connected to both ends of the other secondary battery, and the plurality of secondary batteries by performing a switching operation that repeatedly performs the switching
- a balancer circuit that corrects a voltage balance state between the capacitor elements, and includes a detection unit that detects the balance state by detecting the magnitude of an overshoot component in a voltage waveform connected to the capacitive element.
- the capacitive element is a component having a lead wire connected to an electrode of the capacitive element
- the detection unit includes a ferrite bead core passed through the lead wire, and the lead wire And an electric wire passed through the ferrite bead core, and the balance state may be detected based on a voltage signal output from the electric wire.
- the above configuration may be configured to control the switching operation based on the detection result of the balance state. More specifically, the above configuration may be configured such that the period of the switching operation is adjusted based on the detection result of the balance state.
- the battery unit according to the present invention includes a battery pack in which a plurality of secondary batteries are connected in series, and a balancer circuit having the above-described configuration that corrects a voltage balance state between the plurality of secondary batteries. And According to this configuration, it is possible to enjoy the advantages of the balancer circuit configured as described above.
- the balancer circuit according to the present invention can detect the balance state while correcting the balance state between the secondary batteries by executing the switching operation. Further, according to the battery unit of the present invention, it is possible to receive the advantages of the balancer circuit of the present invention.
- FIG. 1 is a configuration diagram of a battery unit 1 according to the present embodiment. As shown in the figure, the battery unit 1 includes a battery pack (battery pack module) 2 and a balancer circuit 3. FIG. 2 schematically shows a part of the balancer circuit 3 mounted.
- a battery pack battery pack module
- FIG. 2 schematically shows a part of the balancer circuit 3 mounted.
- the battery pack 2 has a configuration in which a plurality of single cells (21 to 23) are connected in series, and is connected to a DC power supply circuit (not shown) for charging and discharging the battery pack 2. More specifically, the positive electrode of the single battery 21 is connected to the negative electrode of the single battery 22, and the positive electrode of the single battery 22 is connected to the negative electrode of the single battery 23. The negative electrode of the single cell 21 is connected to the negative electrode P ⁇ (which is set to the ground potential) of the DC power supply circuit described above, and the positive electrode of the single cell 23 is connected to the positive electrode P + of the DC power supply circuit described above.
- Each cell (21 to 23) is a secondary battery (for example, a lithium ion battery) that can be repeatedly charged and discharged.
- the battery pack 2 may be fixed to the battery unit 1 or may be detachable.
- the balancer circuit 3 includes an oscillator 31, a switch unit 32, each capacitive element (33a, 33b), each ferrite bead core (34a, 34b), an electric wire 35, an integration circuit 36, a diode 37, a mounting substrate 38, and the like. Yes.
- the oscillator 31 continuously outputs a pulse signal S1 (a signal in which H level and L level appear alternately) toward the switch unit 32.
- the oscillator 31 changes the frequency of the pulse signal S1 according to the control signal S2 input from the integrating circuit 36 side. How the frequency of the pulse signal S1 is changed will be apparent from the following description.
- the switch unit 32 has switches (32a to 32c). Each switch (32a to 32c) is configured by using, for example, an FET device, and has terminals P, Q, and X.
- Each switch (32a to 32c) has a PX connection state Sp (terminal X is connected to terminal P and terminal Q is not connected to any terminal), and QX connection state Sq (terminal X is terminal). Q can be switched between each state of a state where the terminal P is not connected to any terminal) and a non-connected state Sn (a state where none of the terminals are connected to other terminals). It is configured.
- terminal P of the switch 32 a is connected to the positive electrode of the unit cell 23.
- the terminal Q of the switch 32 a and the terminal P of the switch 32 b are connected to the negative electrode of the unit cell 23 and the positive electrode of the unit cell 22.
- the terminal Q of the switch 32b and the terminal P of the switch 32c are connected to the negative electrode of the unit cell 22 and the positive electrode of the unit cell 21.
- the terminal Q of the switch 32c is connected to the negative electrode of the unit cell 21.
- Each capacitive element (33a, 33b) is an element having a predetermined electric capacity, for example, an electrolytic capacitor.
- Each capacitive element (33a, 33b) is a component in which two lead wires (terminal legs) are extended from a main body portion in which both electrodes are built. These lead wires are a lead wire connected to one electrode and a lead wire connected to the other electrode.
- Each capacitive element (33a, 33b) forms part of the balancer circuit 3 by attaching the two lead wires to the mounting substrate.
- one end (one electrode) of the capacitive element 33a is connected to the terminal X of the switch 32a.
- the other end (the other electrode) of the capacitive element 33a is connected to the terminal X of the switch 32b and one end (one electrode) of the capacitive element 33b.
- the other end (the other electrode) of the capacitive element 33b is connected to the terminal X of the switch 32c.
- the ferrite bead core 34a is passed through one of the lead wires of the capacitive element 33a (the lead wire connected to the terminal X of the switch 32a).
- the ferrite bead core 34a is sandwiched between the main body portion of the capacitive element 33a and the mounting substrate 38.
- the ferrite bead core 34b is passed through one of the lead wires of the capacitive element 33b (the lead wire connected to the terminal X of the switch 32b).
- the ferrite bead core 34b is sandwiched between the main body portion of the capacitive element 33b and the mounting substrate 38.
- the electric wire 35 is, for example, a UEW line, and is passed through the ferrite bead core 34a and the ferrite bead core 34b in this order, as shown in FIG.
- the other end side of the electric wire 35 is U-turned and tied to the electric wire 35 itself so as not to come out of the ferrite bead core 34a.
- the electric wire 35 is highly flexible, and the operation of passing the electric wire 35 through each ferrite bead core (34a, 34b) is easy. In this way, one lead wire of the capacitive element 33a is inserted into the ferrite bead core 34a, and the electric wire 35 is put in a state along the lead wire. Also, one lead wire of the capacitive element 33b is inserted into the ferrite bead core 34b, and the electric wire 35 is put in a state along the lead wire.
- the integrating circuit 36 is a circuit provided on the mounting substrate 38 and includes a resistance element R and a capacitance element C.
- An electric wire 35 is connected to one end of the resistor element R, and the other end of the resistor element R is grounded via the capacitor element C and connected to the anode of the diode 37.
- the cathode of the diode 37 is connected to the oscillator 31.
- the integrating circuit 36 functions to integrate the voltage signal input from the electric wire 35 and output a voltage signal corresponding to the result to the oscillator 31 via the diode 37.
- the battery unit 1 having the above-described configuration operates so as to charge the battery pack 2 using the power received from the DC power supply circuit described above or supply the power discharged from the battery pack 2 to the DC power supply circuit. .
- the balance circuit 3 corrects the voltage balance state between the single cells (21 to 23) (the degree of balance is good or bad, and may hereinafter be referred to as “balance state between the single cells”). To work.
- the switch unit 32 performs a switching operation that repeats a series of operations in the following steps A to D.
- Step A is an operation of switching the state of each switch (32a to 32c) to the unconnected state Sn. While the operation of Step A is performed and the switches (32a to 32c) are in the non-connected state Sn, the capacitors (33a, 33b) are not charged or discharged, and the capacitors (33a, 33b) are not charged. Is kept charged by a certain amount of charge.
- Step B The operation of Step B is performed after the operation of Step A, and the state of each switch (32a to 32c) is switched to the PX connection state Sp. While the operation of Step B is performed and each switch (32a to 32c) is in the PX connection state Sp, in each capacitive element (33a, 33b) according to the voltage of the unit cell in the battery pack 2. Charges enter and exit (apparent charge transfer through the capacitive element).
- the electric charge enters and exits the capacitive element 33a so that the voltage V3 of the unit cell 23 and the voltage between both electrodes of the capacitive element 33a are balanced.
- the electric charge enters and exits the capacitive element 33b so that the voltage V2 of the unit cell 22 and the voltage between both electrodes of the capacitive element 33b are balanced.
- Step C The operation of Step C is performed after the operation of Step B, and switches the state of each switch (32a to 32c) to the unconnected state Sn. While the operation of Step C is performed and the switches (32a to 32c) are in the non-connected state Sn, the capacitors (33a and 33b) are not charged or discharged, and the capacitors (33a and 33b) are not charged. Is kept charged by a certain amount of charge.
- Step D is an operation of switching the state of each switch (32a to 32c) to the QX connection state Sq. While the operation of step D is performed and each switch (32a to 32c) is in the QX connection state Sq, according to the voltage of the unit cell in the battery pack 2, each capacitor element (33a, 33b) Charges enter and exit (apparent charge transfer through the capacitive element).
- the electric charge in and out of the capacitive element 33a is performed so that the voltage V2 of the unit cell 22 and the voltage between both electrodes of the capacitive element 33a are balanced.
- the electric charge enters and exits the capacitive element 33b so that the voltage V1 of the unit cell 21 and the voltage between both electrodes of the capacitive element 33b are balanced.
- step D the operation of step A is performed.
- steps A to D are sequentially performed in synchronization with the pulse signal S1 received from the oscillator 31 (for example, every time an H level pulse arrives). By executing the switching operation described above, the balance state between the single cells is corrected.
- the voltage waveforms at one end of the capacitive element 33a (fixed point TP1 shown in FIG. 1) and one end of the capacitive element 33b (fixed point TP1a shown in FIG. 1) An overshoot component corresponding to the balance state is included.
- the fixed point TP1 is an example of a location connected to the capacitive element 33a, and the fixed point TP1a can be said to be an example of a location connected to the capacitive element 33b.
- FIG. 3 exemplifies the voltage waveform at the fixed point TP1 under the situation where the switching operation is performed.
- FIG. 3 shows (a) a voltage waveform when the balance between the cells is good and (b) a voltage waveform when the balance between the cells is bad.
- the illustration of the voltage waveform at the fixed point TP1a is omitted, it basically conforms to the waveform shown in FIG.
- the timing Ta indicates the timing at which the operation of step A is performed
- the timing Tb indicates the timing at which the operation of step B is performed
- the timing Tc indicates the timing at which the operation of step C is performed
- the timing Td indicates the step.
- the timing at which operation D is performed is shown.
- the switching operation is an operation in which a series of operations of Steps A to D are repeated with a period Pe.
- the balance between the single cells is poor, that is, when the voltage variation between the single cells (21 to 23) is large, as shown in FIG. 3B, the fixed point TP1 (or the fixed point TP1a)
- the overshoot component in the voltage waveform increases.
- the overshoot component shown in the example of FIG. 3 occurs when the operation of Step B is performed.
- the balance between the single cells is good, that is, when the voltage variation between the single cells (21 to 23) is relatively small, as shown in FIG. The shoot component is very small.
- the balancer circuit 3 has a function of detecting the balance state between the single cells using this phenomenon. That is, the balancer circuit 3 has a function of detecting the magnitude of the overshoot component in the voltage waveform at the fixed point TP1 (or the fixed point TP1a) as an index of the balance state between the single cells.
- each ferrite bead core (34a, 34b), electric wire 35, and integrating circuit 36 This function is mainly realized by each ferrite bead core (34a, 34b), electric wire 35, and integrating circuit 36. That is, the ferrite bead core 34 a causes electromagnetic induction corresponding to the overshoot component in the voltage waveform at the fixed point TP 1, and spatially induces this overshoot component to the electric wire 35. Further, the ferrite bead core 34 b generates electromagnetic induction corresponding to the overshoot component in the voltage waveform at the fixed point TP1 a, and spatially induces this overshoot component to the electric wire 35.
- the overshoot component in the voltage waveform of the fixed point TP1 (or the fixed point TP1a) is detected. That is, when the voltage waveform at the fixed point TP1 (or the fixed point TP1a) is in the state shown in FIG. 4A, the voltage waveform in the electric wire 35 (voltage waveform at the fixed point TP2 shown in FIG. 1) is shown in FIG. Thus, the voltage waveform represents the result of the detection.
- the integration circuit 36 When a signal having such a voltage waveform is input to the integration circuit 36, the integration circuit 36 outputs a voltage signal obtained by integrating the signal. That is, the voltage waveform output from the integration circuit 36 (voltage waveform at the fixed point TP3 shown in FIG. 1) is a voltage waveform of the DC voltage obtained by the integration, as illustrated in FIG. 4C.
- the magnitude of this DC voltage reflects the magnitude of the overshoot component in the voltage waveform at the fixed point TP1 (or fixed point TP1a). That is, the smaller the overshoot component (the better the balance between the cells), the smaller the DC voltage, and the greater the overshoot component (the worse the balance between the cells), the greater the DC voltage.
- the balancer circuit 3 can easily detect the balance state between the single cells by obtaining the voltage waveform of the DC voltage.
- the voltage waveform signal at the fixed point TP3 is input to the oscillator 31 as the control signal S2.
- the oscillator 31 changes the frequency of the pulse signal S1 according to the voltage value of the control signal S2. More specifically, the higher the voltage value of the control signal S2 (that is, the better the balance between the single cells), the lower the frequency of the pulse signal S1, and the lower the voltage value of the control signal S2 (that is, the single cell). The worse the balance between them), the higher the frequency of the pulse signal S1.
- the specific form of the frequency change is not particularly limited.
- the frequency of the pulse signal S1 may be changed depending on whether or not the voltage value of the control signal S2 exceeds a predetermined threshold, and the pulse signal S1 may be changed according to the voltage value of the control signal S2.
- the frequency may be changed in an analog manner.
- the higher the frequency of the pulse signal S1 the shorter the period Pe of the switching operation performed by the switch unit 32 (the higher the operating frequency). Therefore, the balance state of the single cells is corrected more frequently, and accordingly, the balance state can be improved quickly and sufficiently.
- the lower the frequency of the pulse signal S1 the longer the period Pe of the switching operation performed by the switch unit 32. Therefore, although the frequency of the correction is low, the power consumption required for the switching operation can be reduced accordingly.
- the balancer circuit 3 efficiently executes the correction of the balance state between the single cells.
- the balancer circuit 3 shortens the period Pe of the switching operation when the balance state between the single cells is relatively bad, so that the balance state is improved quickly and sufficiently.
- the balancer circuit 3 increases the period Pe of the switching operation to suppress power consumption required for the switching operation.
- the balancer circuit 3 only increases the period Pe of the switching operation as described above, and does not stop the switching operation. Therefore, means for restarting the switching operation when the balance state between the single cells deteriorates is unnecessary.
- the balance state between the single cells even if the balance state between the single cells is once improved, there may be a situation where the balance state between the single cells deteriorates due to variations in the charge / discharge waveform during subsequent charge / discharge. If the specification is such that the switching operation is stopped when the balance between the cells is good, in order to maintain the balance between the cells properly even in such a case, the balance between the cells A separate means is required to restart the switching operation when it deteriorates.
- the means there are means for detecting the start of charging and discharging, and means for starting the switching operation in accordance with the detection result.
- the switching operation is continued even when the balance state between the single cells is good, and when the balance state between the single cells deteriorates, the voltage of the control signal S2 The value automatically increases. Since the balancer circuit 3 can automatically shorten the period Pe of the switching operation by utilizing this phenomenon, the balancer circuit 3 does not require another external control trigger signal or the like and corrects the balance state between the cells. It is possible to activate the operation.
- the balancer circuit 3 of the present embodiment is connected to the battery pack 2 in which a plurality of single cells (21 to 23) are connected in series, and each capacitor element (33a, 33b) and the switch unit 32 are connected to each other. I have.
- the switch unit 32 switches the connection state of both ends of the capacitive element 33a between the states including the state connected to both ends of the unit cell 23 and the state connected to both ends of the unit cell 22, and The connection state of both ends is switched between each state including a state where both ends of the unit cell 22 are connected and a state where both ends of the unit cell 21 are connected.
- the balancer circuit 3 is configured to correct the balance state of each unit cell by executing a switching operation that repeatedly performs such switching.
- the balancer circuit 3 detects the balance state between the single cells by detecting the magnitude of the overshoot component in the voltage waveform of the fixed point TP1 connected to the capacitive element 33a (or the fixed point TP1a connected to the capacitive element 33b). Part (detection part). Therefore, according to the balancer circuit 3, it is possible to detect the balance state while correcting the balance state between the single cells by executing the switching operation.
- the balancer circuit 3 controls the switching operation based on the detection result of the balance state between the single cells. More specifically, the balancer circuit 3 adjusts the cycle of the switching operation based on the detection result of the balance state between the single cells. As a result, the balancer circuit 3 efficiently performs the correction of the balance state between the single cells. In addition, you may make it utilize the detection result of the balance state between each single cell for other various uses.
- the configuration of the balancer circuit 3 of this embodiment can be realized with relatively few modifications based on the configuration of the conventional balancer circuit (see FIG. 5). Therefore, it is relatively easy to modify such a conventional balancer circuit so as to have the configuration of the present embodiment, and thereby, it is possible to exhibit the same effect as that of the present embodiment.
- the balancer circuit 3 of the present embodiment corresponds to a battery pack in which three unit cells are connected in series as an example, but a battery pack in which two unit cells (secondary cells) are connected in series.
- the battery pack may be a battery pack in which four or more single cells (secondary batteries) are connected in series. In any case, it can be handled by appropriately setting the configuration of the switch unit 32, the number of capacitative elements and ferrite bead cores according to the number of single cells (secondary cells) in the battery pack. is there.
- the switching operation in the present embodiment is an operation in which a series of operations of Steps A to D are repeated.
- the switching operation may be an operation in which the operations in Steps A and C described above are not performed, and the operations in Step B and Step D are alternately repeated.
- the present invention can be used for a battery unit or the like.
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Abstract
Description
図1は、本実施形態に係るバッテリユニット1の構成図である。本図に示すようにバッテリユニット1は、バッテリパック(バッテリパックモジュール)2、およびバランサ回路3を備えている。また図2は、バランサ回路3の一部の実装形態を、模式的に示している。
次にバランス回路3の動作について、より詳細に説明する。スイッチ部32は、以下のステップA~Dの一連の動作を繰返すスイッチング動作を実行する。
以上に説明した通り、本実施形態のバランサ回路3は、複数の単電池(21~23)を直列に接続させたバッテリパック2に接続され、各容量素子(33a、33b)およびスイッチ部32を備えている。なおスイッチ部32は、容量素子33aの両端の接続状態を、単電池23の両端に接続させた状態および単電池22の両端に接続させた状態を含む各状態の間で切替え、容量素子33bの両端の接続状態を、単電池22の両端に接続させた状態および単電池21の両端に接続させた状態を含む各状態の間で切替える。バランサ回路3は、このような切替を繰返し行うスイッチング動作の実行により、各単電池のバランス状態を補正するようになっている。
2 バッテリパック
21~23 単電池(二次電池)
3 バランサ回路
31 発振器
32 スイッチ部
32a~32c スイッチ
33a、33b 容量素子
34a、34b フェライトビーズコア
35 電線
36 積分回路
37 ダイオード
38 実装基板
C 容量素子
R 抵抗素子
Claims (5)
- 複数の二次電池を直列に接続させたバッテリパックに接続され、
容量素子と、
前記容量素子の両端の接続状態を、何れかの前記二次電池の両端に接続させた状態および他の前記二次電池の両端に接続させた状態を含む各状態、の間で切替えるスイッチ部と、を備え、
前記切替を繰返し行うスイッチング動作の実行により、前記複数の二次電池間の電圧のバランス状態を補正するバランサ回路であって、
前記容量素子に繋がる箇所の電圧波形におけるオーバーシュート成分の大きさ検出することにより、前記バランス状態を検出する検出部を備えたことを特徴とするバランサ回路。 - 前記容量素子は、該容量素子の電極に繋がるリード線を有する部品であり、
前記検出部は、
前記リード線に通されたフェライトビーズコアと、
前記リード線とともに前記フェライトビーズコアに通された電線と、を有し、
前記電線から出力される電圧信号に基づいて、前記バランス状態を検出することを特徴とする請求項1に記載のバランサ回路。 - 前記バランス状態の検出結果に基づいて、前記スイッチング動作を制御することを特徴とする請求項2に記載のバランサ回路。
- 前記バランス状態の検出結果に基づいて、前記スイッチング動作の周期を調節することを特徴とする請求項3に記載のバランサ回路。
- 複数の二次電池を直列に接続させたバッテリパックと、
該複数の二次電池間の電圧のバランス状態を補正する請求項1から請求項4の何れかに記載のバランサ回路と、
を備えたことを特徴とするバッテリユニット。
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CN201380055727.3A CN104756355A (zh) | 2012-10-24 | 2013-09-10 | 均衡电路和使用其的电池单元 |
US14/432,259 US20150244189A1 (en) | 2012-10-24 | 2013-09-10 | Balancer circuit and battery unit using same |
JP2014543183A JP5964982B2 (ja) | 2012-10-24 | 2013-09-10 | バランサ回路およびこれを用いたバッテリユニット |
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US (1) | US20150244189A1 (ja) |
JP (1) | JP5964982B2 (ja) |
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Cited By (2)
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WO2020241214A1 (ja) * | 2019-05-27 | 2020-12-03 | 株式会社オートネットワーク技術研究所 | 車載用バックアップ電源装置 |
JP7067139B2 (ja) | 2018-03-08 | 2022-05-16 | いすゞ自動車株式会社 | セルバランス制御装置およびセルバランス制御システム |
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US10447045B2 (en) * | 2015-01-30 | 2019-10-15 | Sony Corporation | Power control device, power control method, and power control system |
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- 2013-09-10 WO PCT/JP2013/074299 patent/WO2014065031A1/ja active Application Filing
- 2013-09-10 JP JP2014543183A patent/JP5964982B2/ja active Active
- 2013-09-10 US US14/432,259 patent/US20150244189A1/en not_active Abandoned
- 2013-09-10 CN CN201380055727.3A patent/CN104756355A/zh active Pending
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JP7067139B2 (ja) | 2018-03-08 | 2022-05-16 | いすゞ自動車株式会社 | セルバランス制御装置およびセルバランス制御システム |
WO2020241214A1 (ja) * | 2019-05-27 | 2020-12-03 | 株式会社オートネットワーク技術研究所 | 車載用バックアップ電源装置 |
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JP7059982B2 (ja) | 2019-05-27 | 2022-04-26 | 株式会社オートネットワーク技術研究所 | 車載用バックアップ電源装置 |
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JP5964982B2 (ja) | 2016-08-03 |
CN104756355A (zh) | 2015-07-01 |
JPWO2014065031A1 (ja) | 2016-09-08 |
US20150244189A1 (en) | 2015-08-27 |
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