WO2014063379A1 - Mosfet的制造方法 - Google Patents

Mosfet的制造方法 Download PDF

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Publication number
WO2014063379A1
WO2014063379A1 PCT/CN2012/083748 CN2012083748W WO2014063379A1 WO 2014063379 A1 WO2014063379 A1 WO 2014063379A1 CN 2012083748 W CN2012083748 W CN 2012083748W WO 2014063379 A1 WO2014063379 A1 WO 2014063379A1
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semiconductor layer
shallow trench
layer
semiconductor
forming
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French (fr)
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尹海洲
秦长亮
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US14/759,324 priority Critical patent/US20150380297A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a stress-enhanced MOSFET. Background technique
  • MOSFETs metal oxide semiconductor field effect transistors
  • the performance of the semiconductor material e.g., mobility
  • the device performance of the MOSFET itself e.g., threshold voltage
  • the carrier mobility can be increased, thereby reducing the on-resistance and increasing the switching speed of the device.
  • a tensile stress should be applied to the channel region along the longitudinal direction of the channel region, and a compressive stress is applied to the channel region along the lateral direction of the channel region to enhance the carrier as a carrier.
  • the mobility of electrons Conversely, when the transistor is a P-type MOSFET, the channel region should be stressed along the longitudinal direction of the channel region, and a tensile stress is applied to the channel region along the lateral direction of the channel region to enhance the carrier as a carrier.
  • the mobility of holes is
  • the formation of the source and drain regions using a semiconductor material different from the material of the semiconductor substrate can produce the desired stress.
  • the Si:C source and drain regions formed on the Si substrate can act as a stressor, and a tensile stress is applied to the channel region along the longitudinal direction of the channel region.
  • the SiGe source and drain regions formed on the Si substrate can serve as a stressor, and the channel region is subjected to a compressive stress along the longitudinal direction of the channel region.
  • FIGS 1-4 show schematic diagrams of semiconductor structures for fabricating various stages of a stress-enhanced MOSFET in accordance with methods of the prior art, wherein the semiconductor structures are shown in the longitudinal direction of the channel region in Figures la, 2a, 3a, 4a
  • a cross-sectional view of the semiconductor structure along the lateral direction of the channel region is shown in Figures 3b, 4b
  • a top view of the semiconductor structure is shown in Figures lb, 2b, 3c, 4c.
  • line AA indicates the longitudinal direction along the channel region
  • line BB indicates the intercepting position in the lateral direction of the channel region.
  • the method begins with the semiconductor structure shown in FIGS. 1a and 1b, in which a shallow trench isolation 102 is formed in the semiconductor substrate 101 to define an active region of the MOSFET, and a gate surrounded by the sidewall 105 is formed on the semiconductor substrate 101.
  • the stacked, gate stack includes a gate dielectric 103 and a gate conductor 104.
  • the semiconductor substrate 101 is etched to a desired depth, thereby forming an opening at a position corresponding to the source and drain regions of the semiconductor substrate 101, as shown in FIG. 2a and 2b are shown.
  • the semiconductor layer 106 is epitaxially grown to form a source region and a drain region. A portion of the semiconductor substrate 101 below the gate dielectric 103 and between the source and drain regions will serve as a channel region.
  • the semiconductor layer 106 grows from the surface of the semiconductor substrate 101 and is selective. That is, the growth rate of the semiconductor layer 106 on the crystal l ine surface of the semiconductor substrate 101 is different.
  • the semiconductor layer 106 grows the slowest on the ⁇ 1 1 1 ⁇ crystal plane of the semiconductor substrate 101.
  • the formed semiconductor layer 106 includes not only the (100) main surface parallel to the surface of the semiconductor substrate 101, but also the ⁇ 1 1 1 ⁇ facet at a position adjacent to the shallow trench isolation 102 and the side wall 105. (facet), this is called the edge effect of the growth of the semiconductor layer 106, as shown in Figures 3a, 3b and 3c.
  • the facet of the semiconductor layer 106 is undesirable because it results in an increase in its free surface, causing stress in the semiconductor layer 106 to be released, thereby reducing the stress applied to the channel region.
  • silicidation is performed on the surface of the semiconductor layer 106 to form a metal silicide layer 107 as shown in Figs. 4a, 4b and 4c. This silicidation consumes a portion of the semiconductor material of the semiconductor layer 106. Due to the presence of the small facets of the semiconductor layer 106, silicidation can proceed along the small facets, possibly eventually reaching the semiconductor substrate 101.
  • silicidation in the semiconductor substrate 101 is undesirable because it may form a metal silicide in the junction region, resulting in an increase in junction leakage.
  • a method of fabricating a MOSFET comprising: epitaxially growing a first semiconductor layer on a semiconductor substrate; epitaxially growing a second semiconductor layer on the first semiconductor layer; in the first semiconductor layer and the second semiconductor layer Forming shallow trench isolation for defining an active region of the MOSFET; forming a gate stack and a sidewall surrounding the gate stack on the second semiconductor; using a shallow trench isolation, a gate stack, and a sidewall spacer as a hard mask Forming an opening in the second semiconductor layer; growing the third semiconductor layer by using the bottom surface and the sidewall of the opening as a growth seed layer, wherein the material of the third semiconductor layer is different from the material of the second semiconductor layer; and performing ion on the third semiconductor layer Injection is performed to form source and drain regions.
  • the method applies stress to the channel region in the second semiconductor layer using the source and drain regions formed by the third semiconductor layer. Since the bottom surface and the side walls of the opening are growth seed layers during epitaxial growth, the third semiconductor layer can completely fill the openings of the second semiconductor layer. The U 1 1 ⁇ facet of the third semiconductor layer is only located in its continued growth portion, thereby suppressing the influence of the edge effect.
  • FIGS 1-4 show schematic diagrams of semiconductor structures for fabricating various stages of a stress-enhanced MOSFET in accordance with methods of the prior art, wherein the semiconductor structures are shown in the longitudinal direction of the channel region in Figures la, 2a, 3a, 4a
  • Figures 3b, 4b In cross-section, a cross-sectional view of the semiconductor structure along the lateral direction of the channel region is shown in Figures 3b, 4b, and a top view of the semiconductor structure is shown in Figures lb, 2b, 3c, 4c.
  • FIGS. 1b, 12b show schematic diagrams of semiconductor structures at various stages of fabricating stress-enhanced MOSFETs in accordance with an embodiment of the method of the present invention, wherein semiconductor structures are shown along trenches in Figures 5-8, 9a, 10a, 11a, 12a
  • FIGS. 1b, 12b A cross-sectional view in the longitudinal direction of the track region, a cross-sectional view of the semiconductor structure along the lateral direction of the channel region is shown in FIGS. 1b, 12b, and a top view of the semiconductor structure is shown in FIGS. 9b, 10b, 1 lc, 12c. .
  • semiconductor structure refers to the general term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed;
  • longitudinal direction of the channel region refers to the source region to The drain region and the direction, or the opposite direction;
  • transverse direction of the channel region is a direction perpendicular to the longitudinal direction of the channel region in a plane parallel to the main surface of the semiconductor substrate.
  • the longitudinal direction of the channel region is generally along the ⁇ 110> direction of the silicon wafer, and the lateral direction of the channel region is generally along the ⁇ 011> direction of the silicon wafer.
  • the semiconductor material includes, for example, a group III-V semiconductor such as GaAs, InP, GaN, SiC, and a Group IV semiconductor such as Si, Ge.
  • the gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, RuOx and the various conductive materials described above The combination.
  • conductive materials such as TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni 3
  • the gate dielectric may be composed of 510 2 or a material having a dielectric constant greater than SiO 2 , and includes, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, Si0 2 . , Hf0 2 Zr0 2, A1 2 0 3, Ti0 2, L3 ⁇ 40 3, e.g. nitrides include Si, silicates such as including Hf Si0x, e.g. aluminates including LaA10 3, titanates include, for example SrTi0 3, oxynitrides For example, SiON is included.
  • the gate dielectric may be formed not only by materials well known to those skilled in the art, but also materials developed for the gate dielectric in the future.
  • the following steps shown in Figures 5 through 12 are performed to fabricate a stress-enhanced MOSFET, in which cross-sectional views of semiconductor structures at different stages are shown. If necessary, a top view is also shown in the drawing, in which the line AA is used to indicate the intercept position in the longitudinal direction of the channel region, and the line BB is used to indicate the intercept position in the lateral direction of the channel region.
  • the method begins with the semiconductor structure shown in FIG. 5, in which a first semiconductor layer 202, a second semiconductor layer 203, a pad oxide layer 204, and a pad nitride layer 205 are sequentially formed on the semiconductor substrate 201.
  • the semiconductor substrate 201 is composed of, for example, Si.
  • the first semiconductor layer 202 is an epitaxially grown layer, for example, an atomic percentage of Ge is about It is composed of 10-15% SiGe and has a thickness of about 30-50 nm.
  • the second semiconductor layer 203 is an epitaxially grown layer, for example composed of Si, having a thickness of about 100 to 200 nm.
  • the pad oxide layer 204 is composed of, for example, silicon oxide and has a thickness of about 2 to 5 nm.
  • the pad nitride layer 205 is composed, for example, of silicon nitride and has a thickness of about 10 to 50 nm. As is known, the pad oxide layer 204 can alleviate stress between the second semiconductor layer 203 and the pad nitride layer 205.
  • the substrate nitride layer 205 is used as a hard mask in the subsequent etching step.
  • the first semiconductor layer 202 and the second semiconductor layer 203 are epitaxially grown by a known deposition process such as electron beam evaporation (EBM), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, or the like.
  • EBM electron beam evaporation
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • sputtering or the like.
  • the pad oxide layer 204 is formed by thermal oxidation.
  • the pad nitride layer 205 is formed by chemical vapor deposition.
  • a photoresist layer (not shown) is formed on the pad nitride layer 205 by spin coating, and the photoresist layer is formed into a shallow trench isolation by a photolithography process including exposure and development therein. pattern.
  • a photoresist layer as a mask, by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution therein, sequentially removing from top to bottom Pad nitride layer 205 and exposed portions of pad oxide layer 204.
  • the photoresist layer is removed by dissolving or ashing in a solvent.
  • the exposed portion of the second semiconductor layer 203 is removed by a known dry etching or wet etching using the pad nitride layer 205 and the pad oxide layer 204 as a hard mask, so that the second semiconductor layer 203 is removed.
  • the first portion of the shallow trench is formed, as shown in FIG.
  • the etching selectively removes the material of the second semiconductor layer 203 with respect to the material of the first semiconductor layer 202, thereby stopping at the surface of the first semiconductor layer 202.
  • the etch is anisotropic, and by selecting a suitable etchant and etching conditions, the width of the top portion of the first portion of the shallow trench is greater than the width of the bottom portion. That is, the sidewalls of the first portion of the shallow trench are sloped.
  • the angle between the top surface of the first portion of the shallow trench and the sidewall is less than 70 °. It should be noted that it is well known to those skilled in the art that the morphology of the etched opening can be varied by selecting a suitable etchant and etching conditions such that the opening has steep side walls or sloped sidewalls.
  • the exposed portion of the first semiconductor layer 202 is removed through the first portion of the shallow trench by known dry etching or wet etching, thereby forming a second portion of the shallow trench in the first semiconductor layer 202, such as Figure 7 shows.
  • the etching selectively removes the material of the first semiconductor layer 202 with respect to the materials of the second semiconductor layer 203 and the semiconductor substrate 201, thereby stopping at the surface of the semiconductor substrate 201.
  • the etch is isotropic such that the second portion of the shallow trench is not only directly below the first portion of the shallow trench but also partially extends to the second Below the semiconductor layer 203.
  • a layer of insulating material (not shown) is formed on the surface of the semiconductor structure by a known deposition process.
  • the layer of insulating material fills the first portion and the second portion of the shallow trench.
  • the portion of the insulating material layer outside the shallow trench is removed by chemical mechanical polishing (CMP), and the pad nitride layer 203 and the pad oxide layer 204 are further removed.
  • CMP chemical mechanical polishing
  • the portion of the insulating material layer remaining in the shallow trench forms a shallow trench isolation 206, as shown in FIG.
  • the shallow trench isolation 206 defines an active region of the MOSFET and includes a first portion and a second portion corresponding to the first and second portions of the shallow trench, respectively.
  • the sidewalls of the first portion of the shallow trench isolation 206 are sloped, and a portion of the second semiconductor layer 203 adjacent to the shallow trench isolation 206 may remain in a subsequent etching step.
  • the second portion of the shallow trench isolation 206 extends the bottom of the shallow trench isolation 206 to improve its electrical insulation properties.
  • a dielectric layer and a polysilicon layer are sequentially formed on the surface of the semiconductor structure by a known deposition process, patterned to form a gate stack including a gate dielectric 207 and a gate conductor 208.
  • a nitride layer of, for example, 10 to 50 nm is deposited on the entire surface of the semiconductor structure by the above-described known process, and then the sidewall spacer 209 surrounding the gate stack is formed by anisotropic etching, as shown in FIGS. 9a and 9b. .
  • the etch is anisotropic, and the shape of the opening is substantially identical to the pattern of the hard mask by selecting a suitable etchant and etching conditions. That is, the side walls of the opening are steep. Since the sidewalls of the first portion of the shallow trench isolation 206 are sloped, a portion of the second semiconductor layer 203 adjacent to the shallow trench isolation 206 can be retained. Therefore, both the side wall and the bottom surface of the opening are composed of the material of the second semiconductor layer 203.
  • the third semiconductor layer 210 is epitaxially grown.
  • the third semiconductor layer 210 grows from the bottom surface and the side walls of the opening of the second semiconductor layer 203, and is selective. That is, the growth rates of the third semiconductor layer 210 on different crystal faces of the second semiconductor layer 203 are different.
  • the third semiconductor layer 210 grows the slowest on the ⁇ 1 1 1 ⁇ crystal plane of the second semiconductor layer 203.
  • the bottom surface and the side walls of the opening of the second semiconductor layer 203 serve as a growth seed layer, with the result that the third semiconductor layer 210 can completely fill the opening of the second semiconductor layer 203.
  • the third semiconductor layer 210 After completely filling the opening, the third semiconductor layer 210 loses the growth seed layer of the open sidewall and continues to epitaxially grow.
  • the continuation growth portion of the third semiconductor layer 210 includes not only the (100) main surface parallel to the surface of the second semiconductor layer 203 but also the position adjacent to the shallow trench isolation 206 and the side wall 209 including ⁇ 1 1 1 ⁇ facets, as shown in Figures la, l ib and 11c.
  • the ⁇ 1 1 1 ⁇ facet of the third semiconductor layer 210 is only located in its continued growth portion.
  • a portion of the third semiconductor layer 210 that is located within the opening of the second semiconductor layer 203 has a constrained bottom surface and sidewalls. Therefore, the facet of the third semiconductor layer 203 does not adversely affect the stress applied to the channel region.
  • the third semiconductor layer 210 is ion-implanted according to a conventional process, and then, for example, a spike anneal is performed at a temperature of about 1000 to 1080 ° C,
  • the source and drain regions are formed by activating the dopant implanted through the previous implantation step and eliminating damage caused by the implantation.
  • a portion of the second semiconductor layer 203 under the gate dielectric 207 and between the source and drain regions serves as a channel region.
  • silicidation is performed on the surface of the third semiconductor layer 210 to form a metal silicide layer 211 to reduce contact resistance of the source and drain regions as shown in Figs. 12a, 12b and 12c.
  • This silicidation process is known. For example, a Ni layer having a thickness of about 5 to 12 nm is first deposited, and then heat-treated at a temperature of 300 to 500 ° C for 1 to 10 seconds to form a surface portion of the third semiconductor layer 210 to form NiSi, and finally the wet etching is used to remove the layer. Reaction of Ni.
  • This silicidation consumes a portion of the semiconductor material of the third semiconductor layer 210. Due to the presence of the facets of the third semiconductor layer 210, silicidation can be performed along the facets. Since the third semiconductor layer 210 completely fills the opening of the second semiconductor layer 203, silicidation does not reach the second semiconductor layer 203.
  • an interlayer insulating layer, a via hole in the interlayer insulating layer, a wiring or an electrode on the upper surface of the interlayer insulating layer are formed on the resultant semiconductor structure, thereby completing other portions of the MOSFET. .
  • the present invention is equally applicable to stress-enhanced n-type MOSFETs.
  • the third semiconductor layer 210 is composed of, for example, Si:C for forming a source region and a drain region, and as a stress source for applying a tensile stress to the channel region along the longitudinal direction of the channel region.
  • a stress-enhanced n-type MOSFET can be fabricated by a method similar to that described above.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

公开了一种MOSFET的制造方法，包括：在半导体衬底上外延生长第一半导体层；在第一半导体层上外延生长第二半导体层；在第一半导体层和第二半导体层中形成用于限定MOSFET的有源区的浅沟槽隔离；在第二半导体上形成栅叠层和围绕栅叠层的侧墙；以浅沟槽隔离、栅叠层和侧墙为硬掩模在第二半导体层中形成开口；以开口的底面和侧壁为生长籽层，外延生长第三半导体层，其中第三半导体层的材料与第二半导体层的材料不同；以及对第三半导体层进行离子注入以形成源区和漏区。该方法利用由第三半导体层形成的源区和漏区对第二半导体层中的沟道区施加应力。

Description

MOSFET的制造方法 本申请要求了 2012年 10月 23日提交的、 申请号为 201210407433. X、 发明名称 为 "MOSFET的制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在本申 请中。 技术领域
本发明涉及半导体器件的制造方法， 更具体地， 涉及应力增强的 MOSFET的制造 方法。 背景技术
集成电路技术的一个重要发展方向是金属氧化物半导体场效应晶体管 （MOSFET) 的尺寸按比例缩小， 以提高集成度和降低制造成本。 然而， 在 MOSFET的尺寸减小时， 半导体材料的性能 （例如迁移率） 以及 MOSFET 自身的器件性能 （例如阈值电压） 均 可能变劣。
通过向 MOSFET的沟道区施加合适的应力， 可以提高载流子的迁移率， 从而减小 导通电阻并提高器件的开关速度。 当形成的器件是 n型 MOSFET时， 应当沿着沟道区 的纵向方向对沟道区施加拉应力， 并且沿着沟道区的横向方向对沟道区施加压应力， 以提高作为载流子的电子的迁移率。 相反， 当晶体管是 P型 MOSFET时， 应当沿着沟 道区的纵向方向对沟道区压应力， 并且沿着沟道区的横向方向对沟道区施加拉应力， 以提高作为载流子的空穴的迁移率。
采用与半导体衬底的材料不同的半导体材料形成源区和漏区，可以产生期望的应 力。 对于 n 型 M0SFET , 在 Si 衬底上形成的 Si : C 源区和漏区可以作为应力源 (stressor) , 沿着沟道区的纵向方向对沟道区施加拉应力。 对于 p型 M0SFET, 在 Si 衬底上形成的 SiGe源区和漏区可以作为应力源， 沿着沟道区的纵向方向对沟道区施 加压应力。
图 1-4示出根据现有技术的方法制造应力增强的 MOSFET的各个阶段的半导体结 构的示意图， 其中在图 la、 2a、 3a、 4a中示出了半导体结构沿沟道区的纵向方向的 截面图， 在图 3b、 4b中示出了半导体结构沿沟道区的横向方向的截面图， 在图 lb、 2b、 3c、 4c中示出了半导体结构的俯视图。 在图中， 线 AA表示沿沟道区的纵向方向 的截取位置， 线 BB表示沿沟道区的横向方向的截取位置。
该方法开始于图 la和 lb所示的半导体结构， 其中， 在半导体衬底 101中形成浅 沟槽隔离 102以限定 M0SFET的有源区， 在半导体衬底 101上形成由侧墙 105包围的 栅叠层， 栅叠层包括栅极电介质 103和栅极导体 104。
以浅沟槽隔离 102、栅极导体 104和侧墙 105作为硬掩模， 蚀刻半导体衬底 101， 达到期望的深度，从而在半导体衬底 101对应于源区和漏区的位置形成开口，如图 2a 和 2b所示。
在半导体衬底 101的位于开口内的暴露表面上， 外延生长半导体层 106， 以形成 源区和漏区。半导体衬底 101的位于栅极电介质 103下方以及源区和漏区之间的一部 分将作为沟道区。
半导体层 106从半导体衬底 101的表面开始生长， 并且是选择性的。 也即， 半导 体层 106在半导体衬底 101的不同晶面 （crystal l ine surface ) 上的生长速率不同。 在半导体衬底 101由 Si组成、以及半导体层 106由 SiGe组成的示例中，半导体层 106 在半导体衬底 101的 {1 1 1}晶面上生长最慢。 结果， 所形成的半导体层 106不仅包 括与半导体衬底 101的表面平行的 （100 ) 主表面， 而且在与浅沟槽隔离 102和侧墙 105相邻的位置还包括 {1 1 1}刻面 （facet ), 这称为半导体层 106生长的边缘效应 ( edge effect ), 如图 3a、 3b和 3c所示。
然而， 半导体层 106的小刻面是不期望的， 因为这导致其自由表面的增加， 使得 半导体层 106中的应力得以释放， 从而减小对沟道区施加的应力。
进一步地， 在半导体层 106的表面进行硅化以形成金属硅化物层 107， 如图 4a、 4b和 4c所示。 该硅化消耗半导体层 106的一部分半导体材料。 由于半导体层 106的 小刻面的存在， 硅化可以沿着小刻面进行， 最终可能到达半导体衬底 101。
然而，半导体衬底 101中的硅化是不期望的，因为这可能在结区形成金属硅化物， 导致结泄漏的增加。
因此， 期望在应力增强的 M0SFET抑制用于形成源区和漏区的半导体层的边缘效 应。 发明内容
本发明的目的是提供一种提高沟道区应力和 /或减小结泄漏的 M0SFET 的制造方 法。 根据本发明， 提供一种 MOSFET的制造方法， 包括： 在半导体衬底上外延生长第 一半导体层； 在第一半导体层上外延生长第二半导体层； 在第一半导体层和第二半导 体层中形成用于限定 MOSFET的有源区的浅沟槽隔离； 在第二半导体上形成栅叠层和 围绕栅叠层的侧墙； 以浅沟槽隔离、栅叠层和侧墙为硬掩模在第二半导体层中形成开 口； 以开口的底面和侧壁为生长籽层， 外延生长第三半导体层， 其中第三半导体层的 材料与第二半导体层的材料不同； 以及对第三半导体层进行离子注入以形成源区和漏 区。
该方法利用由第三半导体层形成的源区和漏区对第二半导体层中的沟道区施加 应力。 由于在外延生长时以开口的底面和侧壁为生长籽层， 因此第三半导体层可以完 全填充第二半导体层的开口。 第三半导体层的 U 1 1}刻面仅仅位于其继续生长部分 中， 从而抑制了边缘效应的影响。 附图说明
图 1-4示出根据现有技术的方法制造应力增强的 MOSFET的各个阶段的半导体结 构的示意图， 其中在图 la、 2a、 3a、 4a中示出了半导体结构沿沟道区的纵向方向的 截面图， 在图 3b、 4b中示出了半导体结构沿沟道区的横向方向的截面图， 在图 lb、 2b、 3c、 4c中示出了半导体结构的俯视图。
图 5-12示出根据本发明的方法的实施例制造应力增强的 MOSFET的各个阶段的半 导体结构的示意图， 其中在图 5-8、 9a、 10a, 11a, 12a中示出了半导体结构沿沟道 区的纵向方向的截面图， 在图 l lb、 12b中示出了半导体结构沿沟道区的横向方向的 截面图， 在图 9b、 10b、 l lc、 12c中示出了半导体结构的俯视图。 具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中， 相同的元件采用类似的附 图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
为了简明起见， 可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一个 区域 "上面"或 "上方" 时， 可以指直接位于另一层、 另一个区域上面， 或者在其与 另一层、 另一个区域之间还包含其它的层或区域。 并且， 如果将器件翻转， 该一层、 一个区域将位于另一层、 另一个区域 "下面"或 "下方" 。 如果为了描述直接位于另一层、 另一个区域上面的情形， 本文将采用 "直接 在……上面"或 "在……上面并与之邻接" 的表述方式。
在本申请中，术语 "半导体结构"指在制造半导体器件的各个步骤中形成的整个 半导体结构的统称， 包括已经形成的所有层或区域； 术语 "沟道区的纵向方向"指从 源区到漏区和方向， 或相反的方向； 术语 "沟道区的横向方向"在与半导体衬底的主 表面平行的平面内与沟道区的纵向方向垂直的方向。 例如， 对于在 U 0 0}硅晶片上 形成的 M0SFET, 沟道区的纵向方向通常沿着硅晶片的〈110〉方向， 沟道区的横向方向 通常沿着硅晶片的〈011〉方向。
在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处理 工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那样， 可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出， M0SFET的各个部分可以由本领域的技术人员公知的材料 构成。 半导体材料例如包括 III-V族半导体， 如 GaAs、 InP、 GaN、 SiC， 以及 IV族半 导体， 如 Si、 Ge。 栅极导体可以由能够导电的各种材料形成， 例如金属层、 掺杂多晶 硅层、或包括金属层和掺杂多晶硅层的叠层栅导体或者是其他导电材料，例如为 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx 和所述各 种导电材料的组合。栅极电介质可以由 5102或介电常数大于 Si02的材料构成，例如包 括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括 Si02、 Hf02 Zr02、 A1203、 Ti02、 L¾03, 氮化物例如包括 Si ， 硅酸盐例如包括 Hf Si0x， 铝酸 盐例如包括 LaA103， 钛酸盐例如包括 SrTi03， 氧氮化物例如包括 SiON。 并且， 栅极电 介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发的用于栅极 电介质的材料。
按照本发明的实施例， 执行图 5 至 12 中所示的以下步骤以制造应力增强的 M0SFET, 在图中示出了不同阶段的半导体结构的截面图。 如果必要， 在图中还示出了 俯视图， 在俯视图中采用线 AA表示沿沟道区的纵向方向的截取位置， 采用线 BB表示 沿沟道区的横向方向的截取位置。
该方法开始于图 5所示的半导体结构，在半导体衬底 201上依次形成第一半导体 层 202、 第二半导体层 203、 衬垫氧化物层 204和衬垫氮化物层 205。 半导体衬底 201 例如由 Si组成。 第一半导体层 202是外延生长的层， 例如由 Ge的原子百分比约为 10-15%的 SiGe组成， 厚度约为 30-50nm。第二半导体层 203是外延生长的层， 例如由 Si组成，厚度约为 100-200nm。衬垫氧化物层 204例如由氧化硅组成，厚度约为 2_5nm。 衬垫氮化物层 205例如由氮化硅组成， 厚度约为 10-50nm。 正如已知的那样， 衬垫氧 化物层 204可以减轻第二半导体层 203和衬垫氮化物层 205之间的应力。衬底氮化物 层 205在随后的蚀刻步骤中用作硬掩模。
用于形成上述各层的工艺是已知的。 例如， 通过已知的沉积工艺， 如电子束蒸发 ( EBM)、 化学气相沉积 （CVD)、 原子层沉积 （ALD)、 溅射等， 外延生长第一半导体层 202和第二半导体层 203。例如， 通过热氧化形成衬垫氧化物层 204。例如， 通过化学 气相沉积形成衬垫氮化物层 205。
然后， 通过旋涂在衬垫氮化物层 205上形成光致抗蚀剂层 （未示出）， 并通过其 中包括曝光和显影的光刻工艺将光致抗蚀剂层形成浅沟槽隔离的图案。利用光致抗蚀 剂层作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧 蚀， 或者通过其中使用蚀刻剂溶液的湿法蚀刻， 从上至下依次去除衬垫氮化物层 205 和衬垫氧化物层 204的暴露部分。 该蚀刻在第二半导体层 203的表面停止， 并且在衬 垫氮化物层 205和衬垫氧化物层 204形成浅沟槽隔离的图案。通过在溶剂中溶解或灰 化去除光致抗蚀剂层。
利用衬垫氮化物层 205和衬垫氧化物层 204—起作为硬掩模，通过已知的干法蚀 刻或湿法蚀刻， 去除第二半导体层 203的暴露部分， 从而在第二半导体层 203中形成 浅沟槽的第一部分， 如图 6所示。 该蚀刻相对于第一半导体层 202的材料选择性地去 除第二半导体层 203的材料， 从而在第一半导体层 202的表面停止。 而且， 该蚀刻是 各向异性的， 通过选择合适的蚀刻剂和蚀刻条件， 使得浅沟槽的第一部分的顶部的宽 度大于底部的宽度。 也即， 浅沟槽的第一部分的侧壁是倾斜的。 优选地， 浅沟槽的第 一部分的顶部表面与侧壁的夹角小于 70 ° 。应当注意，本领域的技术人员公知通过选 择合适的蚀刻剂和蚀刻条件可以改变蚀刻得到的开口的形态，使得开口具有陡直的侧 壁或倾斜的侧壁。
进一步地， 通过已知的干法蚀刻或湿法蚀刻， 经由浅沟槽的第一部分去除第一半 导体层 202的暴露部分， 从而在第一半导体层 202中形成浅沟槽的第二部分， 如图 7 所示。该蚀刻相对于第二半导体层 203和半导体衬底 201的材料选择性地去除第一半 导体层 202的材料，从而在半导体衬底 201的表面停止。而且，该蚀刻是各向同性的， 使得浅沟槽的第二部分不仅位于浅沟槽的第一部分的正下方，而且部分地延伸到第二 半导体层 203的下方。
然后， 通过已知的沉积工艺， 在半导体结构的表面上形成绝缘材料层 （未示出）。 该绝缘材料层填充浅沟槽的第一部分和第二部分。 通过化学机械抛光 （CMP ) 去除绝 缘材料层位于浅沟槽外部的部分，并且进一步去除衬垫氮化物层 203和衬垫氧化物层 204。绝缘材料层留在浅沟槽内的部分形成浅沟槽隔离 206， 如图 8所示。浅沟槽隔离 206限定 M0SFET的有源区，并且包括分别对应于浅沟槽的第一部分和第二部分的第一 部分和第二部分。 浅沟槽隔离 206的第一部分的侧壁是倾斜的， 在随后的蚀刻步骤中 可以保留与浅沟槽隔离 206相邻的第二半导体层 203的一部分。浅沟槽隔离 206的第 二部分则扩大了浅沟槽隔离 206的底部， 从而改善了其电绝缘性能。
通过已知的沉积工艺， 在半导体结构的表面上依次形成电介质层以及多晶硅层， 对其进行图案化， 从而形成包括栅极电介质 207和栅极导体 208的栅极叠层。 接着， 通过上述已知的工艺， 在半导体结构的整个表面上沉积例如 10-50纳米的氮化物层， 然后通过各向异性蚀刻形成包围栅叠层的侧墙 209， 如图 9a、 9b所示。
以浅沟槽隔离 206、栅极导体 208和侧墙 209作为硬掩模，蚀刻第二半导体层 203， 达到期望的深度， 从而在第二半导体层 203对应于源区和漏区的位置形成开口， 如图 10a, 10b所示。 该蚀刻是各向异性的， 通过选择合适的蚀刻剂和蚀刻条件， 使得开口 的形状与硬掩模的图案基本一致。也即，该开口的侧壁是陡直的。由于浅沟槽隔离 206 的第一部分的侧壁是倾斜的， 因此可以保留与浅沟槽隔离 206 相邻的第二半导体层 203的一部分。 因此， 开口的侧壁和底面均由第二半导体层 203的材料组成。
然后， 在第二半导体层 203的开口内， 外延生长第三半导体层 210。 第三半导体 层 210从第二半导体层 203的开口的底面和侧壁开始生长， 并且是选择性的。 也即， 第三半导体层 210在第二半导体层 203的不同晶面上的生长速率不同。在第二半导体 层 203由 Si组成、 以及第三半导体层 210由 SiGe组成的示例中， 第三半导体层 210 在第二半导体层 203的 {1 1 1}晶面上生长最慢。 然而， 与现有技术不同， 第二半导 体层 203的开口的底面和侧壁均作为生长籽层，结果第三半导体层 210可以完全填充 第二半导体层 203的开口。
在完全填充该开口之后， 第三半导体层 210失去开口侧壁的生长籽层， 并继续自 由外延生长。 结果， 第三半导体层 210的继续生长部分不仅包括与第二半导体层 203 的表面平行的 （100 ) 主表面， 而且在与浅沟槽隔离 206和侧墙 209相邻的位置还包 括 {1 1 1}刻面， 如图 l la、 l ib和 11c所示。 第三半导体层 210的 {1 1 1}刻面仅仅位于其继续生长部分中。 第三半导体层 210 的位于第二半导体层 203的开口内的部分具有受约束的底面和侧壁。 因此， 第三半导 体层 203的刻面并未不利地影响对沟道区施加的应力。
尽管未示出， 在图 5-11所示的步骤之后， 按照常规的工艺对第三半导体层 210 进行离子注入， 然后例如在约 1000-1080°C的温度下执行尖峰退火 （spike anneal ), 以激活通过先前的注入步骤而注入的掺杂剂并消除注入导致的损伤，从而形成源区和 漏区。第二半导体层 203的位于栅极电介质 207下方以及源区和漏区之间的一部分作 为沟道区。
优选地， 在第三半导体层 210的表面进行硅化以形成金属硅化物层 211， 以减小 源区和漏区的接触电阻， 如图 12a、 12b和 12c所示。
该硅化的工艺是已知的。 例如， 首先沉积厚度约为 5-12nm 的 Ni 层， 然后在 300-500°C的温度下热处理 1-10秒钟， 使得第三半导体层 210的表面部分形成 NiSi， 最后利用湿法蚀刻去除未反应的 Ni。
该硅化消耗第三半导体层 210的一部分半导体材料。由于第三半导体层 210的小 刻面的存在， 硅化可以沿着小刻面进行。 由于第三半导体层 210完全填充第二半导体 层 203的开口， 硅化并未到达第二半导体层 203。
在图 12所示的步骤之后， 在所得到的半导体结构上形成层间绝缘层、 位于层间 绝缘层中的通孔、 位于层间绝缘层上表面的布线或电极， 从而完成 M0SFET的其他部 分。
尽管在上述实施例中描述了应力增强的 P型 M0SFET及其中使用的应力源的材料， 但本发明同样适应于应力增强的 n型 M0SFET。 在 n型 M0SFET中， 第三半导体层 210 例如由 Si : C组成， 用于形成源区和漏区， 并且作为沿着沟道区的纵向方向对沟道区 施加拉应力的应力源。 除了应力源的材料不同之外， 可以采用与上述方法类似的方法 制造应力增强的 n型 M0SFET。
以上描述只是为了示例说明和描述本发明， 而非意图穷举和限制本发明。 因此， 本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改， 均 在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种 M0SFET的制造方法， 包括：
在半导体衬底上外延生长第一半导体层；
在第一半导体层上外延生长第二半导体层；
在第一半导体层和第二半导体层中形成用于限定 M0SFET的有源区的浅沟槽隔离； 在第二半导体上形成栅叠层和围绕栅叠层的侧墙；
以浅沟槽隔离、 栅叠层和侧墙为硬掩模在第二半导体层中形成开口；
以开口的底面和侧壁为生长籽层， 外延生长第三半导体层， 其中第三半导体层的 材料与第二半导体层的材料不同； 以及
对第三半导体层进行离子注入以形成源区和漏区。
2、 根据权利要求 1所述的方法， 其中所述浅沟槽隔离在第二半导体层中的部分 具有倾斜的侧壁。
3、 根据权利要求 2所述的方法， 其中所述浅沟槽隔离在第一半导体层中的部分 地延伸到第二半导体层的下方。
4、 根据权利要求 3所述的方法， 其中形成浅沟槽隔离的步骤包括：
在第二半导体上形成其中包括浅沟槽隔离的图案的硬掩模；
采用各向异性蚀刻在第二半导体层中形成浅沟槽的第一部分，使得该浅沟槽的第 一部分具有倾斜的侧壁并到达第一半导体层的表面；
采用各向同性蚀刻在第一半导体层中形成浅沟槽的第二部分，使得该浅沟槽的第 二部分部分地延伸到第二半导体层的下方； 以及
采用绝缘材料填充浅沟槽， 以形成浅沟槽隔离。
5、 根据权利要求 2所述的方法， 其中浅沟槽的第一部分的顶部表面与侧壁的夹 角小于 70 ° 。
6、 根据权利要求 1所述的方法， 其中形成开口的步骤包括：
采用各向异性蚀刻在第二半导体层中形成开口， 使得该开口具有陡直的侧壁。
7、 根据权利要求 1所述的方法， 其中所述 M0SFET为 p型 M0SFET。
8、 根据权利要求 7所述的方法， 其中所述第一半导体层由 SiGe组成， 所述第二 半导体层由 Si组成， 所述第三半导体层由 SiGe组成。
9、 根据权利要求 1所述的方法， 其中所述 M0SFET为 n型 M0SFET。
10、 根据权利要求 9所述的方法， 其中所述第一半导体层由 Si : C组成， 所述第 二半导体层由 Si组成， 所述第三半导体层由 Si : C组成。
11、 根据权利要求 1所述的方法， 其中在形成源区和漏区之后中， 还包括： 执行硅化以在源区和漏区的表面形成金属硅化物。
PCT/CN2012/083748 2012-10-23 2012-10-30 Mosfet的制造方法 Ceased WO2014063379A1 (zh)

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