WO2014046784A1 - Interfaçage entre des circuits intégrés avec une excursion de tension asymétrique - Google Patents

Interfaçage entre des circuits intégrés avec une excursion de tension asymétrique Download PDF

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Publication number
WO2014046784A1
WO2014046784A1 PCT/US2013/052126 US2013052126W WO2014046784A1 WO 2014046784 A1 WO2014046784 A1 WO 2014046784A1 US 2013052126 W US2013052126 W US 2013052126W WO 2014046784 A1 WO2014046784 A1 WO 2014046784A1
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WIPO (PCT)
Prior art keywords
transmitter
receiver
signal
memory
voltage swing
Prior art date
Application number
PCT/US2013/052126
Other languages
English (en)
Inventor
Srikanth Gondi
Roger Isaac
Original Assignee
Silicon Image, Inc.
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Publication date
Application filed by Silicon Image, Inc. filed Critical Silicon Image, Inc.
Priority to CN201380048274.1A priority Critical patent/CN104641359B/zh
Priority to KR1020157010177A priority patent/KR20150060806A/ko
Priority to EP13839285.7A priority patent/EP2898416B1/fr
Priority to JP2015533056A priority patent/JP2015535983A/ja
Publication of WO2014046784A1 publication Critical patent/WO2014046784A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Definitions

  • Embodiments of the invention generally relate to the field of electronic devices and, more particularly, to interfacing between integrated circuits with asymmetric voltage swing.
  • circuits such as computer memory needs to be designed to provide high performance without causing excessive power drain.
  • link design is a key element in high data rate chip-to-chip interconnects for interface applications. Issues that affect link design includes high performance communication and computation, the technology of integrated circuits, and the electrical connection between integrated circuits, such the electrical connection between a controller and a computer memory.
  • Figure 1A illustrates an embodiment of an apparatus or system with unidirectional I/O interface having asymmetric voltage swing between connected integrated circuits
  • Figure IB illustrates an embodiment of an apparatus or system with bidirectional I/O interface having asymmetric voltage swing between integrated connected integrated circuits
  • Figure 2A is an illustration of a simplified voltage-division single-ended driver
  • Figure 2B illustrates driver and receiver structures that are used for power analysis
  • Figure 3 shows the average power as a function of voltage swing for different swing conditions
  • Figure 4A is a graph to illustrate a time domain representation of transmitter driver output
  • Figure 4B is a graph to illustrate and instantaneous power consumption on a power supply over time
  • Figure 4C illustrates an eye diagram including average high, average low and average voltage swing parameters
  • Figure 4D illustrates a time domain waveform of the output signal with definition for peak high, peak low voltages with DC high value and DC low value;
  • Figure 5A illustrates a memory interface with a symmetric swing
  • Figure 5B illustrates an embodiment of a memory interface with an asymmetric voltage swing
  • Figure 6 is a flowchart to illustrate an embodiment of a process for memory operation with asymmetric voltage swing operation
  • Figure 7 is an illustration of an apparatus or system including a memory with asymmetric voltage swing.
  • Embodiments of the invention are generally directed to an interfacing between integrated circuits with asymmetric voltage swing.
  • an embodiment of an apparatus includes a first integrated circuit including a first transmitter and a first receiver; a second integrated circuit including a second transmitter and a second receiver; and an interface including communication channel linking the first transmitter with the second receiver and the first receiver with the second transmitter, wherein the communication channel is one of a single channel or a dual channel.
  • the first transmitter is operable to transmit a first signal and the second transmitter is operable to transmit a second signal, a first average voltage swing of the first signal being asymmetric with a second average voltage swing of the second signal.
  • an embodiment of a method includes establishing a first voltage swing for transmission from a first integrated circuit, the first integrated circuit including a first transmitter and a first receiver, to a second integrated circuit, the second integrated circuit including a second transmitter and a second receiver; establishing a second voltage swing for transmission from the second integrated circuit to the first integrated circuit; transmitting a first signal from the first transmitter to the second receiver using the first voltage swing; and transmitting a second signal from the second transmitter to the first receiver using the second voltage swing, wherein the first voltage swing and the second voltage swing are asymmetric.
  • Embodiments of the invention are generally directed to interfacing between integrated circuits with asymmetric voltage swing.
  • a memory interface utilizes asymmetric voltage swings at a controller transmitter and at a memory transmitter. In some embodiments, a larger voltage swing is established for transmission from the controller to the memory than a voltage swing established from the memory to the controller.
  • DRAM dynamic random access memory
  • Devices such as dynamic random access memory (DRAM) are commonly slower (which may be by an order of two) than their counterparts in the controller of a memory interface, due to the fact that the transistors in the DRAM process have larger threshold voltages than their counterparts in the controller.
  • the fact that only lower metal layers are available in the DRAM process means more parasitic capacitance and resistance are introduced that, accordingly, makes the routing and design process in memory more complicated and slower than in the controller.
  • an asymmetric-swing memory interface is applied to address issues regarding the interfacing between controller and memory.
  • the controller circuitry is responsible for the majority of equalization, detection and timing duties. The responsibility is placed in the controller because devices in the controller generally have higher transit frequency and lower threshold voltages than memory, which consequently makes analog and digital design in the controller more power efficient in comparison with DRAM.
  • CMOS technology performance metrics can directly influence link characteristics.
  • An inferior CMOS process will significantly manifest itself in the receiver sensitivity.
  • the signal to noise ratio (SNR) at the receiver of the memory side of an interface may be increased, where the higher SNR may be provided by boosting the signal swing at the transmitter side.
  • SNR signal to noise ratio
  • the receiver sensitivity of the controller allows the DRAM transmitter driver signal swing to be lowered for power efficiency purposes.
  • packaging technology may vary between devices, such as between controller and memory, a controller having a first packaging technology and the memory having a second packaging technology
  • a controller may include an SoC (System on Chip) with, for example, flip-chip packaging and a DRAM with, for example, wire bonding, where packaging technology of the SoC allows for lower signal voltage operation than the DRAM.
  • the DRAM may include higher inductances, capacitances and resistances than the SoC, thus having more loss and ISI (Interfering Switching Inputs) effects in the packaging and requiring a higher received signal voltage.
  • the DRAM transmitter when transmitting using lower swing signal can reduce the effect of SSO (Simultaneous Switching Outputs) in the DRAM packaging and provide better signaling at the SoC receiver.
  • SSO Simultaneous Switching Outputs
  • the signal swing at the output of the controller transmitter driver may be chosen to be higher than signal swing at the output of the transmitter at the DRAM side, which typically has slower technology and higher V TH (threshold voltage) voltage values.
  • V TH threshold voltage
  • an increase in voltage swing from controller to memory and a decrease in voltage swing from memory to controller may be utilized to improve performance while potentially reducing overall power consumption.
  • a voltage supply difference between a controller and a memory may enable asymmetric voltage swing operation in order to improve power dissipation overall.
  • the overall power dissipation of the link can be reduced.
  • FIG. 1A illustrates an embodiment of an apparatus or system with unidirectional I O interface having asymmetric voltage swing between connected integrated circuits.
  • the apparatus or system may include, for example a memory device 100 with an I/O interface between a memory controller 110 and a DRAM memory 130.
  • the controller 110 is coupled with the DRAM 130, where a transmitter (TX) 112 of the controller 110 is coupled via a first unidirectional channel 122 of a dual communication channel of the memory I/O interface with a receiver (RX) 132 of the DRAM 110 and a transmitter 134 of the DRAM 130 is coupled via a second unidirectional channel 124 of the dual communication channel with a receiver 114 of the controller 110.
  • TX transmitter
  • RX receiver
  • the interface including first channel 122 and second channel 124 may vary in different implementations, and may include, for example, either single-ended channels or differential channels, and either unidirectional channels or bidirectional channels.
  • the controller 110 is a device such as a system on chip (SoC) with faster performance and more sensitivity that can tolerate lower signal voltages in comparison with the memory 130, while the memory 130 is a DRAM that requires higher signal voltages in comparison with the controller.
  • SoC system on chip
  • coding of signal may include non-return to zero encoding in which each binary signal has a non-zero potential, such as a T being represented by a positive voltage and a '0' signal being represented by negative voltage.
  • the controller 110 provides a signal 140 with a particular voltage swing indicated as aV peak-peak swing to be transmitted through the channel 122, with the signal 142, as attenuated by the channel 122, at the receiver 132 of the DRAM 130.
  • the transmitter 134 of the DRAM transmits a signal 144 with Vpp (peak-to-peak) swing through the second channel 124, with the signal 146, as attenuated by the channel, being received at the receiver 114 of the controller 110.
  • the voltage swing aV for the signal transmission from controller 110 to DRAM 130 is not equal to the voltage swing V for the signal transmission from DRAM 130 to controller 110. In some embodiments, a > 1.0, thus providing a greater voltage swing from the controller to the memory than the voltage swing from the memory to the controller.
  • Figure IB illustrates an embodiment of an apparatus or system with bidirectional I/O interface having asymmetric voltage swing between integrated connected integrated circuits.
  • a memory device 150 includes a controller 160 coupled with a DRAM 180, where a transmitter 162 of the controller 160 is coupled to a bidirectional channel 172 of the memory I/O interface for transmission of signals to a receiver 182 of the DRAM 180, and a transmitter 184 of the DRAM 180 is coupled to the same bidirectional channel 172 for transmission of signals to receiver 164 of the controller 160.
  • the controller 160 again is a device such as an SoC with faster performance and more sensitivity that can tolerate lower signal voltages in comparison with the memory 180, and the memory 180 is a DRAM that requires higher signal voltages in comparison with the controller.
  • the controller 160 provides a signal 190 with a particular voltage swing indicated as aV peak-peak swing to be transmitted through the channel 172, with the signal 192, as attenuated by the channel 172, at the receiver 182 of the DRAM 180.
  • the transmitter 184 of the DRAM transmits a signal 194 with Vpp swing through the same channel 172, with the signal 196, as attenuated by the channel, being received at the receiver 164 of the controller 160.
  • the voltage swing aV illustrated in Figure IB for the signal transmission from controller 160 to DRAM 180 is not equal to the voltage swing V for the signal transmission from DRAM 180 to controller 160, with a > 1.0, thus providing a greater voltage swing from the controller to the memory than the voltage swing from the memory to the controller.
  • FIG. 2A is an illustration of a simplified voltage-division single-ended driver.
  • a device 200 includes a driver (TX) 210, where the driver is shown as including resistances Rl 212 and R3 214 in series between power supply voltage VDD and ground, providing a voltage division at a node between Rl and R3.
  • the node between Rl 212 and R3 214 is coupled with a channel 220 for the transmission of a signal 240 to be received a receiver 230, shown as including a resistance 232 that is shown as having a value of 50 ohms.
  • the resistance of Rl in parallel with R3 will be 50 ohms.
  • FIG. 2B illustrates driver and receiver structures that are used for power analysis.
  • a driver 260 consists of an output stage 262 and pre-drive stage 264, where the pre- drive stage drives PU (pull up), PD (pull down), and ODT (on die termination) signals.
  • a differential receiver 270 consists of 2 gain stages, GainStage 1 272 and GainStage 2 274, with equalization, wherein the sampler is included for completeness and is not considered in receiver power analysis.
  • the PU signal operates to switch transistor Ml to enable or disable pull up resistor Rl
  • the PD signal operates to switch transistor M2 to enable or disable pull down resistor R2.
  • the ODT signal controlling transistor M3 is intended to enable or disable the R3 leg, which may or may not switch as per the input data signal as is the case with PU/PD signals.
  • the driver 210 creates the signal 240 representing a bit "1" with signal amplitude of V swing . Because the driver 210 ideally does not draw any current from the VDD power supply during bit "0", a power calculation may only consider the bit "1" as the power consumption state. From Figure 2A, power may be calculated by the product of the VDD and the amount of the DC current drawn from VDD during bit "1". Substituting values for V swing and the impedance of Rl and R2 in parallel, an expression for the value of average DC power may be determined as follows:
  • V s s w w i l n n 3 a V DD x R 1 R + 2 R" 2 5
  • V swing ⁇ — ⁇ - is derived from the fact that both sides of the channel have ideally 50 ⁇ terminations.
  • the TX average total power includes TX average DC power and TX average AC power, where the TX average AC power is determined by:
  • Ci Ci * Vswing 2 * / + Cp * Vswing 2 * / [5]
  • Ci driver internal capacitance
  • Cp pad capacitance of both driver and input receiver load
  • Vswing output average output swing voltage
  • the TX average total power therefore is:
  • TX Average Total Power TX Average DC Power + TX Average AC Power [6]
  • the TX average DC power contributes 80% of total power and the TX average AC power contributes 20% of total power.
  • Figure 3 shows the average power as a function of voltage swing for different swing conditions.
  • a graph 300 plots average power consumption versus desired TX driver signal swing. As shown in Figure 3, power increases non-linearly, by signal swing in a squared fashion. For example, if the swing at a TX driver is halved from 400 mV to 200 mV, average power consumption at the driver will drop from 6.4 mW to 4 mW.
  • Figure 4A is a graph to illustrate a time domain representation of transmitter driver output
  • Figure 4B is a graph to illustrate and instantaneous power consumption on a power supply over time.
  • Figure 4A illustrates a typical TX driver output for two different swing conditions
  • Figure 4B shows the instantaneous power for the respective swings.
  • Figure 4A illustrate a voltage curve 400 (in millivolts) over time (in nanoseconds) for particular voltage swing values for a transmitter driver, the swing voltage value being 400 mV for the upper curve 412 and 200 mV for the lower curve 414.
  • Figure 4B illustrates a curve 420 of instantaneous power consumption versus time the swing voltage value being 400 mV for the upper curve 422 and 200 mV for the lower curve 424.
  • Figure 4C illustrates an eye diagram including average high, average low and average voltage swing parameters
  • Figure 4D illustrates a time domain waveform of the output signal with definition for peak high, peak low voltages with DC high value and DC low value
  • Figure 4C includes an "average Vswing" parameter 434, which is defined herein as the average "high” value 432 in the case of output of a single-ended driver referenced to ground and the peak-peak value that is referenced to average "low” value 436 in case of differential signals.
  • the eye diagram illustrated in the driver output 430 includes instantaneous values in and around the center that are usually different from a DC value due to the transients associated with the non-ideal nature of the driver and its interconnect.
  • Figure 4D shows voltage over time for a device. Depending on the parasitic resistances in the driver, receiver, and the interconnect, as illustrated in figure 4D, after a certain amount of time, the output would reach the DC voltage value, the value being either the high-level DC voltage 444 or and the -level low DC voltage 446.
  • a driver output may be referenced to low supply, wherein signal levels are referenced to ground (zero); may be referenced to high supply, wherein signal levels are referenced to a supply voltage (VDD); or may be referenced to combination of both low supply and high supply, wherein signal levels do not relate to either the low or high value.
  • a higher voltage swing at a controller transmitter and lower voltage swing at a DRAM transmitter also allows the receiver block at the DRAM to be designed with more relaxed requirements, providing a lower sensitivity, compared to the receiver at the controller.
  • Such an implementation may be utilized to achieve a power efficient link design because of access to a better circuit process at the controller together with lower power consumption in the DRAM receiver block.
  • the output of a driver may be substantially equal to a supply voltage of one or more supply voltages supplied to the transmitter, the transmitter thus utilizing a full voltage swing based on such supply voltage.
  • Figure 5A illustrates a memory interface with a symmetric swing
  • Figure 5B illustrates an embodiment of a memory interface with an asymmetric voltage swing.
  • a memory device 500 includes a controller 510 coupled with a DRAM 530, a transmitter 512 of the controller 510 being coupled via first channel 522 with receiver 532 of the DRAM 530, and transmitter 534 of the DRAM 530 being coupled via second channel 524 with receiver 514 of the controller 510. While two channels are illustrated here, in another implementation there may be a single channel for transmission between devices. With the channel 522 and channel 524 assumed to provide 6-decibel loss in the average swing of a signal transmitting through the channel, due to limited sensitivity and equalization level of receiver 532 of the DRAM 530, the transmitter 512 of the controller 510 needs to transmit a large enough signal swing to compensate for the channel loss and provide a sufficient signal at the receiver 532.
  • the transmitter 534 of the DRAM 530 also transmits the same increased signal swing to the controller receiver 514 of the controller 510, these signals resulting in increasing power consumption in both the controller side and the DRAM side.
  • the controller 510 provides a signal 540 with voltage swing of 200 mV, which is received at the DRAM as a signal 542 with a voltage swing of 100 mV.
  • the DRAM 530 transmits symmetric signal 546 with voltage swing 200 mV, which is received at the controller 510 as signal 548 with voltage swing 100 mV.
  • an embodiment of a memory device 550 includes a controller 560 coupled with a DRAM 580, a transmitter 562 of the controller 560 being coupled with receiver 582 of the DRAM 580 via first channel 572, and transmitter 584 of the DRAM 580 being coupled with receiver 564 of the controller 560 via second channel 574.
  • channel 572 and channel 574 are again assumed to provide 6-decibel loss in average swing of a signal transmitting through the channels.
  • the memory device provides an increased voltage swing from the controller to provide improved performance at the memory, while providing a decreased voltage swing from the DRAM to reduce power while taking advantage of the better sensitivity of the controller.
  • the controller 560 provides a signal 590 with voltage swing of 400 mV, which is received at the DRAM as a signal 592 with a voltage swing of 200 mV.
  • the DRAM 580 transmits an asymmetric signal 596 with voltage swing 100 mV, which is received at the controller 590 as signal 598 with voltage swing 50 mV.
  • a 4.0.
  • the controller has native 0.9V transistors in 28nm process technology, while the DRAM has 1.2V thicker oxide transistors in 40nm process technology.
  • Reported power values are derived by simulating operation at a data rate of 4 Gb/s.
  • a reduced voltage swing of 100 mV at the DRAM transmitter 584 requires that the receiver 564 of the controller 560 is capable of detecting the signal with 50 mV swing.
  • the amplifier stage at the receiver 564 of controller 560 is doubled in comparison with receiver 514 of Figure 5A.
  • the first gain stage is mainly for common mode gain and equalization of the input signal and the second stage provides the signal gain.
  • the first term is a power factor resulting from eliminating one gain stage from the receiver
  • the second term is DRAM receiver DC power scaling due to input voltage swing
  • the last term is the DRAM receiver AC power scaling. Equation [7] provides that average DRAM receiver power is 5.55 times less than the power consumption at the DRAM receiver 582 in comparison with DRAM receiver 532.
  • Figure 6 is a flowchart to illustrate an embodiment of a process for memory operation with asymmetric voltage swing operation. While Figure 6 provides a method 600 for a specific implementation of a memory interface, embodiments are not limited to this
  • a memory I/O interface between a controller and a memory is initiated or operation is otherwise commenced 605.
  • a first voltage swing is established for transmission from the controller to the memory 610
  • a second voltage swing is established from transmission from the memory to the controller, where the second voltage swing and first voltage swings are asymmetric 615.
  • the first and second voltage swings are established at levels dependent on the technologies of the connected integrated circuits.
  • voltages may be established to provide a higher voltage swing for the transmission of a signal from the controller to the memory in comparison with the voltage swing from the memory to the controller, such as illustrated in Figure 5B.
  • a first signal is transmitted from the controller to the memory using the first voltage swing 620
  • a second signal is transmitted from the memory to the controller using the second voltage swing 625.
  • the transmission of the first signal using the first voltage swing and the second signal using the second voltage swing may provide for reduced power consumption and improved operation in comparison with a symmetric voltage swing operation by taking advantage of, for example, of lower voltage requirements at the controller compared with the memory allowing for a reduced swing from memory to controller, together with improved operation at the memory resulting from an increased voltage swing from controller to memory.
  • the description may include an interface where a processor is connected to a modem base-band chip in a mobile platform.
  • driver and receiver implementations may be different than as illustrated and described herein. However, in that case the power benefit could either be higher or lower than the example embodiment shown above in Table 1.
  • FIG. 7 is an illustration of an apparatus or system including a memory with asymmetric voltage swing.
  • the apparatus or system 700 (referred to here generally as an apparatus) comprises a bus or interconnects 702 or other communication means for transmission of data.
  • the apparatus 700 may include a processing means, such as one or more processors 704 coupled with the interconnect 702 for processing information.
  • the processors 704 may comprise one or more physical processors and one or more logical processors.
  • the bus or interconnect 702 is illustrated as a single
  • interconnect 702 shown in Figure 7 is an abstraction that represents any one or more separate physical buses, point-to-point connections, or both connected by appropriate bridges, adapters, or controllers.
  • the apparatus 700 further comprises a random access memory
  • RAM random access memory
  • main memory 712 for storing information and instructions to be executed by the processors 704.
  • RAM memory may include dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • memory of the apparatus may further include certain registers or other special purpose memory.
  • the main memory 712 may include memory 714 utilizing asymmetric voltage swing, where the memory 714 provides a larger voltage swing between the controller and memory than voltage swing between the memory and the controller.
  • the asymmetric voltage swing of the memory 714 may be utilized at least in part to improve performance of the apparatus 700, reduce power consumption of the apparatus 700, or both.
  • asymmetric voltage swing may additionally or alternatively be implemented in other interfaces between integrated circuits.
  • the voltage swings are established to meet the specifications the controller and the memory.
  • the apparatus 700 may include a read only memory (ROM) 716 or other static storage device for storing static information and instructions for the processors 704.
  • ROM read only memory
  • the apparatus 700 may include one or more non-volatile memory elements 718 for the storage of certain elements, including, for example, flash memory, hard disk drive, or solid-state drive.
  • One or more transmitters or receivers 720 may also be coupled to the interconnect 702.
  • the receivers or transmitters 720 may be coupled to one or more ports 722, where the ports may include, for example, one or more HDMITM (High-Definition Multimedia Interface) ports, and one or more MHLTM (Mobile High-Definition Link) ports.
  • HDMITM High-Definition Multimedia Interface
  • MHLTM Mobile High-Definition Link
  • the apparatus 700 includes one or more input devices 724, where the input devices include one or more of a keyboard, mouse, touch pad, voice command recognition, gesture recognition, or other device for providing an input to a computing system.
  • the input devices include one or more of a keyboard, mouse, touch pad, voice command recognition, gesture recognition, or other device for providing an input to a computing system.
  • the apparatus 700 may also be coupled via the interconnect 702 to an output device 726.
  • the display 726 may include a liquid crystal display (LCD) or any other display technology, for displaying information or content to a user.
  • the display 726 may include a touch-screen that is also utilized as at least a part of an input device.
  • the display 726 may be or may include an audio device, such as a speaker for providing audio information.
  • the apparatus 700 may also comprise a power device or apparatus 730, which may comprise a power supply, a battery, a solar cell, a fuel cell, or other system or device for providing or generating power.
  • the power provided by the power device or system 730 may be distributed as required to elements of the apparatus 700.
  • the present invention may include various processes.
  • the processes of the present invention may be performed by hardware components or may be embodied in computer-readable instructions, which may be used to cause a general purpose or special purpose processor or logic circuits programmed with the instructions to perform the processes.
  • the processes may be performed by a combination of hardware and software.
  • Portions of the present invention may be provided as a computer program product, which may include a computer-readable or machine-readable storage medium, including a non- transitory medium, having stored thereon computer program instructions, which may be used to program a computer (or other electronic devices) to perform a process according to the present invention.
  • the computer-readable storage medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (compact disk read-only memory), and magneto-optical disks, ROMs (read-only memory), RAMs (random access memory), EPROMs (erasable programmable read-only memory), EEPROMs (electrically-erasable programmable read-only memory), magnet or optical cards, flash memory, or other type of media / computer-readable medium suitable for storing electronic instructions.
  • the present invention may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer.
  • element A may be directly coupled to element B or be indirectly coupled through, for example, element C.
  • a component, feature, structure, process, or characteristic A “causes” a component, feature, structure, process, or characteristic B, it means that "A” is at least a partial cause of "B” but that there may also be at least one other component, feature, structure, process, or characteristic that assists in causing "B.”
  • a component, feature, structure, process, or characteristic may”, “might”, or “could” be included, that particular component, feature, structure, process, or characteristic is not required to be included. If the specification refers to "a” or “an” element, this does not mean there is only one of the described elements.
  • An embodiment is an implementation or example of the invention.
  • Reference in the specification to "an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments.
  • the various appearances of "an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects.
  • an apparatus includes a first integrated circuit including a first transmitter and a first receiver; a second integrated circuit including a second transmitter and a second receiver; and an interface including communication channel linking the first transmitter with the second receiver and the first receiver with the second transmitter, wherein the communication channel is one of a single channel or a dual channel.
  • the first transmitter is operable to transmit a first signal and the second transmitter is operable to transmit a second signal, a first average voltage swing of the first signal being asymmetric with a second average voltage swing of the second signal.
  • the first transmitter is one of a single-ended transmitter or a differential transmitter.
  • the first transmitter output is referenced either to low supply wherein a signal reference is to ground, to high supply wherein a signal reference is to a supply voltage, or to a combination of both low supply and high supply.
  • an output of the first transmitter includes non-return to zero (NRZ) coding.
  • NRZ non-return to zero
  • one of the first transmitter's outputs is substantially equal to a supply voltage of one or more supply voltages supplied to the transmitter.
  • the first integrated circuit includes a memory controller and wherein the second integrated circuit includes a memory
  • the memory is a dynamic random access memory (DRAM)
  • the memory controller is a system on chip
  • the first receiver of the first integrated circuit has greater signal sensitivity than the second receiver of the second integrated circuit.
  • a supply voltage of the first integrated circuit is smaller than a supply voltage of the second integrated circuit.
  • a method includes establishing a first voltage swing for transmission from a first integrated circuit, the first integrated circuit including a first transmitter and a first receiver, to a second integrated circuit, the second integrated circuit including a second transmitter and a second receiver; establishing a second voltage swing for transmission from the second integrated circuit to the first integrated circuit; transmitting a first signal from the first transmitter to the second receiver using the first voltage swing; and transmitting a second signal from the second transmitter to the first receiver using the second voltage swing.
  • the first voltage swing and the second voltage swing are asymmetric.
  • the first integrated circuit includes a memory controller and wherein the second integrated circuit includes a memory.
  • establishing the first voltage swing includes establishing a signal swing that is sufficient to meet specifications of the second integrated circuit after attenuation by a communication channel between the first transmitter and the second receiver; and establishing the second voltage swing includes establishing a signal swing that is sufficient to meet specifications of the first integrated circuit after attenuation by a communication channel between the second transmitter and the first receiver.
  • the communication channel between the first transmitter and the second receiver is a first channel of a dual communication channel and the communication channel between the second transmitter and the first receiver is a second channel of the dual communication channel.
  • the communication channel between the first transmitter and the second receiver is the same as the communication channel between the second transmitter and the first receiver.
  • a system includes a processor for processing data; a memory controller including a first transmitter and a first receiver; a DRAM for storage of data, the DRAM including a second transmitter and a second receiver; and an interface between the memory controller and the DRAM including a communication channel linking the first transmitter with the second receiver and the first receiver with the second transmitter.
  • the first transmitter is operable to transmit a first signal and the second transmitter is operable to transmit a second signal, a first average voltage swing of the first signal being asymmetric with a second average voltage swing of the second signal.
  • the memory controller of the memory device is an SoC.
  • the first receiver of the controller has greater signal sensitivity than the second receiver of the DRAM.
  • a computer-readable storage medium has stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising: establishing a first voltage swing for transmission from a memory controller, the first memory controller including a first transmitter and a first receiver, to a memory, the memory including a second transmitter and a second receiver, via an I/O
  • the (input/output) interface establishing a second voltage swing for transmission from the memory to the memory controller; transmitting a first signal from the first transmitter to the second receiver using the first voltage swing; and transmitting a second signal from the second transmitter to the first receiver using the second voltage swing.
  • the first voltage swing of the memory controller and the second voltage swing of the memory are asymmetric with each other.
  • establishing the first voltage swing includes establishing a signal swing that is sufficient to meet specifications of the memory after attenuation by a communication channel between the first transmitter and the second receiver; and establishing the second voltage swing includes establishing a signal swing that is sufficient to meet specifications of the memory controller after attenuation by a communication channel between the second transmitter and the first receiver.
  • the communication channel between the first transmitter and the second receiver is a first channel of a dual communication channel and the communication channel between the second transmitter and the first receiver is a second channel of the dual communication channel. [00103] In some embodiments, the communication channel between the first transmitter and the second receiver is the same as the communication channel between the second transmitter and the first receiver.
  • the controller is a device with faster performance and more sensitivity than the memory and can tolerate lower signal voltages in comparison with the memory

Abstract

Des modes de réalisation de la présente invention portent de manière générale sur un interfaçage entre des circuits intégrés avec une excursion de tension asymétrique. Un mode de réalisation d'un appareil comprend un premier circuit intégré comprenant un premier émetteur et un premier récepteur; un second circuit intégré comprenant un second émetteur et un second récepteur; et une interface comprenant un canal de communication reliant le premier émetteur au second récepteur et le premier récepteur au second émetteur, le canal de communication étant un canal unique ou un canal double. Le premier émetteur est fonctionnel pour émettre un premier signal et le second émetteur est fonctionnel pour émettre un second signal, une première excursion de tension moyenne du premier signal étant asymétrique avec une seconde excursion de tension moyenne du second signal.
PCT/US2013/052126 2012-09-18 2013-07-25 Interfaçage entre des circuits intégrés avec une excursion de tension asymétrique WO2014046784A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201380048274.1A CN104641359B (zh) 2012-09-18 2013-07-25 集成电路之间具有不对称电压摆动的接口
KR1020157010177A KR20150060806A (ko) 2012-09-18 2013-07-25 비대칭 전압 스윙을 이용한 집적 회로들 간의 인터페이싱
EP13839285.7A EP2898416B1 (fr) 2012-09-18 2013-07-25 Interfaçage entre des circuits intégrés avec une excursion de tension asymétrique
JP2015533056A JP2015535983A (ja) 2012-09-18 2013-07-25 電圧スイングが非対称な集積回路間のインターフェース接続

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Application Number Priority Date Filing Date Title
US13/622,286 US8885435B2 (en) 2012-09-18 2012-09-18 Interfacing between integrated circuits with asymmetric voltage swing
US13/622,286 2012-09-18

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WO2014046784A1 true WO2014046784A1 (fr) 2014-03-27

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EP (1) EP2898416B1 (fr)
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KR (1) KR20150060806A (fr)
CN (1) CN104641359B (fr)
TW (1) TWI594573B (fr)
WO (1) WO2014046784A1 (fr)

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US8885435B2 (en) 2014-11-11
EP2898416A1 (fr) 2015-07-29
TWI594573B (zh) 2017-08-01
EP2898416B1 (fr) 2019-09-25
JP2015535983A (ja) 2015-12-17
CN104641359A (zh) 2015-05-20
CN104641359B (zh) 2018-09-21
US20140078838A1 (en) 2014-03-20
EP2898416A4 (fr) 2016-06-22
KR20150060806A (ko) 2015-06-03
TW201414203A (zh) 2014-04-01

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