WO2014035950A1 - Co-support system and microelectronic assembly - Google Patents

Co-support system and microelectronic assembly Download PDF

Info

Publication number
WO2014035950A1
WO2014035950A1 PCT/US2013/056773 US2013056773W WO2014035950A1 WO 2014035950 A1 WO2014035950 A1 WO 2014035950A1 US 2013056773 W US2013056773 W US 2013056773W WO 2014035950 A1 WO2014035950 A1 WO 2014035950A1
Authority
WO
WIPO (PCT)
Prior art keywords
microelectronic
contacts
microelectronic assembly
type
assembly
Prior art date
Application number
PCT/US2013/056773
Other languages
English (en)
French (fr)
Inventor
Richard Dewitt Crisp
Belgacem Haba
Wael Zohni
Original Assignee
Invensas Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/840,542 external-priority patent/US8848392B2/en
Priority claimed from US13/840,353 external-priority patent/US8848391B2/en
Priority claimed from US13/839,402 external-priority patent/US8787034B2/en
Application filed by Invensas Corporation filed Critical Invensas Corporation
Priority to JP2015529922A priority Critical patent/JP6185995B2/ja
Publication of WO2014035950A1 publication Critical patent/WO2014035950A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1052—Wire or wire-like electrical connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • microelectronic structures e.g., structures incorporating active circuit elements, such as, without limitation, structures including at least one semiconductor chip or portion of at least one semiconductor chip, as well as assemblies incorporating microelectronic structures.
  • a standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip.
  • Each individual chip typically is contained in a package having external terminals connected to the contacts of the chip.
  • the terminals i.e., the external connection points of the package, are configured to electrically connect to a circuit panel, such as a printed circuit board.
  • the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself.
  • the "area of the chip” should be understood as referring to the area of the front face.
  • Size is a significant consideration in any physical arrangement of chips.
  • the demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices.
  • devices commonly referred to as "smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips.
  • Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device.
  • Complex portable devices require packing numerous chips into a small space.
  • I/Os input and output connections
  • the components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
  • Microelectronic elements such as semiconductor chips which contain memory storage arrays, particularly dynamic random access memory chips (DRAMs) and flash memory chips, are commonly packaged in single- or multiple-chip packages and assemblies. Each package has many electrical connections for carrying signals, power and ground between terminals and the microelectronic elements, e.g., chips therein.
  • the electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extend in both horizontal and vertical directions relative to the surface of the chip.
  • microelectronic packages can incorporate a microelectronic element having active elements defining a memory storage array.
  • transistors or other active elements constitute a memory storage array with or without additional elements.
  • the microelectronic element can be configured to predominantly provide memory storage array function, i.e., in which case microelectronic element may embody a greater number of active elements to provide memory storage array function than any other function.
  • a microelectronic element may be or include a DRAM chip, or may be or include a stacked electrically interconnected assembly of such semiconductor chips.
  • all of the terminals of such package are placed in sets of columns adjacent to one or more peripheral edges of a package substrate to which the microelectronic element is mounted.
  • circuit panels or other microelectronic components are typically configured to be coupled to a microelectronic package having one or more first type microelectronic elements therein. Such circuit panels or other microelectronic components typically cannot be coupled to a microelectronic package having one or more microelectronic elements therein that are of a different or second type.
  • a component can be configured for connection with a microelectronic assembly which includes a set of terminals and a microelectronic element having a memory storage array having a given number of storage locations, the microelectronic element of the assembly having inputs connected with the terminals for receiving command and address information specifying one of the storage locations.
  • the component can include a support structure bearing a set of conductors configured to carry the command and address information, and a plurality of contacts coupled to the set of conductors, the contacts configured for connection with corresponding ones of the terminals of the microelectronic assembly.
  • the contacts can have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through the contacts at a first sampling rate, the contacts having a first number thereof.
  • the contacts can have address and command information assignments arranged according to a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts including a second number of the contacts at a second sampling rate being greater than the first sampling rate, the subset including some contacts occupying identical positions with the contacts that are assigned to the first predetermined arrangement, the second number being fewer than the first number .
  • all of the contacts of the subset of contacts arranged according to the second predetermined arrangement can occupy identical positions with the contacts that are assigned to the first predetermined arrangement.
  • the second sampling rate can be an integer multiple of the first sampling rate.
  • the component can also include a device coupled to the set of conductors, the device being operable to drive the command and address information to the contacts.
  • the device can be a microprocessor.
  • the device can be a buffering element.
  • the device can be configured to operate in each of first and second modes for connection of the component with the first type microelectronic assembly via the first arrangement, and with the second type microelectronic assembly via the second arrangement, respectively.
  • the component can also include the first type microelectronic assembly, wherein the contacts are electrically connected with the terminals.
  • the component can also include the second type microelectronic assembly, wherein the contacts are electrically connected with the terminals.
  • the component can be a circuit panel, and the contacts can be exposed at a surface of the circuit panel.
  • the microelectronic assembly can be a microelectronic package, and wherein the terminals can be surface mount terminals and can be exposed at a surface of the microelectronic package.
  • the component can be a circuit panel, and the contacts can be disposed in a socket electrically connected with the circuit panel.
  • the microelectronic assembly can include a module card having first and second opposed surfaces.
  • the terminals can be a plurality of parallel exposed terminals at at least one of the first and second surfaces for mating with the contacts of the socket when the module is inserted in the socket.
  • the component can be a circuit panel and the contacts can be disposed in a connector electrically connected with the circuit panel.
  • the microelectronic assembly can include a module card having first and second opposed surfaces.
  • the terminals can be a plurality of terminals exposed at one of the first and second surfaces for mating with the contacts of the connector when the module is attached to the connector.
  • the microelectronic assembly can be a first microelectronic assembly and the component can be a second microelectronic assembly, and the contacts can be terminals of the second microelectronic assembly.
  • the second microelectronic assembly can be coupled to the support structure and can include a microelectronic element having active devices therein. The terminals of the second microelectronic assembly can be coupled with the microelectronic element of the second microelectronic assembly by electrical connections that extend only within the second microelectronic assembly .
  • the electrical connections between the terminals of the second microelectronic assembly and the microelectronic element of the second microelectronic assembly can include interconnection elements extending in a direction normal to a surface of the second microelectronic assembly at which the terminals of the second microelectronic assembly are exposed.
  • the interconnection elements can be configured for package-on-package stacking.
  • the electrical connections between the terminals of the second microelectronic assembly and the microelectronic element of the second microelectronic assembly can include a bond via array extending from the terminals of the second microelectronic assembly to contacts exposed at a surface of a substrate of the second microelectronic assembly.
  • the second microelectronic assembly can be coupled to the support structure and can include a microelectronic element having active devices therein.
  • the terminals of the second microelectronic assembly can be exposed at a surface of the microelectronic element of the second microelectronic assembly.
  • the microelectronic element of the second microelectronic assembly can be a first microelectronic element.
  • the second microelectronic assembly can also include at least one second microelectronic element each having active devices therein.
  • the first and second microelectronic elements can be arranged in a stacked configuration.
  • the terminals of the second microelectronic assembly can be electrically connected with the set of conductors of the support structures by through- silicon vias extending through the at least one second microelectronic element.
  • the microelectronic element of the second microelectronic assembly can include a logic function.
  • the contacts can be first contacts and the conductors can be a first set of conductors.
  • the component can also include a plurality of second contacts coupled to a second set of conductors.
  • the second contacts can be configured for connection with corresponding terminals of the microelectronic assembly.
  • the second contacts can be configured to carry information other than the command and address information.
  • the contacts can be first contacts and the conductors can be a first set of conductors.
  • the component can also include a plurality of power and ground contacts coupled to a second set of conductors.
  • the power and ground contacts can be configured for connection with corresponding terminals of the microelectronic assembly.
  • the power and ground contacts can be configured to carry a power potential and a reference potential, respectively.
  • the microelectronic element of the second type of the microelectronic assembly when the first contacts have assignments arranged according to the second predetermined arrangement, can be configured to connect with the power and ground contacts, the power and ground contacts having a third number thereof.
  • the microelectronic element of the first type of the microelectronic assembly can be configured to connect with a subset of the power and ground contacts including a fourth number of the power and ground contacts, the fourth number being fewer than the third number.
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDRx .
  • the microelectronic element in the second type of the microelectronic assembly can be of type LPDDRx .
  • the microelectronic element in the first type of the microelectronic assembly can be of type GDDRx .
  • a system can include a component as described above and one or more other electronic components electrically connected to the component.
  • the system can also include a housing, the component and the one or more other electronic components being assembled with the housing.
  • a component can be configured for connection with a microelectronic assembly which includes a set of terminals and a microelectronic element having a memory storage array having a given number of storage locations, the microelectronic element of the assembly having inputs connected with the terminals for receiving command and address information specifying one of the storage locations.
  • the component can include a support structure bearing a set of conductors configured to carry the command and address information, and a plurality of contacts coupled to the set of conductors, the contacts configured for connection with corresponding ones of the terminals of the microelectronic assembly.
  • the contacts can have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a first subset of the contacts including a first number of the contacts.
  • the contacts can have address and command information assignments arranged according to a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a second subset of the contacts including a second number of the contacts, the first and second subsets including some contacts occupying identical positions, the second number being fewer than the first number.
  • the command and address information of the first type of the microelectronic assembly can include parity information
  • the microelectronic element in the first type of the microelectronic assembly can be configured to sample the parity information
  • the second subset of the contacts for connection with the second type of the microelectronic assembly may not be configured to sample the parity information.
  • the microelectronic element in the second type of the microelectronic assembly can be of type DDR3
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDR4.
  • the command and address information of the first type of the microelectronic assembly having the DDR4 type microelectronic element can include parity information
  • the DDR4 type microelectronic element in the first type of the microelectronic assembly can be configured to sample the parity information.
  • the microelectronic element in the second type of the microelectronic assembly can be of type DDRx
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDR(x+l) .
  • a module can be configured for connection with at least one microelectronic assembly, each microelectronic assembly including a set of terminals and a microelectronic element having a memory storage array having a given number of storage locations, the microelectronic element of each microelectronic assembly having inputs connected with the terminals for receiving command and address information specifying one of the storage locations.
  • the module can include a circuit panel having first and second opposed surfaces and bearing a set of conductors configured to carry the command and address information, and at least one set of co-support contacts coupled to the set of conductors. Each set of co-support contacts can be exposed at the first surface or the second surface. Each set of co-support contacts can be configured for connection to the set of terminals of a single microelectronic assembly of the at least one microelectronic assembly.
  • the module can also include a plurality of module contacts coupled to the set of conductors.
  • the module contacts can be configured for carrying information for transfer to and from the at least one set of co-support contacts.
  • the module contacts can be configured for connection with a component external to the module.
  • Each of the at least one set of co- support contacts can include first contacts that have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through the first contacts at a first sampling rate, the first contacts having a first number thereof .
  • Each of the at least one set of co-support contacts can include first contacts that have address and command information assignments arranged according to a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts including a second number of the first contacts at a second sampling rate being greater than the first sampling rate, the subset including some first contacts occupying identical positions with the first contacts which are assigned to the first predetermined arrangement, the second number being fewer than the first number.
  • all of the contacts of the subset of first contacts arranged according to the second predetermined arrangement can occupy identical positions with the first contacts that are assigned to the first predetermined arrangement.
  • the second sampling rate can be an integer multiple of the first sampling rate.
  • the first contacts in each set of co-support contacts can include contacts assigned for carrying address information usable to specify a location within the memory storage array.
  • the module can include a device coupled to the set of conductors, the device being operable to drive the command and address information to the first contacts.
  • the device can be a buffering element.
  • the device can be configured to operate in each of first and second modes for connection of the module with the first type microelectronic assembly via the first arrangement, and with the second type microelectronic assembly via the second arrangement, respectively.
  • the module can include the first type microelectronic assembly.
  • a set of the at least one set of co-support contacts can be electrically connected with the terminals of the first type microelectronic assembly.
  • the module can include the second type microelectronic assembly.
  • a set of the at least one set of co- support contacts can be electrically connected with the terminals of the second type microelectronic assembly.
  • the microelectronic assembly can be a microelectronic package.
  • the terminals can be surface mount terminals and can be exposed at a surface of the microelectronic package.
  • the circuit panel can be a module card.
  • the module contacts can be a plurality of parallel exposed contacts at at least one of the first and second surfaces for mating with contacts of a socket of a second circuit panel when the module is inserted in the socket.
  • the circuit panel can be a module card.
  • the module contacts can be a plurality of contacts at one of the first and second surfaces for mating with the contacts of a connector of a second circuit panel when the module is attached to the connector.
  • the module contacts can be surface mount contacts exposed at one of the first and second surfaces for facing and electrically connecting with contacts of a second circuit panel when the module is joined with the second circuit panel.
  • each of the at least one set of co-support contacts can include second contacts configured to carry information other than the command and address information.
  • each of the at least one set of co-support contacts can be exposed in a corresponding region of the first surface of the circuit panel. At least some of the second contacts each of the at least one set of co- support contacts can be disposed in first and second areas adjacent to at least first and second opposite edges of a periphery of the region of the respective set of co-support contacts. All of the first contacts of the respective set of co-support contacts can be disposed between the first and second areas of the respective set of co-support contacts.
  • each of the at least one set of co-support contacts can be disposed in third and fourth areas adjacent to at least third and fourth opposite edges of the periphery of the region of the respective set of co-support contacts.
  • Each of the third and fourth edges can extend in a direction between the first and second edges.
  • All of the first contacts of the respective set of co-support contacts can be disposed between the third and fourth areas of the respective set of co-support contacts.
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDRx .
  • the microelectronic element in the second type of the microelectronic assembly can be of type LPDDRx .
  • the microelectronic element in the first type of the microelectronic assembly can be of type GDDRx .
  • the at least one set of co- support contacts can include a first set at the first surface and second set at the first surface spaced apart from the first set in a direction parallel to the first surface.
  • the at least one set of co-support contacts can include a first set at the first surface and second set at the second surface .
  • the first contacts in each set of co-support contacts can include first and second groups of the first contacts, each group of first contacts assigned for carrying address information usable to specify a location within the memory storage array.
  • each of the first contacts of the first group can have a signal assignment that is symmetric about a theoretical axis with the signal assignment of a corresponding first contact of the second group.
  • the microelectronic element of the first type of the microelectronic assembly can be configured to connect with the first contacts in each of the first and second groups.
  • the first type of the microelectronic assembly can include a plurality of microelectronic elements.
  • each set of co-support contacts has assignments arranged according to the first predetermined arrangement
  • each of the plurality of microelectronic elements of the first type of the microelectronic assembly can be configured to connect with the first contacts in each of the first and second groups.
  • the microelectronic element of the second type of the microelectronic assembly can be configured to connect with the first contacts of the first group but not with the first contacts of the second group.
  • the second type of the microelectronic assembly can include a plurality of microelectronic elements comprising a first half of the microelectronic elements and a second half of the microelectronic elements.
  • each set of co-support contacts has assignments arranged according to the second predetermined arrangement
  • each of the first half of the microelectronic elements of the second type of the microelectronic assembly can be configured to connect with the first group of first contacts but not with the second group of first contacts
  • each of the second half of the microelectronic elements of the second type of the microelectronic assembly can be configured to connect with the second group of first contacts but not with the first group of first contacts.
  • a system can include a module as described above and one or more other electronic components electrically connected to the module.
  • the system can also include a housing, the module and the one or more other electronic components being assembled with the housing.
  • a module can be configured for connection with at least one microelectronic assembly, each microelectronic assembly including a set of terminals and a microelectronic element having a memory storage array having a given number of storage locations, the microelectronic element of each microelectronic assembly having inputs connected with the terminals for receiving command and address information specifying one of the storage locations.
  • the module can include a circuit panel having first and second opposed surfaces and bearing a set of conductors configured to carry the command and address information .
  • the module can also include at least one set of co- support contacts coupled to the set of conductors, each set of co-support contacts exposed at the first surface or the second surface, each set of co-support contacts being configured for connection to the set of terminals of a single microelectronic assembly of the at least one microelectronic assembly.
  • the module can also include a plurality of module contacts coupled to the set of conductors, the module contacts being configured for carrying information for transfer to and from the at least one set of co-support contacts, the module contacts configured for connection with a component external to the module.
  • Each of the at least one set of co-support contacts can include first contacts that have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a first subset of the first contacts including a first number of the first contacts.
  • Each of the at least one set of co-support contacts can include first contacts that have address and command information assignments arranged according to a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a second subset of the first contacts including a second number of the first contacts, the first and second subsets including some first contacts occupying identical positions, the second number being fewer than the first number.
  • the command and address information of the first type of the microelectronic assembly can include parity information
  • the microelectronic element in the first type of the microelectronic assembly can be configured to sample the parity information
  • the second subset of the first contacts for connection with the second type of the microelectronic assembly may not be configured to sample the parity information.
  • the microelectronic element in the second type of the microelectronic assembly can be of type DDR3
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDR4.
  • the command and address information of the first type of the microelectronic assembly having the DDR4 type microelectronic element can include parity information
  • the DDR4 type microelectronic element in the first type of the microelectronic assembly can be configured to sample the parity information.
  • the microelectronic element in the second type of the microelectronic assembly can be of type DDRx
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDR(x+l) .
  • a system can include a microelectronic assembly which includes a set of terminals and a microelectronic element having a memory storage array having a given number of storage locations, the microelectronic element of the assembly having inputs connected with the terminals for receiving command and address information specifying one of the storage locations, and a component for connection with the microelectronic assembly.
  • the component can include a support structure bearing a set of conductors configured to carry the command and address information, and a plurality of contacts coupled to the set of conductors, the contacts electrically connected with corresponding ones of the terminals of the microelectronic assembly.
  • the contacts can have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through the contacts at a first sampling rate, the contacts having a first number thereof.
  • the contacts can have address and command information assignments arranged according to a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts including a second number of the contacts at a second sampling rate being greater than the first sampling rate, the subset including some contacts occupying identical positions with the contacts that are assigned to the first predetermined arrangement, the second number being fewer than the first number .
  • all of the contacts of the subset of contacts arranged according to the second predetermined arrangement can occupy identical positions with the contacts that are assigned to the first predetermined arrangement.
  • the second sampling rate can be an integer multiple of the first sampling rate.
  • the system can also include a device coupled to the set of conductors, the device being operable to drive the command and address information to the contacts.
  • the device can be a microprocessor.
  • the device can be configured to operate in each of first and second modes for connection of the component with the first type microelectronic assembly via the first arrangement, and with the second type microelectronic assembly via the second arrangement, respectively.
  • the system can also include at least one central processing unit (“CPU") .
  • the CPU can be configured to control operations of a plurality of components in the system including read operations from the microelectronic assembly and write operations to the microelectronic assembly.
  • the system can also include a power supply configured to supply power for use by the component and the microelectronic assembly.
  • the microelectronic assembly can be the first type microelectronic assembly.
  • the microelectronic assembly can be the second type microelectronic assembly.
  • the component can be a circuit panel, and the contacts can be exposed at a surface of the circuit panel.
  • the microelectronic assembly can be a microelectronic package.
  • the terminals can be surface mount terminals exposed at a surface of the microelectronic package.
  • the circuit panel can be a motherboard.
  • the circuit panel can be a module card, the module card including one or more rows of exposed module contacts, at least one of the rows of module contacts disposed adjacent an edge of the first or second surfaces for mating with contacts of a socket of a second circuit panel when the module is inserted in the socket.
  • the component can be a circuit panel, and the contacts can be disposed in a socket electrically connected with the circuit panel.
  • the microelectronic assembly can include a module card having first and second opposed surfaces. The terminals can be a plurality of parallel exposed terminals adjacent an edge of at least one of the first and second surfaces for mating with the contacts of the socket when the module is inserted in the socket.
  • the component can be a circuit panel and the contacts can be disposed in a connector electrically connected with the circuit panel.
  • the microelectronic assembly can include a module card having first and second opposed surfaces. The terminals can be a plurality of parallel terminals exposed at one of the first and second surfaces for mating with the contacts of the connector when the module is attached to the connector.
  • the microelectronic assembly can be a first microelectronic assembly and the component can be a second microelectronic assembly, and the contacts can be terminals of the second microelectronic assembly .
  • the second microelectronic assembly can be coupled to the support structure and includes a microelectronic element having active devices therein.
  • the microelectronic element of the first microelectronic assembly can be coupled with the microelectronic element of the second microelectronic assembly by electrical connections that extend only within the first and second microelectronic assemblies.
  • the electrical connections between the microelectronic element of the first microelectronic assembly and the microelectronic element of the second microelectronic assembly can include interconnection elements extending in a direction normal to a surface of the second microelectronic assembly at which the terminals of the second microelectronic assembly are exposed.
  • the interconnection elements can be configured for package-on-package stacking.
  • the electrical connections between the microelectronic element of the first microelectronic assembly and the microelectronic element of the second microelectronic assembly can include a bond via array extending from the terminals of the second microelectronic assembly to contacts exposed at a surface of a substrate of the second microelectronic assembly.
  • the second microelectronic assembly can be coupled to the support structure and includes a microelectronic element having active devices therein, the terminals of the second microelectronic assembly being exposed at a surface of the microelectronic element of the second microelectronic assembly.
  • the microelectronic element of the second microelectronic assembly can be a first microelectronic element.
  • the second microelectronic assembly can also include at least one second microelectronic element each having active devices therein.
  • the first and second microelectronic elements can be arranged in a stacked configuration.
  • the terminals of the second microelectronic assembly can be electrically connected with the set of conductors of the support structures by through-silicon vias extending through the at least one second microelectronic element.
  • the microelectronic element of the second microelectronic assembly can include a logic function.
  • the contacts can be first contacts and the conductors can be a first set of conductors.
  • the component can also include a plurality of second contacts coupled to a second set of conductors.
  • the second contacts can be configured for connection with corresponding terminals of the microelectronic assembly.
  • the second contacts can be configured to carry information other than the command and address information .
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDRx .
  • the microelectronic element in the second type of the microelectronic assembly can be of type LPDDRx .
  • the microelectronic element in the first type of the microelectronic assembly can be of type GDDRx .
  • a system as described above can include one or more other electronic components electrically connected to the component.
  • the system can include a housing, the component and the one or more other electronic components being assembled with the housing.
  • a system can include a microelectronic assembly which includes a set of terminals and a microelectronic element having a memory storage array having a given number of storage locations, the microelectronic element of the assembly having inputs connected with the terminals for receiving command and address information specifying one of the storage locations, and a component for connection with the microelectronic assembly.
  • the component can include a support structure bearing a set of conductors configured to carry the command and address information, and a plurality of contacts coupled to the set of conductors, the contacts electrically connected with corresponding ones of the terminals of the microelectronic assembly.
  • the contacts can have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a first subset of the contacts including a first number of the contacts.
  • the contacts can have address and command information assignments arranged according to a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a second subset of the contacts including a second number of the contacts, the first and second subsets including some contacts occupying identical positions, the second number being fewer than the first number.
  • the command and address information of the first type of the microelectronic assembly can include parity information
  • the microelectronic element in the first type of the microelectronic assembly can be configured to sample the parity information
  • the second subset of the contacts for connection with the second type of the microelectronic assembly may not be configured to sample the parity information.
  • the microelectronic element in the second type of the microelectronic assembly can be of type DDR3
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDR4.
  • the command and address information of the first type of the microelectronic assembly having the DDR4 type microelectronic element can include parity information
  • the DDR4 type microelectronic element in the first type of the microelectronic assembly can be configured to sample the parity information.
  • the microelectronic element in the second type of the microelectronic assembly can be of type DDRx
  • the microelectronic element in the first type of the microelectronic assembly can be of type DDR(x+l) .
  • FIG. 1 is a schematic view illustrating a component according to an embodiment of the invention.
  • FIG. 2A is a side sectional view illustrating a component having a microelectronic package and a circuit panel according to an embodiment of the invention.
  • FIG. 2B is a side sectional view illustrating a component having a microelectronic package and a module card according to an embodiment of the invention.
  • FIG. 2C is a side sectional view illustrating a component having a first type microelectronic package and a circuit panel according to an embodiment of the invention.
  • FIG. 2D is a side sectional view illustrating a component having a second type microelectronic package and a circuit panel according to an embodiment of the invention.
  • FIG. 3A is a side sectional view illustrating a component having a module and a circuit panel according to an embodiment of the invention.
  • FIG. 3B is a side sectional view illustrating a component having a module and a circuit panel according to a variation of the embodiment of the invention seen in FIG. 3A.
  • FIG. 3C is a perspective view illustrating the module card of FIG. 3A having various potential configurations of terminals .
  • FIG. 4A is a side sectional view illustrating a component having a package-on-package structure and a circuit panel according to an embodiment of the invention.
  • FIG. 4B is a side sectional view illustrating a component having a package-on-package structure according to an embodiment of the invention.
  • FIG. 4C is a side sectional view illustrating a component having a package-on-package structure according to an embodiment of the invention.
  • FIG. 5A is a side sectional view illustrating a component having a microelectronic package, a TSV stack, and a circuit panel according to an embodiment of the invention.
  • FIG. 5B is a side sectional view illustrating a component having a microelectronic package and a TSV stack according to an embodiment of the invention.
  • FIG. 6 is a schematic sectional view illustrating a system according to an embodiment of the invention.
  • FIG. 7 is a schematic sectional view illustrating a system according to an embodiment of the invention.
  • FIG. 1 A component 5 according to an embodiment of the invention is illustrated in FIG. 1. As seen in FIG. 1, the component 5 is configured to be connected with a microelectronic assembly 10.
  • the microelectronic assembly 10 includes a set of terminals 25 and a microelectronic element 30 having a memory storage array having a given number of storage locations.
  • the microelectronic element 30 has element contacts 35 including inputs 35a connected with the terminals 25 for receiving command and address information specifying one of the storage locations, and other element contacts 35b for sending and receiving information other than the command and address information (e.g., data information).
  • the microelectronic assembly 10 can take various forms, for example, as described below with reference to FIGS. 2-5.
  • the microelectronic assembly 10 can include active elements, e.g., active devices such as transistors, or other active elements thereon, which, with or without additional elements, define a memory storage array.
  • active elements e.g., active devices such as transistors, or other active elements thereon, which, with or without additional elements, define a memory storage array.
  • the active elements and the memory storage array defined by the active elements can be incorporated in a portion of a microelectronic element 30, or in one or more microelectronic elements, e.g., one or more semiconductor chips, of the microelectronic assembly 10, or may be incorporated in one or more microelectronic packages of the microelectronic assembly.
  • the microelectronic assembly 10 may be, for example, a microelectronic package or portion thereof wherein the terminals 25 are exposed at a surface of the microelectronic package.
  • the microelectronic assembly can include a plurality of electrically connected microelectronic packages or a structure that includes electrically connected microelectronic elements, semiconductor chips, or portions of microelectronic elements or semiconductor chips, or portions of microelectronic packages .
  • an electrically conductive element is "exposed at" a surface of a structure indicates that the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface toward the surface from outside the structure.
  • a terminal or other conductive element which is exposed at a surface of a structure can project from such surface; can be flush with such surface; or can be recessed relative to such surface and exposed through a hole or depression in the structure.
  • the memory storage array of the one or more microelectronic elements 30 comprises a functional part of the microelectronic assembly 10 whose role may be subservient to another functional part of the microelectronic assembly.
  • the microelectronic assembly 10 may include a logic functional part, e.g., processor, and a memory functional part, and the memory functional part may assist with or help serve a function of the logic functional part.
  • the microelectronic assembly 10 may be configured to predominantly provide memory storage array function.
  • the microelectronic assembly 10 may have a greater number of active elements, e.g., active devices such as transistors, configured to provide memory storage array function than the number of active elements in other components of the microelectronic assembly that are configured to provide function other than memory storage array function.
  • active elements e.g., active devices such as transistors
  • the microelectronic assembly 10 may contain wiring therein that directly electrically couples a set of the terminals 25, e.g., "first terminals" 25a, with corresponding address inputs 35a of the microelectronic element 30.
  • each "first terminal” 25a has a signal assignment on the microelectronic assembly 10 that includes one or more of the address inputs 35a.
  • the microelectronic assembly 10 may include a buffer element, such as a semiconductor chip having a plurality of active elements thereon, such semiconductor chip being configured to at least one of regenerate, or partially or fully decode at least one of address or command information received at the terminals 25 for transfer by the microelectronic structure to the address inputs.
  • Command information may be information that controls an operating mode of a memory storage array or portion thereof within the microelectronic assembly 10.
  • the microelectronic assembly 10 is configured to provide address information received at the first terminals 25a to the address inputs 35a of the one or more microelectronic elements 30.
  • address information or command address bus information or signals and the address inputs of a microelectronic element or portion thereof a statement that address information on terminals is "provided to address inputs" means that the address information on the terminals is transferred to the address inputs via electrical connections therewith, or through a buffer element which may perform at least one of regenerating, partially decoding or decoding of the address information received at the terminals .
  • each one of some contacts of the address inputs 35a may be configured to receive particular address information of the address information supplied to the microelectronic element.
  • each of such contacts may be an address input 35a configured to receive address information, supplied to the microelectronic element 30 from outside the microelectronic element, i.e., through wiring of the microelectronic package 10 such as wire bonds, and through the first terminals 25a.
  • Contacts of the microelectronic elements 30 may also be configured to receive other information or signals from outside the microelectronic element.
  • the first terminals 25a can be configured to carry address information transferred to the microelectronic assembly 10 that is usable by circuitry within the microelectronic assembly, e.g., row address and column address decoders, and bank selection circuitry, if present, to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within a microelectronic element in the microelectronic assembly.
  • the first terminals 25a can be configured to carry all the address information used by such circuitry within the microelectronic assembly 10 to determine an addressable memory location within such memory storage array.
  • Each of the first terminals 25a can be configured to carry address information sufficient to specify a location within the memory storage array of the microelectronic assembly 10.
  • the address information in one embodiment can include all address information transferred to the microelectronic assembly from a component external to the microelectronic structure, e.g., the component 5, which is used for determining a random access addressable memory location within the microelectronic assembly for read access thereto, or for either read or write access thereto .
  • the first terminals 25a can be configured to carry information that controls an operating mode of one or more of the microelectronic elements 30. More specifically, the first terminals 25a can be configured to carry all of a particular set of command signals and/or clock signals transferred to the microelectronic assembly 10. In one embodiment, the first terminals 25a can be configured to carry all of the command signals, address signals, bank address signals, and clock signals transferred to the assembly 10 from an external component, e.g., the component 5, wherein the command signals include row address strobe, column address strobe and write enable.
  • the command signals include row address strobe, column address strobe and write enable.
  • the command signals can be write enable, row address strobe, and column address strobe signals.
  • Other signals such as ODT (on die termination) , chip select, clock enable, may or may not be carried by the first terminals 25a.
  • the clock signals can be clocks used by one or more of the microelectronic elements for sampling the address signals.
  • second terminals 25 can also include second terminals 25b that are configured to carry (send and/or receive) information other than the command and address information, such as data signals. At least some of the second terminals 25b can be configured to carry signals other than the address signals that are carried by the first terminals 25a. In particular examples, the second terminals 25b may carry one or more of data, data strobe signals, or other signals or reference potentials such as chip select, reset, power supply voltages, e.g., Vdd, Vddq, and ground, e.g., Vss and Vssq. The second terminals 25b may be electrically connected with the other element contacts 35b for sending and receiving information other than the command and address information.
  • the second terminals 25b can include terminals used for carrying uni-directional or bi-directional data signals to and or from the microelectronic elements 30, and data strobe signals, as well as data masks and ODT or "on die termination" signals used to turn on or off parallel terminations to termination resistors.
  • the second terminals 25b may carry signals such as reset, as well as reference potentials such as power supply voltages, e.g., Vdd, Vddq, or ground, e.g., Vss and Vssq.
  • the command and address information present at the element contacts 35a can be sampled relative to an edge of a clock used by the respective microelectronic element, i.e., upon on a transition of the clock between first and second different voltage states. That is, each command and address signal can be sampled upon a rising transition between a lower voltage state and a higher voltage state of the clock, or upon a falling transition between a higher voltage state and a lower voltage state of the clock.
  • the plurality of command and address signals may all be sampled upon the rising transition of the clock, or such command and address signals may all be sampled upon the falling transition of the clock, or in another example, the command or address signal at one of the element contacts 35a can be sampled upon the rising transition of the clock and the command or address signal at one other external contact can be sampled upon the falling transition of the clock.
  • microelectronic element 30 which may be configured to predominantly provide memory storage array function, one or more of the command or address address contacts 35a thereon can be used in a multiplexed manner.
  • a particular element contact 35a of the respective microelectronic element 30 can receive two or more different signals supplied to the microelectronic element from the outside.
  • a first command or address address signal can be sampled at the particular contact 35a upon a first transition of the clock between the first and second different voltage states (e.g., a rising transition), and a signal other than the first command or address address signal can be sampled at the particular contact upon a second transition of the clock (e.g., a falling transition) between the first and second voltage states that is opposite the first transition.
  • first transition of the clock between the first and second different voltage states
  • a signal other than the first command or address address signal can be sampled at the particular contact upon a second transition of the clock (e.g., a falling transition) between the first and second voltage states that is opposite the first transition.
  • multiplexing in this manner can allow a first address command or address signal and a different signal to be received in the same clock cycle on the same element contact 35a of the respective microelectronic element 30.
  • multiplexing in this manner can allow a first command or address signal and a second different command or address signal to be received in the same clock cycle on the same element contact 35a of the respective microelectronic element 30.
  • the operational parameters may pertain to timing such as the number of clock cycles of latency after the row address strobe signal is detected in an enabled state by circuitry of the microelectronic assembly 10 (hereinafter, "RAS latency") , or may pertain to the number of clock cycles of latency after the column address strobe signal is detected in an enabled state by circuitry of the microelectronic assembly, or may pertain to the capacity of the microelectronic assembly, e.g., such as one gigabit (“1Gb"), two gigabit (“2Gb”), etc., or may pertain to the organization of the microelectronic assembly, such as a "single-rank", “2-rank”, “4-rank” or other structure, etc., or other operating parameter, or a combination of the foregoing operational parameters, or other operating parameter.
  • RAS latency the capacity of the microelectronic assembly
  • the nonvolatile memory may store information of a single one of the aforementioned parameters or may store information of any combination of the operational parameters, without limitation.
  • the nonvolatile memory may contain a table of known bad memory locations within the memory storage array of the microelectronic assembly 10 which should be avoided during read or write access to the memory storage array.
  • the component 5 includes a support structure 60 (e.g., a circuit panel) bearing a first set of conductors 70 configured to carry the command and address information.
  • the support structure 60 can take many different forms, such as a circuit panel 160 (FIG. 2A) , a module card 160b (FIG. 2B) , an interconnection substrate 342 (FIG. 4B) , a molded region 348 (FIG. 4C) , a microelectronic element 440 (FIG. 5B) , or a dielectric layer overlying a microelectronic element (not shown), among others.
  • the component 5 also includes a plurality of first contacts 65 coupled to the set of conductors 70 and configured for connection with corresponding ones of the terminals 25 of the microelectronic assembly 10.
  • the first set of conductors 70 can include at least one bus having a plurality of signal lines configured to carry all of the address information transferred to the first contacts 65.
  • the first contacts 65 can be electrically connected with the at least one bus of the first set of conductors 70.
  • connection between the contacts 65 of the component 5 and the terminals 25 of the microelectronic assembly 10 can take various forms, for example, as described below with reference to FIGS. 2-5.
  • the contacts 65 have a plurality of predetermined arrangements of address and command information assignments, so that the contacts can be connected with terminals 25 of a microelectronic assembly 10 having one or more microelectronic elements 30 of a plurality of types (e.g., DDRx, GDDRx, LPDDRx, etc.).
  • the contacts 65 are arranged according to a first predetermined arrangement for connection with a first type of the microelectronic assembly 10 in which the one or more microelectronic elements 30 are configured to sample the command and address information coupled thereto through a first subset of the contacts including a first number of the contacts (which may be some or all of the contacts) at a first sampling rate (e.g., DDR3 or DDR4) .
  • a first sampling rate e.g., DDR3 or DDR4
  • the same contacts 65 can be arranged according to a second predetermined arrangement for connection with a second type of microelectronic assembly 10 in which the one or more microelectronic elements 30 are configured to sample the command and address information coupled thereto through a second subset of the contacts including a second number of the contacts fewer than the first number at a second sampling rate being greater than the first sampling rate (e.g., LPDDR3 ) .
  • the first and second subsets of the contacts 65 include some contacts occupying identical positions.
  • the contacts 65 that can be arranged according to two different predetermined arrangements for connection with two different types of the microelectronic assembly 10, respectively, are also referred to herein as "co-support contacts.”
  • the second sampling rate can be an integer multiple of the first sampling rate.
  • the component 5 may be configured such that when a first type of the microelectronic assembly 10 having DDR3 or DDR4 memory therein is attached to the component, the microelectronic elements 30 in the microelectronic assembly can be configured to sample the command and address information coupled thereto through a first number of the contacts 65 at a first sampling rate, such as once per clock cycle (e.g., on the rising edge of the clock cycle) .
  • the component 5 may be configured such that when a second type of the microelectronic assembly 10 having LPDDR3 memory therein is attached to the component, the microelectronic elements 30 in the microelectronic assembly can be configured to sample the command and address information coupled thereto through a second number of the contacts 65 at a second sampling rate, such as twice per clock cycle (e.g., once each on the rising edge and falling edge of the clock cycle) . Therefore, in this example, the second sampling rate is an integer multiple (2) of the first sampling rate.
  • the component 5 may be configured such that when a first type of the microelectronic assembly 10 having DDR3 or DDR4 memory therein is attached to the component, the microelectronic elements 30 in the microelectronic assembly can be configured to sample the command and address information coupled thereto through a first number of the contacts 65 at a first sampling rate of once per clock cycle.
  • the component 5 may be configured such that when a second type of the microelectronic assembly 10 having a different type of memory therein is attached to the component, the microelectronic elements 30 in the microelectronic assembly can be configured to sample the command and address information coupled thereto through a second number of the contacts 65 at a second sampling rate of four times per clock cycle (e.g., once each on every quarter of the clock cycle) . Therefore, in this example, the second sampling rate is also an integer multiple (4) of the first sampling rate.
  • the second sampling rate can be a non-integer multiple of the first sampling rate.
  • the component 5 may be configured such that when a first type of the microelectronic assembly 10 having memory therein is attached to the component, the microelectronic elements 30 in the microelectronic assembly can be configured to sample the command and address information coupled thereto through a first number of the contacts 65 at a first sampling rate of four times per clock cycle (e.g., once each on every quarter of the clock cycle) .
  • the component 5 may be configured such that when a second type of the microelectronic assembly 10 having memory therein is attached to the component, the microelectronic elements 30 in the microelectronic assembly can be configured to sample the command and address information coupled thereto through a second number of the contacts 65 at a second sampling rate of six times per clock cycle (e.g., once each on every sixth of the clock cycle) . Therefore, in this example, the second sampling rate is a non-integer multiple (1.5) of the first sampling rate.
  • the second sampling rate is a non-integer multiple of the first sampling rate
  • such a non-integer relationship between the first and second sampling rates can occur when sampling of the command and address information by the microelectronic elements 30 is only performed during some clock cycles but not other clock cycles.
  • the component 5 may be configured such that when a first type of the microelectronic assembly 10 having DDR3 or DDR4 memory therein is attached to the component, the microelectronic elements 30 in the microelectronic assembly can be configured to sample the command and address information coupled thereto through a first number of the contacts 65 at a first sampling rate of one time every other clock cycle.
  • the component 5 may be configured such that when a second type of the microelectronic assembly 10 having another type of memory therein is attached to the component, the microelectronic elements 30 in the microelectronic assembly can be configured to sample the command and address information coupled thereto through a second number of the contacts 65 at a second sampling rate of two times every third clock cycle (e.g., once each on the rising edge and falling edge of every third clock cycle) . Therefore, in this example, the second sampling rate is a non-integer multiple (1.5) of the first sampling rate.
  • the invention contemplates many other integer and non-integer multiple relationships between the second sampling rate and the first sampling rate, in examples where sampling of the command and address information by the microelectronic elements 30 is performed during every clock cycle, and in examples where sampling of the command and address information by the microelectronic elements is only performed during some clock cycles but not other clock cycles.
  • the same predetermined arrangement of contacts 65 of the component 5 can be used to connect with first type microelectronic assemblies 10 that include microelectronic elements which operate according to the industry standard DDR3 or DDR4 specification, or to connect with second type microelectronic structures that include microelectronic elements compliant with the industry standard LPDDR3 specification.
  • some of the terminals 25 can be no-connect terminals that may not be needed to transfer address information to the address inputs 35a of one or more memory storage arrays in the microelectronic assembly 10.
  • a "no-connect terminal" of a microelectronic assembly means a terminal that is not connected in any electrical path, e.g., path for conducting information to any microelectronic element 30, e.g., semiconductor chip, within the microelectronic assembly 10, whether or not there is ever any information present on such no-connect terminal.
  • any electrical path e.g., path for conducting information to any microelectronic element 30, e.g., semiconductor chip, within the microelectronic assembly 10, whether or not there is ever any information present on such no-connect terminal.
  • the information present on the no-connect terminal is not in any path to be provided to any microelectronic element 30 within the microelectronic assembly 10.
  • the component 5 can also include a plurality of second contacts 67 coupled to a second set of conductors 71 and configured for connection with corresponding ones of the second terminals 25b of the microelectronic assembly 10.
  • the second contacts 67 can be configured for connection with corresponding second terminals 25b of the microelectronic assembly 10, the second contacts being configured to carry information other than the command and address information, such as data signals.
  • the second set of conductors 71 can have at least one second bus that is electrically connected with at least some of the second contacts 67. Such a second bus can have a plurality of signal lines configured to carry information other than the address and command information.
  • the component 5 can also include a device 80 coupled to the set of conductors, the device operable to drive the command and address information to the contacts.
  • the device 80 can be a driving element electrically connected to the set of conductors 70.
  • the device 80 can be, for example, a microprocessor or a direct memory access controller ("DMA controller").
  • the device 80 can be a buffering element, or a protocol converter that is configured to convert address information having a first protocol that can be used by the component 5 to a second protocol that can be used by the particular type of microelectronic element 30 in the microelectronic assembly 10.
  • the device 80 can be configured to operate in each of first and second modes for connection of the component 5 with the first type microelectronic assembly 10 via the first arrangement of address and command information assignments, and with the second type microelectronic assembly via the second arrangement of address and command information assignments, respectively.
  • the device 80 can be at least one central processing unit ("CPU") ? the CPU configured to control operations of a plurality of components in the system including read operations from the microelectronic assembly 10 and write operations to the microelectronic assembly.
  • the component 5 may include more than one device 80, including both a direct memory access controller and a CPU, for example.
  • the component 5 can further include a power supply configured to supply power for use by the component and the microelectronic assembly 10.
  • FIG. 1 shows only a single microelectronic assembly 10 electrically connected with the component 5, in other embodiments, a plurality of microelectronic assemblies can be electrically connected with the component.
  • FIG. 2A illustrates a component 105 according to a particular example of the invention shown in FIG. 1.
  • the component 105 includes a circuit panel 160, and the contacts 165 are exposed at a first surface 161 of the circuit panel.
  • the circuit panel 160 (and the circuit panel in other embodiments described herein) can be of various types, such as a printed circuit board used in a dual-inline memory module (“DIMM”) module, a circuit board or panel to be connected with other components in a system, or a motherboard, among others.
  • DIMM dual-inline memory module
  • the microelectronic assembly joined to the circuit panel 160 is in the form of a microelectronic package 110.
  • the microelectronic package 110 has one or more microelectronic elements 130 therein having a surface facing a first surface 121 of a package substrate 120.
  • the microelectronic element 130 has address inputs 135 electrically connected to terminals 125 exposed at a second surface 122 of the substrate 120 opposite the first surface 121.
  • the second surface 122 is an exposed surface of the microelectronic package 110.
  • the terminals 125 can be surface mount terminals (e.g., of type BGA, LGA, PGA, etc . ) .
  • FIG. 2A shows only a single microelectronic package 110 electrically connected with the component 105
  • a plurality of microelectronic packages can be electrically connected with the component.
  • all of the microelectronic packages 110 can be attached to the first surface 161 of the circuit panel 160
  • all of the microelectronic packages can be attached to the second surface 162 of the circuit panel
  • one or more microelectronic packages can be attached to the first surface of the circuit panel and one or more microelectronic packages can be attached to the second surface.
  • the microelectronic package 110 may have a plurality of address inputs 135 for receipt of address information specifying locations within the memory storage array.
  • the address inputs 135 may be contacts exposed at a surface of a microelectronic element 130 as described above.
  • the microelectronic package 110 is configured so as to transfer address information received at particular terminals 125 of the microelectronic structure to the address inputs 135.
  • the microelectronic package 110 may couple signals received on particular terminals 125 of the structure to corresponding particular address inputs 135.
  • the address inputs 135 can be exposed at a face of a microelectronic element 130, e.g., a semiconductor chip, wherein the face faces towards the first surface 121 of the substrate 120.
  • the address inputs 135 can be exposed at a face of a microelectronic element 130 that faces away from the first surface 121.
  • a die attach adhesive may be disposed between a rear face of the microelectronic element and the first surface 121 of the substrate 120, which may mechanically reinforce the connection between the microelectronic element and the substrate .
  • a microelectronic element 130 incorporated in the microelectronic assembly 110 may have element contacts 135 at a face thereof that are electrically connected to respective substrate contacts 124 at the first surface 121 or the second surface 122 of the substrate 120.
  • the microelectronic element 130 can be flip-chip bonded to the substrate 120 via conductive joining elements extending between element contacts 135 of the microelectronic element and corresponding substrate contacts 124 at the first surface 121 of the substrate 120.
  • wire bonds may extend through openings in the substrate 120 and may electrically connect the element contacts 135 with substrate contacts at the second surface 122 of the substrate.
  • other types of conductors e.g., portions of a lead frame, flexible ribbon bonds, etc., may be used to electrically connect the element contacts 135 with the respective substrate contacts 124, which in some cases may connect the element contacts with other conductive elements disposed at a greater height from the front surface 121 than the front face of the microelectronic element 130.
  • the contacts 135 may in some cases be connected with active devices of the semiconductor chip 130 through back end of line (“BEOL”) wiring of the semiconductor which may include vias or other electrically conductive structure and which may in some cases be disposed underneath the contacts 135.
  • BEOL back end of line
  • the terminals 125 can be electrically conductive elements, e.g., contacts, pads, posts, pins, sockets, wiring, or other electrically conductive structure that are exposed at a first surface 112 of the microelectronic package 110, which in the example shown in FIG. 2A, is the same surface as the second surface 122 of the substrate 120.
  • electrically conductive elements e.g., contacts, pads, posts, pins, sockets, wiring, or other electrically conductive structure that are exposed at a first surface 112 of the microelectronic package 110, which in the example shown in FIG. 2A, is the same surface as the second surface 122 of the substrate 120.
  • the terminals 125 can be configured to be conductively bonded to corresponding contacts 165 of another element such as the circuit panel 160, such as with a conductive joining element 111.
  • the conductive joining elements 111 may include a bond metal of a fusible conductive material such as solder, tin, indium, gold, a eutectic material, an electrically conductive matrix material containing metal and polymeric material, among others, or other conductive bond material, and may in some cases also include additional structure such as a conductive bump attached to conductive structure of the substrate 120 such as conductive pads or posts.
  • the terminals 125 can be configured to mechanically and electrically engage corresponding features of the circuit panel 160, such as by a pressure or interference fit between corresponding conductive elements of each component, which in some cases, may slide or wipe relative to corresponding conductive surfaces they engage.
  • the terminals 125 can be electrically connected with the substrate contacts 124 through electrically conductive structure on the substrate 120, such as traces and vias, for example.
  • electrically conductive joining units 111 can extend between all of the terminals 125 of the microelectronic assembly and corresponding circuit panel contacts 165.
  • some of the terminals 125 of the microelectric assembly 110 are no-connect terminals (e.g., when the microelectronic element is of the second type, such as LPDDR3 )
  • no-connect terminals may be connected to corresponding circuit panel contacts 65 while not being connected within the microelectronic assembly 110 in any electrical path for conductive information to a microelectronic element 130 within the microelectronic assembly.
  • the substrate 120 (or any of the other package substrates described herein) and/or the circuit panel 160 (or any of the other circuit panels described herein) shown in FIG. 2A can include a sheet-like or board-like dielectric element, which may consist essentially of polymeric material, e.g., a resin or polyimide, among others.
  • the substrate 120 and/or the circuit panel 160 can include a dielectric element having a composite construction such as glass-reinforced epoxy, e.g., of BT resin or FR-4 construction.
  • the dielectric element of the substrate 120 and/or the circuit panel 160 can have a coefficient of thermal expansion in the plane of the dielectric element, i.e., in a direction parallel to a first surface 110 thereof, of up to 30 parts per million per degree Celsius (hereinafter, "ppm/°C")-
  • the substrate 120 can include a supporting element of material having a coefficient of thermal expansion ("CTE") of less than 12 parts per million per degree Celsius, on which the terminals 125 and other conductive structure can be disposed.
  • CTE coefficient of thermal expansion
  • such low-CTE element can consist essentially of glass, ceramic, or semiconductor material or liquid crystal polymer material, or a combination of such materials.
  • the set of conductors 170 can include at least one bus that can extend in a first direction X parallel to the first surface 161 of the circuit panel 160.
  • the at least one bus of the set of conductors 170 can extend in a second direction Y parallel to the first surface 160 of the circuit panel 160, the second direction being transverse to the first direction X.
  • the signal lines of the busses of the set of conductors 170 can be located in the same plane as one another, and each individual signal line can include conductor portions extending in a plurality of planes and in a plurality of directions .
  • the at least one bus of the set of conductors 170 can have a plurality of signal lines configured to carry all of the address information transferred to the contacts 165 of the circuit panel 160.
  • the contacts 165 can be electrically connected with the at least one bus of the set of conductors 170.
  • the at least one bus of the set of conductors 170 can be configured to carry all of the command signals transferred to the contacts 165, the command signals including write enable, row address strobe, and column address strobe signals.
  • the circuit panel 160 can optionally include one or more termination resistors, which can be connected to a terminal voltage source.
  • One or more of the plurality of signal lines of one or more of the busses of the set of conductors 170 can optionally be electrically connected to a termination resistor.
  • the contacts 165 shown in FIG. 2A can be arranged according to a predetermined arrangement that defines relative positions on the first surface 161 of the circuit panel 160 (or the second surface 162 if the contacts 165 are exposed at the second surface) of contacts carrying address and command information and data.
  • the circuit panel 160 can be usable without requiring alteration thereof in first and second modes, each mode being when a given set of the contacts 165 is connected with terminals of a corresponding type of microelectronic package 110.
  • a component 105 can include a circuit panel 160 and a first type microelectronic package 110 having first terminals 125 joined to first contacts 165 of the circuit panel.
  • a component 5 can include a circuit panel 160 and a second type microelectronic package 110 having first terminals 125 joined to first contacts 165 of the circuit panel.
  • the circuit panel 160 can be coupled to a first type of microelectronic package 110 that is operable to sample the address and command information carried by the first contacts 165 once per clock cycle.
  • microelectronic packages may be of type DDR3 or DDR4 for example, or of type GDDR3, GDDR4 or GDDR5.
  • DDRx double data rate DRAM memory and low power double data rate DRAM, and graphics double data rate DRAM memory
  • LPDDR3 low power double data rate DRAM
  • GDDRx graphics double data rate DRAM memory
  • the circuit panel 160 in the second mode, can be coupled to a second type of microelectronic package 110 that is operable to sample the address and command information carried by the first contacts 165 twice per clock cycle.
  • microelectronic packages 110 may be of type LPDDRx, e.g., LPDDR3 or LPDDR4 among existing and planned standards.
  • circuit panel 160 can be coupled to a first type of microelectronic package 110 using a first subset of the first contacts 165, and the same circuit panel can be coupled to a second type of microelectronic package using a second subset of the first contacts, the second subset having a fewer number of contacts than the first subset.
  • the first type of microelectronic package 110 can be is operable to sample the address and command information carried by the first subset of the first contacts 165 the same number of times per clock cycle (e.g., once per clock cycle) as the second type of microelectronic package 110 can be operable to sample the address and command information carried by the second subset of the first contacts.
  • the first type of microelectronic package 110 can have microelectronic elements of type DDR4, and the second type of microelectronic package can have microelectronic elements of type DDR3.
  • the first subset of the first contacts 165 can include some contacts configured to carry command and address information that is not carried by the second subset of the first contacts, such as, for example, ALERT_N (an I/O signal that can be an output used to signal a parity error), BG (bank group signals), a parity bit input to the chip PAR, sampled just like any other command-address signal, ACT input, and DRAM, which checks the parity based on the information received by the chip, which includes the address information, the PAR bit, and the command info received (i.e., RAS, CAS, ACT (activate an active low signal)) .
  • ALERT_N an I/O signal that can be an output used to signal a parity error
  • BG bank group signals
  • a parity bit input to the chip PAR sampled
  • the second subset of first contacts can include three bank address signals (for use with DDR3 microelectronic elements), while the first subset of the first contacts can include two bank address signals (for use with DDR4 microelectronic elements).
  • the one or more microelectronic elements 130 in the first type microelectronic package can incorporate a different type of memory storage array than the one or more microelectronic elements in the second type microelectronic package.
  • the circuit panel 160 can be coupled to another type of microelectronic package 110 that is operable to sample the address and command information carried by the first contacts 165 four times per clock cycle.
  • all of the microelectronic elements of the first type microelectronic package can be configured to connect with the same set of conductors 170 that is configured to carry a single set of command-address signals.
  • the component 105 may be configured such that when a first type of the microelectronic package 100 having DDR3 or DDR4 memory therein is attached to the component, the microelectronic elements 130 in the microelectronic package can be configured to sample the command and address information coupled thereto through a first number of the contacts 165 at a first sampling rate, such as once per clock cycle (e.g., on the rising edge of the clock cycle) .
  • a first group of first contacts 165 can be connected to a first command-address signal bus of the set of conductors 170, which can be connected to a first half of the microelectronic elements, and a second group of contacts 165 can be connected to a second command- address signal bus of the set of conductors, which can be connected to a second half of the microelectronic elements.
  • the component 105 may be configured such that when a second type of the microelectronic package 110 having LPDDR3 memory therein is attached to the component, the microelectronic elements 30 in the microelectronic package can be configured to sample the command and address information coupled thereto through a second number of the contacts 165 at a second sampling rate, such as twice per clock cycle (e.g., once each on the rising edge and falling edge of the clock cycle) .
  • a second sampling rate such as twice per clock cycle (e.g., once each on the rising edge and falling edge of the clock cycle) .
  • a second type microelectronic package 110 can include a plurality of microelectronic elements 130, a first half of the microelectronic elements being configured to connect with the first contacts 165 in a first group of first contacts but not with a second group of first contacts, and a second half of the microelectronic elements being configured to connect with the first contacts in the second group of first contacts but not with the first group of first contacts.
  • the set of conductors 170 can be configured to carry two identical sets of command-address signals, such that each half of the microelectronic elements 130 can be connected to one of the two sets of command-address signals of the set of conductors.
  • the set of conductors 170 be used to carry signals.
  • the set of conductors 170 when the conductors are electrically connected to a microelectronic package 110, it is not necessary that all of the conductors carry signals to the microelectronic package. Even when the set of conductors 170 is configured to carry two identical sets of command-address signals, it is possible for the microelectronic assembly to not use some or all of the conductors configured to carry the duplicate set of command-address signals, in order to reduce the number of switching signals being carried by the set of conductors 170 to reduce power dissipation.
  • a second type microelectronic package 110 can include a single microelectronic element that is connected with the first contacts 165 in a first group of first contacts but not with a second group of first contacts, such that the single microelectronic element is connected with a first command-address signal bus of the set of conductors 170 but not with a second command-address signal bus of the set of conductors .
  • the component 105 can also include a device 180 coupled to the set of conductors 170, the device operable to drive the command and address information to the contacts 165.
  • the device 180 can be configured to operate in each of first and second modes for connection of the component 105 with the first type microelectronic assembly 110 via the first arrangement of address and command information assignments, and with the second type microelectronic assembly via the second arrangement of address and command information assignments, respectively, without alteration of the physical configuration of the conductors 170.
  • FIG. 2B illustrates a component 105b according to a variation of the invention shown in FIG. 2A.
  • the component 105b includes a circuit panel 160b having at least one row of exposed contacts 164 adjacent an edge 163 of the circuit panel.
  • the exposed contacts 164 can be configured in one or more parallel rows, for example, and the exposed contacts can be configured in any of the ways described below with reference to FIGS. 3A-3C.
  • the component 105b can be coupled to a second circuit panel 190 by inserting the edge 163 into a corresponding socket 193 of the second circuit panel.
  • the component 105b can be coupled to the circuit panel 190 in any of the ways described below with reference to FIGS. 3A-3C.
  • the second circuit panel 190 can include a device 180a coupled to a set of conductors 195 of the second circuit panel, the device operable to drive the command and address information to the contacts 165 of the circuit panel 160b.
  • the component 105b can include a device 180b coupled to the set of conductors.
  • the device 180b can be a buffering element, or a protocol converter that is configured to convert address information having a first protocol that can be used by the component 5 or the circuit panel 190 to a second protocol that can be used by the particular type of microelectronic element 130 in the microelectronic assembly 110.
  • One or both of the devices 180a and 180b can be configured to operate in each of first and second modes for connection of the component 105 with the first type microelectronic assembly 110 via the first arrangement of address and command information assignments, and with the second type microelectronic assembly via the second arrangement of address and command information assignments, respectively.
  • the circuit panel shown in any of the embodiments of described herein can be a first circuit panel such as the circuit panel 160b having a connector interface for electrical connection with a second circuit panel such as the circuit panel 190, the connector interface being configured to carrying information for transfer to and from the contacts 165.
  • a first circuit panel such as the circuit panel 160b having a connector interface for electrical connection with a second circuit panel such as the circuit panel 190, the connector interface being configured to carrying information for transfer to and from the contacts 165.
  • FIG. 7 shows a particular example of such an arrangement. 7, where a plurality of components 606, each of which can include a circuit panel 160b, are shown coupled to a second circuit panel 602 via a respective connector interface.
  • the connector interface can include a socket 605 having a plurality of contacts 607 at one or both sides of the socket, the socket being configured to receive a circuit panel such as the circuit panel 160b having corresponding exposed edge contacts disposed at at least one edge 163 of the circuit panel.
  • the connector interface between the circuit panel 160c and the second circuit panel 190 can be of the types shown in FIGS. 3A and 3B, or, surface mount connections (e.g., BGA, LGA, etc . ) .
  • FIG. 2C illustrates a component 105c including a circuit panel 160c that is configured for coupling to one or more microelectronic packages 110c.
  • the circuit panel 160c shown in FIGS. 2C and 2D is the same circuit panel, and each of the FIGS. 2C and 2D shows a component 105c including the circuit panel 160c coupled to a different respective microelectronic assembly 110c or llOd.
  • the circuit panel 160c can define first and second surfaces 161, 162.
  • the circuit panel 160c can have at least one set of contacts 168 exposed at the first surface 161 for connection with corresponding surface mount terminals 125 and 127 (e.g., of type BGA, LGA, etc.) of a microelectronic package 110c that incorporates one or more microelectronic elements 131 having a memory storage array.
  • the circuit panel 160c can have a plurality of sets of contacts 165 and 167, each set 168 of the contacts 165, 167 being configured for connection to a single microelectronic package 110c.
  • the contacts in each set 168 can include first contacts 165 for carrying address and command information and second contacts 167 for carrying information other than the command and address information (e.g., data input /output information) .
  • each set 168 of the contacts can have a predetermined arrangement that defines relative positions on the first surface 161 (or the second surface 162 if the set of contacts is exposed at the second surface) of contacts carrying address and command information and data.
  • the contacts in each set 168 can be arranged according to the predetermined arrangement.
  • the set 168 of the contacts that can be arranged according to two different predetermined arrangements for connection with two different types of the microelectronic assembly 110, respectively, are also referred to herein as a set of "co-support contacts.”
  • the circuit panel 160c can be usable without requiring alteration thereof in first and second modes, each mode being when a given set 168 of contacts is connected with terminals of a corresponding type of microelectronic package 110c or llOd.
  • a component 105c can be joined with a first type microelectronic package 110c (FIG. 2C) having first terminals 125 joined to first contacts 165 of the circuit panel.
  • the same component 105c a second type microelectronic package llOd (FIG. 2D) having first terminals 125 joined to first contacts 165 of the circuit panel.
  • the circuit panel 160c can be coupled to a first type of microelectronic package 110c that is operable to sample the address and command information carried by the first contacts 165 once per clock cycle.
  • a first type of microelectronic package include the microelectronic package 110c having four microelectronic elements 131a, 131b, 131c, and 131d, as shown in FIG. 2C, or other numbers of microelectronic elements as will be described below.
  • Such a microelectronic package 110c can include microelectronic elements 131 of type DDR3 or DDR4 (generally referred to as DDRx) or of type GDDR3 or GDDR4 (generally referred to as GDDRx) .
  • DDRx type DDR3 or DDR4
  • GDDRx type GDDR3 or GDDR4
  • the circuit panel 160c can be coupled to a second type of microelectronic package llOd that is operable to sample the address and command information carried by the first contacts 165 twice per clock cycle.
  • a second type of microelectronic package include the microelectronic package llOd having four microelectronic elements 132a, 132b, 132c, and 132d, shown in FIG. 2D, or other numbers of microelectronic elements as will be described below.
  • Such a microelectronic package llOd can include microelectronic elements 132 of type LPDDR3 or LPDDR4 (generally referred to as LPDDRx) .
  • the one or more microelectronic elements 110c in the first type microelectronic package can incorporate a different type of memory storage array than the one or more microelectronic elements in the second type microelectronic package (e.g., the microelectronic package llOd shown in FIG. 2D) .
  • the circuit panel 160c can include first contacts 165 in each set of contacts 168 that can include first and second groups of first contacts 165a and 165b. Each group of first contacts 165a and 165b can be assigned for carrying address information usable to specify a location within the memory storage array of the one or more microelectronic elements 131.
  • both of the first and second groups of first contacts 165a and 165b can be used to together specify a location within the memory storage array of the one or more microelectronic elements 110c.
  • a first type microelectronic package can include one or two microelectronic elements 131, each microelectronic element being configured to connect with the first contacts 165 in each of the first and second groups of first contacts 165a, 165b.
  • a first type microelectronic package can include more than two microelectronic elements 131, each microelectronic element being configured to connect with the first contacts 165 in each of the first and second groups of first contacts 165a, 165b.
  • the microelectronic package 110c has four microelectronic elements 131, and each of those microelectronic elements can be connected to both the first and second command-address signal busses FO and Fl of the set of conductors 170.
  • FO and Fl command-address signal busses
  • each microelectronic element 131a, 131b, 131c, and 131d can receive 16 bits of command-address signal information: 8 bits from the signal bus F0, and 8 bits from the signal bus Fl.
  • These connections between the signal busses F0 and Fl and the microelectronic elements 131 are schematically shown in FIG. 2C as conductors GO that are connected with the signal bus F0 and conductors Gl that are connected with the signal bus Fl.
  • the first type microelectronic package 110c can have eight microelectronic elements 131, and each of those microelectronic elements can be connected to both the first and second command- address signal busses F0 and Fl.
  • each microelectronic element 131 can receive 16 bits of command- address signal information: 8 bits from the signal bus F0, and 8 bits from the signal bus Fl.
  • both of the first and second groups of first contacts 165a and 165b can be used separately to each specify a location within the memory storage array of the one or more microelectronic elements 132a, 132b, 132c, and 132d.
  • 165a can be connected to a first command-address signal bus F0 of the set of conductors 170, which can be connected to a first half of the microelectronic elements 132, and the second group of contacts 165b can be connected to a second command-address signal bus Fl of the set of conductors, which can be connected to a second half of the microelectronic elements 132.
  • a second type microelectronic package can include a plurality of microelectronic elements 132, a first half of the microelectronic elements being configured to connect with the first contacts 165 in the first group of first contacts 165a but not with the second group of first contacts 165b, and a second half of the microelectronic elements being configured to connect with the first contacts in the second group of first contacts 165b but not with the first group of first contacts 165a.
  • a second type microelectronic package can include a single microelectronic element 132 that is connected with the first contacts 165 in the first group of first contacts 165a but not with the second group of first contacts 165b, such that the single microelectronic element is connected with the first command-address signal bus FO but not with the second command-address signal bus Fl.
  • the microelectronic package llOd has four microelectronic elements 132a, 132b, 132c, and 132d. Two of those microelectronic elements 132a and 132b can be connected with the first group of first contacts 165a but not with the second group of first contacts 165b, such that the microelectronic elements 132a and 132b are connected with the first command-address signal bus FO of the set of conductors 170 but not the second command-address signal bus Fl.
  • Two of the microelectronic elements 132c and 132d can be connected with the second group of first contacts 165b but not with the first group of first contacts 165a, such that the microelectronic elements 132c and 132d are connected to the second command-address signal bus Fl but not the first command-address signal bus FO.
  • each signal bus FO and Fl is configured to carry two identical sets of command-address signals, such that each of the four microelectronic elements 132 can be connected to one of the two sets of command-address signals of a particular signal bus FO or Fl.
  • two of the microelectronic elements 132a and 132b can receive 32 bits of command-address signal information from the first command-address signal bus FO, and two of the microelectronic elements 132c and 132d can receive 32 bits of command-address signal information from the second command-address signal bus Fl.
  • two of the microelectronic elements 132a and 132b can receive 16 bits of command-address signal information from the first command-address signal bus FO, and two of the microelectronic elements 132c and 132d can receive 16 bits of command-address signal information from the second command-address signal bus Fl.
  • These connections between the signal busses FO and Fl and the microelectronic elements 132 are schematically shown in FIG. 2D as conductors GO that are connected with the signal bus FO and conductors Gl that are connected with the signal bus Fl.
  • the second type microelectronic package llOd can have two microelectronic elements 132.
  • a first one of the microelectronic elements 132 can be connected with the first group of first contacts 165a but not with the second group of first contacts 165b, such that the first microelectronic element is connected with the first command-address signal bus FO but not with the second command-address signal bus Fl.
  • a second one of the microelectronic elements 132 can be connected with the second group of first contacts 165b but not with the first group of first contacts 165a, such that the second microelectronic element is connected with the second command-address signal bus Fl but not with the first command-address signal bus FO.
  • each microelectronic element 132 can receive 32 bits of command-address signal information from either the first command-address signal bus FO or the second command-address signal bus Fl .
  • each of the first contacts of the first group 165a can have a signal assignment that is symmetric about a theoretical axis 174 with the signal assignment of a corresponding first contact of the second group 165b.
  • a first type microelectronic package such as the microelectronic package 110c having signal assignments that are symmetric about a theoretical axis 174 or a second type microelectronic package such as the microelectronic package llOd having signal assignments that are symmetric (e.g., address signal and no- connect symmetry) about a theoretical axis can be mounted to the same circuit panel 160c.
  • circuit panel 160c shown herein have first contacts of the first group 165a that have signal assignments that are symmetric about a theoretical axis 174 (FIG. 2C) with signal assignments of corresponding first contacts of the second group 165b, that need not always be the case.
  • the invention described and claimed herein also contemplates circuit panels 160c that have first contacts of the first group 165a that have signal assignments that are not symmetric about a theoretical axis with signal assignments of corresponding first contacts of the second group 165b.
  • the circuit panel 160c can further include second contacts 167 in each set of contacts 168, and such second contacts in each set of contacts can include first and second groups of second contacts 167a and 167b.
  • the second contacts 167 can be assigned for carrying information other than the address and command information.
  • the circuit panel 160c can have at least one second bus F2, F3 of the set of conductors 171 that is electrically connected with at least some of the second contacts 167.
  • Such a second bus F2, F3 can have a plurality of signal lines configured to carry information other than the address and command information.
  • each of the four microelectronic elements 131 can be electrically connected with different signal lines within the set of conductors 171.
  • the microelectronic element 131a can receive 16 bits of data signal information from a first half of conductors of the signal bus F2
  • the microelectronic element 131b can receive 16 bits of data signal information from a second half of conductors of the signal bus F2
  • the microelectronic element 131c can receive 16 bits of data signal information from a first half of conductors of the signal bus F3
  • the microelectronic element 131d can receive 16 bits of data signal information from a second half of conductors of the signal bus F3.
  • each of the at least one set of contacts 168 can be disposed in first and second areas 167a, 167b adjacent to at least first and second opposite edges 168a, 168b of a periphery of the predetermined of the respective set of contacts, such that all of the first contacts 165 of the respective set of contacts can be disposed between the first and second areas of the respective set of contacts.
  • each of the at least one set of contacts 168 can be disposed in third and fourth areas adjacent to at least third and fourth opposite edges of the periphery of the predetermined of the respective set of contacts, the third and fourth edges extending in a direction between the first and second edges 168a, 168b, such that all of the first contacts 165 of the respective set of contacts are disposed between the third and fourth areas of the respective set of contacts.
  • the circuit panel 160c shown in any of the embodiments of FIGS. 2C and 2D can have a first set of contacts 168 at the first surface 161 and a second set of contacts 168 at the second surface 162, each of the first and second contacts 165, 167 in each set of contacts 168 being arranged according to the same predetermined arrangement.
  • the circuit panel 160c shown in any of the embodiments of FIGS. 2C and 2D can have a first set of contacts 168 at the first surface 161 and a second set of contacts 168 at the first surface spaced apart from the first set in a direction parallel to the first surface, each of the first and second contacts 165, 167 in each set of contacts 168 being arranged according to the same predetermined arrangement.
  • circuit panels 160c having more than one set of contacts 168 can use the same channel of conductors 170 for carrying command and address information to each of the sets of contacts. In other embodiments, circuit panels 160c having more than one set of contacts 168 can use different channels of conductors 170, each channel of conductors being configured for carrying command and address information to a different one of the sets of contacts.
  • FIG. 3A illustrates a component 205a according to a particular example of the invention shown in FIG. 1.
  • the component 205a includes a circuit panel 260, and the contacts 265a are disposed in a socket 266a attached to the first surface 261 of the circuit panel and electrically connected with the set of conductors 270.
  • the microelectronic assembly joined to the circuit panel 260a is a module 210a including a module card 220a and one or more microelectronic elements 230 attached thereto, each microelectronic element having a surface facing a first surface 221 of the module card.
  • the microelectronic element 230 has address inputs 235 electrically connected to terminals 225a of the module card 210a.
  • the module 210a can include a plurality of microelectronic elements 230 that are connected with busses F0, Fl, F2, and F3 of the set of conductors 270 in the same manner as shown and described with respect to FIG. 2C or FIG. 2D, depending on whether the microelectronic elements are of the first type or the second type .
  • the terminals 225a are a plurality of parallel exposed edge terminals adjacent an edge 223 of at least one of the first and second surfaces 221, 222 of the module card 220a for mating with the contacts 265a of more sockets 266a when the module is inserted in the socket.
  • terminals 225a are shown in FIG. 3A exposed at both the first and second surfaces 221, 222 of the module card 220a, terminals 225a may be exposed at only the first surface, only the second surface, or both the first and second surfaces of the module card.
  • the module card 220a may have one row of parallel exposed edge terminals 225a adjacent the edge 223, a first row of parallel exposed edge terminals 226a and a second row of parallel exposed terminals 226b adjacent the first row of terminals, or a first row of parallel exposed edge terminals 227a and a plurality of rows of parallel exposed terminals 227b, 227c (two additional rows 227 are shown in FIG. 3C, but the module card may include more than two additional rows), the second row of terminals 227b being adjacent the first row of terminals 227a, and the third row of terminals 227c being adjacent the second row of terminals 227b.
  • the module card 220a may have notches 228 extending from the edge 223, such notches facilitating registration of the module card with a multi-part socket 266a that is configured to receive the module card.
  • the terminals 225, 226, and 227 shown in FIG. 3C are shown exposed at the first surface 221 of the module card 220a, terminals 225, 226, and 227 may be exposed at only the first surface, only the second surface 222, or both the first and second surfaces of the module card.
  • FIG. 3B illustrates a component 205b according to a variation of the invention shown in FIG. 3A.
  • the component 205b includes a circuit panel 260, and the contacts 265b are disposed in a connector 266b attached to the first surface 261 of the circuit panel and electrically connected with the set of conductors 270.
  • the terminals 225b of the module 210b are a plurality of parallel terminals exposed at one of the first and second surfaces 221, 222 of the module card 220b for mating with the contacts 265b of the connector 266b when the module is attached to the connector.
  • the module 210b can include a plurality of microelectronic elements 230 that are connected with busses F0, Fl, F2, and F3 of the set of conductors 270 in the same manner as shown and described with respect to FIG. 2C or FIG. 2D, depending on whether the microelectronic elements are of the first type or the second type.
  • the module card 220b may have two rows of parallel exposed terminals 225b exposed at a surface of the module card, four parallel rows of exposed terminals (e.g., one additional row of parallel terminals disposed adjacent each row of terminals 225b), or six or more parallel rows of exposed terminals (e.g., two or more additional rows of parallel terminals disposed adjacent each row of terminals 225b) . Also similar to the embodiment of FIG. 3A, the module card 220b may have one or more notches configured to facilitate registration of the module card with a socket 266b that is configured to receive the module card .
  • FIGS. 3A and 3B each show only a single module 210a or 210b electrically connected with the component 205a or 205b, in other embodiments, a plurality of modules can be electrically connected with the component.
  • all of the modules 210a or 210b can be attached to the first surface 261 of the circuit panel 260a or 260b, all of the modules can be attached to the second surface 262 of the circuit panel, or one or more modules can be attached to the first surface of the circuit panel and one or more modules can be attached to the second surface.
  • FIGS. 3A and 3B show a module card 220a or 220b oriented substantially perpendicular (FIG. 3A) or parallel (FIG. 3B) to the first surface 261 of the circuit panel 260a or 260b
  • a module card of a module similar to the module 210a or 210b may be inclined at any other angle relative to the first surface of the circuit panel, such as 15°, 30°, 45°, 60°, or 75°, for example.
  • FIGS. 3A and 3B show module cards 220a, 220b electrically connected to a circuit panel 260a, 260b via a socket 266a, 266b
  • the invention contemplates module cards electrically connected to a circuit panel using a ribbon connector extending between terminals of the module card and contacts of the circuit panel.
  • FIG. 4A illustrates a component 305 according to another particular example of the invention shown in FIG. 1.
  • the component 305 includes a circuit panel 360, and the contacts 365 are upper terminals of a second microelectronic assembly 340 exposed at a first surface 347 of the second microelectronic assembly.
  • the second microelectronic assembly 340 is attached to the first surface 361 of the circuit panel and is electrically connected with the set of conductors 370.
  • Lower terminals 345 of the second microelectronic assembly 340 are electrically connected with corresponding contacts 375 exposed at the first surface 361 of the circuit panel 360.
  • the microelectronic assembly joined to the circuit panel 360 is in the form of a first microelectronic assembly 310.
  • the microelectronic assembly 310 is a microelectronic package having one or more microelectronic elements 330 therein having a surface facing a first surface 321 of a package substrate 320.
  • the first microelectronic assembly 310 can include a plurality of microelectronic elements 330 that are connected with busses F0, Fl, F2, and F3 of the set of conductors 370 in the same manner as shown and described with respect to FIG. 2C or FIG. 2D, depending on whether the microelectronic elements are of the first type or the second type.
  • microelectronic assembly [0181] In a particular example, the microelectronic assembly
  • microelectronic element 330 can include a plurality of stacked microelectronic elements 330 electrically interconnected by conductive structure such as through-silicon vias ("TSVs")-
  • TSVs through-silicon vias
  • the microelectronic element 330 has address inputs 335 electrically connected to terminals 325 exposed at a second surface 322 of the substrate 320 opposite the first surface 321.
  • the second microelectronic assembly 340 includes a microelectronic element 341 having active devices therein, and the upper terminals 365 of the second microelectronic assembly are electrically connected with the set of conductors 370 of the circuit panel extending through the second microelectronic assembly .
  • the microelectronic elements 330 of the first microelectronic assembly (or microelectronic package) 310 can have memory storage array function
  • the microelectronic element 341 of the second microelectronic assembly (or microelectronic package) 340 can have microprocessor function.
  • the microelectronic element 330 of the first microelectronic assembly 310 can be directly electrically connected to the microelectronic element 341 of the second microelectronic assembly 340 by electrical connections that extend only within the first and second microelectronic assemblies, not within the circuit panel 360.
  • a first microelectronic element of a first microelectronic assembly and a second microelectronic element of a second microelectronic assembly are "directly" connected to one another when the electrical connections extending between the first and second microelectronic elements extend only within the first and second microelectronic assemblies, not within a structure external to the first and second microelectronic assemblies (e.g., a circuit panel).
  • the electrical connections between the microelectronic element 330 of the first microelectronic assembly 310 and the microelectronic element 341 of the second microelectronic assembly 340 can include interconnection elements extending in a direction normal to the first surface 347 of the second microelectronic assembly at which the upper terminals (the contacts 365) of the second microelectronic assembly are exposed, the interconnection elements being configured for package-on-package stacking.
  • the electrical connections between the microelectronic element 330 of the first microelectronic assembly 310 and the microelectronic element 341 of the second microelectronic assembly 340 can include a bond via array extending from the terminals 365 of the second microelectronic assembly to contacts exposed at a surface 343 of a substrate of the second microelectronic assembly.
  • FIG. 4B illustrates a component 305b that is a variation of the component 305 of FIG. 4A, according to another particular example of the invention shown in FIG. 1.
  • the component 305b includes the same second microelectronic assembly 340 shown in FIG. 4A, but it does not include the circuit panel 360.
  • a set of conductors 370 is supported by and/or located within the substrate 342 of the second microelectronic assembly 340.
  • the set of conductors 370 is electrically connected with the contacts 365 at the first surface 347 of the second microelectronic assembly 340.
  • the component 305b can be electrically connected with a circuit panel such as the circuit panel 360 through terminals 345 exposed at a lower surface 344 of the second microelectronic assembly 340.
  • FIG. 4C illustrates a component 305c that is a variation of the component 305b of FIG. 4B, according to another particular example of the invention shown in FIG. 1.
  • the component 305c includes a second microelectronic assembly 340c that is similar to the second microelectronic assembly 340 shown in FIG. 4B, but it does not include the substrate 342.
  • a set of conductors 370c is supported by and/or located within a molded region 348 of the second microelectronic assembly 340c.
  • the set of conductors 370c is electrically connected with the contacts 365 at the first surface 347 of the second microelectronic assembly 340.
  • the set of conductors 370c can electrically connect element contacts 349 of the microelectronic element 341 with the terminals 345 exposed at a lower surface 344 of the second microelectronic assembly 340c.
  • FIG. 5A illustrates a component 405 according to yet another particular example of the invention shown in FIG. 1.
  • the component 405 includes a circuit panel 460, and the contacts 465 are upper terminals of a second microelectronic assembly 440 exposed at a first surface 447 of the second microelectronic assembly, or exposed at a dielectric layer (not shown) at a first surface of the second microelectronic assembly.
  • the second microelectronic assembly 440 is attached to the first surface 461 of the circuit panel and is electrically connected with the set of conductors 470.
  • Lower terminals 445 exposed at a second surface 444 of the second microelectronic assembly 440 are electrically connected with corresponding contacts 475 exposed at the first surface 461 of the circuit panel 460.
  • the microelectronic assembly joined to the circuit panel 460 is in the form of a first microelectronic assembly 410.
  • the microelectronic assembly 410 is a microelectronic package having one or more microelectronic elements 430 therein having a surface facing a first surface 421 of a package substrate 420.
  • the microelectronic element 430 has address inputs 435 electrically connected to terminals 425 exposed at a second surface 422 of the substrate 420 opposite the first surface 421.
  • the first microelectronic assembly 410 can include a plurality of microelectronic elements 430 that are connected with busses FO, Fl, F2, and F3 of the set of conductors 470 in the same manner as shown and described with respect to FIG. 2C or FIG. 2D, depending on whether the microelectronic elements are of the first type or the second type .
  • the first microelectronic assembly 410 can include a first microelectronic element 430 and additional microelectronic elements each having active devices therein.
  • the terminals 425 of the first microelectronic assembly 410 can be electrically connected with the additional microelectronic elements by through-silicon vias extending through the first microelectronic element 430.
  • the second microelectronic assembly 440 can include one or more microelectronic elements each having active devices therein, and the upper terminals 465 of the second microelectronic assembly can be electrically connected with the set of conductors 470 of the circuit panel by electrical connections extending at least partially within the second microelectronic package.
  • the contacts (or upper terminals) 465 can be exposed at a dielectric layer overlying the first surface 447 of the second microelectronic assembly 440.
  • one or more of the microelectronic elements of the second microelectronic assembly 440 can have a logic function.
  • these electrical connections between the upper terminals 465 of the second microelectronic assembly 440 and the set of conductors 470 can include through- silicon vias 446 extending through the one or more microelectronic elements. These electrical connections can also include by joining units extending between the lower terminals 445 and corresponding contacts 475 exposed at the first surface 461 of the circuit panel 460.
  • the second microelectronic assembly has
  • the 440 can include a first microelectronic element and at least one second microelectronic element, each microelectronic element having active devices therein, the first and second microelectronic elements arranged in a stacked configuration.
  • the upper terminals 465 of the second microelectronic assembly 440 can be electrically connected with the set of conductors 470 of the circuit panel 460 by through-silicon vias 446 extending through the at least one second microelectronic element of the second microelectronic assembly.
  • each of the upper terminals 465 are shown as being aligned with (in a horizontal direction) and connected to the through-silicon vias 446, it is not required that the upper terminals be aligned with the through-silicon vias, nor is it required that all of the upper terminals be connected with these through-silicon vias.
  • first and second microelectronic assemblies 410 and 440 are shown as packaged structures, that need not be the case.
  • the first microelectronic assembly 410 can be a microelectronic element having a memory storage array function
  • the second microelectronic assembly 440 can be a microelectronic element having logic function.
  • the first microelectronic assembly 410 is shown as having a flip-chip connection between the terminals 425 and the contacts 465, that need not be the case.
  • the first microelectronic assembly 410 can be a microelectronic element having a memory storage array function that is oriented with a contact-bearing surface thereof facing away from the upper surface 447 of the second microelectronic assembly 440, and terminals 425 (which can be element contacts) of the first microelectronic assembly 410 can be wire-bonded to the contacts 465 at the upper surface of the second microelectronic assembly.
  • contacts 465 at the upper surface 447 of the second microelectronic assembly 440 can offer co-support of microelectronic assemblies 410 having DDR3 or DDR4 memory elements therein.
  • FIG. 5B illustrates a component 405b that is a variation of the component 405 of FIG. 5A, according to another particular example of the invention shown in FIG. 1.
  • the component 405b includes the same second microelectronic assembly 440 shown in FIG. 5A, but it does not include the circuit panel 460.
  • a set of conductors 470b can be supported by and/or located within the microelectronic elements of the second microelectronic assembly 440.
  • the set of conductors 470b can include TSVs and/or redistribution traces connected to TSVs, for example.
  • the set of conductors 470 can be electrically connected with the contacts 465 at the first surface 447 of the second microelectronic assembly 340.
  • the component 405b can be electrically connected with a circuit panel such as the circuit panel 460 through terminals 445 exposed at a lower surface 444 of the second microelectronic assembly 440. In the embodiment of FIG.
  • one or more of the microelectronic elements in the microelectronic assembly 440 can be a support structure for the set of conductors 470b, or a dielectric layer overlying one of the microelectronic elements in the microelectronic assembly can be a support structure for the set of conductors.
  • Each of the examples illustrated and discussed above can be implemented with microelectronic elements therein having contacts on faces thereof which either face in the same direction which the first surface of the microelectronic assembly faces, or can face away from the direction in which the first surface of the microelectronic assembly faces.
  • the microelectronic assemblies may be as shown and described in the examples of any of FIGS. 13-20 of commonly owned United States Application 13/439,317, the disclosure of which is incorporated by reference herein.
  • the substrate may be omitted in an appropriate case, as when the microelectronic elements are arranged together within a molded unit, e.g., a wafer-level unit, in which a dielectric layer may be formed on or above contact-bearing faces of the microelectronic elements for supporting traces and electrical interconnections thereon.
  • a molded unit e.g., a wafer-level unit
  • a dielectric layer may be formed on or above contact-bearing faces of the microelectronic elements for supporting traces and electrical interconnections thereon.
  • microelectronic assemblies having multiple stacked microelectronic elements therein may be single or multiple stack implementations as shown and/or described with reference to FIGS. 21-25 of commonly owned United States Application 13/439,317, the disclosure of which is incorporated by reference herein.
  • microelectronic assemblies having four microelectronic elements therein may be as shown and described in FIGS. 9A-B, 9C, 9D, 9F, 9G, 9H, 12B, 12C or 12D of commonly owned United States Applications 13/337,565 and 13/337, 575, or may be as shown and described in FIGS. 7A-B, 8, 11A, 11B, llC, 11D, 12, 13B, 14B, or 14C of commonly owned United States Application 13/354,747, the disclosures of which are incorporated by reference herein.
  • microelectronic packages and microelectronic assemblies described above with reference to FIGS. 1-5 above can be utilized in construction of diverse electronic systems, such as the system 500 shown in FIG. 6.
  • the system 500 in accordance with a further embodiment of the invention includes a plurality of modules or components 506 such as the microelectronic packages and/or microelectronic assemblies as described above in conjunction with other electronic components 508, 510 and 511.
  • the system can include a circuit panel, motherboard, or riser panel 502 such as a flexible printed circuit board, and the circuit panel can include numerous conductors 504, of which only one is depicted in FIG. 6, interconnecting the modules or components 506, 508, 510 with one another.
  • a circuit panel 502 can transport signals to and from each of the microelectronic packages and/or microelectronic assemblies included in the system 500.
  • this is merely exemplary; any suitable structure for making electrical connections between the modules or components 506 can be used.
  • the system 500 can also include a processor such as the semiconductor chip 508, such that each module or component 506 can be configured to transfer a number N of data bits in parallel in a clock cycle, and the processor can be configured to transfer a number M of data bits in parallel in a clock cycle, M being greater than or equal to N.
  • the component 508 is a semiconductor chip and component 510 is a display screen, but any other components can be used in the system 500.
  • the system 500 can include any number of such components.
  • Modules or components 506 and components 508 and 511 can be mounted in a common housing 501, schematically depicted in broken lines, and can be electrically interconnected with one another as necessary to form the desired circuit.
  • the housing 501 is depicted as a portable housing of the type usable, for example, in a cellular telephone or personal digital assistant, and screen 510 can be exposed at the surface of the housing.
  • a structure 506 includes a light-sensitive element such as an imaging chip
  • a lens 511 or other optical device also can be provided for routing light to the structure.
  • the simplified system shown in FIG. 6 is merely exemplary; other systems, including systems commonly regarded as fixed structures, such as desktop computers, routers and the like can be made using the structures discussed above.
  • microelectronic packages and microelectronic assemblies described above with reference to FIGS. 1-5 can also be utilized in construction of an electronic system such as the system 600 shown in FIG. 7.
  • the system 600 in accordance with a further embodiment of the invention is the same as the system 500 shown in FIG. 6, except the component 506 has been replaced by a plurality of components 606.
  • Each of the components 606 can be or can include one or more of the microelectronic packages or microelectronic assemblies described above with reference to FIGS. 1-5.
  • one or more of the components 606 can be a variation of the component 5 shown in FIG. 1, in which the support structure 60 includes exposed edge contacts, and the support structure of each component 5 can be suitable for insertion into a socket 605.
  • Each socket 605 can include a plurality of contacts 607 at one or both sides of the socket, such that each socket
  • the system can include a second circuit panel 602 or motherboard such as a flexible printed circuit board, and the second circuit panel can include numerous conductors 604, of which only one is depicted in FIG. 7, interconnecting the components 606 with one another.
  • a module such as the system
  • each component 600 can include a plurality of components 606, each component
  • Each component 606 can be mounted to, and electrically connected with the second circuit panel 602 for transport of signals to and from each component 606.
  • the specific example of the system 600 is merely exemplary; any suitable structure for making electrical connections between the components 606 can be used.
  • a microelectronic package family including
  • each microelectronic package each having terminals for connection with corresponding contacts of an external component and each including a microelectronic element having a memory storage array having a given number of storage locations, the terminals of each microelectronic package being configured to receive corresponding command and address information specifying one of the storage locations, each microelectronic element having inputs connected with the terminals of the respective microelectronic package,
  • microelectronic element of a first microelectronic package of the family is configured to sample first command and address information coupled thereto through the terminals of the first package at a first sampling rate
  • microelectronic element of a second microelectronic package of the family is configured to sample second command and address information coupled thereto through the terminals of the second package at a second sampling rate being greater than the first sampling rate
  • the terminals of the first package being configured to connect to a set of contacts of the external component arranged according to a first predetermined arrangement for receipt of the first command and address information
  • the terminals of the second package being configured to connect to a set of contacts of the external component arranged according to a second predetermined arrangement for receipt of the second command and address information
  • the set of contacts arranged according to the second predetermined arrangement include at least some contacts occupying identical positions with the set of contacts arranged according to the first predetermined arrangement, the set of contacts arranged according to the second predetermined arrangement being fewer in number than the set of contacts arranged according to the first predetermined arrangement.
  • the microelectronic package 10 shown in FIG. 1 can in any of the foregoing embodiments be any of the types of packages described in the foregoing embodiments.
  • the first type of microelectronic package 110c (FIG. 2C) , for example, can include a microelectronic element 131 configured to sample first command and address information coupled thereto through the terminals 125 of such package at a first sampling rate.
  • the second type of microelectronic package llOd for example, can include microelectronic element 132 configured to sample second command and address information coupled thereto through the terminals 125 through the second package at a second sampling rate greater than the first sampling rate.
  • the terminals 125 of the first package 110c can be configured to connect to a set of contacts 165 of the external component 105c arranged according to a first predetermined arrangement for receipt of the first command and address information.
  • the terminals 125 of the second package llOd can be configured to connect to a set of contacts 165 of the external component 105d arranged according to a second predetermined arrangement for receipt of the second command and address information.
  • the set 168 of contacts 165 arranged according to the second predetermined arrangement can include at least some contacts occupying identical positions with the set of contacts arranged according to the first predetermined arrangement.
  • the set 168 of contacts 165 arranged according to the second predetermined arrangement can be fewer in number than the set of contacts arranged according to the first predetermined arrangement.
  • a module for connection with at least one microelectronic assembly each microelectronic assembly including a set of terminals and a microelectronic element having a memory storage array having a given number of storage locations, the microelectronic element of each microelectronic assembly having inputs connected with the terminals for receiving command and address information specifying one of the storage locations, the module comprising:
  • circuit panel having first and second opposed surfaces and bearing a set of conductors configured to carry the command and address information
  • each set of co-support contacts coupled to the set of conductors, each set of co-support contacts exposed at the first surface or the second surface, each set of co-support contacts being configured for connection to the set of terminals of a single microelectronic assembly of the at least one microelectronic assembly;
  • module contacts coupled to the set of conductors, the module contacts being configured for carrying information for transfer to and from the at least one set of co- support contacts, the module contacts configured for connection with a component external to the module,
  • each of the at least one set of co-support contacts includes first contacts that have address and command information assignments arranged according to
  • a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts including a second number of the first contacts at a second sampling rate being greater than the first sampling rate, the subset including some first contacts occupying identical positions with the first contacts which are assigned to the first predetermined arrangement, the second number being fewer than the first number.
  • microelectronic assembly is a microelectronic package
  • terminals are surface mount terminals and are exposed at a surface of the microelectronic package.
  • circuit panel is a module card
  • module contacts are a plurality of parallel exposed contacts at at least one of the first and second surfaces for mating with contacts of a socket of a second circuit panel when the module is inserted in the socket.
  • circuit panel is a module card
  • module contacts are a plurality of contacts at one of the first and second surfaces for mating with the contacts of a connector of a second circuit panel when the module is attached to the connector.
  • module contacts are surface mount contacts exposed at one of the first and second surfaces for facing and electrically connecting with contacts of a second circuit panel when the module is joined with the second circuit panel.
  • each of the at least one set of co-support contacts includes second contacts configured to carry information other than the command and address information.
  • each of the at least one set of co-support contacts is exposed in a corresponding region of the first surface of the circuit panel, wherein at least some of the second contacts each of the at least one set of co-support contacts are disposed in first and second areas adjacent to at least first and second opposite edges of a periphery of the region of the respective set of co- support contacts, and wherein all of the first contacts of the respective set of co-support contacts are disposed between the first and second areas of the respective set of co-support contacts .
  • each of the at least one set of co-support contacts are disposed in third and fourth areas adjacent to at least third and fourth opposite edges of the periphery of the region of the respective set of co-support contacts, each of the third and fourth edges extending in a direction between the first and second edges, and wherein all of the first contacts of the respective set of co-support contacts are disposed between the third and fourth areas of the respective set of co-support contacts.
  • microelectronic element in the first type of the microelectronic assembly is of type DDRx
  • microelectronic element in the second type of the microelectronic assembly is of type LPDDRx
  • microelectronic element in the first type of the microelectronic assembly is of type GDDRx .
  • the at least one set of co-support contacts includes a first set at the first surface and second set at the first surface spaced apart from the first set in a direction parallel to the first surface.
  • each of the first contacts in each set of co-support contacts include first and second groups of the first contacts, each group of first contacts assigned for carrying address information usable to specify a location within the memory storage array.
  • each of the first contacts of the first group has a signal assignment that is symmetric about a theoretical axis with the signal assignment of a corresponding first contact of the second group.
  • the second type of the microelectronic assembly includes a plurality of microelectronic elements comprising a first half of the microelectronic elements and a second half of the microelectronic elements, and wherein when each set of co- support contacts has assignments arranged according to the second predetermined arrangement, each of the first half of the microelectronic elements of the second type of the microelectronic assembly is configured to connect with the first group of first contacts but not with the second group of first contacts, and each of the second half of the microelectronic elements of the second type of the microelectronic assembly is configured to connect with the second group of first contacts but not with the first group of first contacts.
  • a module for connection with at least one microelectronic assembly each microelectronic assembly including a set of terminals and a microelectronic element having a memory storage array having a given number of storage locations, the microelectronic element of each microelectronic assembly having inputs connected with the terminals for receiving command and address information specifying one of the storage locations, the module comprising:
  • circuit panel having first and second opposed surfaces and bearing a set of conductors configured to carry the command and address information
  • each set of co-support contacts coupled to the set of conductors, each set of co-support contacts exposed at the first surface or the second surface, each set of co-support contacts being configured for connection to the set of terminals of a single microelectronic assembly of the at least one microelectronic assembly;
  • module contacts coupled to the set of conductors, the module contacts being configured for carrying information for transfer to and from the at least one set of co- support contacts, the module contacts configured for connection with a component external to the module,
  • each of the at least one set of co-support contacts includes first contacts that have address and command information assignments arranged according to
  • the present invention enjoys wide industrial applicability including, but not limited to, components for connection with one or more microelectronic assemblies and methods of fabricating components for connection with one or more microelectronic assemblies.

Landscapes

  • Semiconductor Memories (AREA)
PCT/US2013/056773 2012-08-27 2013-08-27 Co-support system and microelectronic assembly WO2014035950A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015529922A JP6185995B2 (ja) 2012-08-27 2013-08-27 共通サポートシステム及び超小型電子アセンブリ

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US201213595486A 2012-08-27 2012-08-27
US13/595,486 2012-08-27
US13/839,402 2013-03-15
US13/840,353 2013-03-15
US13/840,542 US8848392B2 (en) 2012-08-27 2013-03-15 Co-support module and microelectronic assembly
US13/840,542 2013-03-15
US13/840,353 US8848391B2 (en) 2012-08-27 2013-03-15 Co-support component and microelectronic assembly
US13/839,402 US8787034B2 (en) 2012-08-27 2013-03-15 Co-support system and microelectronic assembly

Publications (1)

Publication Number Publication Date
WO2014035950A1 true WO2014035950A1 (en) 2014-03-06

Family

ID=49223843

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2013/056773 WO2014035950A1 (en) 2012-08-27 2013-08-27 Co-support system and microelectronic assembly

Country Status (3)

Country Link
JP (1) JP6185995B2 (ja)
TW (2) TWI541651B (ja)
WO (1) WO2014035950A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI711149B (zh) * 2018-08-15 2020-11-21 台灣積體電路製造股份有限公司 半導體封裝及其製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109983782B (zh) * 2016-09-30 2021-06-01 雅马哈株式会社 会话辅助装置及会话辅助方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4747081A (en) * 1983-12-30 1988-05-24 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US5163024A (en) * 1983-12-30 1992-11-10 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US5210639A (en) * 1983-12-30 1993-05-11 Texas Instruments, Inc. Dual-port memory with inhibited random access during transfer cycles with serial access
US20070260841A1 (en) * 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09298217A (ja) * 1996-05-07 1997-11-18 Hitachi Ltd 半導体装置の製造方法、半導体装置および電子装置
JP2000223657A (ja) * 1999-02-03 2000-08-11 Rohm Co Ltd 半導体装置およびそれに用いる半導体チップ
JP3935321B2 (ja) * 2001-02-16 2007-06-20 松下電器産業株式会社 マルチチップモジュール
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP4610235B2 (ja) * 2004-06-07 2011-01-12 ルネサスエレクトロニクス株式会社 階層型モジュール
TWM398313U (en) * 2009-03-27 2011-02-11 Molex Inc Microelectronic component support with reinforced structure
TWI533412B (zh) * 2010-08-13 2016-05-11 金龍國際公司 半導體元件封裝結構及其形成方法
WO2012019909A1 (de) * 2010-08-13 2012-02-16 Tesa Se Verfahren zur kapselung einer elektronischen anordnung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4747081A (en) * 1983-12-30 1988-05-24 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US5163024A (en) * 1983-12-30 1992-11-10 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US5210639A (en) * 1983-12-30 1993-05-11 Texas Instruments, Inc. Dual-port memory with inhibited random access during transfer cycles with serial access
US20070260841A1 (en) * 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI711149B (zh) * 2018-08-15 2020-11-21 台灣積體電路製造股份有限公司 半導體封裝及其製造方法

Also Published As

Publication number Publication date
TW201415232A (zh) 2014-04-16
JP6185995B2 (ja) 2017-08-23
JP2015529980A (ja) 2015-10-08
TWI488042B (zh) 2015-06-11
TWI541651B (zh) 2016-07-11
TW201530316A (zh) 2015-08-01

Similar Documents

Publication Publication Date Title
US8848392B2 (en) Co-support module and microelectronic assembly
US8787034B2 (en) Co-support system and microelectronic assembly
US8848391B2 (en) Co-support component and microelectronic assembly
US10643977B2 (en) Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows
US9530458B2 (en) Stub minimization using duplicate sets of signal terminals
EP2888762B1 (en) Co-support circuit panel and microelectronic packages
US20160276316A1 (en) Stub minimization for wirebond assemblies without windows
US10026467B2 (en) High-bandwidth memory application with controlled impedance loading
US9928883B2 (en) TFD I/O partition for high-speed, high-density applications
US9640282B1 (en) Flexible I/O partition of multi-die memory solution
WO2014035950A1 (en) Co-support system and microelectronic assembly
US20170186474A1 (en) Dual-channel dimm

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13765537

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2015529922

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13765537

Country of ref document: EP

Kind code of ref document: A1