WO2014030383A1 - Mémoire associative - Google Patents

Mémoire associative Download PDF

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Publication number
WO2014030383A1
WO2014030383A1 PCT/JP2013/060326 JP2013060326W WO2014030383A1 WO 2014030383 A1 WO2014030383 A1 WO 2014030383A1 JP 2013060326 W JP2013060326 W JP 2013060326W WO 2014030383 A1 WO2014030383 A1 WO 2014030383A1
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Prior art keywords
signal
counter
distance
detection circuit
clock
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PCT/JP2013/060326
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English (en)
Japanese (ja)
Inventor
ハンスユルゲン マタウシュ
小出　哲士
静龍 佐々木
智信 赤澤
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国立大学法人広島大学
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Publication of WO2014030383A1 publication Critical patent/WO2014030383A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Definitions

  • the present invention relates to an associative memory.
  • the former is called CAM (Contents Addressable Memory), and is used to realize the routing of the IP address table of the network router and the cache of the processor.
  • CAM Content Addressable Memory
  • a memory having a function for realizing such a flexible comparison is particularly referred to as an associative memory.
  • Non-patent Document 1 As means for realizing an associative memory, (1) an implementation method using a digital method (Non-patent Document 1), (2) an implementation method using an analog method, and (3) a digital / analog fusion method (Non-Patent Document 2) have been proposed.
  • Non-Patent Document 2 “A High-Speed and Low-Voltage Associative Co-Processor with Hamming Distance Ordering Using Word-Parallel and Hierarchical Search Architecture,” CICC, 2004.
  • Y. Oike et al. “A Word-Parallel Digital Associative Engine with Wide Search RangeBased on ManhattanDistance,” CICC, 2004.
  • Non-Patent Document 1 performs a similar search using the Hamming distance between the search data and the reference data, there is a problem that it is difficult to perform a similar search using the Manhattan distance. Further, in the associative memory described in Non-Patent Document 2, since the distance representing the similarity between the search data and the reference data is converted into a voltage, there is a problem that an erroneous search occurs.
  • an object of the present invention is to provide an associative memory capable of performing a similar search accurately and at high speed even when the Manhattan distance is used. It is to be.
  • the content addressable memory includes a reference data storage circuit, R distance calculation circuits, R distance / clock number conversion circuits, and a Winner detector.
  • the reference data storage circuit stores R reference data each having a bit length of M ⁇ W bits.
  • the R distance calculation circuits are provided corresponding to the R reference data, each of which has a bit length of M ⁇ W bits, and represents the distance between the search data to be searched and the reference data. Number of distance signals are output.
  • the R distance / clock number conversion circuits are provided corresponding to the R distance calculation circuits, each receiving W distance signals each having an M-bit bit length from the corresponding distance calculation circuit, The number of clocks of the clock signal when a counter value that matches the sum of the received W distance signals is obtained is counted, and a timing signal indicating the coincidence timing that is the timing at which the number of clocks is counted is output.
  • the Winner detector detects k timing signals in order of the matching timing based on the R timing signals received from the R distance / clock number conversion circuits, and searches for the detected k timing signals. A match signal indicating the similarity between the data and the reference data is output.
  • each of the R distance / clock number conversion circuits has a counter value that matches the sum of the W distance signals received from the corresponding distance calculation circuit. The number of clocks of the clock signal is counted, and a timing signal indicating the coincidence timing that is the timing of counting the number of clocks is output. That is, each of the R distance / clock number conversion circuits converts the sum of the W distance signals into the clock number of the clock signal, and outputs a timing signal indicating the timing at which the converted clock number is obtained.
  • the timing signal indicates an earlier coincidence timing, and if the distance represented by the sum of the W distance signals is large, the timing signal is slower. Indicates the match timing.
  • the number of clocks of the clock signal when a counter value matching the sum of the W distance signals is obtained is W of the clock signal when the W counter values matching each of the W distance signals are obtained. Since the number of clocks is added, the clock signal when the counter value matching the distance signal between the search data and the reference data when the distance between the search data and the reference data is expressed by the Manhattan distance is obtained. It becomes the number of clocks.
  • the two timings indicated by the two timing signals have a time difference of at least one period of the clock signal. Further, the search time is shortened by increasing the frequency of the clock signal.
  • the similarity search can be performed accurately and at high speed.
  • FIG. 2 is a schematic diagram illustrating a configuration of a distance / clock number conversion circuit illustrated in FIG. 1.
  • FIG. 3 is a schematic diagram illustrating a configuration of a counter coincidence detection circuit illustrated in FIG. 2.
  • FIG. 4 is a diagram for explaining the operation of the counter coincidence detection circuit shown in FIG. 3.
  • FIG. 2 is a diagram for explaining the operation of a distance / clock number conversion circuit shown in FIG. 1. It is a figure for demonstrating operation
  • FIG. 3 is a schematic diagram showing another configuration of the distance / clock number conversion circuit shown in FIG. 1.
  • FIG. 5 is a schematic diagram showing still another configuration of the distance / clock number conversion circuit shown in FIG. 1.
  • FIG. 10 is a schematic diagram showing a specific configuration of the distance / clock number conversion circuit shown in FIG. 9. It is a figure for demonstrating operation
  • FIG. 10 is a schematic diagram showing another specific configuration of the distance / clock number conversion circuit shown in FIG. 9. It is a figure for demonstrating operation
  • FIG. 11 is a schematic diagram illustrating a specific configuration of the distance / clock number conversion circuit illustrated in FIG. 10.
  • FIG. 16 is a diagram for explaining the operation of the distance / clock number conversion circuit shown in FIG. 15;
  • FIG. 11 is a schematic diagram showing still another specific configuration of the distance / clock number conversion circuit shown in FIG. 10.
  • FIG. 18 is a diagram for explaining the operation of the distance / clock number conversion circuit shown in FIG. 17. It is a figure which shows the comparison of the shortest search time. It is a figure which shows the comparison of power consumption.
  • FIG. 1 is a schematic block diagram showing a configuration of an associative memory according to an embodiment of the present invention.
  • an associative memory 100 according to the first embodiment of the present invention includes a memory array unit 10 and a Winner detector 20.
  • the memory array unit 10 includes a memory unit 1, a row decoder 2, a column decoder 3, a read / write circuit 4, and a search data storage circuit 5.
  • the memory unit 1 includes a reference data storage circuit (Storage Cell: SC) SC 11 to SC 1W , SC 21 to SC 2W ,..., SC R1 to SC RW, and a distance calculation circuit (Distance Processor: DP) DP 11 to DP 1W , DP 21 to DP 2W ,..., DP R1 to DP RW , and distance / clock number conversion circuits DC 1 to DC R are included.
  • Each of W and R is an integer of 2 or more.
  • the distance calculation circuits DP 11 to DP 1W are provided corresponding to the reference data storage circuits SC 11 to SC 1W , respectively.
  • the distance calculation circuits DP 21 to DP 2W are provided corresponding to the reference data storage circuits SC 21 to SC 2W , respectively.
  • the distance calculation circuits DP R1 to DP RW are provided corresponding to the reference data storage circuits SC R1 to SC RW , respectively.
  • the distance / clock number conversion circuit DC 1 is provided corresponding to the distance calculation circuits DP 11 to DP 1W .
  • the distance / clock number conversion circuit DC 2 is provided corresponding to the distance calculation circuits DP 21 to DP 2W .
  • the distance / clock number conversion circuit DC R is provided corresponding to the distance calculation circuits DP R1 to DP RW .
  • Reference data storage circuits SC 11 to SC 1W , SC 21 to SC 2W ,..., SC R1 to SC RW store reference data written by the row decoder 2, the column decoder 3, and the read / write circuit 4. .
  • the reference data storage circuits SC 11 to SC 1W store M ⁇ W (M is an integer of 1 or more) bits of reference data 1, and the reference data storage circuits SC 21 to SC 2W have M ⁇ W bits.
  • the reference data 2 is stored, and the reference data storage circuits SC R1 to SC RW store the M ⁇ W bit reference data R in the same manner. That is, each of the reference data storage circuits SC 11 to SC 1W , SC 21 to SC 2W ,..., SC R1 to SC RW stores M bits of reference data.
  • the distance calculation circuits DP 11 to DP 1W include M ⁇ W bit reference data 1 stored in the reference data storage circuits SC 11 to SC 1W , M ⁇ W bit search data stored in the search data storage circuit 5, and Is calculated by a method described later.
  • the distance calculation circuits DP 21 to DP 2W search for the M ⁇ W bit reference data 2 stored in the reference data storage circuits SC 21 to SC 2W and the M ⁇ W bit search stored in the search data storage circuit 5.
  • the distance from the data is calculated by the method described later.
  • the distance calculation circuits DP R1 to DP RW perform the M ⁇ W bit reference data R stored in the reference data storage circuits SC R1 to SC RW and the M ⁇ W stored in the search data storage circuit 5.
  • the distance from the W-bit search data is calculated by a method described later.
  • the distance calculation circuits DP 11 to DP 1W , the distance calculation circuits DP 21 to DP 2W ,..., And the distance calculation circuits DP R1 to DP RW calculate the distance between the reference data and the search data in parallel. .
  • the distance calculation circuits DP 11 to DP 1W output the distance between the reference data 1 and the search data to the distance / clock number conversion circuit DC 1 as a distance signal of M ⁇ W bits
  • the distance calculation circuits DP 21 to DP 2W is the distance between the reference data 2 and the search data is output as the distance signal of the M ⁇ W bits to distance / clock number conversion circuit DC 2
  • the distance calculation circuit DP R1 ⁇ DP RW are reference data the distance between R and the search data is output to the distance / clock number conversion circuit DC R as a distance signal M ⁇ W bits.
  • Each of the distance calculation circuits DP 11 to DP 1W calculates the distance between the reference data 1 and the search data using the following equation.
  • In j is the search data
  • Re rj is the reference data. is there.
  • Each of the data In j and Re rj consists of M bits.
  • the distance calculation circuits DP 11 to DP 1W calculate the distance between the M ⁇ W bit reference data 1 and the M ⁇ W bit search data in M bits, and each has a bit length of M bits.
  • the W distance signals D 1j are output to the distance / clock number conversion circuit DC 1 .
  • the distance calculation circuits DP 21 to DP 2W ,... And the distance calculation circuits DP R1 to DP RW also calculate the distances between the reference data 2 to R and the search data using the equation (1). Further, the distance calculation circuits DP 21 to DP 2W ,... And the distance calculation circuits DP R1 to DP RW also receive W distance signals D 2j to D Rj each having a bit length of M bits, respectively. Output to the conversion circuits DC 2 to DC R.
  • the distance / clock number conversion circuit DC 1 receives W distance signals D 1j from the distance calculation circuits DP 11 to DP 1W, and the number of clock signals CLK that matches the sum of the received W distance signals D 1j. counted by a method described later CN_total1, and outputs a timing signal C 1 indicating a timing of counting the number of clocks CN_total1 to Winner detector 20.
  • the timing at which the clock number CN_total1 is counted is the coincidence timing that matches the distance between the search data and the reference data 1.
  • the distance / clock number conversion circuit DC 2 receives W distance signals D 2j from the distance calculation circuits DP 21 to DP 2W , and receives the clock signal CLK that matches the sum of the received W distance signals D 2j . It was counted by the method described below a clock number CN_total2, and outputs a timing signal C 2 which shows the timing of counting the number of clocks CN_total2 to Winner detector 20.
  • the timing at which the number of clocks CN_total2 is counted is the coincidence timing at which the search data and the reference data 2 coincide.
  • the distance / clock number conversion circuit DC R receives W distance signals D Rj from the distance calculation circuits DP R1 to DP RW and matches the sum of the received W distance signals D Rj. It was counted by the method described below the number of clocks CN_totalR of the clock signal CLK, and outputs a timing signal C R indicating the timing of counting the number of clocks CN_totalR to Winner detector 20.
  • the timing at which the clock number CN_totalR is counted is the coincidence timing at which the search data and the reference data R coincide.
  • the row decoder 2 designates an address in the row direction of the memory unit 1.
  • the column decoder 3 designates an address in the column direction of the memory unit 1.
  • Read / write circuit 4 writes reference data to reference data storage circuits SC 11 to SC 1W , SC 21 to SC 2W ,..., SC R1 to SC RW designated by row decoder 2 and column decoder 3.
  • the search data is written into the search data storage circuit 5.
  • the search data storage circuit 5 stores the search data (M ⁇ W bit data) written by the read / write circuit 4.
  • Winner detector 20 receives from the timing signal C 1 ⁇ C R, respectively distance / clock number conversion circuits DC 1 ⁇ DC R, among the received timing signals C 1 ⁇ C R, the matching timing chronological order k (k Are integers satisfying 1 ⁇ k ⁇ R), and the detected k timing signals are output as match signals M 1 to M k indicating the similarity between the search data and the reference data.
  • Figure 2 is a schematic diagram showing the structure of a distance / clock number converting circuit DC 1 shown in FIG.
  • the distance / clock number converting circuit DC 1 includes an amplifier 21 ⁇ 2W, a counter coincidence detection circuit 31 ⁇ 3W.
  • the amplifier 21 receives a clock signal CLK from a clock generation circuit (not shown) built in the associative memory 100, amplifies the received clock signal CLK, and outputs it to the amplifier 22 and the counter coincidence detection circuit 31.
  • the amplifier 22 receives the clock signal CLK from the amplifier 21 and outputs the received clock signal CLK to the amplifier 23 (not shown) and the counter coincidence detection circuit 32.
  • the amplifier 2W receives the clock signal CLK from the amplifier 2W-1 (not shown) and outputs the received clock signal CLK to the counter coincidence detection circuit 3W.
  • Counter coincidence detection circuits 31 to 3W are provided corresponding to distance calculation circuits DP 11 to DP 1W , respectively.
  • the counter match detection circuits 31 to 3W are connected in series.
  • Counter coincidence detection circuit 31 receives a clock signal CLK from the amplifier 21, receiving the search start signal SB from the control circuit for the associative memory 100 (not shown), the distance calculation circuit distance signal from the DP 11 has a bit length of M bits subject to D 11.
  • Counter match detection circuit 31, when the search start signal SB is switched from L (logical low) level to H (logical high) level, when counted in ascending order in synchronization with the counter value to the clock signal CLK, the distance signal D 11 The number of clocks of the clock signal CLK when a counter value that matches is obtained is counted. Then, the counter coincidence detection circuit 31 outputs a coincidence signal MTH1 indicating the timing of counting the number of clocks to the counter coincidence detection circuit 32 in synchronization with the clock signal CLK.
  • the counter coincidence detection circuit 31 stops its operation when outputting the coincidence signal MTH1.
  • Counter coincidence detection circuit 32 receives a clock signal CLK from the amplifier 22 receives the coincidence signal MTH1 from the counter coincidence detection circuit 31 receives the distance signal D 12 having a bit length of M bits from the distance calculation circuit DP 12. The counter coincidence detection circuit 32 stops operating until it receives the coincidence signal MTH1 from the counter coincidence detection circuit 31. Counter coincidence detection circuit 32 is driven to undergo a coincidence signal MTH1 from the counter coincidence detection circuit 31, when the count in ascending order in synchronization with the counter value to the clock signal CLK, the counter value matches the distance signal D 12 is obtained The number of clocks of the clock signal CLK is counted.
  • the counter coincidence detection circuit 32 outputs a coincidence signal MTH2 indicating the timing of counting the number of clocks to the counter coincidence detection circuit 33 (not shown) in synchronization with the clock signal CLK.
  • the counter coincidence detection circuit 32 stops its operation when outputting the coincidence signal MTH2.
  • counter coincidence detection circuit 3W receives clock signal CLK from amplifier 2W, receives coincidence signal MTHW-1 from counter coincidence detection circuit 3W-1, and sets a bit length of M bits from distance calculation circuit DP 1W. It has a distance signal D 1W .
  • the counter coincidence detection circuit 3W stops operating until it receives a coincidence signal MTHW-1 from the counter coincidence detection circuit 3W-1.
  • Counter coincidence detection circuit 3W is driven from the counter coincidence detecting circuit 3W-1 and receives a match signal MTHW-1, when the count in ascending order in synchronization with the counter value of the clock signal CLK, and coincides with the distance signal D 1W
  • the number of clocks of the clock signal CLK when the counter value is obtained is counted.
  • the counter coincidence detection circuit 3W outputs a coincidence signal MTHW indicating a timing of counting the number of clocks in synchronization with the clock signal CLK as a timing signal C 1 to Winner detector 20.
  • Counter match detection circuit 3W when a timing signal C 1, to stop the operation.
  • FIG. 3 is a schematic diagram showing the configuration of the counter coincidence detection circuit 31 shown in FIG.
  • counter match detection circuit 31 includes a counter 311 and a match detection circuit 312.
  • the counter 311 receives a clock signal CLK from the amplifier 21 and a reset signal RST from a control circuit (not shown) of the associative memory 100. Upon receiving the reset signal RST, the counter 311 resets the counter value, and counts the M-bit bit value in ascending order in synchronization with the clock signal CLK. Then, the counter 311 sequentially outputs the counted counter value CV 11 to the coincidence detection circuit 312 in synchronization with the clock signal CLK.
  • Coincidence detection circuit 312 receives a clock signal CLK from the amplifier 21, receiving the search start signal SB from the control circuit for the associative memory 100 (not shown), sequentially receives the counter value CV 11 from the counter 311, the distance calculation circuit DP 11 receiving a distance signal D 11 from.
  • the search start signal SB when switched from L level to H level, and counts the number of clocks of the clock signal CLK when the counter value CV 11 matching the distance signal D 11 is obtained. Then, the coincidence detection circuit 312 outputs a coincidence signal MTH1 indicating the timing of counting the number of clocks to the counter coincidence detection circuit 32.
  • each of the counter coincidence detection circuits 32 to 3W shown in FIG. 2 has the same configuration as the counter coincidence detection circuit 31 shown in FIG.
  • the coincidence detection circuit 312 of the counter coincidence detection circuits 32 to 3W stops operation until it receives the coincidence signals MTH1 to MTHW-1 from the coincidence detection circuit 312 of the counter coincidence detection circuits 31 to 3W-1, respectively.
  • the signals MTH1 to MTHW-1 are received, they are driven and start operating.
  • FIG. 4 is a diagram for explaining the operation of the counter coincidence detection circuit 31 shown in FIG.
  • the operation of the counter coincidence detection circuit 31 will be described by taking as an example the case where each of the counter value CV 11 and the distance signal D 11 is 3 bits.
  • the distance signal D 11 is assumed to consist of "011".
  • counter 311 of counter coincidence detection circuit 31 receives reset signal RST from the control circuit of associative memory 100, counter 311 resets the number of counts, and period T1, T2, T3, in which clock signal CLK continues.
  • the bit values of “000”, “001”, “010”, “011” are sequentially counted, and the counted “000”, “001”, “010”, “011” are counted.
  • the counter value CV 11 is sequentially output to the coincidence detection circuit 312.
  • the coincidence detection circuit 312 receives the distance signal D 11 from the distance computing circuit DP 11 "011", when receiving a counter value CV 11 for synchronization with the cycle T1 of the clock signal CLK "000” from the counter 311, At timing t1, the number of clocks “0” is counted, and it is detected that the counter value CV 11 of “000” does not match the distance signal D 11 of “011” at the number of clocks “0”.
  • the coincidence detection circuit 312 When the coincidence detection circuit 312 receives the counter value CV 11 of “001” from the counter 311 in synchronization with the next cycle T2 of the cycle T1 of the clock signal CLK, it counts the number of clocks of “1” at the timing t2. , It is detected that the counter value CV 11 of “001” does not coincide with the distance signal D 11 of “011” in the number of clocks of “1”.
  • the coincidence detection circuit 312 receives a counter value CV 11 for synchronization with the next cycle T3 of the period T2 of the clock signal CLK "010" from the counter 311 counts the number of clocks of the "2" at the timing t3 , It is detected that the counter value CV 11 of “010” does not coincide with the distance signal D 11 of “011” in the number of clocks “2”.
  • the coincidence detection circuit 312 receives the counter value CV 11 of “011” from the counter 311 in synchronization with the period T4 next to the period T3 of the clock signal CLK, it counts the number of clocks of “3” at the timing t4. , It is detected that the counter value CV 11 of “011” matches the distance signal D 11 of “011” in the number of clocks “3”.
  • the coincidence detection circuit 312, a timing t4 counted clock number ( "3") of the clock signal CLK when the counter value CV 11 are obtained "011” matches the distance signal D 11 of "011”
  • the coincidence signal MTH1 is output to the counter coincidence detection circuit 32 and the control circuit of the associative memory 100. Thereafter, the coincidence detection circuit 312 stops the operation so that the counter value “011” is held at the clock numbers “4” and “5” in FIG. 4.
  • the counter 311 stops operating until it receives a reset signal RST from the control circuit of the associative memory 100, and the reset signal from the control circuit of the associative memory 100.
  • RST a reset signal
  • the bit values “000”, “001”, “010”, “011”,... are sequentially counted, and the counted “000”, “001”, “010”, “011” are counted.
  • the match detection circuits 312 of the counter match detection circuits 32 to 3W-1 stop operating until they receive the match signals MTH1 to MTHW-2 from the match detection circuits 312 of the counter match detection circuits 31 to 3W-2, respectively.
  • MTH1 to MTHW-2 the number of clocks of the clock signal CLK when the counter values CV 12 to CV 1W-1 coincide with the distance signals D 12 to D 1W-1 , respectively, is counted.
  • Match signals MTH2 to MTHW-1 indicating timing are output to the counter match detection circuits 33 to 3W and the control circuit of the content addressable memory 100, respectively. Then, the coincidence detection circuit 312 of the counter coincidence detection circuits 32 to 3W-1 stops its operation.
  • the counter 311 of the counter coincidence detection circuit 3W stops operating until it receives a reset signal RST from the control circuit of the associative memory 100.
  • a reset signal RST from the control circuit of the associative memory 100
  • “000”, “001” , “010”, “011”,... are sequentially counted, and the counter values CV 1W of “000”, “001”, “010”, “011” ,.
  • the data is sequentially output to the detection circuit 312.
  • the coincidence detection circuit 312 of the counter coincidence detection circuit 3W stops operating until it receives the coincidence signal MTHW-1 from the coincidence detection circuit 312 of the counter coincidence detection circuit 3W-1, and when receiving the coincidence signal MTHW-1, The number of clocks of the clock signal CLK when 1W coincides with the distance signal D 1W is counted, and timing signals (respective timing signals C 1 to C R ) indicating the timing at which the number of clocks is counted are used as the Winner detector 20 and the associative memory. To 100 control circuits. Then, the coincidence detection circuit 312 of the counter coincidence detection circuit 3W stops its operation.
  • the control circuit of the associative memory 100 When receiving the coincidence signals MTH1 to MTHW-1 from the counter coincidence detection circuits 31 to 3W-1, the control circuit of the associative memory 100 outputs the reset signal RST to the counter coincidence detection circuits 32 to 3W, respectively.
  • the control circuit of the associative memory 100 receives a timing signal C 1 from the counter coincidence detection circuit 3W, outputs a reset signal RST to the counter coincidence detection circuits 31 ⁇ 3W.
  • Figure 5 is a diagram for explaining the operation of the distance / clock number converting circuit DC 1 shown in FIG.
  • the distance / clock number converting circuit DC 1 is an illustrating the operation of the distance / clock number converting circuit DC 1 as an example the case of two counter match detection circuits 31 and 32.
  • the distance signal D 11 is composed of "3”
  • the distance signal D 12 is assumed to consist of "5".
  • the counter coincidence detection circuit 32 outputs a timing signal C 1 indicating the timing at which the number of clocks of “5” is counted to the Winner detector 20 and the associative memory 100 control circuit. Then, the counter coincidence detection circuit 32 stops its operation.
  • the counter coincidence detection circuit 32 determines the number of clocks of the clock signal CLK when a counter value that coincides with the distance signal “8” that is the sum of the distance signal “3” and the distance signal “5” is obtained.
  • a timing signal C 1 indicating the timing at which the number of clocks is counted is output.
  • the total number of clocks “8” counted by the two counter coincidence detection circuits 31 and 32 is “3” that the counter coincidence detection circuit 31 counts and “5” that the counter coincidence detection circuit 32 counts. This is the sum of the number of clocks.
  • the distance / clock number conversion circuit DC 1 generally receives W distance signals D 11 to D 1W . Each of the W distance signals D 11 to D 1W has a bit length of M bits. Therefore, the distance / clock number converting circuit DC 1 receives the distance signal D 11 D 12 ⁇ D 1W having a bit length of M ⁇ W bits.
  • the counter coincidence detection circuits 31 to 3 W respectively receive the clock signals CLK when the counter values CV 11 to CV 1W respectively corresponding to the distance signals D 11 to D 1W are obtained.
  • the number of clocks CN1 to CNW is counted.
  • the counter coincidence detection circuits 32 to 3W receive the coincidence signals MTH2 to MTHW-1 from the counter coincidence detection circuits 31 to 3W-1, respectively, and then the counter values CV 12 coincide with the distance signals D 12 to D 1W , respectively.
  • the count of the clock numbers CN2 to CNW of the clock signal CLK when .about.CV 1W is obtained is started.
  • the number of clocks CN_total distance / clock number conversion circuit DC 1 counts is equal to the sum of the number of clocks CN1 ⁇ CNW.
  • clock numbers CN1 to CNW represent distance signals D 11 to D 1W , respectively
  • clock number CN_total represents the sum of distance signals D 11 to D 1W .
  • the Manhattan distance n M equals the distance calculated by equation (1) to those obtained by adding the W number of distance.
  • each of the distance / clock number conversion circuits DC 2 ⁇ DC R also by the distance / operation and the same operation of the clock number conversion circuit DC 1 described in FIG. 5, respectively, and outputs a timing signal C 2 ⁇ C R.
  • FIG. 6 is a diagram for explaining the operation of the Winner detector 20 shown in FIG. Referring to FIG. 6, the distance / clock number conversion circuits DC 1 ⁇ DC R, respectively, and output to the Winner detector 20 in synchronization with timing signals C 1 ⁇ C R to the clock signal CLK.
  • Winner detector 20 receives a timing signal C 1 ⁇ C R, detects the rising timing t 1 ⁇ t R of the received timing signals C 1 ⁇ C R. Then, the Winner detector 20 detects the k timing signals C ′ 1 to C ′ k in order from the earliest rise timing t 1 to t R. Then, the Winner detector 20 outputs the timing signals C ′ 1 to C ′ k as the match signals M 1 to M k .
  • the detected k timing signals C ′ 1 to C ′ k are output as match signals M 1 to M k .
  • Winner detector 20 outputs a timing signal corresponding to the reference data most similar to the search data (any timing signals C 1 ⁇ C R) as a match signal M 1.
  • the Winner detector 20 When k ⁇ 1, the Winner detector 20 outputs k timing signals C ′ 1 to C ′ k corresponding to k reference data similar to the search data as match signals M 1 to M k. To do. In this case, in the k timing signals C ′ 1 to C ′ k , the k rising timings differ from each other by at least one cycle of the clock signal CLK. ' 1 to C' k can be detected accurately. That is, the associative memory 100 can accurately search k reference data similar to the search data.
  • the associative memory 100 can perform the similarity search accurately and at high speed even when the Manhattan distance is used.
  • FIG. 7 is a schematic diagram showing a preferred configuration of the counter 311 shown in FIG.
  • the counter 311 preferably comprises a counter 311A shown in FIG.
  • counter 311A includes frequency dividers 311-1 to 311-M.
  • Divider 311-1 a clock signal CLK to 2 0 times division and outputs a frequency division signal DV 1 that the dividing into coincidence detection circuit 312.
  • Divider 311-2 is a clock signal CLK and 2 one time division and outputs a frequency division signal DV 2 that the dividing into coincidence detection circuit 312.
  • the frequency divider 311 -M divides the clock signal CLK by 2 M ⁇ 1 times, and outputs the divided frequency signal DV M to the coincidence detection circuit 312.
  • FIG. 8 is a diagram for explaining the operation of the counter 311A shown in FIG. In FIG. 8, the operation of the counter 311A will be described by taking as an example the case where the counter 311A includes four frequency dividers 311-1 to 311-4.
  • the frequency divider 311-1 a clock signal CLK to 2 0 times division and outputs a frequency division signal DV 1 that the dividing into coincidence detection circuit 312.
  • Divider 311-2 is a clock signal CLK and 2 one time division and outputs a frequency division signal DV 2 that the dividing into coincidence detection circuit 312.
  • Divider 311-3 is a clock signal CLK 2 2 times by frequency, and outputs a divided signal DV 3 that the division into coincidence detection circuit 312.
  • Divider 311-4 is a clock signal CLK to 2 3 times division and outputs a frequency division signal DV 4 that the dividing into coincidence detection circuit 312.
  • the four frequency dividers 311-1 to 311-4 first output the counter value “0000”, the second output the counter value “0001”, the third “ The counter value “0010” is output, and thereafter, similarly, the counter value “1110” is output 15th, and the counter value “1111” is output last.
  • the counter 311A outputs a counter value other than 4 bits, it is constituted by M frequency dividers 311-1 to 311-M, and the M frequency dividers 311-1 to 311-M are configured as shown in FIG. in the same manner as the embodiment illustrated in, respectively, the clock signal CLK 2 0 times, 2 once, 2 twice, ⁇ ⁇ ⁇ , 2 M-1 times by frequency, the frequency-divided divided signal DV 1 ⁇ DV M Is output.
  • the counter 311A is a counter value of M bits "0 1 0 2 0 3 ⁇ 0 M", "0 1 0 2 0 3 ⁇ 1 M", ⁇ , "1 1 1 2 Output in the order of 1 3 ... 1 M ′′.
  • the bit value of the m-th (m is an integer satisfying 1 ⁇ m ⁇ M) in the direction from the least significant bit to the most significant bit of the M-bit counter value.
  • the circuit size can be reduced and the power consumption can be reduced as compared with a normal counter.
  • distance signal D 11 ⁇ D 1W having a length, D 21 ⁇ D 2W, ⁇ , D R1 ⁇ D timing signals C 1 ⁇ shows the timing obtained by counting the matching number of clocks CN_total1 ⁇ CN_totalR respectively to the sum of the RW C R Is output to the Winner detector 20.
  • each range / clock number conversion circuits DC 1 ⁇ DC R as shown in FIG. 2, a W number of counter match detecting circuits 31 ⁇ 3W connected in series.
  • each of the distance / clock number conversion circuits DC 1 to DC R includes counter coincidence detection circuits 31 and 32.
  • the distance calculation circuits DP 11 to DP 1W are made up of distance calculation circuits DP 11 and DP 12
  • the distance signals D 11 to D 1W are made up of distance signals D 11 and D 12 .
  • the counter coincidence detection circuit 31 the distance signal D 11, provided in correspondence with one of the distance signal of the edge first distance signal D 11 when the sequence D 12 in a line, the first distance signal D upon receiving the 11 from the distance calculation circuit DP 11, when counted in ascending order in synchronization with the counter value to the clock signal CLK, the clock number when the counter value matches the first distance signal D 11 having received the obtained CN1 is counted, and a coincidence signal MTH1 indicating the timing when the number of clocks CN1 is counted is output.
  • the counter coincidence detection circuit 31 constitutes a “first counter coincidence detection circuit”
  • the counter coincidence detection circuit 32 constitutes a “second counter coincidence detection circuit”.
  • each of the distance / clock number conversion circuits DC 1 to DC R includes counter coincidence detection circuits 31 to 3W.
  • the counter coincidence detection circuit 31 is provided corresponding to the first distance signal D 11 that is the distance signal at one end when the distance signals D 11 to D 1W are arranged in a line.
  • the clock number when the counter value matches the first distance signal D 11 having received the obtained CN1 is counted, and a coincidence signal MTH1 indicating the timing when the number of clocks CN1 is counted is output.
  • the counter coincidence detection circuits 32 ⁇ 3W-1 is corresponding to the second distance signal W-2 pieces of distance signals D 12 ⁇ D 1W-1 from D 12 to W-1 th distance signal D 1W-1 Provided.
  • Each of the counter coincidence detection circuits 32 to 3W-1 includes a counter coincidence detection circuit 31 or a counter provided corresponding to the w-1 (w is an integer satisfying 2 ⁇ w ⁇ W ⁇ 1) -th distance signal.
  • a counter value corresponding to the first or wth distance signal from the counter match detection circuits 31 to 3W-2 provided corresponding to the first or w-1th distance signal from the coincidence detection circuits 32 to 3W-2 is obtained.
  • the counter coincidence detection circuit 3W is provided corresponding to the W-th distance signal D 1W, consistent from the counter coincidence detecting circuit 3W-1 provided corresponding to the W-1 th distance signal signal MTHW-1 receiving the W th distance signal D 1W with driven to undergo, when receiving a coincidence signal MTH3W-1 from the counter coincidence detecting circuit 3W-1, when the count in ascending order in synchronization with the counter value of the clock signal CLK counts the number of clocks CN4 when the counter value matches the W th distance signal D 1W is obtained, a timing signal C 1 indicating a timing of counting the number of clocks CN4 to Winner detector 20.
  • the counter coincidence detection circuit 31 constitutes a “first counter coincidence detection circuit”
  • the counter coincidence detection circuits 32 to 3W-1 constitute “W-2 third counter coincidence detection circuits”.
  • the counter coincidence detection circuit 3W constitutes a “fourth counter coincidence detection circuit”.
  • FIG. 9 is a schematic diagram showing another configuration of distance / clock number conversion circuits DC 1 to DC R shown in FIG.
  • each of the distance / clock number conversion circuits DC 1 ⁇ DC R may consist Distance / clock number conversion circuit DC '1 shown in FIG.
  • W 2 i (i is an integer of 2 or more).
  • distance / clock number conversion circuit DC ′ 1 includes amplifiers 41 to 4L and counter match detection circuits 51 to 5L.
  • L W / s (s is an integer satisfying 2 x equal to or less than W, and x is a positive integer).
  • the amplifier 41 receives a clock signal CLK from a clock generation circuit (not shown) built in the associative memory 100, amplifies the received clock signal CLK, and outputs it to the amplifier 42 and the counter coincidence detection circuit 51.
  • the amplifier 42 receives the clock signal CLK from the amplifier 41, amplifies the received clock signal CLK, and outputs the amplified clock signal CLK to the amplifier 43 (not shown) and the counter coincidence detection circuit 52.
  • the amplifier 4L receives the clock signal CLK from the amplifier 4L-1 (not shown), amplifies the received clock signal CLK, and outputs it to the counter coincidence detection circuit 5L.
  • the counter coincidence detection circuits 51, 52,..., 5L have s distance calculation circuits DP 11 , DP 1 (1 + L) ,..., DP 1 (1+ (u ⁇ 1) L) s, respectively.
  • U is 1, 2, 3,..., S.
  • the counter coincidence detection circuits 51 to 5L are connected in series. Each of the counter coincidence detection circuits 51 to 5L has the same configuration as the counter coincidence detection circuit 31 shown in FIG. In this case, each of the counter match detection circuits 51 to 5L includes the counter 311 shown in FIG. 3 or the counter 311A shown in FIG.
  • the counter coincidence detection circuit 51 receives the clock signal CLK from the amplifier 41, the search start signal SB from the control circuit (not shown) of the associative memory 100, and the distance calculation circuits DP 11 , DP 1 (1 + L) ,. , DP 1 (1+ (u ⁇ 1) L) receive distance signals D 11 , D 1 (1 + L) ,..., D 1 (1+ (u ⁇ 1) L) , respectively.
  • the counter coincidence detection circuit 51 receives the distance signals D 11 , D 1 (1 + L) ,..., D 1 (1+ (u ⁇ 1) L) , and when the search start signal SB switches from the L level to the H level, The clock of the clock signal CLK when the counter value CV 11 that matches the sum of the distance signals D 11 , D 1 (1 + L) ,..., D 1 (1+ (u ⁇ 1) L) is obtained by the method described above.
  • the number CN_1 is counted.
  • the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing of counting the clock number CN_1 to the counter coincidence detection circuit 52 in synchronization with the clock signal CLK. Thereafter, the counter coincidence detection circuit 51 stops its operation.
  • the counter coincidence detection circuit 52 receives the clock signal CLK from the amplifier 42, the coincidence signal MTH1 from the counter coincidence detection circuit 51, and the distance calculation circuits DP 12 , DP 1 (2 + L) ,..., DP 1 (2+ (U ⁇ 1) L) receives distance signals D 12 , D 1 (2 + L) ,..., D 1 (2+ (u ⁇ 1) L) .
  • the counter coincidence detection circuit 52 When the counter coincidence detection circuit 52 receives the distance signals D 12 , D 1 (2 + L) ,..., D 1 (2+ (u ⁇ 1) L) and receives the coincidence signal MTH1, the counter signal is detected by the method described above. D 12, D 1 (2 + L), ⁇ , counts the number of clocks CN_2 of the clock signal CLK when the counter value CV 12 that matches the sum of D 1 (2+ (u-1 ) L) is obtained. Then, the counter coincidence detection circuit 52 outputs a coincidence signal MTH2 indicating the timing of counting the clock number CN_2 to the counter coincidence detection circuit 53 in synchronization with the clock signal CLK. Thereafter, the counter match detection circuit 52 stops its operation.
  • the counter coincidence detection circuit 5L receives the clock signal CLK from the amplifier 4L, receives the coincidence signal MTHL-1 from the counter coincidence detection circuit 5L-1, and receives the distance calculation circuits DP 1L , DP 1 (L + L) , ..., DP 1 (L + (u-1) L) receives distance signals D1L , D1 (L + L) , ..., D1 (L + (u-1) L) , respectively.
  • the counter coincidence detection circuit 5L receives the distance signals D 1L , D 1 (L + L) ,..., D 1 (L + (u ⁇ 1) L) and receives the coincidence signal MTHL ⁇ 1, the above-described method is performed.
  • the counter coincidence detection circuit 5L outputs to Winner detector 20 a timing signal C 1 indicating a timing of counting the number of clocks CN_L synchronism with the clock signal CLK. Thereafter, the counter coincidence detection circuit 5L stops its operation.
  • Taimi showing And it outputs a ring signal (any timing signals C 1 ⁇ C R) to the Winner detector 20.
  • FIG. 10 is a schematic diagram showing still another configuration of the distance / clock number conversion circuits DC 1 to DC R shown in FIG.
  • each of the distance / clock number conversion circuits DC 1 to DC R may comprise the distance / clock number conversion circuit DC ′′ 1 shown in FIG. 10.
  • W 2 i (i is an integer of 2 or more).
  • distance / clock number conversion circuit DC ′′ 1 is obtained by adding switching control circuit 60 and multiplexers 61 to 6L to distance / clock number conversion circuit DC ′ 1 shown in FIG. is the same as the distance / clock number conversion circuit DC '1.
  • the amplifiers 41 to 4L amplify the clock signal CLK, output the amplified clock signal CLK to the counter coincidence detection circuits 51 to 5L, respectively, and the amplified clock signal. CLK is output to the switching control circuit 60.
  • multiplexer 61, 62, ⁇ ⁇ ⁇ , 6L respectively, s pieces of distance calculation circuit DP 11, DP 1 (1 + L), ⁇ , DP 1 ( 1+ (u ⁇ 1) L) , s distance arithmetic circuits DP 12 , DP 1 (2 + L) ,..., DP 1 (2+ (u ⁇ 1) L) ,. DP 1L , DP 1 (L + L) ,..., DP 1 (L + (u ⁇ 1) L) are provided, and counter match detection circuits 51 to 5L correspond to multiplexers 61 to 6L, respectively. Provided.
  • the switching control circuit 60 receives the search start signal SB and the reset signal RST from the control circuit of the associative memory 100, and receives the match signals MTH1 to MTHL from the counter match detection circuits 51 to 5L, respectively.
  • switching control circuit 60 When switching control circuit 60 receives search start signal SB and reset signal RST, switching control circuit 60 outputs reset signal RST to counter match detection circuit 51 and output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. .
  • switching control circuit 60 When switching control circuit 60 receives coincidence signal MTHL from counter coincidence detection circuit 5L, it outputs reset signal RST to counter coincidence detection circuit 51 and outputs output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. To do. The switching control circuit 60 executes this process s-1 times.
  • the switching control circuit 60 when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do. The switching control circuit 60 performs this process s times.
  • the switching control circuit 60 when receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 53 and outputs the output signal OUT3 to the multiplexer 63 in synchronization with the clock signal CLK. To do. The switching control circuit 60 performs this process s times.
  • the switching control circuit 60 receives the coincidence signal MTHL-1 from the counter coincidence detection circuit 5L-1, it outputs a reset signal RST to the counter coincidence detection circuit 5L in synchronization with the clock signal CLK. Output signal OUTL is output to multiplexer 6L. The switching control circuit 60 performs this process s times.
  • the multiplexer 61 receives s distance signals D 11 , D 1 (1 + L) ,..., D 1 (1+ (u ⁇ 1) L) .
  • the multiplexer 61 receives the first output signal OUT1 from the switching control circuit 60 outputs a distance signal D 11 to the counter match detection circuit 51, when receiving the second output signal OUT1 from the switching control circuit 60, The distance signal D 1 (1 + L) is output to the counter coincidence detection circuit 51.
  • the distance signal D 1 (1+ (u ⁇ 1) L ) Is output to the counter coincidence detection circuit 51.
  • the multiplexer 62 receives s distance signals D 12 , D 1 (2 + L) ,..., D 1 (2+ (u ⁇ 1) L) .
  • the multiplexer 62 receives the first output signal OUT2 from the switching control circuit 60 outputs a distance signal D 12 to the counter coincidence detection circuit 52, when receiving the second output signal OUT2 from the switching control circuit 60, The distance signal D 1 (2 + L) is output to the counter coincidence detection circuit 52.
  • the distance signal D 1 (2+ (u ⁇ 1) L ) Is output to the counter match detection circuit 52.
  • the multiplexer 6L receives s distance signals D 1L , D 1 (L + L) ,..., D 1 (L + (u ⁇ 1) L) .
  • the multiplexer 6L receives the first output signal OUTL from the switching control circuit 60
  • the multiplexer 6L outputs the distance signal D1L to the counter coincidence detection circuit 5L, and receives the second output signal OUTL from the switching control circuit 60.
  • the distance signal D1 (L + (u-1) L is output when the distance signal D1 (L + L) is output to the counter coincidence detection circuit 5L and the s-th output signal OUTL is similarly received from the switching control circuit 60.
  • the counter coincidence detection circuit 51 is driven when it receives the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 51 receives the distance signal D 11 from the multiplexer 61, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 11 is obtained
  • the clock number CN_1 of the clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60.
  • the counter coincidence detection circuit 51 stops its operation.
  • the counter coincidence detection circuit 51 executes this processing for all s distance signals D 11 , D 1 (1 + L) ,..., D 1 (1+ (u ⁇ 1) L) .
  • the counter coincidence detection circuit 52 is driven when it receives the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 52 receives the distance signal D 12 from the multiplexer 62, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 12 is obtained
  • the clock number CN_2 of the clock signal CLK is counted, and the coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60.
  • the counter match detection circuit 52 stops its operation.
  • the counter coincidence detection circuit 52 executes this process for all s distance signals D 12 , D 1 (2 + L) ,..., D 1 (2+ (u ⁇ 1) L) .
  • the counter coincidence detection circuit 5L is driven when it receives the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 5L receives the distance signal D 1L from the multiplexer 6L, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 1L is obtained
  • the clock number CN_L of the clock signal CLK is counted, and a coincidence signal MTHL indicating the timing at which the clock number CN_L is counted is output to the switching control circuit 60.
  • the counter match detection circuit 5L stops its operation.
  • the counter coincidence detection circuit 5L executes this process for all of the s ⁇ 1 distance signals D 12 , D 1 (2 + L) ,..., D 1 (2+ (u ⁇ 1) L ⁇ 1) .
  • the counter coincidence detection circuit 5L is driven when the s-th reset signal RST is received from the switching control circuit 60, receives the distance signal D1 (L + (u ⁇ 1) L) from the multiplexer 6L, and receives the counter value as a clock.
  • the number of clocks CN_L of the clock signal CLK when the counter value matching the distance signal D1 (L + (u-1) L) is obtained is counted, and the number of clocks CN_L a timing signal C 1 indicating timing for counting the output to Winner detector 20.
  • the switching control circuit 60 In synchronization with the signal CLK, the reset signal RST is output to the counter coincidence detection circuit 51 and the output signal OUT1 is output to the multiplexer 61.
  • the multiplexer 61 depending on the first output signal OUT1 from the switching control circuit 60 outputs a distance signal D 11 to the counter match detection circuit 51.
  • the counter coincidence detection circuit 51 is driven in response to the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 51 receives the distance signal D 11 from the multiplexer 61, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 11 is obtained
  • the clock number CN_1 of the clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.
  • the switching control circuit 60 outputs the reset signal RST to the counter match detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK according to the match signal MTH1 from the counter match detection circuit 51. Output.
  • Multiplexer 62 in response to the first output signal OUT2 from the switching control circuit 60 outputs a distance signal D 12 to the counter coincidence detection circuit 52.
  • the counter coincidence detection circuit 52 is driven in response to the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 52 receives the distance signal D 12 from the multiplexer 62, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 12 is obtained
  • the clock number CN_2 of the clock signal CLK is counted, and the coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.
  • the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 5L in synchronization with the clock signal CLK in response to the coincidence signal MTHL-1 from the counter coincidence detection circuit 5L-1. At the same time, the output signal OUTL is output to the multiplexer 6L.
  • the multiplexer 6L outputs the distance signal D1L to the counter coincidence detection circuit 5L in response to the first output signal OUTL from the switching control circuit 60.
  • the counter coincidence detection circuit 5L is driven according to the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 5L receives the distance signal D 1L from the multiplexer 6L, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 1L is obtained
  • the clock number CN_L of the clock signal CLK is counted, and a coincidence signal MTHL indicating the timing at which the clock number CN_L is counted is output to the switching control circuit 60. Then, the counter match detection circuit 5L stops its operation.
  • the switching control circuit 60 outputs the reset signal RST to the counter match detection circuit 51 and the output signal OUT1 to the multiplexer 61 in synchronization with the clock signal CLK according to the match signal MTHL from the counter match detection circuit 5L. Output.
  • the counter match detection circuits 51 to 5L-1, the switching control circuit 60, and the multiplexers 61 to 6L-1 repeatedly execute the above-described operation s-1 times, and the counter match detection circuit 5L and the multiplexer 6L perform the above-described operation. Are repeatedly executed s-2 times.
  • the counter coincidence detection circuit 5L When the counter coincidence detection circuit 5L receives the s-th reset signal RST from the switching control circuit 60 and the distance signal D1 (L + (u ⁇ 1) L) from the multiplexer 6L, the counter value is converted to the clock signal CLK. When counting in ascending order synchronously, the clock number CN_L of the clock signal CLK when the counter value matching the distance signal D1 (L + (u ⁇ 1) L) is obtained is counted, and the clock number CN_L is counted A timing signal C 1 indicating the timing is output to the Winner detector 20. Then, the counter match detection circuit 5L stops its operation.
  • the counter coincidence detection circuits 51 to 5L count the clock numbers CN_1 to CN_L of the clock signal CLK when the counter values coincident with the distance signals D 11 to D 1L are obtained, and the timing at which the clock numbers CN_1 to CN_L are counted
  • the coincidence signals MTH1 to MTHL indicating the number of clock signals CLK when the counter coincidence detection circuit MDC obtains a counter value that coincides with the sum of the distance signals D 11 to D 1L (CN_1 + CN_2 +... + CN_L )
  • the coincidence signal indicating the timing when the number of clocks (CN_1 + CN_2 +... + CN_L) is counted is output.
  • the counter match detection circuit MDC repeatedly executes this process s-1 times.
  • CLK clock signals
  • CN_1 + CN_2 +... + CN_L clock number
  • Figure 11 is a schematic diagram showing a specific configuration of the distance / clock number converting circuit DC '1 shown in FIG.
  • Conversion circuit DC ′ 1 ⁇ 1 includes amplifiers 41 to 44 and counter coincidence detection circuits 51 to 54.
  • the W distance signals D 11 to D 1W are composed of eight distance signals D 11 to D 18 , and the W distance calculation circuits DP 11 to DP 1W are eight distance calculation circuits DP 11 to DP 1. It consists of 18 .
  • the counter coincidence detection circuit 51 is provided corresponding to the two distance arithmetic circuits DP 11 and DP 15
  • the counter coincidence detection circuit 52 is provided corresponding to the two distance arithmetic circuits DP 12 and DP 16.
  • the counter match detection circuit 53 is provided corresponding to the two distance calculation circuits DP 13 and DP 17
  • the counter match detection circuit 54 is provided corresponding to the two distance calculation circuits DP 14 and DP 18. It is done.
  • FIG. 12 is a diagram for explaining the operation of the distance / clock number conversion circuit DC ′ 1 ⁇ 1 shown in FIG.
  • Each of the distance / clock number conversion circuits DC 1 to DC R includes a distance / clock number conversion circuit DC ′ 1 ⁇ 1 shown in FIG.
  • each of the distance / clock number conversion circuits DC 1 to DC R is composed of the distance / clock number conversion circuit DC ′ 1 ⁇ 1
  • Figure 13 is a schematic diagram showing another specific configuration of the distance / clock number converting circuit DC '1 shown in FIG.
  • Conversion circuit DC ′ 1 -2 includes amplifiers 41 and 42 and counter coincidence detection circuits 51 and 52.
  • the W distance signals D 11 to D 1W are composed of eight distance signals D 11 to D 18
  • the W distance calculation circuits DP 11 to DP 1W are eight distance calculation circuits DP 11 to DP 1. It consists of 18 .
  • Each of the distance signals D 11 to D 18 is composed of a 4-bit bit value.
  • the counter coincidence detection circuit 51 is provided corresponding to the four distance arithmetic circuits DP 11 , DP 13 , DP 15 , and DP 17 , and the counter coincidence detection circuit 52 includes the four distance arithmetic circuits DP 12 , DP 14 , DP 16 , and DP 18 .
  • the counter 311 or 311A outputs a 4-bit counter value to the coincidence detection circuit 312.
  • FIG. 14 is a diagram for explaining the operation of the distance / clock number conversion circuit DC ′ 1 -2 shown in FIG.
  • the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing of counting the clock number CN1 to the counter coincidence detection circuit 52 in synchronization with the clock signal CLK. Then, the counter coincidence detection circuit 51 stops its operation.
  • the counter coincidence detection circuit 52 is driven when the coincidence signal MTH1 is received from the counter coincidence detection circuit 51.
  • FIG. 15 is a schematic diagram showing a specific configuration of the distance / clock number conversion circuit DC ′′ 1 shown in FIG.
  • the conversion circuit DC ′′ 1 ⁇ 1 includes amplifiers 41 to 44, counter coincidence detection circuits 51 to 54, a switching control circuit 60, and multiplexers 61 to 64.
  • the W distance signals D 11 to D 1W are composed of eight distance signals D 11 to D 18 , and the W distance calculation circuits DP 11 to DP 1W are eight distance calculation circuits DP 11 to DP 1. It consists of 18 .
  • the multiplexer 61 is provided corresponding to the two distance calculation circuits DP 11 and DP 15
  • the multiplexer 62 is provided with the two distance calculation circuits DP 12 and DP 15
  • the multiplexer 63 is provided corresponding to the two distance arithmetic circuits DP 13 and DP 17
  • the multiplexer 64 is provided corresponding to the two distance arithmetic circuits DP 14 and DP 18. It is done.
  • Counter coincidence detection circuits 51 to 54 are provided corresponding to the multiplexers 61 to 64, respectively.
  • the amplifiers 41 to 44 amplify the clock signal CLK, and output the amplified clock signal CLK to the counter coincidence detection circuits 51 to 54, respectively.
  • the clock signal CLK is output to the switching control circuit 60.
  • Switching control circuit 60 receives search start signal SB and reset signal RST from the control circuit of associative memory 100, and receives match signals MTH1 to MTH4 from counter match detection circuits 51 to 54, respectively.
  • switching control circuit 60 When switching control circuit 60 receives search start signal SB and reset signal RST, switching control circuit 60 outputs reset signal RST to counter match detection circuit 51 and output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. .
  • the switching control circuit 60 when receiving the coincidence signal MTH4 from the counter coincidence detection circuit 54, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 and outputs the output signal OUT1 to the multiplexer 61 in synchronization with the clock signal CLK. To do.
  • the switching control circuit 60 when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do.
  • the switching control circuit 60 when receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 53 and outputs the output signal OUT3 to the multiplexer 63 in synchronization with the clock signal CLK. To do.
  • the switching control circuit 60 when receiving the coincidence signal MTH3 from the counter coincidence detection circuit 53, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 54 and outputs the output signal OUT4 to the multiplexer 64 in synchronization with the clock signal CLK. To do.
  • the multiplexer 61 receives two distance signals D 11 and D 15 .
  • the multiplexer 61 receives the first output signal OUT1 from the switching control circuit 60 outputs a distance signal D 11 to the counter match detection circuit 51, when receiving the second output signal OUT1 from the switching control circuit 60, and it outputs a distance signal D 15 to the counter match detection circuit 51.
  • the multiplexer 62 receives two distance signals D 12 and D 16 .
  • the multiplexer 62 receives the first output signal OUT2 from the switching control circuit 60 outputs a distance signal D 12 to the counter coincidence detection circuit 52, when receiving the second output signal OUT2 from the switching control circuit 60, and it outputs a distance signal D 16 to the counter coincidence detection circuit 52.
  • the multiplexer 63 receives the two distance signals D 13 and D 17 .
  • the multiplexer 63 receives the first output signal OUT3 from the switching control circuit 60 outputs a distance signal D 13 to the counter coincidence detection circuit 53, when receiving the second output signal OUT3 from the switching control circuit 60, The distance signal D 17 is output to the counter coincidence detection circuit 53.
  • the multiplexer 64 receives the two distance signals D 14 and D 18 .
  • the multiplexer 64 receives the first output signal OUT4 from the switching control circuit 60 outputs a distance signal D 14 to the counter coincidence detection circuit 54, when receiving the second output signal OUT4 from the switching control circuit 60, and it outputs the distance signal D 18 to the counter coincidence detection circuit 54.
  • the counter coincidence detection circuit 51 is driven when it receives the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 51 receives the distance signal D 11 from the multiplexer 61, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 11 is obtained
  • the clock number CN_1 of the clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.
  • the counter coincidence detection circuit 51 executes this process for all the two distance signals D 11 and D 15 .
  • the counter coincidence detection circuit 52 is driven when it receives the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 52 receives the distance signal D 12 from the multiplexer 62, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 12 is obtained
  • the clock number CN_2 of the clock signal CLK is counted, and the coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60.
  • the counter match detection circuit 52 stops its operation.
  • the counter coincidence detection circuit 52 executes this process for all of the two distance signals D 12 and D 16 .
  • the counter coincidence detection circuit 53 is driven when it receives the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 53 receives the distance signals D 13 from the multiplexer 63, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 13 is obtained
  • the clock number CN_3 of the clock signal CLK is counted, and a coincidence signal MTH3 indicating the timing at which the clock number CN_3 is counted is output to the switching control circuit 60.
  • the counter coincidence detection circuit 53 stops its operation.
  • the counter coincidence detection circuit 53 executes this process for all of the two distance signals D 13 and D 17 .
  • the counter coincidence detection circuit 54 is driven when it receives the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuit 54 receives the distance signal D 14 from the multiplexer 64, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D 14 is obtained.
  • the clock number CN_4 of the clock signal CLK is counted, and a coincidence signal MTH4 indicating the timing at which the clock number CN_4 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 54 stops its operation.
  • FIG. 16 is a diagram for explaining the operation of the distance / clock number conversion circuit DC ′′ 1 ⁇ 1 shown in FIG.
  • the switching control circuit 60 In synchronization with the clock signal CLK, the reset signal RST is output to the counter coincidence detection circuit 51 and the output signal OUT1 is output to the multiplexer 61.
  • the counter coincidence detection circuit 51 is driven in response to the reset signal RST from the switching control circuit 60.
  • the switching control circuit 60 when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do.
  • the counter coincidence detection circuit 52 is driven in response to the reset signal RST from the switching control circuit 60.
  • the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 53 and outputs the output signal OUT3 to the multiplexer 63 in synchronization with the clock signal CLK. To do.
  • the counter coincidence detection circuit 53 is driven in response to the reset signal RST from the switching control circuit 60.
  • the switching control circuit 60 when receiving the coincidence signal MTH3 from the counter coincidence detection circuit 53, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 54 and outputs the output signal OUT4 to the multiplexer 64 in synchronization with the clock signal CLK. To do.
  • the counter coincidence detection circuit 54 is driven according to the reset signal RST from the switching control circuit 60.
  • the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 and the output signal OUT1 to the multiplexer 61 in synchronization with the clock signal CLK. To do.
  • the counter coincidence detection circuit 51 is driven in response to the reset signal RST from the switching control circuit 60.
  • the switching control circuit 60 when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do.
  • the counter coincidence detection circuit 52 is driven in response to the reset signal RST from the switching control circuit 60.
  • the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 53 and outputs the output signal OUT3 to the multiplexer 63 in synchronization with the clock signal CLK. To do.
  • the counter coincidence detection circuit 53 is driven in response to the reset signal RST from the switching control circuit 60.
  • the switching control circuit 60 when receiving the coincidence signal MTH3 from the counter coincidence detection circuit 53, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 54 and outputs the output signal OUT4 to the multiplexer 64 in synchronization with the clock signal CLK. To do.
  • the counter coincidence detection circuit 54 is driven according to the reset signal RST from the switching control circuit 60.
  • the counter coincidence detection circuits 51 to 54 count the clock numbers CN_1 to CN_4 of the clock signal CLK when the counter values coincident with the distance signals D 11 to D 14 are obtained, and the clock numbers CN_1 to CN_4 after outputting a coincidence signal MTH1 ⁇ MTH4 showing a timing of counting, counts the number of clocks CN_1 ⁇ CN_4 of the clock signal CLK when the respective counter value matches the distance signal D 15 ⁇ D 18 is obtained, Match signals MTH1 to MTH4 indicating the timings when the clock numbers CN_1 to CN_4 are counted are output.
  • each of the counter coincidence detection circuits 51 to 54 counts the clock number of the clock signal CLK when a counter value that coincides with the distance signal is obtained, and outputs a coincidence signal indicating the timing at which the clock number is counted. Repeat twice.
  • each of the distance / clock number conversion circuits DC 1 to DC R is composed of the distance / clock number conversion circuit DC ′′ 1 ⁇ 1
  • FIG. 17 is a schematic diagram showing still another specific configuration of the distance / clock number conversion circuit DC ′′ 1 shown in FIG.
  • the conversion circuit DC ′′ 1 -2 includes amplifiers 41 and 42, counter coincidence detection circuits 51 and 52, a switch control circuit 60, and multiplexers 61 and 62.
  • the multiplexer 61 is provided corresponding to the four distance calculation circuits DP 11 , DP 13 , DP 15 , DP 17 , and the multiplexer 62 is added to the four distance calculation circuits DP 12 , DP 14 , DP 16 , DP 18 . Correspondingly provided.
  • the counter match detection circuit 51 is provided corresponding to the multiplexer 61, and the counter match detection circuit 52 is provided corresponding to the multiplexer 62.
  • the switching control circuit 60 receives the search start signal SB and the reset signal RST from the control circuit of the associative memory 100. Further, the switching control circuit 60 receives the clock signal CLK from the amplifiers 41 and 42. Further, the switching control circuit 60 receives the coincidence signal MTH1 from the counter coincidence detection circuit 51 and the coincidence signal MTH2 from the counter coincidence detection circuit 52.
  • switching control circuit 60 When switching control circuit 60 receives search start signal SB and reset signal RST, switching control circuit 60 outputs reset signal RST to counter match detection circuit 51 and output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. .
  • switching control circuit 60 When switching control circuit 60 receives match signal MTH2 from counter match detection circuit 52, switching control circuit 60 outputs reset signal RST to counter match detection circuit 51 and output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. To do.
  • the switching control circuit 60 when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do.
  • the multiplexer 61 receives distance signals D 11 , D 13 , D 15 , and D 17 from the distance calculation circuits DP 11 , DP 13 , DP 15 , and DP 17 , respectively, and receives an output signal OUT 1 from the switching control circuit 60.
  • the multiplexer 61 receives the first output signal OUT1, the distance and outputs a signal D 11 to the counter match detection circuit 51, when receiving the second output signal OUT1, the distance signal D 13 counter match detection circuit 51 and outputs to and receives the output signal OUT1 of the third, and outputs a distance signal D 15 to the counter coincidence detection circuit 51 receives the output signal OUT1 of the fourth, it outputs a distance signal D 17 to the counter match detection circuit 51 To do.
  • the multiplexer 62 receives distance signals D 12 , D 14 , D 16 , D 18 from the distance calculation circuits DP 12 , DP 14 , DP 16 , DP 18 , respectively, and receives the output signal OUT 2 from the switching control circuit 60.
  • the multiplexer 62 receives the first output signal OUT2, and outputs a distance signal D 12 to the counter coincidence detection circuit 52, when receiving the second output signal OUT2, the distance signal D 14 counter coincidence detection circuit 52 and outputs to and receives the output signal OUT2 of the third, and outputs a distance signal D 16 to the counter coincidence detection circuit 52 receives the output signal OUT2 of the fourth, it outputs a distance signal D 18 to the counter coincidence detection circuit 52 To do.
  • Counter coincidence detection circuit 51 receives the distance signal D 11 from the multiplexer 61 receives the reset signal RST from the switching control circuit 60, by the above-described method, when the counter value CV 11 matching the distance signal D 11 is obtained.
  • the clock number CN_1 of the clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.
  • the counter coincidence detection circuit 51 receives the distance signal D 13 from the multiplexer 61 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value CV 11 matching the distance signal D 13 is obtained
  • the clock number CN_1 of the current clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.
  • the counter coincidence detection circuit 51 receives the distance signal D 15 from the multiplexer 61 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value CV 11 matching the distance signal D 15 is obtained
  • the clock number CN_1 of the current clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.
  • the counter coincidence detection circuit 51 receives the distance signal D 17 from the multiplexer 61 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value CV 11 matching the distance signal D 17 is obtained
  • the clock number CN_1 of the current clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.
  • Counter coincidence detection circuit 52 receives the distance signal D 12 from the multiplexer 62 receives the reset signal RST from the switching control circuit 60, by the above-described method, when the counter value CV 12 matching the distance signal D 12 is obtained.
  • the clock number CN_2 of the clock signal CLK is counted, and a coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.
  • the counter coincidence detection circuit 52 receives the distance signal D 14 from the multiplexer 62 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value CV 12 matching the distance signal D 14 is obtained
  • the clock number CN_2 of the current clock signal CLK is counted, and a coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.
  • the counter coincidence detection circuit 52 receives the distance signal D 16 from the multiplexer 62 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value CV 12 matching the distance signal D 16 is obtained
  • the clock number CN_2 of the current clock signal CLK is counted, and a coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.
  • the counter coincidence detection circuit 52 receives the distance signal D 18 from the multiplexer 62 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value CV 12 matching the distance signal D 18 is obtained
  • the clock number CN_2 of the current clock signal CLK is counted, and a coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.
  • FIG. 18 is a diagram for explaining the operation of the distance / clock number conversion circuit DC ′′ 1 -2 shown in FIG.
  • switching control circuit 60 generates reset signal RST as counter match detection circuit 51 in synchronization with clock signal CLK in response to search start signal SB and reset signal RST from the control circuit of associative memory 100. And output signal OUT1 to multiplexer 61.
  • the multiplexer 61 receives distance signals D 11 , D 13 , D 15 , and D 17 from the distance calculation circuits DP 11 , DP 13 , DP 15 , and DP 17 , respectively. Then, the multiplexer 61, depending on the first output signal OUT1, and outputs a distance signal D 11 to the counter match detection circuit 51.
  • the switching control circuit 60 when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. Output.
  • the switching control circuit 60 when receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 in synchronization with the clock signal CLK, and outputs the output signal OUT1 to the multiplexer 61. Output to.
  • the switching control circuit 60 When receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and outputs the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. .
  • the switching control circuit 60 When receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 in synchronization with the clock signal CLK and outputs the output signal OUT1 to the multiplexer 61. Output.
  • the switching control circuit 60 When receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 in synchronization with the clock signal CLK and outputs the output signal OUT2 to the multiplexer 62. Output.
  • the switching control circuit 60 When receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 in synchronization with the clock signal CLK and outputs the output signal OUT1 to the multiplexer 61. Output.
  • the switching control circuit 60 when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. Output.
  • CN_2 is counted, and coincidence signals MTH1 and MTH2 indicating the timing when the clock numbers CN_1 and CN_2 are counted are output to the switching control circuit 60.
  • the case where the coincidence detection circuits 51 and 52 are formed has been described.
  • each of the distance / clock number conversion circuits DC 1 to DC R includes the distance / clock number conversion circuit DC ′ 1-2 shown in FIG. 13 or the distance / clock number conversion circuit DC ′′ 1-2 shown in FIG.
  • the clock number CN_1 of the clock signal CLK when the counter value matching the p-th distance signal is obtained is counted, and the clock number
  • the matching process for outputting the matching signal MTH1 indicating the timing when CN_1 is counted is repeatedly executed W / 2 times.
  • the distance signal is received, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the number of clocks CN_2 of the clock signal CLK when the counter value matching the qth distance signal is obtained is counted.
  • the coincidence process for outputting the coincidence signal MTH2 indicating the timing of counting the number CN_2 is repeatedly executed ((W / 2) -1) times, the coincidence signal MTH1 is received W / 2 times, and the Wth distance signal is received.
  • the counter coincidence detection circuit 51 constitutes a “first counter coincidence detection circuit”
  • the counter coincidence detection circuit 52 constitutes a “second counter coincidence detection circuit”.
  • the counter 311 (or the counter 311A) of the counter coincidence detection circuit 51 constitutes a “first counter”, and the coincidence detection circuit 312 of the counter coincidence detection circuit 51 constitutes a “first coincidence detection circuit”.
  • the counter 311 (or the counter 311A) of the counter coincidence detection circuit 52 constitutes a “second counter”, and the coincidence detection circuit 312 of the counter coincidence detection circuit 52 constitutes a “second coincidence detection circuit”.
  • the distance / reduces the circuit area of the clock number conversion circuits DC 1 ⁇ DC R power consumption can be reduced.
  • FIG. 19 is a diagram showing a comparison of the shortest search times.
  • the frequency mapping type in FIG. 19 means an associative memory that searches for reference data similar to the search data by converting the distance between the search data and the reference data into a frequency.
  • the shortest search time is 1280 (ns) in the frequency mapping type associative memory.
  • the shortest search time is 20 (ns).
  • the shortest search time is 210000 (ns) in the frequency mapping type associative memory.
  • the shortest search time is 40 (ns).
  • the associative memory 100 can search for reference data similar to the search data in a time shorter by two digits or more than the conventional frequency mapping type associative memory.
  • the associative memory 100 according to the embodiment of the present invention can drastically shorten the search time as the number of bits of reference data increases.
  • FIG. 20 is a diagram showing a comparison of power consumption.
  • the associative memory of the conventional example is the associative memory described in Non-Patent Document 3.
  • 64 reference data are used in the associative memory of the conventional example, and 128 reference data are used in the associative memory 100 of the present invention.
  • the power consumption is 321 (mW), whereas in the associative memory 100 of the present invention, the power consumption is 2.13 (mW).
  • the associative memory 100 can reduce power consumption by two orders of magnitude or more than the conventional associative memory although the number of reference data is twice as large. .
  • the reference data similar to the search data can be searched at high speed with low power consumption by using the associative memory 100 according to the embodiment of the present invention.
  • k reference data similar to the search data is searched using the Manhattan distance.
  • the search data is not limited to this and may be searched using the Hamming distance. You may search k similar reference data.
  • the M bit consists of 1 bit
  • each of the reference data storage circuits SC 11 to SC 1W , SC 21 to SC 2W ,..., SC R1 to SC RW stores 1-bit reference data.
  • each of the distance calculation circuits DP 11 to DP 1W , DP 21 to DP 2W ,..., DP R1 to DP RW determines the distance between one bit of the search data and one bit of the reference data according to the equation (1). Calculate.
  • the associative memory 100 searches the k reference data similar to the search data using the Hamming distance according to the above-described operation.
  • This invention is applied to an associative memory.

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Abstract

Une mémoire associative comprend R convertisseurs distance/signal d'horloge (DC1 à DCR), chacun d'eux comportant un circuit de détection de correspondance de compteur (31 à 3W). Chaque signal de distance (D11 à D1W) représente la distance entre des données devant être récupérées et des données de référence. Le circuit de détection de correspondance de compteur (31) compte le nombre de signaux d'horloge qui a une valeur de compteur qui correspond au signal de distance (D11). Puis le circuit de détection de correspondance de compteur (32) compte le nombre de signaux d'horloge qui a une valeur de compteur qui correspond au signal de distance (D12). De même, quand le circuit de détection de correspondance de compteur (3W-1) compte le nombre de signaux d'horloge qui a une valeur de compteur qui correspond au signal de distance (D1W-1), le circuit de détection de correspondance de compteur (3W) compte le nombre de signaux d'horloge qui a une valeur de compteur qui correspond au signal de distance (D1W).
PCT/JP2013/060326 2012-08-23 2013-04-04 Mémoire associative WO2014030383A1 (fr)

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