WO2014030383A1 - Associative memory - Google Patents

Abstract

An associative memory is provided with R distance/clock converters (DC₁ to DC_R), each of which includes a counter match detection circuit (31 to 3W). Each distance signal (D₁₁ to D_1W) represents the distance between data to be retrieved and reference data. The counter match detection circuit (31) counts the number of clocks that has a counter value that matches the distance signal (D₁₁). Thereafter, the counter match detection circuit (32) counts the number of clocks that has a counter value that matches the distance signal (D₁₂). Similarly, when the counter match detection circuit (3W-1) counts the number of clocks that has a counter value that matches the distance signal (D_1W-1), the counter match detection circuit (3W) counts the number of clocks that has a counter value that matches the distance signal (D_1W).

Description

Associative memory

The present invention relates to an associative memory.

In recent years, applications that require pattern matching, such as character recognition and image recognition, have attracted a great deal of attention. In particular, by realizing pattern matching on LSI (Large Scale Integrated Circuit), it will be applicable to high-function applications such as artificial intelligence and mobile devices in the future, and the realization of this technology has received much attention. .

In pattern matching, "complete match search process" that searches for a pattern that completely matches the search data from multiple reference data stored in the database, and "most similar search" that searches for the most similar pattern to the search data. Treatment ".

The former is called CAM (Contents Addressable Memory), and is used to realize the routing of the IP address table of the network router and the cache of the processor. In order for a computer to perform flexible search / comparison such as the human brain, it is indispensable to realize the latter most similar search process. A memory having a function for realizing such a flexible comparison is particularly referred to as an associative memory.

As means for realizing an associative memory, (1) an implementation method using a digital method (Non-patent Document 1), (2) an implementation method using an analog method, and (3) a digital / analog fusion method (Non-Patent Document 2) have been proposed. Yes.
Y. Oike, et al., "A High-Speed and Low-Voltage Associative Co-Processor with Hamming Distance Ordering Using Word-Parallel and Hierarchical Search Architecture," CICC, 2004. M. A. Abedin, et al., "Nearest-euclidean-distance search associative memory with fully parallel mixed digital-analog match circuitry," Proc. Of SSDM2006, pp. 282-283, 2006. Y. Oike et al., "A Word-Parallel Digital Associative Engine with Wide Search RangeBased on ManhattanDistance," CICC, 2004.

However, since the associative memory described in Non-Patent Document 1 performs a similar search using the Hamming distance between the search data and the reference data, there is a problem that it is difficult to perform a similar search using the Manhattan distance. Further, in the associative memory described in Non-Patent Document 2, since the distance representing the similarity between the search data and the reference data is converted into a voltage, there is a problem that an erroneous search occurs.

Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide an associative memory capable of performing a similar search accurately and at high speed even when the Manhattan distance is used. It is to be.

The content addressable memory according to the embodiment of the present invention includes a reference data storage circuit, R distance calculation circuits, R distance / clock number conversion circuits, and a Winner detector. The reference data storage circuit stores R reference data each having a bit length of M × W bits. The R distance calculation circuits are provided corresponding to the R reference data, each of which has a bit length of M × W bits, and represents the distance between the search data to be searched and the reference data. Number of distance signals are output. The R distance / clock number conversion circuits are provided corresponding to the R distance calculation circuits, each receiving W distance signals each having an M-bit bit length from the corresponding distance calculation circuit, The number of clocks of the clock signal when a counter value that matches the sum of the received W distance signals is obtained is counted, and a timing signal indicating the coincidence timing that is the timing at which the number of clocks is counted is output. The Winner detector detects k timing signals in order of the matching timing based on the R timing signals received from the R distance / clock number conversion circuits, and searches for the detected k timing signals. A match signal indicating the similarity between the data and the reference data is output.

In the associative memory according to the embodiment of the present invention, each of the R distance / clock number conversion circuits has a counter value that matches the sum of the W distance signals received from the corresponding distance calculation circuit. The number of clocks of the clock signal is counted, and a timing signal indicating the coincidence timing that is the timing of counting the number of clocks is output. That is, each of the R distance / clock number conversion circuits converts the sum of the W distance signals into the clock number of the clock signal, and outputs a timing signal indicating the timing at which the converted clock number is obtained. As a result, if the distance represented by the sum of the W distance signals is small, the timing signal indicates an earlier coincidence timing, and if the distance represented by the sum of the W distance signals is large, the timing signal is slower. Indicates the match timing. Further, the number of clocks of the clock signal when a counter value matching the sum of the W distance signals is obtained is W of the clock signal when the W counter values matching each of the W distance signals are obtained. Since the number of clocks is added, the clock signal when the counter value matching the distance signal between the search data and the reference data when the distance between the search data and the reference data is expressed by the Manhattan distance is obtained. It becomes the number of clocks. Furthermore, the two timings indicated by the two timing signals have a time difference of at least one period of the clock signal. Further, the search time is shortened by increasing the frequency of the clock signal.

Therefore, according to the embodiment of the present invention, even when the Manhattan distance is used, the similarity search can be performed accurately and at high speed.

It is a schematic block diagram which shows the structure of the content addressable memory by embodiment of this invention. FIG. 2 is a schematic diagram illustrating a configuration of a distance / clock number conversion circuit illustrated in FIG. 1. FIG. 3 is a schematic diagram illustrating a configuration of a counter coincidence detection circuit illustrated in FIG. 2. FIG. 4 is a diagram for explaining the operation of the counter coincidence detection circuit shown in FIG. 3. FIG. 2 is a diagram for explaining the operation of a distance / clock number conversion circuit shown in FIG. 1. It is a figure for demonstrating operation | movement of the Winner detector shown in FIG. It is the schematic which shows the preferable structure of the counter shown in FIG. It is a figure for demonstrating operation | movement of the counter shown in FIG. FIG. 3 is a schematic diagram showing another configuration of the distance / clock number conversion circuit shown in FIG. 1. FIG. 5 is a schematic diagram showing still another configuration of the distance / clock number conversion circuit shown in FIG. 1. FIG. 10 is a schematic diagram showing a specific configuration of the distance / clock number conversion circuit shown in FIG. 9. It is a figure for demonstrating operation | movement of the distance / clock number conversion circuit shown in FIG. FIG. 10 is a schematic diagram showing another specific configuration of the distance / clock number conversion circuit shown in FIG. 9. It is a figure for demonstrating operation | movement of the distance / clock number conversion circuit shown in FIG. FIG. 11 is a schematic diagram illustrating a specific configuration of the distance / clock number conversion circuit illustrated in FIG. 10. FIG. 16 is a diagram for explaining the operation of the distance / clock number conversion circuit shown in FIG. 15; FIG. 11 is a schematic diagram showing still another specific configuration of the distance / clock number conversion circuit shown in FIG. 10. FIG. 18 is a diagram for explaining the operation of the distance / clock number conversion circuit shown in FIG. 17. It is a figure which shows the comparison of the shortest search time. It is a figure which shows the comparison of power consumption.

Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

FIG. 1 is a schematic block diagram showing a configuration of an associative memory according to an embodiment of the present invention. Referring to FIG. 1, an associative memory 100 according to the first embodiment of the present invention includes a memory array unit 10 and a Winner detector 20.

The memory array unit 10 includes a memory unit 1, a row decoder 2, a column decoder 3, a read / write circuit 4, and a search data storage circuit 5.

The memory unit 1 includes a reference data storage circuit (Storage Cell: SC) SC ₁₁ to SC _1W , SC ₂₁ to SC _2W ,..., SC _R1 to SC _RW, and a distance calculation circuit (Distance Processor: DP) DP ₁₁ to DP _1W , DP ₂₁ to DP _2W ,..., DP _R1 to DP _RW , and distance / clock number conversion circuits DC ₁ to DC _R are included. Each of W and R is an integer of 2 or more.

The distance calculation circuits DP ₁₁ to DP _1W are provided corresponding to the reference data storage circuits SC ₁₁ to SC _1W , respectively. The distance calculation circuits DP ₂₁ to DP _2W are provided corresponding to the reference data storage circuits SC ₂₁ to SC _2W , respectively. Similarly, the distance calculation circuits DP _R1 to DP _RW are provided corresponding to the reference data storage circuits SC _R1 to SC _RW , respectively.

The distance / clock number conversion circuit DC ₁ is provided corresponding to the distance calculation circuits DP ₁₁ to DP _1W . The distance / clock number conversion circuit DC ₂ is provided corresponding to the distance calculation circuits DP ₂₁ to DP _2W . Similarly, the distance / clock number conversion circuit DC _R is provided corresponding to the distance calculation circuits DP _R1 to DP _RW .

Reference data storage circuits SC ₁₁ to SC _1W , SC ₂₁ to SC _2W ,..., SC _R1 to SC _RW store reference data written by the row decoder 2, the column decoder 3, and the read / write circuit 4. . In this case, the reference data storage circuits SC ₁₁ to SC _1W store M × W (M is an integer of 1 or more) bits of reference data 1, and the reference data storage circuits SC ₂₁ to SC _2W have M × W bits. The reference data 2 is stored, and the reference data storage circuits SC _R1 to SC _RW store the M × W bit reference data R in the same manner. That is, each of the reference data storage circuits SC ₁₁ to SC _1W , SC ₂₁ to SC _2W ,..., SC _R1 to SC _RW stores M bits of reference data.

The distance calculation circuits DP ₁₁ to DP _1W include M × W bit reference data 1 stored in the reference data storage circuits SC ₁₁ to SC _1W , M × W bit search data stored in the search data storage circuit 5, and Is calculated by a method described later. The distance calculation circuits DP ₂₁ to DP _2W search for the M × W bit reference data 2 stored in the reference data storage circuits SC ₂₁ to SC _2W and the M × W bit search stored in the search data storage circuit 5. The distance from the data is calculated by the method described later. In the same manner, the distance calculation circuits DP _R1 to DP _RW perform the M × W bit reference data R stored in the reference data storage circuits SC _R1 to SC _RW and the M × W stored in the search data storage circuit 5. The distance from the W-bit search data is calculated by a method described later. The distance calculation circuits DP ₁₁ to DP _1W , the distance calculation circuits DP ₂₁ to DP _2W ,..., And the distance calculation circuits DP _R1 to DP _RW calculate the distance between the reference data and the search data in parallel. .

The distance calculation circuits DP ₁₁ to DP _1W output the distance between the reference data 1 and the search data to the distance / clock number conversion circuit DC ₁ as a distance signal of M × W bits, and the distance calculation circuits DP ₂₁ to DP _2W. is the distance between the reference data 2 and the search data is output as the distance signal of the M × W bits to distance / clock number conversion circuit DC _2, in the same manner, the distance calculation circuit DP R1 _~ DP _RW are reference data the distance between R and the search data is output to the distance / clock number conversion circuit DC _R as a distance signal M × W bits.

Each of the distance calculation circuits DP ₁₁ to DP _1W calculates the distance between the reference data 1 and the search data using the following equation.

In Expression (1), D _rj (r = 1 to R, j = 1 to W) is the distance between the reference data and the search data, In _j is the search data, and Re _rj is the reference data. is there. Each of the data In _j and Re _rj consists of M bits.

As described above, the distance calculation circuits DP ₁₁ to DP _1W calculate the distance between the M × W bit reference data 1 and the M × W bit search data in M bits, and each has a bit length of M bits. The W distance signals D _1j are output to the distance / clock number conversion circuit DC ₁ .

The distance calculation circuits DP ₂₁ to DP _2W ,... And the distance calculation circuits DP _R1 to DP _RW also calculate the distances between the reference data 2 to R and the search data using the equation (1). Further, the distance calculation circuits DP ₂₁ to DP _2W ,... And the distance calculation circuits DP _R1 to DP _RW also _receive W distance signals D _2j to D _Rj each having a bit length of M bits, respectively. Output to the conversion circuits DC ₂ to DC _R.

The distance / clock number conversion circuit DC ₁ receives W distance signals D _1j from the distance calculation circuits DP ₁₁ to DP _1W, and the number of clock signals CLK that matches the sum of the received W distance signals D _1j. counted by a method described later CN_total1, and outputs a timing signal _{C 1} indicating a timing of counting the number of clocks CN_total1 to Winner detector 20. The timing at which the clock number CN_total1 is counted is the coincidence timing that matches the distance between the search data and the reference data 1.

Further, the distance / clock number conversion circuit DC ₂ receives W distance signals D _2j from the distance calculation circuits DP ₂₁ to DP _2W , and receives the clock signal CLK that matches the sum of the received W distance signals D _2j . It was counted by the method described below a clock number CN_total2, and outputs a timing signal _{C 2} which shows the timing of counting the number of clocks CN_total2 to Winner detector 20. The timing at which the number of clocks CN_total2 is counted is the coincidence timing at which the search data and the reference data 2 coincide.

Similarly, the distance / clock number conversion circuit DC _R receives W distance signals D _Rj from the distance calculation circuits DP _R1 to DP _RW and matches the sum of the received W distance signals D _Rj. It was counted by the method described below the number of clocks CN_totalR of the clock signal CLK, and outputs a timing signal _{C R} indicating the timing of counting the number of clocks CN_totalR to Winner detector 20. The timing at which the clock number CN_totalR is counted is the coincidence timing at which the search data and the reference data R coincide.

The row decoder 2 designates an address in the row direction of the memory unit 1. The column decoder 3 designates an address in the column direction of the memory unit 1. Read / write circuit 4 writes reference data to reference data storage circuits SC ₁₁ to SC _1W , SC ₂₁ to SC _2W ,..., SC _R1 to SC _RW designated by row decoder 2 and column decoder 3. The search data is written into the search data storage circuit 5.

The search data storage circuit 5 stores the search data (M × W bit data) written by the read / write circuit 4.

Winner detector 20 receives from the timing signal _C 1 ~ _{C R,} respectively distance / clock number conversion circuits _DC 1 ~ DC _R, among the received timing signals _C 1 ~ _{C R,} the matching timing chronological order k (k Are integers satisfying 1 ≦ k <R), and the detected k timing signals are output as match signals M ₁ to M _k indicating the similarity between the search data and the reference data.

Figure 2 is a schematic diagram showing the structure of a distance / clock number converting circuit DC ₁ shown in FIG. Referring to FIG. 2, the distance / clock number converting circuit DC ₁ includes an amplifier 21 ~ 2W, a counter coincidence detection circuit 31 ~ 3W.

The amplifier 21 receives a clock signal CLK from a clock generation circuit (not shown) built in the associative memory 100, amplifies the received clock signal CLK, and outputs it to the amplifier 22 and the counter coincidence detection circuit 31.

The amplifier 22 receives the clock signal CLK from the amplifier 21 and outputs the received clock signal CLK to the amplifier 23 (not shown) and the counter coincidence detection circuit 32.

Similarly, the amplifier 2W receives the clock signal CLK from the amplifier 2W-1 (not shown) and outputs the received clock signal CLK to the counter coincidence detection circuit 3W.

Counter coincidence detection circuits 31 to 3W are provided corresponding to distance calculation circuits DP ₁₁ to DP _1W , respectively. The counter match detection circuits 31 to 3W are connected in series.

Counter coincidence detection circuit 31 receives a clock signal CLK from the amplifier 21, receiving the search start signal SB from the control circuit for the associative memory 100 (not shown), the distance calculation circuit distance signal from the DP ₁₁ has a bit length of M bits subject to D _11. Counter match detection circuit 31, when the search start signal SB is switched from L (logical low) level to H (logical high) level, when counted in ascending order in synchronization with the counter value to the clock signal CLK, the distance signal D ₁₁ The number of clocks of the clock signal CLK when a counter value that matches is obtained is counted. Then, the counter coincidence detection circuit 31 outputs a coincidence signal MTH1 indicating the timing of counting the number of clocks to the counter coincidence detection circuit 32 in synchronization with the clock signal CLK. The counter coincidence detection circuit 31 stops its operation when outputting the coincidence signal MTH1.

Counter coincidence detection circuit 32 receives a clock signal CLK from the amplifier 22 receives the coincidence signal MTH1 from the counter coincidence detection circuit 31 receives the distance signal _{D 12} having a bit length of M bits from the distance calculation circuit _{DP 12.} The counter coincidence detection circuit 32 stops operating until it receives the coincidence signal MTH1 from the counter coincidence detection circuit 31. Counter coincidence detection circuit 32 is driven to undergo a coincidence signal MTH1 from the counter coincidence detection circuit 31, when the count in ascending order in synchronization with the counter value to the clock signal CLK, the counter value matches the distance signal D ₁₂ is obtained The number of clocks of the clock signal CLK is counted. Then, the counter coincidence detection circuit 32 outputs a coincidence signal MTH2 indicating the timing of counting the number of clocks to the counter coincidence detection circuit 33 (not shown) in synchronization with the clock signal CLK. The counter coincidence detection circuit 32 stops its operation when outputting the coincidence signal MTH2.

Similarly, counter coincidence detection circuit 3W receives clock signal CLK from amplifier 2W, receives coincidence signal MTHW-1 from counter coincidence detection circuit 3W-1, and sets a bit length of M bits from distance calculation circuit DP _1W. It has a distance signal D _1W . The counter coincidence detection circuit 3W stops operating until it receives a coincidence signal MTHW-1 from the counter coincidence detection circuit 3W-1. Counter coincidence detection circuit 3W is driven from the counter coincidence detecting circuit 3W-1 and receives a match signal MTHW-1, when the count in ascending order in synchronization with the counter value of the clock signal CLK, and coincides with the distance signal D _1W The number of clocks of the clock signal CLK when the counter value is obtained is counted. The counter coincidence detection circuit 3W outputs a coincidence signal MTHW indicating a timing of counting the number of clocks in synchronization with the clock signal CLK as a timing signal _{C 1} to Winner detector 20. Counter match detection circuit 3W, when a timing signal C _1, to stop the operation.

Also each of the distance / clock number conversion circuits DC 2 _~ Distance / clock number conversion circuit DC _R shown in FIG. 1, the same configuration as the distance / clock number conversion circuit DC ₁ shown in FIG.

FIG. 3 is a schematic diagram showing the configuration of the counter coincidence detection circuit 31 shown in FIG. Referring to FIG. 3, counter match detection circuit 31 includes a counter 311 and a match detection circuit 312.

The counter 311 receives a clock signal CLK from the amplifier 21 and a reset signal RST from a control circuit (not shown) of the associative memory 100. Upon receiving the reset signal RST, the counter 311 resets the counter value, and counts the M-bit bit value in ascending order in synchronization with the clock signal CLK. Then, the counter 311 sequentially outputs the counted counter value CV ₁₁ to the coincidence detection circuit 312 in synchronization with the clock signal CLK.

Coincidence detection circuit 312 receives a clock signal CLK from the amplifier 21, receiving the search start signal SB from the control circuit for the associative memory 100 (not shown), sequentially receives the counter value _{CV 11} from the counter 311, the distance calculation circuit _{DP 11} receiving a distance signal _{D 11} from.

Coincidence detection circuit 312, the search start signal SB when switched from L level to H level, and counts the number of clocks of the clock signal CLK when the counter value CV ₁₁ matching the distance signal D ₁₁ is obtained. Then, the coincidence detection circuit 312 outputs a coincidence signal MTH1 indicating the timing of counting the number of clocks to the counter coincidence detection circuit 32.

When the coincidence detection circuit 312 outputs the coincidence signal MTH1, the operation is stopped.

Note that each of the counter coincidence detection circuits 32 to 3W shown in FIG. 2 has the same configuration as the counter coincidence detection circuit 31 shown in FIG. In this case, the coincidence detection circuit 312 of the counter coincidence detection circuits 32 to 3W stops operation until it receives the coincidence signals MTH1 to MTHW-1 from the coincidence detection circuit 312 of the counter coincidence detection circuits 31 to 3W-1, respectively. When the signals MTH1 to MTHW-1 are received, they are driven and start operating.

FIG. 4 is a diagram for explaining the operation of the counter coincidence detection circuit 31 shown in FIG. In FIG. 4, the operation of the counter coincidence detection circuit 31 will be described by taking as an example the case where each of the counter value CV ₁₁ and the distance signal D ₁₁ is 3 bits. The distance signal _{D 11} is assumed to consist of "011".

Referring to FIG. 4, when counter 311 of counter coincidence detection circuit 31 receives reset signal RST from the control circuit of associative memory 100, counter 311 resets the number of counts, and period T1, T2, T3, in which clock signal CLK continues. In synchronization with T4, the bit values of “000”, “001”, “010”, “011” are sequentially counted, and the counted “000”, “001”, “010”, “011” are counted. The counter value CV ₁₁ is sequentially output to the coincidence detection circuit 312.

The coincidence detection circuit 312 receives the distance signal _{D 11} from the distance computing circuit _{DP 11} "011", when receiving a counter value _{CV 11} for synchronization with the cycle T1 of the clock signal CLK "000" from the counter 311, At timing t1, the number of clocks “0” is counted, and it is detected that the counter value CV ₁₁ of “000” does not match the distance signal D ₁₁ of “011” at the number of clocks “0”.

When the coincidence detection circuit 312 receives the counter value CV ₁₁ of “001” from the counter 311 in synchronization with the next cycle T2 of the cycle T1 of the clock signal CLK, it counts the number of clocks of “1” at the timing t2. , It is detected that the counter value CV ₁₁ of “001” does not coincide with the distance signal D ₁₁ of “011” in the number of clocks of “1”.

Moreover, the coincidence detection circuit 312 receives a counter value _{CV 11} for synchronization with the next cycle T3 of the period T2 of the clock signal CLK "010" from the counter 311 counts the number of clocks of the "2" at the timing t3 , It is detected that the counter value CV ₁₁ of “010” does not coincide with the distance signal D ₁₁ of “011” in the number of clocks “2”.

Further, when the coincidence detection circuit 312 receives the counter value CV ₁₁ of “011” from the counter 311 in synchronization with the period T4 next to the period T3 of the clock signal CLK, it counts the number of clocks of “3” at the timing t4. , It is detected that the counter value CV ₁₁ of “011” matches the distance signal D ₁₁ of “011” in the number of clocks “3”. The coincidence detection circuit 312, a timing t4 counted clock number (= "3") of the clock signal CLK when the counter value _{CV 11} are obtained "011" matches the distance signal _{D 11} of "011" The coincidence signal MTH1 is output to the counter coincidence detection circuit 32 and the control circuit of the associative memory 100. Thereafter, the coincidence detection circuit 312 stops the operation so that the counter value “011” is held at the clock numbers “4” and “5” in FIG. 4.

In this case, the counter coincidence detection circuit 31 counts from the timing t1 until it counts the number of clocks “0” at the timing t1 and outputs the coincidence signal MTH1 after counting the number of clocks “3” at the timing t4. It takes time to t4 (= t4-t1).

In each of the counter match detection circuits 32 to 3W-1 shown in FIG. 2, the counter 311 stops operating until it receives a reset signal RST from the control circuit of the associative memory 100, and the reset signal from the control circuit of the associative memory 100. When RST is received, the bit values “000”, “001”, “010”, “011”,... Are sequentially counted, and the counted “000”, “001”, “010”, “011” are counted. ,... (= Counter values CV ₁₂ to CV _1W−1 ) are sequentially output to the coincidence detection circuit 312.

The match detection circuits 312 of the counter match detection circuits 32 to 3W-1 stop operating until they receive the match signals MTH1 to MTHW-2 from the match detection circuits 312 of the counter match detection circuits 31 to 3W-2, respectively. When MTH1 to MTHW-2 are received, the number of clocks of the clock signal CLK when the counter values CV ₁₂ to CV _1W-1 coincide with the distance signals D ₁₂ to D _1W-1 , respectively, is counted. Match signals MTH2 to MTHW-1 indicating timing are output to the counter match detection circuits 33 to 3W and the control circuit of the content addressable memory 100, respectively. Then, the coincidence detection circuit 312 of the counter coincidence detection circuits 32 to 3W-1 stops its operation.

The counter 311 of the counter coincidence detection circuit 3W stops operating until it receives a reset signal RST from the control circuit of the associative memory 100. When the reset signal RST is received from the control circuit of the associative memory 100, “000”, “001” , “010”, “011”,... Are sequentially counted, and the counter values CV _1W of “000”, “001”, “010”, “011” _,. The data is sequentially output to the detection circuit 312.

The coincidence detection circuit 312 of the counter coincidence detection circuit 3W stops operating until it receives the coincidence signal MTHW-1 from the coincidence detection circuit 312 of the counter coincidence detection circuit 3W-1, and when receiving the coincidence signal MTHW-1, _The number of clocks of the clock signal CLK when _1W coincides with the distance signal D _1W is counted, and timing signals (respective timing signals C ₁ to C _R ) indicating the timing at which the number of clocks is counted are used as the Winner detector 20 and the associative memory. To 100 control circuits. Then, the coincidence detection circuit 312 of the counter coincidence detection circuit 3W stops its operation.

When receiving the coincidence signals MTH1 to MTHW-1 from the counter coincidence detection circuits 31 to 3W-1, the control circuit of the associative memory 100 outputs the reset signal RST to the counter coincidence detection circuits 32 to 3W, respectively. The control circuit of the associative memory 100 receives a timing signal _{C 1} from the counter coincidence detection circuit 3W, outputs a reset signal RST to the counter coincidence detection circuits 31 ~ 3W.

Figure 5 is a diagram for explaining the operation of the distance / clock number converting circuit DC ₁ shown in FIG. In FIG. 5, the distance / clock number converting circuit DC ₁ is an illustrating the operation of the distance / clock number converting circuit DC ₁ as an example the case of two counter match detection circuits 31 and 32. The distance signal _{D 11} is composed of "3", the distance signal _{D 12} is assumed to consist of "5".

Referring to FIG. 5, distance calculation circuit DP ₁₁ calculates the distance between search data and reference data SC ₁₁ according to equation (1), and outputs distance signal D ₁₁ (= “011”) to counter match detection circuit 31. Output. The distance calculation circuit DP ₁₂ calculates the distance between the search data and the reference data SC ₁₂ according to the equation (1), and outputs a distance signal D ₁₂ (= “101”) to the counter coincidence detection circuit 32.

When the counter coincidence detection circuit 31 receives the distance signal D ₁₁ (= “011”) from the distance calculation circuit DP ₁₁ and the reset signal RST and the search start signal SB from the control circuit of the associative memory 100, A coincidence signal indicating the timing of counting the number of clocks of the clock signal CLK (= “3”) when the counter value CV ₁₁ coincides with the distance signal D ₁₁ (= “011”) and counting the number of clocks of “3”. MTH1 is output to the counter coincidence detection circuit 32 and the associative memory 100 control circuit. Then, the counter match detection circuit 31 stops its operation.

The counter coincidence detection circuit 32 receives the distance signal D ₁₂ (= “101”) from the distance calculation circuit DP ₁₂ and the reset signal RST from the control circuit of the associative memory 100. When the counter coincidence detection circuit 32 receives the coincidence signal MTH1 from the counter coincidence detection circuit 31 at the timing when the number of clocks of “3” is obtained, the counter coincidence detection circuit 32 starts the operation and generates the distance signal D ₁₂ (= “101”). The number of clocks (= “5”) of the clock signal CLK when the matching counter value CV ₁₂ (= “101”) is obtained is counted, and the counter value CV ₁₂ (= It is detected that “101”) matches the distance signal D ₁₂ (= “101”).

Then, the counter coincidence detection circuit 32 outputs a timing signal C ₁ indicating the timing at which the number of clocks of “5” is counted to the Winner detector 20 and the associative memory 100 control circuit. Then, the counter coincidence detection circuit 32 stops its operation.

As described above, the counter coincidence detection circuit 32 counts the number of clocks “5” at the timing of counting the number of clocks “5” after the counter coincidence detection circuit 31 completes the counting of the number of clocks “3”. a timing signal C ₁ indicating the timing. Therefore, the counter coincidence detection circuit 32 is “5” at the timing when the time from the count start of the clock number by the counter coincidence detection circuit 31 to the counting of the number of clocks “3” + “5” = “8” has elapsed. a timing signal C ₁ indicating a timing of counting the number of clocks. That is, the counter coincidence detection circuit 32 determines the number of clocks of the clock signal CLK when a counter value that coincides with the distance signal “8” that is the sum of the distance signal “3” and the distance signal “5” is obtained. A timing signal C ₁ indicating the timing at which the number of clocks is counted is output.

The total number of clocks “8” counted by the two counter coincidence detection circuits 31 and 32 is “3” that the counter coincidence detection circuit 31 counts and “5” that the counter coincidence detection circuit 32 counts. This is the sum of the number of clocks. This is counter coincidence detection circuit 32, clock number "3" in the counter coincidence detection circuit 31 is matched from the counter coincidence detection circuit 31 by the count timing when receiving a coincidence signal MTH1, the distance signal D ₁₂ counter It is also apparent from starting the operation of counting the number of clocks when the value CV ₁₂ is obtained (see FIG. 5).

As a result, the fact that the two counter coincidence detection circuits 31 and 32 collectively count the number of clocks “8” means that the counter value coincides with the sum (= “8”) of the distance “3” and the distance “5”. Is equivalent to counting the number of clocks of the clock signal CLK.

The distance / clock number conversion circuit DC ₁ generally receives _W distance signals D ₁₁ to D _1W . Each of the W distance signals D ₁₁ to D _1W has a bit length of M bits. Therefore, the distance / clock number converting circuit DC ₁ receives the distance signal _D 11 _D 12 ··· _{D 1W} having a bit length of M × W bits.

In the distance / clock number conversion circuit DC ₁ , the counter coincidence detection circuits 31 to 3 _W respectively receive the clock signals CLK when the counter values CV ₁₁ to CV _1W respectively corresponding to the distance signals D ₁₁ to D _1W are obtained. The number of clocks CN1 to CNW is counted. The counter coincidence detection circuits 32 to 3W receive the coincidence signals MTH2 to MTHW-1 from the counter coincidence detection circuits 31 to 3W-1, respectively, and then the counter values CV ₁₂ coincide with the distance signals D ₁₂ to D _1W , respectively. The count of the clock numbers CN2 to CNW of the clock signal CLK when .about.CV _1W is obtained is started.

As a result, the number of clocks CN_total distance / clock number conversion circuit DC ₁ counts is equal to the sum of the number of clocks CN1 ~ CNW. Then, clock numbers CN1 to CNW represent distance signals D ₁₁ to D _1W , respectively, and clock number CN_total represents the sum of distance signals D ₁₁ to D _1W .

On the other hand, the Manhattan distance n _M is represented by the following equation.

| In _j -Re _j | on the right side of Expression (2) is the distance between the search data and the reference data in one row (represented by r) in | In _j -Re _rj | on the right side of Expression (1). | In _j −Re _j |

Accordingly, the Manhattan distance n _M equals the distance calculated by equation (1) to those obtained by adding the W number of distance.

Then, outputting the timing signal C ₁ indicating the timing at which the distance / clock number conversion circuit DC ₁ counts the clock number CN_total searches the reference data similar to the search data by the Manhattan distance n _M and is similar to the search data. This is equivalent to outputting a Winner signal indicating that reference data to be detected is detected.

Incidentally, each of the distance / clock number conversion circuits _DC 2 ~ DC _R also by the distance / operation and the same operation of the clock number conversion circuit DC ₁ described in FIG. 5, respectively, and outputs a timing signal _C 2 ~ _{C R.}

FIG. 6 is a diagram for explaining the operation of the Winner detector 20 shown in FIG. Referring to FIG. 6, the distance / clock number conversion circuits _DC 1 ~ DC _R, respectively, and output to the Winner detector 20 in synchronization with timing signals _C 1 ~ _{C R} to the clock signal CLK.

Winner detector 20 receives a timing signal _C 1 ~ _{C R,} detects the rising timing _t 1 ~ _{t R} of the received timing signals _C 1 ~ _{C R.} Then, the Winner detector 20 detects the k timing signals C ′ ₁ to C ′ _k in order from the earliest rise timing t ₁ to t _R. Then, the Winner detector 20 outputs the timing signals C ′ ₁ to C ′ _k as the match signals M ₁ to M _k .

For example, when detecting the two match signals _M 1, _{M 2,} Winner detector 20, of the timing signals _C 1 ~ _{C R,} detects the two timing signals _C 1, _{C 3} to rise timing is earlier order The detected timing signals C ₁ and C ₃ are output as match signals M ₁ and M ₂ .

When detecting _k timing signals C ′ ₁ to C ′ _k other than k = 2, the Winner detector 20 similarly detects k timing signals C ′ ₁ to C ′ _k. The detected k timing signals C ′ ₁ to C ′ _k are output as match signals M ₁ to M _k .

If a k = 1, Winner detector 20 outputs a timing signal corresponding to the reference data most similar to the search data (any timing signals _C 1 ~ _{C R)} as a match signal _{M 1.}

When k ≠ 1, the Winner detector 20 outputs k timing signals C ′ ₁ to C ′ _k corresponding to k reference data similar to the search data as match signals M ₁ to M _k. To do. In this case, in the k timing signals C ′ ₁ to C ′ _k , the k rising timings differ from each other by at least one cycle of the clock signal CLK. ' ₁ to C' _k can be detected accurately. That is, the associative memory 100 can accurately search k reference data similar to the search data.

The distance / operation of the clock number conversion circuits _DC 1 ~ DC _R, since is performed in synchronization with the clock signal CLK, by increasing the frequency of the clock signal CLK, the possible operation of the associative memory 100 at high speed.

Therefore, the associative memory 100 can perform the similarity search accurately and at high speed even when the Manhattan distance is used.

FIG. 7 is a schematic diagram showing a preferred configuration of the counter 311 shown in FIG. In the embodiment of the present invention, the counter 311 preferably comprises a counter 311A shown in FIG.

Referring to FIG. 7, counter 311A includes frequency dividers 311-1 to 311-M. The frequency divider 311-1 is provided corresponding to the least significant bit of the M-bit distance signal (= distance signals D ₁₁ to D _1W , D ₂₁ to D _2W ,..., D _R1 to D _RW ). . The frequency divider 311-2 is provided corresponding to the second bit of the M-bit distance signal (= distance signals D ₁₁ to D _1W , D ₂₁ to D _2W ,..., D _R1 to D _RW ). It is done. Hereinafter, similarly, the frequency divider 311 -M is the most significant bit of the M-bit distance signal (= distance signals D ₁₁ to D _1W , D ₂₁ to D _2W ,..., D _R1 to D _RW ). It is provided corresponding to.

Divider 311-1, a clock signal CLK to ^{2 0} times division and outputs a frequency division signal DV ₁ that the dividing into coincidence detection circuit 312. Divider 311-2 is a clock signal CLK and ^{2 one} time division and outputs a frequency division signal DV ₂ that the dividing into coincidence detection circuit 312. Similarly, the frequency divider 311 -M divides the clock signal CLK by 2 ^M−1 times, and outputs the divided frequency signal DV _M to the coincidence detection circuit 312.

FIG. 8 is a diagram for explaining the operation of the counter 311A shown in FIG. In FIG. 8, the operation of the counter 311A will be described by taking as an example the case where the counter 311A includes four frequency dividers 311-1 to 311-4.

Referring to FIG. 8, the frequency divider 311-1, a clock signal CLK to ^{2 0} times division and outputs a frequency division signal DV ₁ that the dividing into coincidence detection circuit 312. Divider 311-2 is a clock signal CLK and ^{2 one} time division and outputs a frequency division signal DV ₂ that the dividing into coincidence detection circuit 312. Divider 311-3 is a clock signal CLK ^{2 2} times by frequency, and outputs a divided signal DV ₃ that the division into coincidence detection circuit 312. Divider 311-4 is a clock signal CLK to ^{2 3} times division and outputs a frequency division signal DV ₄ that the dividing into coincidence detection circuit 312.

As a result, the four frequency dividers 311-1 to 311-4 first output the counter value “0000”, the second output the counter value “0001”, the third “ The counter value “0010” is output, and thereafter, similarly, the counter value “1110” is output 15th, and the counter value “1111” is output last.

Even when the counter 311A outputs a counter value other than 4 bits, it is constituted by M frequency dividers 311-1 to 311-M, and the M frequency dividers 311-1 to 311-M are configured as shown in FIG. in the same manner as the embodiment illustrated in, respectively, the clock signal CLK ^{2 0} times, ^{2 once, 2 twice,} · · ^{·, 2 M-1} times by frequency, the frequency-divided divided signal _DV 1 ~ DV _M Is output. As a result, the counter 311A is a counter value of M bits _{"0 1 0 2 0 3 ···} 0 M", "0 1 0 2 0 3 ··· 1 M", ···, "1 1 1 2 Output in the order of 1 ₃ ... 1 _M ″.

Accordingly, among the frequency dividers 311-1 to 311-M, the bit value of the m-th (m is an integer satisfying 1 ≦ m ≦ M) in the direction from the least significant bit to the most significant bit of the M-bit counter value. , Outputs a signal obtained by dividing the clock signal CLK by 2 ^m−1 times.

Thus, by configuring the counter 311A with the frequency dividers 311-1 to 311-M, the circuit size can be reduced and the power consumption can be reduced as compared with a normal counter.

Even when the counter 311 of the counter coincidence detection circuits 31 to 3W is composed of the counter 311A shown in FIG. 7, the distance / clock number conversion circuits DC ₁ to DC _R are each provided with M × W bit bits by the above-described method. distance signal _D 11 _~ D 1W having a _{length, D 21 ~ D 2W, ···} , D R1 ~ D timing signals _C 1 ~ shows the timing obtained by counting the matching number of clocks CN_total1 ~ CN_totalR respectively to the sum of the _{RW C R} Is output to the Winner detector 20.

As described above, each range / clock number conversion circuits DC 1 _~ DC _R, as shown in FIG. 2, a W number of counter match detecting circuits 31 ~ 3W connected in series.

When W = 2, each of the distance / clock number conversion circuits DC ₁ to DC _R includes counter coincidence detection circuits 31 and 32. In this case, the distance calculation circuits DP ₁₁ to DP _1W are made up of distance calculation circuits DP ₁₁ and DP ₁₂ , and the distance signals D ₁₁ to D _1W are made up of distance signals D ₁₁ and D ₁₂ .

The counter coincidence detection circuit 31, the distance signal D _11, provided in correspondence with one of the distance signal of the edge first distance signal D ₁₁ when the sequence D ₁₂ in a line, the first distance signal D upon receiving the ₁₁ from the distance calculation circuit DP _11, when counted in ascending order in synchronization with the counter value to the clock signal CLK, the clock number when the counter value matches the first distance signal D ₁₁ having received the obtained CN1 is counted, and a coincidence signal MTH1 indicating the timing when the number of clocks CN1 is counted is output.

The counter coincidence detection circuit 32, the distance signal _{D 11, D 12} and W th from one end when arranged in a line W th the distance signal (= second) (= 2nd) the distance signal _{D 12} of It provided corresponding to undergo W th while being driven to undergo coincidence signal MTH1 from the counter coincidence detection circuit 31 the distance signal _{D 12} (= the second) from the distance calculating circuit _{DP 12,} the clock counter value signal CLK when counted in ascending order in synchronization with the timing of counting the number of clocks CN2 when the counter value matches the distance signal D ₁₂ of the received W th (= second) was obtained by counting the number of clocks CN2 a timing signal _{C 1} indicating the output to Winner detector 20.

In this case, the counter coincidence detection circuit 31 constitutes a “first counter coincidence detection circuit”, and the counter coincidence detection circuit 32 constitutes a “second counter coincidence detection circuit”.

When W = 3 or more, each of the distance / clock number conversion circuits DC ₁ to DC _R includes counter coincidence detection circuits 31 to 3W.

The counter coincidence detection circuit 31 is provided corresponding to the first distance signal D ₁₁ that is the distance signal at one end when the distance signals D ₁₁ to D _1W are arranged in a line. upon receiving the ₁₁ from the distance calculation circuit DP _11, when counted in ascending order in synchronization with the counter value to the clock signal CLK, the clock number when the counter value matches the first distance signal D ₁₁ having received the obtained CN1 is counted, and a coincidence signal MTH1 indicating the timing when the number of clocks CN1 is counted is output.

The counter coincidence detection circuits 32 ~ 3W-1 is corresponding to the second distance signal W-2 pieces of distance signals _D 12 _{~ D 1W-1} from _{D 12} to W-1 th distance signal _{D 1W-1} Provided. Each of the counter coincidence detection circuits 32 to 3W-1 includes a counter coincidence detection circuit 31 or a counter provided corresponding to the w-1 (w is an integer satisfying 2 ≦ w ≦ W−1) -th distance signal. A counter value corresponding to the first or wth distance signal from the counter match detection circuits 31 to 3W-2 provided corresponding to the first or w-1th distance signal from the coincidence detection circuits 32 to 3W-2 is obtained. while being driven and receives match signal MTH1 ~ MTH3W-2 showing a timing obtained by counting the number of clocks of the clock signal CLK when the obtained w th distance signal (= distance signal either _D 12 _{~ D 1W-1)} receiving one of the counter value when the count in ascending order in synchronization with the clock signal CLK, the w-th distance signal (= distance signal either _{D 12 ~} D _1W-1) To count the number of clocks CN3 when the counter value is obtained, the coincidence signal (= either match signals MTH2 ~ MTHW-1) outputs the indicating timing for counting the number of clocks CN3.

Furthermore, the counter coincidence detection circuit 3W is provided corresponding to the W-th distance signal D _1W, consistent from the counter coincidence detecting circuit 3W-1 provided corresponding to the W-1 th distance signal signal MTHW-1 receiving the W th distance signal D _1W with driven to undergo, when receiving a coincidence signal MTH3W-1 from the counter coincidence detecting circuit 3W-1, when the count in ascending order in synchronization with the counter value of the clock signal CLK counts the number of clocks CN4 when the counter value matches the W th distance signal _{D 1W} is obtained, a timing signal _{C 1} indicating a timing of counting the number of clocks CN4 to Winner detector 20.

In this case, the counter coincidence detection circuit 31 constitutes a “first counter coincidence detection circuit”, and the counter coincidence detection circuits 32 to 3W-1 constitute “W-2 third counter coincidence detection circuits”. The counter coincidence detection circuit 3W constitutes a “fourth counter coincidence detection circuit”.

FIG. 9 is a schematic diagram showing another configuration of distance / clock number conversion circuits DC ₁ to DC _R shown in FIG.

In the embodiment of the present invention, each of the distance / clock number conversion circuits DC 1 _~ DC _R may consist Distance / clock number conversion circuit DC _'1 shown in FIG. In this case, W = 2 ⁱ (i is an integer of 2 or more).

Referring to FIG. 9, distance / clock number conversion circuit DC ′ ₁ includes amplifiers 41 to 4L and counter match detection circuits 51 to 5L. Here, L = W / s (s is an integer satisfying 2 ^x equal to or less than W, and x is a positive integer).

The amplifier 41 receives a clock signal CLK from a clock generation circuit (not shown) built in the associative memory 100, amplifies the received clock signal CLK, and outputs it to the amplifier 42 and the counter coincidence detection circuit 51.

The amplifier 42 receives the clock signal CLK from the amplifier 41, amplifies the received clock signal CLK, and outputs the amplified clock signal CLK to the amplifier 43 (not shown) and the counter coincidence detection circuit 52.

Thereafter, similarly, the amplifier 4L receives the clock signal CLK from the amplifier 4L-1 (not shown), amplifies the received clock signal CLK, and outputs it to the counter coincidence detection circuit 5L.

The counter coincidence detection circuits 51, 52,..., 5L have s distance calculation circuits DP ₁₁ , DP _{1 (1 + L)} ,..., DP _{1 (1+ (u−1) L)} s, respectively. Distance calculation circuits DP ₁₂ , DP _{1 (2 + L)} ,..., DP _{1 (2+ (u−1) L)} ,..., S distance calculation circuits DP _1L , DP _{1 (L + L)} ,. .., provided corresponding to DP _{1 (L + (u−1) L)} . U is 1, 2, 3,..., S.

The counter coincidence detection circuits 51 to 5L are connected in series. Each of the counter coincidence detection circuits 51 to 5L has the same configuration as the counter coincidence detection circuit 31 shown in FIG. In this case, each of the counter match detection circuits 51 to 5L includes the counter 311 shown in FIG. 3 or the counter 311A shown in FIG.

The counter coincidence detection circuit 51 receives the clock signal CLK from the amplifier 41, the search start signal SB from the control circuit (not shown) of the associative memory 100, and the distance calculation circuits DP ₁₁ , DP _{1 (1 + L)} ,. , DP _{1 (1+ (u−1) L)} receive distance signals D ₁₁ , D _{1 (1 + L)} ,..., D _{1 (1+ (u−1) L)} , respectively.

The counter coincidence detection circuit 51 receives the distance signals D ₁₁ , D _{1 (1 + L)} ,..., D _{1 (1+ (u−1) L)} , and when the search start signal SB switches from the L level to the H level, The clock of the clock signal CLK when the counter value CV ₁₁ that matches the sum of the distance signals D ₁₁ , D _{1 (1 + L)} ,..., D _{1 (1+ (u−1) L)} is obtained by the method described above. The number CN_1 is counted. Then, the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing of counting the clock number CN_1 to the counter coincidence detection circuit 52 in synchronization with the clock signal CLK. Thereafter, the counter coincidence detection circuit 51 stops its operation.

The counter coincidence detection circuit 52 receives the clock signal CLK from the amplifier 42, the coincidence signal MTH1 from the counter coincidence detection circuit 51, and the distance calculation circuits DP ₁₂ , DP _{1 (2 + L)} ,..., DP _{1 (2+ (U−1) L)} receives distance signals D ₁₂ , D _{1 (2 + L)} ,..., D _{1 (2+ (u−1) L)} .

When the counter coincidence detection circuit 52 receives the distance signals D ₁₂ , D _{1 (2 + L)} ,..., D _{1 (2+ (u−1) L)} and receives the coincidence signal MTH1, the counter signal is detected by the method described above. _{D 12, D 1 (2 +} L), ···, counts the number of clocks CN_2 of the clock signal CLK when the counter value _{CV 12} that matches the sum of _{D 1 (2+ (u-1} ) L) is obtained. Then, the counter coincidence detection circuit 52 outputs a coincidence signal MTH2 indicating the timing of counting the clock number CN_2 to the counter coincidence detection circuit 53 in synchronization with the clock signal CLK. Thereafter, the counter match detection circuit 52 stops its operation.

Similarly, the counter coincidence detection circuit 5L receives the clock signal CLK from the amplifier 4L, receives the coincidence signal MTHL-1 from the counter coincidence detection circuit 5L-1, and receives the distance calculation circuits DP _1L , DP _{1 (L + L)} , ..., DP _{1 (L + (u-1) L)} receives distance signals _D1L , D1 _{(L + L)} , ..., D1 _{(L + (u-1) L)} , respectively.

When the counter coincidence detection circuit 5L receives the distance signals D _1L , D _{1 (L + L)} ,..., D _{1 (L + (u−1) L)} and receives the coincidence signal MTHL−1, the above-described method is performed. Counts the number of clocks CN_L of the clock signal CLK when a counter value CV _1L that matches the sum of the distance signals D _1L , D _{1 (L + L)} ,..., D _{1 (L + (u−1) L)} is obtained. . The counter coincidence detection circuit 5L outputs to Winner detector 20 a timing signal _{C 1} indicating a timing of counting the number of clocks CN_L synchronism with the clock signal CLK. Thereafter, the counter coincidence detection circuit 5L stops its operation.

The distance signals D ₁₁ , D _{1 (1 + L)} ,..., D _{1 (1+ (u−1) L)} , D ₁₂ , D _{1 (2 + L)} , ..., D _{1 (2+ (u−1) ) L)} ,..., D _1L , D _{1 (L + L) ,.}

Accordingly, each of the distance / clock number conversion circuits DC ₁ to DC _R (= distance / clock number conversion circuit DC ′ ₁ ) is provided corresponding to L (= W / s) distance signals, and each of them is M based on the W number of distance signal having a bit length of the bit comprise a L (= W / s) number of the counter match detection circuit for outputting a (any timing signals C _{1 ~} C _R) timing signals, L ( = W / s) counter coincidence detection circuits, when receiving s pairs of distance signals each consisting of L (= W / s) distance signals, count the counter values in ascending order in synchronization with the clock signal CLK. The number of clocks of the clock signal CLK when a counter value matching the sum of the W distance signals included in the received s sets of distance signals is obtained, and the timing at which the number of clocks is counted is counted. Taimi showing And it outputs a ring signal (any timing signals _C 1 ~ _{C R)} to the Winner detector 20.

Each of the counter coincidence detection circuits 51 to 5L-1 calculates the number of clocks of the clock signal CLK (= any of the number of clocks CN_1 to CN_L-1) when a counter value matching the sum of s distance signals is obtained. A coincidence signal (= any of coincidence signals MTH1 to MTHL-1) indicating the counted timing is output, and the counter coincidence detection circuit 5L is a clock signal when a counter value that coincides with the sum of the s distance signals is obtained. outputs a timing signal indicating a timing of counting the number of clocks CN_L of CLK (any timing signals _C 1 ~ _{C R),} since it is L = W / s, L ( = W / s) number of the counter match detection The circuits 51 to 5L eventually determine the number of clocks of the clock signal CLK when a counter value that matches the sum of (W / s) × s = W distance signals is obtained. Will output a timing signal indicating the timing count (any timing signals C _{1 ~} C _R).

FIG. 10 is a schematic diagram showing still another configuration of the distance / clock number conversion circuits DC ₁ to DC _R shown in FIG.

In the embodiment of the present invention, each of the distance / clock number conversion circuits DC ₁ to DC _R may comprise the distance / clock number conversion circuit DC ″ ₁ shown in FIG. 10. In this case as well, W = 2 ⁱ (i is an integer of 2 or more).

Referring to FIG. 10, distance / clock number conversion circuit DC ″ ₁ is obtained by adding switching control circuit 60 and multiplexers 61 to 6L to distance / clock number conversion circuit DC ′ ₁ shown in FIG. is the same as the distance / clock number conversion circuit DC _'1.

In the distance / clock number conversion circuit DC ″ ₁ , the amplifiers 41 to 4L amplify the clock signal CLK, output the amplified clock signal CLK to the counter coincidence detection circuits 51 to 5L, respectively, and the amplified clock signal. CLK is output to the switching control circuit 60.

In the distance / clock number conversion circuit DC _"1, multiplexer 61, 62, · · ·, 6L, respectively, s pieces of distance calculation circuit _{DP 11, DP 1 (1 +} L), ···, DP 1 ( _{1+ (u−1) L)} , s distance arithmetic circuits DP ₁₂ , DP _{1 (2 + L)} ,..., DP _{1 (2+ (u−1) L)} ,. DP _1L , DP _{1 (L + L)} ,..., DP _{1 (L + (u−1) L)} are provided, and counter match detection circuits 51 to 5L correspond to multiplexers 61 to 6L, respectively. Provided.

The switching control circuit 60 receives the search start signal SB and the reset signal RST from the control circuit of the associative memory 100, and receives the match signals MTH1 to MTHL from the counter match detection circuits 51 to 5L, respectively.

When switching control circuit 60 receives search start signal SB and reset signal RST, switching control circuit 60 outputs reset signal RST to counter match detection circuit 51 and output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. .

When switching control circuit 60 receives coincidence signal MTHL from counter coincidence detection circuit 5L, it outputs reset signal RST to counter coincidence detection circuit 51 and outputs output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. To do. The switching control circuit 60 executes this process s-1 times.

Further, when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do. The switching control circuit 60 performs this process s times.

Further, when receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 53 and outputs the output signal OUT3 to the multiplexer 63 in synchronization with the clock signal CLK. To do. The switching control circuit 60 performs this process s times.

Similarly, when the switching control circuit 60 receives the coincidence signal MTHL-1 from the counter coincidence detection circuit 5L-1, it outputs a reset signal RST to the counter coincidence detection circuit 5L in synchronization with the clock signal CLK. Output signal OUTL is output to multiplexer 6L. The switching control circuit 60 performs this process s times.

The multiplexer 61 receives s distance signals D ₁₁ , D _{1 (1 + L)} ,..., D _{1 (1+ (u−1) L)} . The multiplexer 61 receives the first output signal OUT1 from the switching control circuit 60 outputs a distance signal _{D 11} to the counter match detection circuit 51, when receiving the second output signal OUT1 from the switching control circuit 60, The distance signal D _{1 (1 + L)} is output to the counter coincidence detection circuit 51. Similarly, when the s-th output signal OUT1 is received from the switching control circuit 60, the distance signal D _{1 (1+ (u−1) L )} Is output to the counter coincidence detection circuit 51.

The multiplexer 62 receives s distance signals D ₁₂ , D _{1 (2 + L)} ,..., D _{1 (2+ (u−1) L)} . The multiplexer 62 receives the first output signal OUT2 from the switching control circuit 60 outputs a distance signal _{D 12} to the counter coincidence detection circuit 52, when receiving the second output signal OUT2 from the switching control circuit 60, The distance signal D _{1 (2 + L)} is output to the counter coincidence detection circuit 52. Similarly, when the s-th output signal OUT2 is received from the switching control circuit 60, the distance signal D _{1 (2+ (u−1) L )} Is output to the counter match detection circuit 52.

Similarly, the multiplexer 6L receives s distance signals D _1L , D _{1 (L + L)} ,..., D _{1 (L + (u−1) L)} . When the multiplexer 6L receives the first output signal OUTL from the switching control circuit 60, the multiplexer 6L outputs the distance signal _D1L to the counter coincidence detection circuit 5L, and receives the second output signal OUTL from the switching control circuit 60. The distance signal D1 _{(L + (u-1) L} is output when the distance signal D1 _{(L + L)} is output to the counter coincidence detection circuit 5L and the s-th output signal OUTL is similarly received from the switching control circuit 60. ₎ Is output to the counter coincidence detection circuit 5L.

The counter coincidence detection circuit 51 is driven when it receives the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 51 receives the distance signal D ₁₁ from the multiplexer 61, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D ₁₁ is obtained The clock number CN_1 of the clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation. The counter coincidence detection circuit 51 executes this processing for all s distance signals D ₁₁ , D _{1 (1 + L)} ,..., D _{1 (1+ (u−1) L)} .

The counter coincidence detection circuit 52 is driven when it receives the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 52 receives the distance signal D ₁₂ from the multiplexer 62, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D ₁₂ is obtained The clock number CN_2 of the clock signal CLK is counted, and the coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation. The counter coincidence detection circuit 52 executes this process for all s distance signals D ₁₂ , D _{1 (2 + L)} ,..., D _{1 (2+ (u−1) L)} .

Similarly, the counter coincidence detection circuit 5L is driven when it receives the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 5L receives the distance signal D _1L from the multiplexer 6L, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D _1L is obtained The clock number CN_L of the clock signal CLK is counted, and a coincidence signal MTHL indicating the timing at which the clock number CN_L is counted is output to the switching control circuit 60. Then, the counter match detection circuit 5L stops its operation. The counter coincidence detection circuit 5L executes this process for all of the s−1 distance signals D ₁₂ , D _{1 (2 + L)} ,..., D _{1 (2+ (u−1) L−1)} .

The counter coincidence detection circuit 5L is driven when the s-th reset signal RST is received from the switching control circuit 60, receives the distance signal D1 _{(L + (u−1) L)} from the multiplexer 6L, and receives the counter value as a clock. When counting in ascending order in synchronization with the signal CLK, the number of clocks CN_L of the clock signal CLK when the counter value matching the distance signal D1 _{(L + (u-1) L)} is obtained is counted, and the number of clocks CN_L a timing signal _{C 1} indicating timing for counting the output to Winner detector 20.

In each of the distance / clock number conversion circuits DC ₁ to DC _R (= distance / clock number conversion circuit DC ″ ₁ ), when the search of the reference data similar to the search data is started, the switching control circuit 60 In synchronization with the signal CLK, the reset signal RST is output to the counter coincidence detection circuit 51 and the output signal OUT1 is output to the multiplexer 61.

Then, the multiplexer 61, depending on the first output signal OUT1 from the switching control circuit 60 outputs a distance signal _{D 11} to the counter match detection circuit 51.

The counter coincidence detection circuit 51 is driven in response to the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 51 receives the distance signal D ₁₁ from the multiplexer 61, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D ₁₁ is obtained The clock number CN_1 of the clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.

Thereafter, the switching control circuit 60 outputs the reset signal RST to the counter match detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK according to the match signal MTH1 from the counter match detection circuit 51. Output.

Multiplexer 62, in response to the first output signal OUT2 from the switching control circuit 60 outputs a distance signal _{D 12} to the counter coincidence detection circuit 52.

The counter coincidence detection circuit 52 is driven in response to the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 52 receives the distance signal D ₁₂ from the multiplexer 62, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D ₁₂ is obtained The clock number CN_2 of the clock signal CLK is counted, and the coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.

Similarly, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 5L in synchronization with the clock signal CLK in response to the coincidence signal MTHL-1 from the counter coincidence detection circuit 5L-1. At the same time, the output signal OUTL is output to the multiplexer 6L.

Then, the multiplexer 6L outputs the distance signal _D1L to the counter coincidence detection circuit 5L in response to the first output signal OUTL from the switching control circuit 60.

The counter coincidence detection circuit 5L is driven according to the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 5L receives the distance signal D _1L from the multiplexer 6L, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D _1L is obtained The clock number CN_L of the clock signal CLK is counted, and a coincidence signal MTHL indicating the timing at which the clock number CN_L is counted is output to the switching control circuit 60. Then, the counter match detection circuit 5L stops its operation.

Thereafter, the switching control circuit 60 outputs the reset signal RST to the counter match detection circuit 51 and the output signal OUT1 to the multiplexer 61 in synchronization with the clock signal CLK according to the match signal MTHL from the counter match detection circuit 5L. Output.

Thereafter, the counter match detection circuits 51 to 5L-1, the switching control circuit 60, and the multiplexers 61 to 6L-1 repeatedly execute the above-described operation s-1 times, and the counter match detection circuit 5L and the multiplexer 6L perform the above-described operation. Are repeatedly executed s-2 times.

When the counter coincidence detection circuit 5L receives the s-th reset signal RST from the switching control circuit 60 and the distance signal D1 _{(L + (u−1) L)} from the multiplexer 6L, the counter value is converted to the clock signal CLK. When counting in ascending order synchronously, the clock number CN_L of the clock signal CLK when the counter value matching the distance signal D1 _{(L + (u−1) L)} is obtained is counted, and the clock number CN_L is counted A timing signal C ₁ indicating the timing is output to the Winner detector 20. Then, the counter match detection circuit 5L stops its operation.

When L (= W / s) counter coincidence detection circuits 51 to 5L are considered as one counter coincidence detection circuit MDC, the counter coincidence detection circuit MDC performs L (= W / s) distances for the first time. Receives signals D ₁₁ to D _1L . Then, the counter coincidence detection circuits 51 to 5L count the clock numbers CN_1 to CN_L of the clock signal CLK when the counter values coincident with the distance signals D ₁₁ to D _1L are obtained, and the timing at which the clock numbers CN_1 to CN_L are counted The coincidence signals MTH1 to MTHL indicating the number of clock signals CLK when the counter coincidence detection circuit MDC obtains a counter value that coincides with the sum of the distance signals D ₁₁ to D _1L (CN_1 + CN_2 +... + CN_L ) And the coincidence signal indicating the timing when the number of clocks (CN_1 + CN_2 +... + CN_L) is counted is output. The counter match detection circuit MDC repeatedly executes this process s-1 times. When the counter coincidence detection circuit MDC outputs the s−1th coincidence signal, L (= W / s) number of distance signals D _{1 (1+ (u−1) L)} , D _{1 (2+ (u−) 1)} Count the number of clock signals CLK (CN_1 + CN_2 +... + CN_L) when a counter value that matches the sum of _L) ,..., D1 _{(L + (u-1) L)} is obtained. and it outputs the clock number (CN_1 + CN_2 + ··· + CN_L ) ( either = timing signals _C 1 ~ _{C R)} timing signal indicating a timing of counting the Winner detector 20.

Accordingly, in the distance / clock number conversion circuit DC ″ ₁ , the L (= W / s) counter coincidence detection circuits 51 to 5L receive the L (= W / s) distance signals D ₁₁ to D _1L . When the counter value is counted in ascending order in synchronization with the clock signal CLK, a counter value that matches the sum of the received L (= W / s) distance signals D ₁₁ to D _1L is obtained. The process of counting the first clock number of the clock signal CLK and outputting the first coincidence signal indicating the timing of counting the first clock number is repeatedly executed s-1 times, and the first coincidence signal is changed to s -1 times and when receiving L (= W / s) distance signals at the sth time, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the received L (= W / S) matches the number of distance signals And second counts the number of clocks of the clock signal CLK when the count value is obtained, the second timing signal indicating a timing of counting the number of clocks (= one of the timing signals C _{1 ~} C _R) the Winner detection Output to the device 20.

Figure 11 is a schematic diagram showing a specific configuration of the distance / clock number converting circuit DC _'1 shown in FIG.

Referring to FIG. 11, when W = 2 ⁱ = 2 ³ = 8 and s = 2 ^x = 2 ¹ = 2, L = W / s = 8/2 = 4, and distance / number of clocks Conversion circuit DC ′ ₁ −1 includes amplifiers 41 to 44 and counter coincidence detection circuits 51 to 54.

The W distance signals D ₁₁ to D _1W are composed of eight distance signals D ₁₁ to D ₁₈ , and the W distance calculation circuits DP ₁₁ to DP _1W are eight distance calculation circuits DP ₁₁ to DP 1. _It consists of ₁₈ . Here, the distance signals D ₁₁ to D ₁₈ are respectively D ₁₁ = “3”, D ₁₂ = “2”, D ₁₃ = “5”, D ₁₄ = “1”, D ₁₅ = “2”, D It is assumed that ₁₆ = “4”, D ₁₇ = “2”, and D ₁₈ = “3”.

The counter coincidence detection circuit 51 is provided corresponding to the two distance arithmetic circuits DP ₁₁ and DP ₁₅ , and the counter coincidence detection circuit 52 is provided corresponding to the two distance arithmetic circuits DP ₁₂ and DP _16. The counter match detection circuit 53 is provided corresponding to the two distance calculation circuits DP ₁₃ and DP ₁₇ , and the counter match detection circuit 54 is provided corresponding to the two distance calculation circuits DP ₁₄ and DP _18. It is done.

FIG. 12 is a diagram for explaining the operation of the distance / clock number conversion circuit DC ′ ₁ −1 shown in FIG.

Each of the distance / clock number conversion circuits DC ₁ to DC _R includes a distance / clock number conversion circuit DC ′ ₁ −1 shown in FIG. When the search of reference data similar to the search data is started in each of the distance / clock number conversion circuits DC ₁ to DC _R (= distance / clock number conversion circuit DC ′ ₁ −1), the counter match detection circuit 51 receives distance signals D ₁₁ (= “3”) and D ₁₅ (= “2”) from the distance calculation circuits DP ₁₁ and DP ₁₅ respectively, and the counter coincidence detection circuit 52 receives the distance calculation circuits DP ₁₂ and DP _16. In response to the distance signals D ₁₂ (= “2”) and D ₁₆ (= “4”), the counter coincidence detection circuit 53 receives the distance signals D ₁₃ (= “5”) from the distance calculation circuits DP ₁₃ and DP ₁₇ , respectively. ), D ₁₇ (= “2”), the counter coincidence detection circuit 54 receives the distance signals D ₁₄ (= “1”) and D ₁₈ (= “3”) from the distance calculation circuits DP ₁₄ and DP ₁₈ , respectively. receive.

Then, the counter coincidence detection circuit 51 obtains a counter value CV ₁₁ that coincides with the sum (= “5” = “101”) of the distance signals D ₁₁ (= “3”) and D ₁₅ (= “2”). The number of clocks CN1 (= “5”) of the clock signal CLK is counted. Then, the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing of counting the clock number CN1 (= “5”) to the counter coincidence detection circuit 52 in synchronization with the clock signal CLK. Then, the counter coincidence detection circuit 51 stops its operation.

When the counter coincidence detection circuit 52 receives the coincidence signal MTH1 from the counter coincidence detection circuit 51, the sum (= “6” = “110”) of the distance signals D ₁₂ (= “2”) and D ₁₆ (= “4”). ) the number of clocks of the clock signal CLK when the counter value _{CV 12} is obtained which matches CN2 (= "6") to count. Then, the counter coincidence detection circuit 52 outputs a coincidence signal MTH2 indicating the timing of counting the clock number CN2 (= “6”) to the counter coincidence detection circuit 53 in synchronization with the clock signal CLK. Then, the counter match detection circuit 52 stops its operation.

When the counter match detection circuit 53 receives the match signal MTH2 from the counter match detection circuit 52, the sum (= “7” = “111”) of the distance signals D ₁₃ (= “5”) and D ₁₇ (= “2”). ) the number of clocks of the clock signal CLK when the counter value _{CV 13} is obtained which matches CN4 (= "7") to count. Then, the counter coincidence detection circuit 53 outputs a coincidence signal MTH3 indicating the timing at which the clock number CN4 (= “7”) is counted to the counter coincidence detection circuit 54 in synchronization with the clock signal CLK. Then, the counter coincidence detection circuit 53 stops its operation.

When the counter coincidence detection circuit 54 receives the coincidence signal MTH3 from the counter coincidence detection circuit 53, the sum (= “4” = “100”) of the distance signals D ₁₄ (= “1”) and D ₁₈ (= “3”). ) Counts the number of clocks CN4 (= “4”) when the counter value CV ₁₄ matching the above is obtained. The counter coincidence detection circuit 54, a clock number CN4 (= "4") and count timing signal indicating a timing (= one of the timing signals _C 1 ~ _{C R)} in synchronization with the clock signal CLK Winner detector 20 output. Then, the counter coincidence detection circuit 54 stops its operation.

In this way, each of the counter coincidence detection circuits 51 to 54 counts the number of clocks when a counter value that matches the sum of the two distance signals is obtained, and a counter value that matches the sum of the two distance signals is obtained. when counting the number of clocks when it is, respectively, it outputs a coincidence signal MTH1 ~ MTH3 and the timing signal (either = timing signals _C 1 ~ _{C R).}

When each of the distance / clock number conversion circuits DC ₁ to DC _R is composed of the distance / clock number conversion circuit DC ′ ₁ −1, each of the distance / clock number conversion circuits DC ₁ to DC _R has a distance signal D ₁₁ = “ _{3 ", D 12 =" 2} ", D 13 =" 5 ", D 14 =" 1 ", D 15 =" 2 ", D 16 =" 4 ", D 17 =" 2 ", D 18 =" 3 The number of clocks (= “22”) of the clock signal CLK when the counter value matching the sum of “=” (“22”) is obtained is counted, and the timing indicating the timing of counting the number of clocks (= “22”) and it outputs a signal (either = timing signals _C 1 ~ _{C R)} to the Winner detector 20.

Figure 13 is a schematic diagram showing another specific configuration of the distance / clock number converting circuit DC _'1 shown in FIG.

Referring to FIG. 13, when W = 2 ⁱ = 2 ³ = 8 and s = 2 ^x = 2 ² = 4, L = W / s = 8/4 = 2, and distance / number of clocks Conversion circuit DC ′ ₁ -2 includes amplifiers 41 and 42 and counter coincidence detection circuits 51 and 52.

The W distance signals D ₁₁ to D _1W are composed of eight distance signals D ₁₁ to D ₁₈ , and the W distance calculation circuits DP ₁₁ to DP _1W are eight distance calculation circuits DP ₁₁ to DP 1. _It consists of ₁₈ . Each of the distance signals D ₁₁ to D ₁₈ is composed of a 4-bit bit value. Here, the distance signals D ₁₁ to D ₁₈ are respectively D ₁₁ = “3”, D ₁₂ = “2”, D ₁₃ = “5”, D ₁₄ = “1”, D ₁₅ = “2”, D It is assumed that ₁₆ = “4”, D ₁₇ = “2”, and D ₁₈ = “3”.

The counter coincidence detection circuit 51 is provided corresponding to the four distance arithmetic circuits DP ₁₁ , DP ₁₃ , DP ₁₅ , and DP ₁₇ , and the counter coincidence detection circuit 52 includes the four distance arithmetic circuits DP ₁₂ , DP ₁₄ , DP ₁₆ , and DP ₁₈ .

In each of the counter coincidence detection circuits 51 and 52, the counter 311 or 311A outputs a 4-bit counter value to the coincidence detection circuit 312.

FIG. 14 is a diagram for explaining the operation of the distance / clock number conversion circuit DC ′ ₁ -2 shown in FIG.

Each of the distance / clock number conversion circuits DC ₁ to DC _R includes a distance / clock number conversion circuit DC ′ ₁ -2 shown in FIG. Then, in each of the distance / clock number conversion circuits DC ₁ to DC _R (= distance / clock number conversion circuit DC ′ ₁ -2), when the search for the reference data similar to the search data is started, the counter coincidence detection circuit Reference numeral 51 denotes distance signals D ₁₁ (= “3”), D ₁₃ (= “5”), D ₁₅ (= “2”), D ₁₇ from the distance calculation circuits DP ₁₁ , DP ₁₃ , DP ₁₅ , DP ₁₇ , respectively. (= “2”), the counter match detection circuit 52 receives the distance signals D ₁₂ (= “2”) and D ₁₄ (= “1” from the distance calculation circuits DP ₁₂ , DP ₁₄ , DP ₁₆ , DP ₁₈ , respectively. ), D ₁₆ (= “4”), D ₁₈ (= “3”).

Then, when the counter match detection circuit 51 counts the counter value in ascending order in synchronization with the clock signal CLK, the distance signals D ₁₁ (= “3”), D ₁₃ (= “5”), D ₁₅ (= “2”) and D ₁₇ (= “2”) (= “12” = “1100”) When the counter value CV ₁₁ is obtained, the number of clocks of the clock signal CLK CN1 (= “12”) Count. Then, the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing of counting the clock number CN1 to the counter coincidence detection circuit 52 in synchronization with the clock signal CLK. Then, the counter coincidence detection circuit 51 stops its operation.

The counter coincidence detection circuit 52 is driven when the coincidence signal MTH1 is received from the counter coincidence detection circuit 51. When the counter value is counted in ascending order in synchronization with the clock signal CLK, the distance signal D ₁₂ (= “2”), _{D 14 (= "1")} , D 16 (= "4"), D 18 (= "3") of the sum (= "10" = "1010") when the counter value _{CV 12} matching can be obtained for The number of clocks CN2 (= “10”) of the clock signal CLK is counted. The counter coincidence detection circuit 52, a clock number CN2 (= "10") counted timing signal indicating the timing (= one of the timing signals _C 1 ~ _{C R)} in synchronization with the clock signal CLK the Winner detector 20 output. Then, the counter match detection circuit 52 stops its operation.

In this way, each of the counter coincidence detection circuits 51 and 52 counts the number of clocks when a counter value that matches the sum of the four distance signals is obtained, and a counter value that matches the sum of the four distance signals is obtained. when counting the number of clocks when it is, respectively, it outputs a coincidence signal MTH1 and the timing signal (either = timing signals _C 1 ~ _{C R).}

Even when each of the distance / clock number conversion circuits DC ₁ to DC _R is composed of the distance / clock number conversion circuit DC ′ ₁ -2, each of the distance / clock number conversion circuits DC ₁ to DC _R has a distance signal D ₁₁ = “3”, D ₁₂ = “2”, D ₁₃ = “5”, D ₁₄ = “1”, D ₁₅ = “2”, D ₁₆ = “4”, D ₁₇ = “2”, D ₁₈ = “ Indicates the timing at which the number of clocks (= “22”) of the clock signal CLK when the counter value matching the sum of 3 ”(=“ 22 ”) is obtained and the number of clocks (=“ 22 ”) is counted (either = timing signals _C 1 ~ _{C R)} timing signal output to the Winner detector 20.

FIG. 15 is a schematic diagram showing a specific configuration of the distance / clock number conversion circuit DC ″ ₁ shown in FIG.

Referring to FIG. 15, when W = 2 ⁱ = 2 ³ = 8 and s = 2 ^x = 2 ¹ = 2, L = W / s = 8/2 = 4, and distance / number of clocks The conversion circuit DC ″ ₁ −1 includes amplifiers 41 to 44, counter coincidence detection circuits 51 to 54, a switching control circuit 60, and multiplexers 61 to 64.

The W distance signals D ₁₁ to D _1W are composed of eight distance signals D ₁₁ to D ₁₈ , and the W distance calculation circuits DP ₁₁ to DP _1W are eight distance calculation circuits DP ₁₁ to DP 1. _It consists of ₁₈ . Here, the distance signals D ₁₁ to D ₁₈ are respectively D ₁₁ = “3”, D ₁₂ = “2”, D ₁₃ = “5”, D ₁₄ = “1”, D ₁₅ = “2”, D It is assumed that ₁₆ = “4”, D ₁₇ = “2”, and D ₁₈ = “3”.

In the distance / clock number conversion circuit DC ″ ₁ −1, the multiplexer 61 is provided corresponding to the two distance calculation circuits DP ₁₁ and DP ₁₅ , and the multiplexer 62 is provided with the two distance calculation circuits DP ₁₂ and DP ₁₅ . ₁₆ , the multiplexer 63 is provided corresponding to the two distance arithmetic circuits DP ₁₃ and DP ₁₇ , and the multiplexer 64 is provided corresponding to the two distance arithmetic circuits DP ₁₄ and DP _18. It is done.

Counter coincidence detection circuits 51 to 54 are provided corresponding to the multiplexers 61 to 64, respectively.

In the distance / clock number conversion circuit DC ″ ₁ −1, the amplifiers 41 to 44 amplify the clock signal CLK, and output the amplified clock signal CLK to the counter coincidence detection circuits 51 to 54, respectively. The clock signal CLK is output to the switching control circuit 60.

Switching control circuit 60 receives search start signal SB and reset signal RST from the control circuit of associative memory 100, and receives match signals MTH1 to MTH4 from counter match detection circuits 51 to 54, respectively.

When switching control circuit 60 receives search start signal SB and reset signal RST, switching control circuit 60 outputs reset signal RST to counter match detection circuit 51 and output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. .

Further, when receiving the coincidence signal MTH4 from the counter coincidence detection circuit 54, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 and outputs the output signal OUT1 to the multiplexer 61 in synchronization with the clock signal CLK. To do. The switching control circuit 60 executes this process 1 (= s−1 = 2-1) times.

Further, when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do. The switching control circuit 60 executes this process twice (= s = 2).

Further, when receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 53 and outputs the output signal OUT3 to the multiplexer 63 in synchronization with the clock signal CLK. To do. The switching control circuit 60 executes this process twice (= s = 2).

Further, when receiving the coincidence signal MTH3 from the counter coincidence detection circuit 53, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 54 and outputs the output signal OUT4 to the multiplexer 64 in synchronization with the clock signal CLK. To do. The switching control circuit 60 executes this process twice (= s = 2).

The multiplexer 61 receives two distance signals D ₁₁ and D ₁₅ . The multiplexer 61 receives the first output signal OUT1 from the switching control circuit 60 outputs a distance signal _{D 11} to the counter match detection circuit 51, when receiving the second output signal OUT1 from the switching control circuit 60, and it outputs a distance signal _{D 15} to the counter match detection circuit 51.

The multiplexer 62 receives two distance signals D ₁₂ and D ₁₆ . The multiplexer 62 receives the first output signal OUT2 from the switching control circuit 60 outputs a distance signal _{D 12} to the counter coincidence detection circuit 52, when receiving the second output signal OUT2 from the switching control circuit 60, and it outputs a distance signal _{D 16} to the counter coincidence detection circuit 52.

The multiplexer 63 receives the two distance signals D ₁₃ and D ₁₇ . The multiplexer 63 receives the first output signal OUT3 from the switching control circuit 60 outputs a distance signal _{D 13} to the counter coincidence detection circuit 53, when receiving the second output signal OUT3 from the switching control circuit 60, The distance signal D ₁₇ is output to the counter coincidence detection circuit 53.

The multiplexer 64 receives the two distance signals D ₁₄ and D ₁₈ . The multiplexer 64 receives the first output signal OUT4 from the switching control circuit 60 outputs a distance signal _{D 14} to the counter coincidence detection circuit 54, when receiving the second output signal OUT4 from the switching control circuit 60, and it outputs the distance signal _{D 18} to the counter coincidence detection circuit 54.

The counter coincidence detection circuit 51 is driven when it receives the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 51 receives the distance signal D ₁₁ from the multiplexer 61, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D ₁₁ is obtained The clock number CN_1 of the clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation. The counter coincidence detection circuit 51 executes this process for all the two distance signals D ₁₁ and D ₁₅ .

The counter coincidence detection circuit 52 is driven when it receives the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 52 receives the distance signal D ₁₂ from the multiplexer 62, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D ₁₂ is obtained The clock number CN_2 of the clock signal CLK is counted, and the coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation. The counter coincidence detection circuit 52 executes this process for all of the two distance signals D ₁₂ and D ₁₆ .

Further, the counter coincidence detection circuit 53 is driven when it receives the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 53 receives the distance signals D ₁₃ from the multiplexer 63, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D ₁₃ is obtained The clock number CN_3 of the clock signal CLK is counted, and a coincidence signal MTH3 indicating the timing at which the clock number CN_3 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 53 stops its operation. The counter coincidence detection circuit 53 executes this process for all of the two distance signals D ₁₃ and D ₁₇ .

Further, the counter coincidence detection circuit 54 is driven when it receives the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 54 receives the distance signal D ₁₄ from the multiplexer 64, when counted in ascending order in synchronization with the counter value to the clock signal CLK, and when the counter value matches the distance signal D ₁₄ is obtained The clock number CN_4 of the clock signal CLK is counted, and a coincidence signal MTH4 indicating the timing at which the clock number CN_4 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 54 stops its operation.

The counter coincidence detection circuit 54 receives a second reset signal RST from the switching control circuit 60, a distance signal D ₁₈ receives from the multiplexer 64, when counted in ascending order in synchronization with the counter value of the clock signal CLK counts the number of clocks CN_4 of the clock signal CLK when the counter value matches the distance signal _{D 18} is obtained (either = timing signals _C 1 ~ _{C R)} timing signal indicating a timing of counting the number of clocks CN_4 Is output to the Winner detector 20. Then, the counter coincidence detection circuit 54 stops its operation.

FIG. 16 is a diagram for explaining the operation of the distance / clock number conversion circuit DC ″ ₁ −1 shown in FIG.

In each of the distance / clock number conversion circuits DC ₁ to DC _R (= distance / clock number conversion circuit DC ″ ₁ −1), when the search of the reference data similar to the search data is started, the switching control circuit 60 In synchronization with the clock signal CLK, the reset signal RST is output to the counter coincidence detection circuit 51 and the output signal OUT1 is output to the multiplexer 61.

Then, the multiplexer 61 outputs the distance signal D ₁₁ (= “3”) to the counter coincidence detection circuit 51 in response to the first output signal OUT 1 from the switching control circuit 60.

The counter coincidence detection circuit 51 is driven in response to the reset signal RST from the switching control circuit 60. When the counter coincidence detection circuit 51 receives the distance signal D ₁₁ (= “3”) from the multiplexer 61, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the distance signal D ₁₁ (= “ When the counter value corresponding to 3 ″) is obtained, the clock number CN_1 (= “3”) of the clock signal CLK is counted, and the coincidence signal MTH1 indicating the timing when the clock number CN_1 (= “3”) is counted is switched. Output to the control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.

After that, when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do.

The multiplexer 62 outputs the distance signal D ₁₂ (= “2”) to the counter coincidence detection circuit 52 in response to the first output signal OUT 2 from the switching control circuit 60.

The counter coincidence detection circuit 52 is driven in response to the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 52 receives the distance signal _D 12 (= the "2") from the multiplexer 62, when counted in ascending order in synchronization with the counter value to the clock signal CLK, the distance signal _D 12 (= " 2 ”), when the counter value corresponding to 2 ″) is obtained, the number of clocks CN_2 (=“ 2 ”) of the clock signal CLK is counted, and the coincidence signal MTH2 indicating the timing when the clock number CN_2 (=“ 2 ”) is counted is switched. Output to the control circuit 60. Then, the counter match detection circuit 52 stops its operation.

Thereafter, when receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 53 and outputs the output signal OUT3 to the multiplexer 63 in synchronization with the clock signal CLK. To do.

The multiplexer 63 outputs the distance signal D ₁₃ (= “5”) to the counter coincidence detection circuit 53 in response to the first output signal OUT 3 from the switching control circuit 60.

The counter coincidence detection circuit 53 is driven in response to the reset signal RST from the switching control circuit 60. The counter coincidence detection circuit 53 receives the distance signal _D 13 (= the "5") from the multiplexer 63, when counted in ascending order in synchronization with the counter value to the clock signal CLK, the distance signal _D 13 (= " When the counter value coincident with 5 ″) is obtained, the clock number CN_3 (= “5”) of the clock signal CLK is counted, and the coincidence signal MTH3 indicating the timing when the clock number CN_3 (= “5”) is counted is switched. Output to the control circuit 60. Then, the counter coincidence detection circuit 53 stops its operation.

After that, when receiving the coincidence signal MTH3 from the counter coincidence detection circuit 53, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 54 and outputs the output signal OUT4 to the multiplexer 64 in synchronization with the clock signal CLK. To do.

The multiplexer 64 outputs the distance signal D ₁₄ (= “1”) to the counter coincidence detection circuit 54 in response to the first output signal OUT 4 from the switching control circuit 60.

The counter coincidence detection circuit 54 is driven according to the reset signal RST from the switching control circuit 60. When the counter coincidence detection circuit 54 receives the distance signal D ₁₄ (= “1”) from the multiplexer 64, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the distance signal D ₁₄ (= “ When the counter value corresponding to 1 ″) is obtained, the clock number CN_4 (= “1”) of the clock signal CLK is counted, and the coincidence signal MTH4 indicating the timing when the clock number CN_4 (= “1”) is counted is switched. Output to the control circuit 60. Then, the counter coincidence detection circuit 54 stops its operation.

Thereafter, when receiving the coincidence signal MTH4 from the counter coincidence detection circuit 54, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 and the output signal OUT1 to the multiplexer 61 in synchronization with the clock signal CLK. To do.

The multiplexer 61 outputs the distance signal D ₁₅ (= “2”) to the counter coincidence detection circuit 51 in response to the second output signal OUT 1 from the switching control circuit 60.

The counter coincidence detection circuit 51 is driven in response to the reset signal RST from the switching control circuit 60. When the counter coincidence detection circuit 51 receives the distance signal D ₁₅ (= “2”) from the multiplexer 61, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the distance signal D ₁₅ (= “ 2 ”), when the counter value corresponding to 2 ″) is obtained, the number of clocks CN_1 (=“ 2 ”) of the clock signal CLK is counted, and the coincidence signal MTH1 indicating the timing when the clock number CN_1 (=“ 2 ”) is counted is switched. Output to the control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.

After that, when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do.

The multiplexer 62 outputs the distance signal D ₁₆ (= “4”) to the counter coincidence detection circuit 52 in response to the second output signal OUT 2 from the switching control circuit 60.

The counter coincidence detection circuit 52 is driven in response to the reset signal RST from the switching control circuit 60. When the counter coincidence detection circuit 52 receives the distance signal D ₁₆ (= “4”) from the multiplexer 62, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the distance signal D ₁₆ (= “ 4 ”), when the counter value corresponding to 4 ″) is obtained, the clock number CN_2 (=“ 4 ”) of the clock signal CLK is counted, and the coincidence signal MTH2 indicating the timing when the clock number CN_2 (=“ 4 ”) is counted is switched. Output to the control circuit 60. Then, the counter match detection circuit 52 stops its operation.

Thereafter, when receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 53 and outputs the output signal OUT3 to the multiplexer 63 in synchronization with the clock signal CLK. To do.

The multiplexer 63 outputs the distance signal D ₁₇ (= “2”) to the counter coincidence detection circuit 53 in response to the second output signal OUT 3 from the switching control circuit 60.

The counter coincidence detection circuit 53 is driven in response to the reset signal RST from the switching control circuit 60. When the counter coincidence detection circuit 53 receives the distance signal D ₁₇ (= “2”) from the multiplexer 63, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the distance signal D ₁₇ (= “ 2 ”), when the counter value corresponding to 2 ″) is obtained, the clock number CN_3 (=“ 2 ”) of the clock signal CLK is counted, and the coincidence signal MTH3 indicating the timing when the clock number CN_3 (=“ 2 ”) is counted is switched. Output to the control circuit 60. Then, the counter coincidence detection circuit 53 stops its operation.

After that, when receiving the coincidence signal MTH3 from the counter coincidence detection circuit 53, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 54 and outputs the output signal OUT4 to the multiplexer 64 in synchronization with the clock signal CLK. To do.

The multiplexer 64 outputs the distance signal D ₁₈ (= “3”) to the counter coincidence detection circuit 54 in response to the second output signal OUT 4 from the switching control circuit 60.

The counter coincidence detection circuit 54 is driven according to the reset signal RST from the switching control circuit 60. When the counter coincidence detection circuit 54 receives the distance signal D ₁₈ (= “3”) from the multiplexer 64, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the distance signal D ₁₈ (= “ When the counter value corresponding to 3 ″) is obtained, the clock number CN_4 (= “3”) of the clock signal CLK is counted, and the coincidence signal MTH4 indicating the timing when the clock number CN_4 (= “3”) is counted is switched. Output to the control circuit 60. Then, the counter coincidence detection circuit 54 stops its operation.

Then, in response to the second coincidence signal MTH4 from the counter coincidence detection circuit 54, the switching control circuit 60 shows a timing signal (= timing signals C ₁ to C) indicating the same timing as that indicated by the second coincidence signal MTH4. Any one of _R ) is output to the Winner detector 20.

As described above, the counter coincidence detection circuits 51 to 54 count the clock numbers CN_1 to CN_4 of the clock signal CLK when the counter values coincident with the distance signals D ₁₁ to D ₁₄ are obtained, and the clock numbers CN_1 to CN_4 after outputting a coincidence signal MTH1 ~ MTH4 showing a timing of counting, counts the number of clocks CN_1 ~ CN_4 of the clock signal CLK when the respective counter value matches the distance signal _D 15 _{~ D 18} is obtained, Match signals MTH1 to MTH4 indicating the timings when the clock numbers CN_1 to CN_4 are counted are output.

That is, each of the counter coincidence detection circuits 51 to 54 counts the clock number of the clock signal CLK when a counter value that coincides with the distance signal is obtained, and outputs a coincidence signal indicating the timing at which the clock number is counted. Repeat twice.

Even when each of the distance / clock number conversion circuits DC ₁ to DC _R is composed of the distance / clock number conversion circuit DC ″ ₁ −1, each of the distance / clock number conversion circuits DC ₁ to DC _R has the distance signal D ₁₁ = “3”, D ₁₂ = “2”, D ₁₃ = “5”, D ₁₄ = “1”, D ₁₅ = “2”, D ₁₆ = “4”, D ₁₇ = “2”, D ₁₈ = “ Indicates the timing at which the number of clocks (= “22”) of the clock signal CLK when the counter value matching the sum of 3 ”(=“ 22 ”) is obtained and the number of clocks (=“ 22 ”) is counted (either = timing signals _C 1 ~ _{C R)} timing signal output to the Winner detector 20.

FIG. 17 is a schematic diagram showing still another specific configuration of the distance / clock number conversion circuit DC ″ ₁ shown in FIG.

Referring to FIG. 17, when W = 2 ⁱ = 2 ³ = 8 and s = 2 ^x = 2 ² = 4, L = W / s = 8/4 = 2, and distance / number of clocks The conversion circuit DC ″ ₁ -2 includes amplifiers 41 and 42, counter coincidence detection circuits 51 and 52, a switch control circuit 60, and multiplexers 61 and 62.

The multiplexer 61 is provided corresponding to the four distance calculation circuits DP ₁₁ , DP ₁₃ , DP ₁₅ , DP ₁₇ , and the multiplexer 62 is added to the four distance calculation circuits DP ₁₂ , DP ₁₄ , DP ₁₆ , DP ₁₈ . Correspondingly provided.

The counter match detection circuit 51 is provided corresponding to the multiplexer 61, and the counter match detection circuit 52 is provided corresponding to the multiplexer 62.

The switching control circuit 60 receives the search start signal SB and the reset signal RST from the control circuit of the associative memory 100. Further, the switching control circuit 60 receives the clock signal CLK from the amplifiers 41 and 42. Further, the switching control circuit 60 receives the coincidence signal MTH1 from the counter coincidence detection circuit 51 and the coincidence signal MTH2 from the counter coincidence detection circuit 52.

When switching control circuit 60 receives search start signal SB and reset signal RST, switching control circuit 60 outputs reset signal RST to counter match detection circuit 51 and output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. .

When switching control circuit 60 receives match signal MTH2 from counter match detection circuit 52, switching control circuit 60 outputs reset signal RST to counter match detection circuit 51 and output signal OUT1 to multiplexer 61 in synchronization with clock signal CLK. To do.

Further, when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. To do.

When the switching control circuit 60 receives the s-th coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 shows a timing signal (= timing signals C ₁ to C _R) indicating the same timing as that indicated by the s-th coincidence signal MTH2. Is output to the Winner detector 20.

The multiplexer 61 receives distance signals D ₁₁ , D ₁₃ , D ₁₅ , and D ₁₇ from the distance calculation circuits DP ₁₁ , DP ₁₃ , DP ₁₅ , and DP ₁₇ , respectively, and receives an output signal OUT 1 from the switching control circuit 60.

The multiplexer 61 receives the first output signal OUT1, the distance and outputs a signal _{D 11} to the counter match detection circuit 51, when receiving the second output signal OUT1, the distance signal _{D 13} counter match detection circuit 51 and outputs to and receives the output signal OUT1 of the third, and outputs a distance signal _{D 15} to the counter coincidence detection circuit 51 receives the output signal OUT1 of the fourth, it outputs a distance signal _{D 17} to the counter match detection circuit 51 To do.

Further, the multiplexer 62 receives distance signals D ₁₂ , D ₁₄ , D ₁₆ , D ₁₈ from the distance calculation circuits DP ₁₂ , DP ₁₄ , DP ₁₆ , DP ₁₈ , respectively, and receives the output signal OUT 2 from the switching control circuit 60.

The multiplexer 62 receives the first output signal OUT2, and outputs a distance signal _{D 12} to the counter coincidence detection circuit 52, when receiving the second output signal OUT2, the distance signal _{D 14} counter coincidence detection circuit 52 and outputs to and receives the output signal OUT2 of the third, and outputs a distance signal _{D 16} to the counter coincidence detection circuit 52 receives the output signal OUT2 of the fourth, it outputs a distance signal _{D 18} to the counter coincidence detection circuit 52 To do.

Counter coincidence detection circuit 51 receives the distance signal _{D 11} from the multiplexer 61 receives the reset signal RST from the switching control circuit 60, by the above-described method, when the counter value _{CV 11} matching the distance signal _{D 11} is obtained The clock number CN_1 of the clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.

The counter coincidence detection circuit 51 receives the distance signal _{D 13} from the multiplexer 61 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value _{CV 11} matching the distance signal _{D 13} is obtained The clock number CN_1 of the current clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.

Furthermore, the counter coincidence detection circuit 51 receives the distance signal _{D 15} from the multiplexer 61 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value _{CV 11} matching the distance signal _{D 15} is obtained The clock number CN_1 of the current clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.

Furthermore, the counter coincidence detection circuit 51 receives the distance signal _{D 17} from the multiplexer 61 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value _{CV 11} matching the distance signal _{D 17} is obtained The clock number CN_1 of the current clock signal CLK is counted, and a coincidence signal MTH1 indicating the timing at which the clock number CN_1 is counted is output to the switching control circuit 60. Then, the counter coincidence detection circuit 51 stops its operation.

Thus, the counter coincidence detection circuit 51, each time receiving the distance signal and the reset signal, either the distance signal (= the distance signal _D odd distance signal _D 11 from _11, D _13, D _{15, D 17} ) to count the clock number CN_1 of the clock signal CLK when the counter value _{CV 11} matching is obtained, and outputs a coincidence signal MTH1 indicating timing for counting the number of clocks CN_1 to the switching control circuit 60, then, stops the operation To do.

Counter coincidence detection circuit 52 receives the distance signal _{D 12} from the multiplexer 62 receives the reset signal RST from the switching control circuit 60, by the above-described method, when the counter value _{CV 12} matching the distance signal _{D 12} is obtained The clock number CN_2 of the clock signal CLK is counted, and a coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.

The counter coincidence detection circuit 52 receives the distance signal _{D 14} from the multiplexer 62 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value _{CV 12} matching the distance signal _{D 14} is obtained The clock number CN_2 of the current clock signal CLK is counted, and a coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.

Furthermore, the counter coincidence detection circuit 52 receives the distance signal _{D 16} from the multiplexer 62 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value _{CV 12} matching the distance signal _{D 16} is obtained The clock number CN_2 of the current clock signal CLK is counted, and a coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.

Furthermore, the counter coincidence detection circuit 52 receives the distance signal _{D 18} from the multiplexer 62 receives the reset signal RST from the switching control circuit 60, by the above-described method, the counter value _{CV 12} matching the distance signal _{D 18} is obtained The clock number CN_2 of the current clock signal CLK is counted, and a coincidence signal MTH2 indicating the timing at which the clock number CN_2 is counted is output to the switching control circuit 60. Then, the counter match detection circuit 52 stops its operation.

As described above, the counter coincidence detection circuit 52 receives the distance signal (= the distance signal D ₁₁ , the even-numbered distance signals D ₁₂ , D ₁₄ , D ₁₆ , D ₁₈ every time the distance signal and the reset signal are received. ) to count the clock number CN_2 of the clock signal CLK when the counter value _{CV 12} matching is obtained, and outputs a coincidence signal MTH2 indicating timing for counting the number of clocks CN_2 to the switching control circuit 60, then, stops the operation To do.

FIG. 18 is a diagram for explaining the operation of the distance / clock number conversion circuit DC ″ ₁ -2 shown in FIG.

Referring to FIG. 18, switching control circuit 60 generates reset signal RST as counter match detection circuit 51 in synchronization with clock signal CLK in response to search start signal SB and reset signal RST from the control circuit of associative memory 100. And output signal OUT1 to multiplexer 61.

The multiplexer 61 receives distance signals D ₁₁ , D ₁₃ , D ₁₅ , and D ₁₇ from the distance calculation circuits DP ₁₁ , DP ₁₃ , DP ₁₅ , and DP ₁₇ , respectively. Then, the multiplexer 61, depending on the first output signal OUT1, and outputs a distance signal _{D 11} to the counter match detection circuit 51.

Then, the counter match detection circuit 51 counts the number of clocks CN_1 (= “3”) of the clock signal CLK when the counter value CV ₁₁ that matches the distance signal D ₁₁ (= “3”) is obtained. Then, the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing when the clock number CN_1 (= “3”) is counted to the switching control circuit 60 in synchronization with the clock signal CLK. Then, the counter coincidence detection circuit 51 stops its operation.

After that, when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. Output.

The multiplexer 62 receives distance signals D ₁₂ , D ₁₄ , D ₁₆ , and D ₁₈ from the distance calculation circuits DP ₁₂ , DP ₁₄ , DP ₁₆ , and DP ₁₈ , respectively. Then, the multiplexer 62 outputs the distance signal D ₁₂ (= “2”) to the counter coincidence detection circuit 52 in accordance with the first output signal OUT2.

Then, the counter match detection circuit 52 counts the number of clocks CN_2 (= “2”) of the clock signal CLK when the counter value CV ₁₂ that matches the distance signal D ₁₂ (= “2”) is obtained. Then, the counter coincidence detection circuit 52 outputs a coincidence signal MTH2 indicating the timing when the clock number CN_2 (= “2”) is counted to the switching control circuit 60 in synchronization with the clock signal CLK. Then, the counter match detection circuit 52 stops its operation.

Subsequently, when receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 in synchronization with the clock signal CLK, and outputs the output signal OUT1 to the multiplexer 61. Output to.

The multiplexer 61 outputs the distance signal D ₁₃ (= “5”) to the counter coincidence detection circuit 51 in response to the second output signal OUT1.

Then, the counter match detection circuit 51 counts the number of clocks CN_1 (= “5”) of the clock signal CLK when the counter value CV ₁₁ that matches the distance signal D ₁₃ (= “5”) is obtained. Then, the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing of counting the clock number CN_1 (= “5”) to the switching control circuit 60 in synchronization with the clock signal CLK. Then, the counter coincidence detection circuit 51 stops its operation.

When receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and outputs the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. .

The multiplexer 62 outputs the distance signal D ₁₄ (= “1”) to the counter coincidence detection circuit 52 in response to the second output signal OUT2.

Then, the counter match detection circuit 52 counts the number of clocks CN_2 (= “1”) when the counter value CV ₁₂ that matches the distance signal D ₁₄ (= “1”) is obtained. Then, the counter coincidence detection circuit 52 outputs a coincidence signal MTH2 indicating the timing of counting the clock number CN_2 (= “1”) to the switching control circuit 60 in synchronization with the clock signal CLK. Then, the counter match detection circuit 52 stops its operation.

When receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 in synchronization with the clock signal CLK and outputs the output signal OUT1 to the multiplexer 61. Output.

The multiplexer 61 outputs the distance signal D ₁₅ (= “2”) to the counter coincidence detection circuit 51 in response to the third output signal OUT1.

Then, the counter coincidence detection circuit 51 counts the number of clocks CN_1 (= “2”) of the clock signal CLK when the counter value CV ₁₁ that coincides with the distance signal D ₁₅ (= “2”) is obtained. Then, the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing at which the number of clocks CN_1 (= “2”) is counted to the switching control circuit 60 in synchronization with the clock signal CLK. Then, the counter coincidence detection circuit 51 stops its operation.

When receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 in synchronization with the clock signal CLK and outputs the output signal OUT2 to the multiplexer 62. Output.

The multiplexer 62 outputs the distance signal D ₁₆ (= “4”) to the counter coincidence detection circuit 52 in response to the third output signal OUT2.

Then, the counter match detection circuit 52 counts the number of clocks CN_2 (= “4”) of the clock signal CLK when the counter value CV ₁₂ matching the distance signal D ₁₆ (= “4”) is obtained. Then, the counter coincidence detection circuit 52 outputs a coincidence signal MTH2 indicating the timing at which the number of clocks CN_2 (= “4”) is counted to the switching control circuit 60 in synchronization with the clock signal CLK. Then, the counter match detection circuit 52 stops its operation.

When receiving the coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 51 in synchronization with the clock signal CLK and outputs the output signal OUT1 to the multiplexer 61. Output.

The multiplexer 61 outputs the distance signal D ₁₇ (= “2”) to the counter coincidence detection circuit 51 in response to the fourth output signal OUT1.

Then, the counter coincidence detection circuit 51 counts the number of clocks CN_1 (= “2”) of the clock signal CLK when the counter value CV ₁₁ that coincides with the distance signal D ₁₇ (= “2”) is obtained. Then, the counter coincidence detection circuit 51 outputs a coincidence signal MTH1 indicating the timing at which the number of clocks CN_1 (= “2”) is counted to the switching control circuit 60 in synchronization with the clock signal CLK. Then, the counter coincidence detection circuit 51 stops its operation.

After that, when receiving the coincidence signal MTH1 from the counter coincidence detection circuit 51, the switching control circuit 60 outputs the reset signal RST to the counter coincidence detection circuit 52 and the output signal OUT2 to the multiplexer 62 in synchronization with the clock signal CLK. Output.

The multiplexer 62 outputs the distance signal D ₁₈ (= “3”) to the counter coincidence detection circuit 52 in response to the fourth output signal OUT2.

Then, the counter match detection circuit 52 counts the number of clocks CN_2 (= “3”) of the clock signal CLK when the counter value CV ₁₂ matching the distance signal D ₁₈ (= “3”) is obtained. Then, the counter coincidence detection circuit 52 outputs a coincidence signal MTH2 indicating the timing at which the clock number CN_2 (= “3”) is counted to the switching control circuit 60 in synchronization with the clock signal CLK. Then, the counter match detection circuit 52 stops its operation.

Then, in response to the fourth coincidence signal MTH2 from the counter coincidence detection circuit 52, the switching control circuit 60 has a timing signal (= timing signals C ₁ to C) indicating the same timing as that indicated by the fourth coincidence signal MTH2. Any one of _R ) is output to the Winner detector 20.

Thus, the counter coincidence detection circuits 51 and 52, alternately, respectively, the distance signal (= distance either signal odd distance signal _D 11 from _{D 11, D 13, D 15} , D 17) and the distance signal The number of clocks CN_1 of the clock signal CLK when the counter values CV ₁₁ and CV ₁₂ that coincide with (= any one of the even-numbered distance signals D ₁₂ , D ₁₄ , D ₁₆ , and D ₁₈ from the distance signal D ₁₁ ) are obtained. CN_2 is counted, and coincidence signals MTH1 and MTH2 indicating the timing when the clock numbers CN_1 and CN_2 are counted are output to the switching control circuit 60. The counter coincidence detection circuits 51 and 52 repeat this process 4 (= s) times.

Even when each of the distance / clock number conversion circuits DC ₁ to DC _R is composed of the distance / clock number conversion circuit DC ″ ₁ -2, each of the distance / clock number conversion circuits DC ₁ to DC _R is connected to the distance signal D ₁₁ = “3”, D ₁₂ = “2”, D ₁₃ = “5”, D ₁₄ = “1”, D ₁₅ = “2”, D ₁₆ = “4”, D ₁₇ = “2”, D ₁₈ = “ Indicates the timing at which the number of clocks (= “22”) of the clock signal CLK when the counter value matching the sum of 3 ”(=“ 22 ”) is obtained and the number of clocks (=“ 22 ”) is counted (either = timing signals _C 1 ~ _{C R)} timing signal output to the Winner detector 20.

Although the case where W = 8 has been described above, W may be a value other than 8 as long as 2 ⁱ is satisfied.

Even when W is other than 8 value satisfying ^{2 i,} the distance / clock number conversion circuits _DC 1 ~ DC _R are each, Winner detector timing signals _C 1 ~ _{C R} by the same operation as described above 20 output.

In the above description, the case of s = 2, 4 has been described. However, as long as s is an integer satisfying 2 ^x equal to or less than W, it may be composed of a value other than 2, 4, and in that case, distance / clock number conversion circuits _DC 1 ~ DC _R, respectively, and outputs a timing signal _C 1 ~ _{C R} to Winner detector 20 by the same operations as described above.

As described above, in FIGS. 13 and 17, each of the distance / clock number conversion circuits DC ₁ to DC _R (= distance / clock number conversion circuits DC ′ ₁ −2, DC ″ ₁ −2) has two counters. The case where the coincidence detection circuits 51 and 52 are formed has been described.

When each of the distance / clock number conversion circuits DC ₁ to DC _R includes the distance / clock number conversion circuit DC ′ _1-2 shown in FIG. 13 or the distance / clock number conversion circuit DC ″ _1-2 shown in FIG. The counter coincidence detection circuit 51 is p-th (p is an odd number satisfying 1 ≦ p <W) -th distance from one end when W distance signals (= distance signals D ₁₁ to D _1W, etc.) are arranged in a line. When receiving the signal, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the clock number CN_1 of the clock signal CLK when the counter value matching the p-th distance signal is obtained is counted, and the clock number The matching process for outputting the matching signal MTH1 indicating the timing when CN_1 is counted is repeatedly executed W / 2 times.

Further, the counter coincidence detection circuit 52 is qth (q is an even number satisfying 1 <q ≦ W) from one end when W distance signals (= distance signals D ₁₁ to D _1W, etc.) are arranged in a line. When the distance signal is received, when the counter value is counted in ascending order in synchronization with the clock signal CLK, the number of clocks CN_2 of the clock signal CLK when the counter value matching the qth distance signal is obtained is counted. The coincidence process for outputting the coincidence signal MTH2 indicating the timing of counting the number CN_2 is repeatedly executed ((W / 2) -1) times, the coincidence signal MTH1 is received W / 2 times, and the Wth distance signal is received. When the counter value is counted in ascending order in synchronization with the clock signal CLK, the clock signal CLK clock when the counter value matching the Wth distance signal is obtained. Counts the click number CN_2, outputs (either = timing signals _C 1 ~ _{C R)} timing signal indicating a timing of counting the number of clocks CN_2 to Winner detector 20.

In this case, the counter coincidence detection circuit 51 constitutes a “first counter coincidence detection circuit”, and the counter coincidence detection circuit 52 constitutes a “second counter coincidence detection circuit”.

Further, the counter 311 (or the counter 311A) of the counter coincidence detection circuit 51 constitutes a “first counter”, and the coincidence detection circuit 312 of the counter coincidence detection circuit 51 constitutes a “first coincidence detection circuit”. .

Further, the counter 311 (or the counter 311A) of the counter coincidence detection circuit 52 constitutes a “second counter”, and the coincidence detection circuit 312 of the counter coincidence detection circuit 52 constitutes a “second coincidence detection circuit”. .

As shown in FIGS. 13 and 17, each of the distance / clock number conversion circuits DC ₁ to DC _R (= distance / clock number conversion circuit DC ′ ₁ −2, DC ″ ₁ −2) is detected as two counter coincidences. by configuring the circuits 51 and 52, the distance / reduces the circuit area of the clock number conversion circuits _DC 1 ~ DC _R, power consumption can be reduced.

FIG. 19 is a diagram showing a comparison of the shortest search times. The frequency mapping type in FIG. 19 means an associative memory that searches for reference data similar to the search data by converting the distance between the search data and the reference data into a frequency.

FIG. 19A shows a comparison of the shortest search times when 64 pieces of reference data of M × W = 16 bits × 8 units = 128 bits are used. Further, FIG. 19B shows a comparison of shortest search times when 64 pieces of reference data of M × W = 16 bits × 16 units = 256 bits are used.

Referring to FIG. 19A, when 64 pieces of reference data of M × W = 16 bits × 8 units = 128 bits are used, the shortest search time is 1280 (ns) in the frequency mapping type associative memory. On the other hand, in the content addressable memory 100 of the present invention, the shortest search time is 20 (ns).

Referring to FIG. 19B, when 64 pieces of reference data of M × W = 16 bits × 16 units = 256 bits are used, the shortest search time is 210000 (ns) in the frequency mapping type associative memory. On the other hand, in the associative memory 100 of the present invention, the shortest search time is 40 (ns).

As described above, it has been experimentally proved that the associative memory 100 according to the embodiment of the present invention can search for reference data similar to the search data in a time shorter by two digits or more than the conventional frequency mapping type associative memory.

Further, it has been experimentally proved that the associative memory 100 according to the embodiment of the present invention can drastically shorten the search time as the number of bits of reference data increases.

FIG. 20 is a diagram showing a comparison of power consumption. In FIG. 20, the associative memory of the conventional example is the associative memory described in Non-Patent Document 3.

Referring to FIG. 20, 64 reference data are used in the associative memory of the conventional example, and 128 reference data are used in the associative memory 100 of the present invention.

In the conventional associative memory, the power consumption is 321 (mW), whereas in the associative memory 100 of the present invention, the power consumption is 2.13 (mW).

Thus, it has been experimentally demonstrated that the associative memory 100 according to the embodiment of the present invention can reduce power consumption by two orders of magnitude or more than the conventional associative memory although the number of reference data is twice as large. .

Therefore, it is apparent that the reference data similar to the search data can be searched at high speed with low power consumption by using the associative memory 100 according to the embodiment of the present invention.

In the above description, it has been described that k reference data similar to the search data is searched using the Manhattan distance. However, in the embodiment of the present invention, the search data is not limited to this and may be searched using the Hamming distance. You may search k similar reference data.

In this case, the M bit consists of 1 bit, and each of the reference data storage circuits SC ₁₁ to SC _1W , SC ₂₁ to SC _2W ,..., SC _R1 to SC _RW stores 1-bit reference data. Further, each of the distance calculation circuits DP ₁₁ to DP _1W , DP ₂₁ to DP _2W ,..., DP _R1 to DP _{RW determines} the distance between one bit of the search data and one bit of the reference data according to the equation (1). Calculate.

Then, the associative memory 100 searches the k reference data similar to the search data using the Hamming distance according to the above-described operation.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

This invention is applied to an associative memory.

Claims (9)

1. A reference data storage circuit for storing R (R is an integer of 2 or more) reference data each having a bit length of M × W (M is an integer of 1 or more, W is an integer of 2 or more) bits;
   R distance signals provided corresponding to the R reference data, each having a bit length of M × W bits, and representing the distance between the search data to be searched and the reference data are output. R distance calculation circuits to perform,
   The R distance arithmetic circuits are provided corresponding to the R distance arithmetic circuits, each receiving W distance signals each having a bit length of M bits from the corresponding distance arithmetic circuits, and summing the received W distance signals. R distance / clock number conversion circuits that count the number of clocks of a clock signal when a matching counter value is obtained and output a timing signal indicating a matching timing that is a timing at which the number of clocks is counted;
   Based on the R timing signals received from the R distance / clock number conversion circuits, k timing signals (k is an integer satisfying 1 ≦ k <R) are detected in order of the matching timing, An associative memory comprising: a Winner detector that outputs the detected k timing signals as a match signal indicating a similarity between the search data and the reference data.
2. Each of the R distance / clock number conversion circuits includes W counter coincidence detection circuits provided corresponding to W distance signals each having a bit length of M bits and connected in series. Including
   The W counter coincidence detection circuits, when W = 2,
   Provided in correspondence with the first distance signal which is the distance signal at one end when the W distance signals are arranged in a line, and upon receiving the first distance signal, the counter value is synchronized with the clock signal. When counting in ascending order, the first clock number of the clock signal when the counter value that matches the received first distance signal is obtained is counted, and the timing at which the first clock number is counted is shown. A first counter match detection circuit for outputting a first match signal;
   The counter is provided corresponding to the Wth distance signal from the one end, and is driven when receiving the first coincidence signal from the first counter coincidence detection circuit and receives the Wth distance signal, When counting in ascending order in synchronization with the clock signal, the second clock number of the clock signal when the counter value corresponding to the received Wth distance signal is obtained is counted, and the second clock number is calculated. A second counter coincidence detection circuit that outputs the timing signal indicating the counted timing to the Winner detector;
   The W counter coincidence detection circuits, when W is 3 or more,
   The first counter coincidence detection circuit;
   Provided corresponding to W-2 distance signals from the second distance signal to the W-1th distance signal, each of which is the first counter coincidence detection circuit or w-1 (w is 2 ≦ w). ≦ integer satisfying W−1) The number of clock signals when the counter value corresponding to the first or wth distance signal is obtained from the counter coincidence detection circuit provided corresponding to the first distance signal. When the second coincidence signal indicating the counted timing is received and the wth distance signal is driven and the counter value is counted in ascending order in synchronization with the clock signal, the received wth distance signal is received. Counts the third clock number of the clock signal when a counter value that coincides with is obtained, and outputs a third coincidence signal indicating the timing of counting the third clock number. A number of third counter match detection circuit,
   When the third coincidence signal is received from the counter coincidence detection circuit provided corresponding to the Wth distance signal and corresponding to the W-1th distance signal, the Wth distance signal is driven. When the counter value is counted in ascending order in synchronization with the clock signal, the fourth clock number of the clock signal when the counter value matching the received Wth distance signal is obtained is counted, The content addressable memory according to claim 1, further comprising: a fourth counter coincidence detection circuit that outputs the timing signal indicating the timing at which the fourth clock number is counted to the Winner detector.
3. The first counter match detection circuit includes:
   A first counter that counts M bit values in ascending order and sequentially outputs the counted counter values;
   The first clock number when the counter value is sequentially received from the first counter and the first distance signal is received from the distance calculation circuit, and the received counter value matches the first distance signal. And a first coincidence detection circuit that outputs the first coincidence signal when the first clock number is obtained,
   The second counter coincidence detection circuit includes:
   A second counter that counts the bit values of M bits in ascending order and sequentially outputs the counted counter values;
   The counter value is sequentially received from the second counter, the Wth distance signal is received from the distance calculation circuit, and the first match signal is received from the first counter match detection circuit. The second clock number when the counter value matches the Wth distance signal is counted, and when the second clock number is obtained, the timing signal is output to the Winner detector. A coincidence detection circuit,
   Each of the W-2 third counter coincidence detection circuits includes:
   A third counter that counts the bit values of M bits in ascending order and sequentially outputs the counted counter values;
   The counter value is sequentially received from the third counter, and the w-th distance signal is received from the distance calculation circuit. The second counter signal is driven, and the received counter value is the w-th distance. A third coincidence detection circuit that counts the third clock number when the signal coincides with a signal and outputs the third coincidence signal when the third clock number is obtained;
   The fourth counter coincidence detection circuit includes:
   A fourth counter that counts the bit values of M bits in ascending order and sequentially outputs the counted counter values;
   The counter value is sequentially received from the fourth counter, and the W-th distance signal is received from the distance calculation circuit. The counter value is driven when the third coincidence signal is received, and the received counter value is the W-th distance. 4. A fourth coincidence detection circuit that counts the fourth clock number when it coincides with a signal and outputs the timing signal to the Winner detector when the fourth clock number is obtained. 2. The associative memory according to 2.
4. W is composed of 2 ⁱ (i is an integer of 2 or more),
   Each of the R distance / clock number conversion circuits is provided corresponding to W / s (s is equal to 2 ^x which is less than or equal to W. x is a positive integer) number of distance signals, each of which is M bits. W / s counter coincidence detection circuits that output the timing signal based on W distance signals having a bit length of
   When each of the W / s counter coincidence detection circuits receives s sets of distance signals each composed of the W / s distance signals, the counter value is counted in ascending order in synchronization with the clock signal. The number of clocks is counted when a counter value corresponding to the sum of W distance signals included in the received s sets of distance signals is obtained, and the timing signal indicating the timing at which the number of clocks is counted is detected by the Winner. The associative memory according to claim 1, wherein the associative memory outputs to a storage device.
5. When the W / s counter coincidence detection circuits receive the W / s distance signals, the received W / s distance signals are counted when the counter values are counted in ascending order in synchronization with the clock signal. The process of counting the first clock number of the clock signal when the counter value matching the sum of the two is obtained and outputting the first coincidence signal indicating the timing at which the first clock number is counted is performed s-1 times. When repeatedly executed, outputting the first coincidence signal s-1 times and receiving the W / s distance signals for the sth time, the counter value is counted in ascending order in synchronization with the clock signal. In addition, the second clock number of the clock signal when a counter value matching the sum of the received W / s distance signals is obtained is counted, and the timing indicating the timing when the second clock number is counted is counted. And it outputs a timing signal to the Winner detector, content addressable memory of claim 4.
6. The W / s counter match detection circuits are:
   When receiving the p-th (p is an odd number satisfying 1 ≦ p <W) distance from one end when the W distance signals are arranged in a line, the counter values are counted in ascending order in synchronization with the clock signal. When the counter value matching the p-th distance signal is obtained, the third clock number of the clock signal is counted, and the second coincidence signal indicating the timing when the third clock number is counted is output. A first counter coincidence detection circuit that repeatedly executes the first coincidence process W / 2 times;
   When q (q is an even number satisfying 1 <q ≦ W) from the one end, when the counter value is counted in ascending order in synchronization with the clock signal, it coincides with the qth distance signal. A second coincidence process ((W / 2) is performed, which counts the fourth clock number of the clock signal when the counter value is obtained, and outputs a third coincidence signal indicating the timing at which the fourth clock number is counted. ) -1) Repeated execution, receiving the second coincidence signal W / 2 times, and receiving the Wth distance signal, when the counter value is counted in ascending order in synchronization with the clock signal, The fifth clock number of the clock signal when the counter value matching the W-th distance signal is obtained is counted, and the timing signal indicating the timing at which the fifth clock number is counted is represented by the W signal. And a second counter coincidence detection circuit for outputting to the nner detector, content addressable memory of claim 4.
7. Each of the R distance / clock number conversion circuits includes:
   When the second match signal is received from the first counter match detection circuit, the received second match signal is output to the second counter match detection circuit, and the second counter match detection circuit outputs the second match signal. A switching control circuit for receiving the third coincidence signal and outputting the received third coincidence signal to the first counter coincidence detection circuit;
   The first counter coincidence detection circuit executes the first coincidence process once every time it receives the third coincidence signal from the switching control circuit,
   The second counter coincidence detection circuit executes the second coincidence process once every time it receives the second coincidence signal from the switching control circuit, and outputs the second coincidence signal W / 2 times. 7. The content addressable memory according to claim 6, wherein upon receipt, the fifth clock number is counted and the timing signal is output to the Winner detector.
8. The first counter match detection circuit includes:
   A first counter that counts M-bit bit values in ascending order and sequentially outputs the counted counter values W / 2 times;
   When the counter value is sequentially received from the first counter and the p-th distance signal is received from the distance calculation circuit, and the counter value is counted in ascending order in synchronization with the clock signal, the received counter value is a first coincidence detection circuit that counts the third clock number when coincident with the p-th distance signal and repeatedly executes the second output process of outputting the second coincidence signal W / 2 times; Including
   The second counter coincidence detection circuit includes:
   A second counter that counts the bit values of M bits in ascending order and repeatedly executes a third output process for sequentially outputting the counted counter values W / 2 times;
   When the counter value is sequentially received from the second counter and the qth distance signal is received from the distance calculation circuit, and the counter value is counted in ascending order in synchronization with the clock signal, the received counter value is counting the number of the fourth clocks when they coincide with the qth distance signal, and repeating the ((W / 2) -1) times of the second output processing for outputting the third coincidence signal, When the second coincidence signal is received W / 2 times, the fifth clock number when the received counter value coincides with the Wth distance signal is counted, and the timing signal is detected by the Winner detector. The content addressable memory of Claim 6 or Claim 7 including the 2nd coincidence detection circuit which outputs to.
9. Each of the first to fourth counters includes M frequency dividers that output M-bit counter values in ascending order,
   The frequency divider that outputs the m-th bit value (m is an integer satisfying 1 ≦ m ≦ M) in the direction from the least significant bit to the most significant bit of the M-bit counter value outputs the clock signal to 2 ^m−. The content addressable memory according to claim 3 or 8, wherein a signal divided by ^one time is output.

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