WO2022181507A1 - Control device - Google Patents

Abstract

A control device (103) for memory included in a device for realizing a stochastic computing calculating mechanism is provided with: a write interface (11) into which a spike train is input; a read interface (12) which outputs the spike train; and shift circuits (13-0 to 13-15). The shift circuits (13-0 to 13-15) read and write levels held by each thereof to memory cells (c0-0 to c0-15, c1-0 to c1-15, c2-0 to c2-15).

Description

Control device

The present disclosure relates to a controller for memory.

A stochastic computing (SC) computing mechanism (hereinafter referred to as an SC computing mechanism) performs information processing based on spike trains (for example, Patent Document 1). More specifically, the SC calculator performs arithmetic processing based on spike trains and memory processing based on spike trains.

Japanese Patent Application Laid-Open No. 2020-38300

In the device that implements the SC calculation mechanism, when performing memory processing based on spike trains, it is preferable that the spike trains are written to the memory as they are, and the spike trains are read from the memory as they are.

An object of one aspect of the present disclosure is to realize a control device for memory having a novel configuration that enables a spike train to be written to the memory as it is, and a spike train to be read from the memory as it is.

In order to solve the above problems, a control device according to one aspect of the present disclosure is a control device for a memory included in a device that implements a stochastic computing computing mechanism, and is a write memory to which a spike train is input. an interface, a read interface to which a spike train is output, and a plurality of shift circuits each holding a level of a signal input thereto, wherein the plurality of shift circuits are connected to the write interface and the read interface. between the two adjacent shift circuits, the shift circuit located on the write interface side shifts the level held by the shift circuit to the shift circuit located on the read interface side. circuit, each of said shift circuits being connected to a plurality of memory cells capable of being written to and read from the level held in each of said shift circuits; When input to the control device, each shift circuit directs the level of each digit of the spike train sequentially input from the write interface to the read interface from the write interface side, After shifting between the two adjacent shift circuits and holding the level of each of the digits in the corresponding shift circuit, the level held by each of the shift circuits is transferred to the level of the digit connected to each of the shift circuits. (ii) when the controller outputs a spike train from the read interface, each shift circuit reads the level of each digit from the memory cell connected to each shift circuit; , after the levels of the respective digits are held in the corresponding shift circuits, the levels held in the respective shift circuits are transferred from the write interface side to the read interface side to two adjacent digits. It is moved between the shift circuits.

According to one aspect of the present disclosure, it is possible to provide a control device for memory that has a novel configuration.

1 is a diagram showing a schematic configuration of a device that implements an SC calculation mechanism according to Embodiment 1 of the present disclosure; FIG. 1 is a diagram illustrating configurations of a control device and a storage device according to Embodiment 1 of the present disclosure; FIG. FIG. 10 is a diagram showing each configuration of a control device and a storage device according to Embodiment 3 of the present disclosure; FIG. 10 is a diagram showing each configuration of a control device and a storage device according to Embodiment 4 of the present disclosure; FIG. 13 is a diagram showing each configuration of a control device and a storage device according to Embodiment 5 of the present disclosure; FIG. 10 is a diagram showing each configuration of a control device and a storage device according to Embodiment 6 of the present disclosure; FIG. 13 is a diagram showing a schematic configuration of a device that implements an SC calculation mechanism according to Embodiment 7 of the present disclosure; FIG. 12 is a diagram for explaining the configuration of a control device according to an eighth embodiment of the present disclosure; FIG. 4 is a timing chart of clock signals input to each of a control device and a storage device according to Embodiment 1 of the present disclosure;

[Overview of the present disclosure]
Research has begun on information processing based on spike trains in SC computing mechanisms. However, most of the current researches focus on arithmetic processing in information processing based on spike trains, and there is no research that focuses on memory processing.

In current research, regarding arithmetic processing based on spike trains, a configuration has already been realized in which the spike train is directly input to the computing unit, and the spike train is directly output from the computing unit. On the other hand, as for memory processing based on spike trains, a configuration in which spike trains are written to memory as they are and read from memory as they are has not yet been realized. In this specification, the term "as is" means that the spike train is not subjected to any processing. For example, "the spike train is directly input to the calculator" means that the spike train is input to the calculator without performing any processing on the spike train.

Current research proposes a configuration that uses conventional memory for memory processing based on spike trains. In this proposed configuration, the spike train output from the calculator is input to a bit number counter located outside the conventional memory. Then, the count value output from the bit number counter is written to the conventional memory. Meanwhile, data read from the conventional memory is input to a spike generator located external to the conventional memory. A spike train is output from the spike generator. A spike train output from the spike generator is input to the calculator.

As described above, in the current research, with regard to memory processing based on spike trains, when writing spike trains to conventional memory, the above-mentioned bit number counter and spike generator are used to perform predetermined processing on spike trains. It is necessary. However, it is preferred that the bit number counter and spike generator are not required. This is because if the bit number counter and the spike generator are not required, it is possible to reduce hardware and increase the speed of data processing in the device that implements the SC calculation mechanism.

In view of the current research results, the present disclosure parties are earnestly working to realize a configuration that enables spike trains to be directly written to memory and spike trains to be read from memory as they are, even with regard to memory processing based on spike trains. As a result of examination, the present disclosure was invented.

Note that each embodiment will be described below by taking as an example a control device for a memory included in a device that implements the SC calculation mechanism. However, the device including the control device according to each embodiment is not limited to the device that implements the SC calculation mechanism.

[Embodiment 1]
An embodiment of the present disclosure will be described in detail below. In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals.

FIG. 1 is a schematic configuration diagram of a device 100 including a control device 103 according to Embodiment 1 of the present disclosure. As shown in FIG. 1 , the device 100 includes an arithmetic device 101 , a storage device 102 and a control device 103 . Device 100 is a device that implements an SC calculation mechanism.

<Structure of Device for Realizing SC Calculation Mechanism>
(arithmetic unit)
The computing device 101 includes a plurality of computing units (not shown). A spike train is directly input to each calculator. Each calculator performs various calculations based on the spike train input to the calculator. Each arithmetic unit outputs the spike train as it is, which is the arithmetic result of the arithmetic unit.

Here, a spike train is a pattern of spikes emitted at predetermined time intervals. The predetermined time interval is the time interval from the timing when the first spike occurs to the timing when the next spike occurs with respect to two consecutive spikes.

Note that in the first embodiment, the number of spikes forming a spike train is two or more. It is also assumed that the time intervals between the generation timings of two consecutive spikes are the same. However, the present disclosure is not limited to the number of spikes and time intervals described above.

Also, in the first embodiment, the presence or absence of occurrence of spikes forming a spike train is represented by "1" level and "0" level. More specifically, the occurrence of a spike is represented by "1" level. A "0" level represents no spike occurrence. Also, the generation timing of the spike train is the generation timing of the first spike. For example, if the number of spikes is 2, the spike train is represented by "1010". In this case, the arithmetic unit 101 sequentially outputs a "1" level signal, a "0" level signal, a "1" level signal, and a "0" level signal in this order at predetermined time intervals. If the spike train generation timing is set to be before the first spike generation timing, the spike train is represented by "0101". In the present application, "1" represents a positive logic value corresponding to a high level voltage, and "0" represents a negative logic value corresponding to a low level voltage.

As shown below, numerical values can be expressed using the presence or absence of spikes that make up a spike train.

(1) Numerical values are expressed based on the number of spikes that occurred counting from a predetermined timing that is the starting point. For example, a numerical value of "1" based on the occurrence of the first spike, a numerical value of "2" based on the occurrence of the second spike, a numerical value of "3" based on the occurrence of the third spike, Each can be expressed

(2) The clock signal is counted from a predetermined timing, which is the starting point, and when a spike occurs at the rise of the clock signal, a numerical value is expressed based on the number of counts at the time of occurrence of the spike. For example, if the number of counts at the time when a spike occurs in accordance with the rising edge of the clock signal is 2, the numerical value "2" can be expressed based on the number of counts.

(3) A numerical value is expressed based on the number of clock signals counted during the period in which one spike is generated. For example, if the number of counts during a period in which one spike is occurring is two, a numerical value of "2" can be expressed based on the number of counts.

(Storage device)
The memory device 102 includes a plurality of memory cells (not shown). Each memory cell is an element that stores either a "1" level or a "0" level. Each memory cell is a writable and readable semiconductor memory cell. Each memory cell is, for example, an SRAM (Static Random Access Memory) memory cell, which is a known semiconductor memory cell. The memory device 102 has a structure in which a plurality of memory cells are arranged two-dimensionally and regularly in an array. This configuration is hereinafter referred to as a memory cell array.

The spike train is input to the storage device 102 as it is. Each memory cell of the memory cell array of storage device 102 stores whether or not a spike occurs in the spike train input to that memory cell. In addition, the memory device 102 outputs the spike train, which is the result of reading from each memory cell, as it is. The read result is the occurrence or non-occurrence of the spike stored in each memory cell.

In the first embodiment, each memory cell stores the presence or absence of a spike in a spike train input to the storage device 102 as "1" level and "0" level, as will be described later. In the first embodiment, each memory cell stores "1" level when a spike occurs, and "0" level when no spike occurs. However, in the present disclosure, each memory cell may store occurrence of a spike as "0" level and store no spike as "1" level.

For example, let the spike train input to the storage device 102 be "0101". In this case, a "1" level signal, a "0" level signal, a "1" level signal, and a "0" level signal are sequentially input to the storage device 102 at predetermined time intervals. . The memory device 102 stores the levels of the sequentially input signals in memory cells selected from the memory cell array. Each signal level is stored in a different memory cell.

(Control device)
The control device 103 outputs the spike train, which is the calculation result of the calculation device 101, to the storage device 102 as it is. Further, the control device 103 outputs the spike train read from the storage device 102 to the arithmetic device 101 as it is.

<Configuration and operation of control device>
The configuration and operation of the control device 103, which is a feature of the present disclosure, will be described in detail below. Regarding the configuration and operation of each of the arithmetic device 101 and the storage device 102, only the content necessary for explaining the configuration and operation of the control device 103 will be described, and the other description will be omitted.

(Constitution)
FIG. 2 is a diagram showing the circuit configuration of the control device 103. As shown in FIG. Various members of the storage device 102 are also shown in FIG. 2, but as described above, descriptions of members unrelated to the control device 103 are omitted.

As shown in FIG. 2, the control device 103 includes a write interface 11, a read interface 12, and shift circuits 13-0, 13-1, . . . , 13-14, 13-15. The shift circuits 13-0, 13-1, . The shift circuits 13-15, 13-14, .

Also, as shown in FIG. 2, the memory device 102 includes the memory cell array 51 described above, a peripheral circuit 52, an address generation circuit 53, and a memory interface . Note that the memory interface 54 is not an essential element of the storage device 102 . The memory interface 54 is an interface used when writing data to the storage device 102 without going through the control device 103 . However, by providing the memory interface 54 in the storage device 102, the function of the storage device 102 can be verified, and the convenience of the storage device 102 and compatibility with conventional systems can be improved.

Here, it should be noted that the clock signal CK is input to the control device 103 and the clock signal CK2 is input to the storage device 102, as shown in FIG. Data is input/output to/from the storage device 102 in synchronization with the clock signal CK2, as will be described later. Data is input/output to/from the control device 103 in synchronization with the clock signal CK, as will be described later.

　Fig. 9 shows a timing chart of the clock signal CK and a timing chart of the clock signal CK2. As shown in FIG. 9, the interval between the rising edges T of the clock signal CK is smaller than the interval between the rising edges T2 of the clock signal CK2. That is, the cycle of the clock signal CK is shorter than the cycle of the clock signal CK2. In other words, it can be said that the clock signal CK is a high frequency clock signal and the clock signal CK2 is a low frequency clock signal.

As described above, the memory device 102 requires known memory cell writing and reading. Therefore, the storage device 102 performs low speed operations based on the clock signal CK2.

On the other hand, unlike the storage device 102, the control device 103 does not need to write and read known memory cells. Therefore, the control device 103 performs high-speed operations based on the clock signal CK.

The memory cell array 51 includes a plurality of memory cells c0-0 to c2-0, c0-1 to c2-1, . . . , c0-14 to c2-14 and c0-15 to c2-15. The peripheral circuit 52 includes read circuits R0 to R15 and write circuits W0 to W15. Memory cells c0-0 to c2-0, c0-1 to c2-1, . . The read circuits R0 to R15 and the write circuits W0 to W15 are collectively referred to as a read circuit R and a write circuit W, respectively.

The memory cells c0-0 to c2-0 are connected to the read circuit R0 and the write circuit W0 via the bit line BL0 and the bit line XBL0, respectively. The memory cells c0-1 to c2-1 are connected to a read circuit R1 and a write circuit W1 via bit lines BL1 and XBL1, respectively. The memory cells c0-14 to c2-14 are connected to a read circuit R14 and a write circuit W14 via bit lines BL14 and XBL14, respectively. The memory cells c0-15 to c2-15 are connected to a read circuit R15 and a write circuit W15 via bit lines BL15 and XBL15, respectively. Hereinafter, bit lines BL0 to BL15 and bit lines XBL0 to XBL15 are collectively referred to as bit lines XBL.

The address generation circuit 53 has row addresses WL0 to WL2. Address generation circuit 53 generates memory cells c0-0 to c2-0, c0-1 to c2- from memory cell array 51 using row addresses WL0 to WL2, bit lines BL0 to BL15, and bit lines XBL0 to XBL15. 1, ..., c0-14 to c2-14 and c0-15 to c2-15.

Although the total number of shift circuits 13 is 16 in the first embodiment, the present disclosure is not limited to this number. The reason why the total number of shift circuits 13 is set to 16 in the first embodiment is that each arithmetic unit of the arithmetic unit 101 is assumed to be designed on the premise of a 16-bit CPU (Central Processing Unit). Since the total number of shift circuits 13 is 16, the total number of read circuits R, write circuits W, bit lines BL, and bit lines XBL is also 16. In the memory cell array 51, 48 memory cells c are arranged in an array of 3 rows×16 columns. Since the total number of shift circuits 13 is 16, the total number of columns is also 16. On the other hand, although the total number of rows is three, the present disclosure is not limited to this number.

The writing interface 11 is an interface for connecting the arithmetic device 101 and the control device 103 in FIG. The write interface 11 has an input terminal connected to the output terminal of the arithmetic unit 101 of FIG. A spike train is input to the input terminal of the write interface 11 . The spike train is the calculation result of the calculation device 101 .

The write interface 11 has an output terminal connected to the input terminals of the shift circuits 13-15. More specifically, the write interface 11 has a pair of output terminals. The output signal of one output terminal is the BLi signal. The output signal of the other output terminal is the XBLi signal. The level of the BLi signal and the level of the XBLi signal are complementary. That is, if the level of the BLi signal is "1" level, the level of the XBLi signal is "0" level. Conversely, if the level of the BLi signal is "0" level, the level of the XBLi signal is "1" level.

When a spike train is input to the input terminal of the write interface 11, the write interface 11 outputs the BLi signal from one output terminal of the write interface 11 and outputs the XBLi signal from the other output terminal of the write interface 11. Output a signal.

For example, let the spike train input to the write interface 11 be "1010". In this case, a "1" level signal, a "0" level signal, a "1" level signal, and a "0" level signal are sequentially input to the write interface 11 at predetermined time intervals. be. When the first "1" level signal is input, the write interface 11 outputs a "1" level BLi signal and a "0" level XBLi signal. When the second "0" level signal is input, the write interface 11 outputs a "0" level BLi signal and a "1" level XBLi signal. When the third "1" level signal is input, the write interface 11 outputs a "1" level BLi signal and a "0" level XBLi signal. When the last "0" level signal is input, the write interface 11 outputs a "0" level BLi signal and a "1" level XBLi signal.

The readout interface 12 is an interface for connecting the arithmetic device 101 and the control device 103 in FIG. The readout interface 12 has an output terminal connected to the input terminal of the arithmetic unit 101 of FIG. A spike train is output from the output terminal of the readout interface 12 . The spike train is a spike train read from the memory cell array 51 of the memory device 102 . The read spike train is an object of computation by the computation device 101 .

The readout interface 12 has an input terminal connected to the output terminal of the shift circuit 13-0. More specifically, readout interface 12 comprises a pair of input terminals. The input signal of one input terminal is the BLo signal. The input signal at the other input terminal is the XBLo signal. The levels of the BLo and XBLo signals are complementary. That is, if the level of the BLo signal is "1" level, the level of the XBLo signal is "0" level. Conversely, if the level of the BLo signal is "0" level, the level of the XBLo signal is "1" level.

When the BLo signal is input to one input terminal of the readout interface 12 and the XBLo signal is input to the other input terminal of the readout interface 12, the output terminal of the readout interface 12 outputs Output a spike train.

For example, let the spike train output from the readout interface 12 be "1010". In this case, the reading interface 12 sequentially outputs a "1" level signal, a "0" level signal, a "1" level signal, and a "0" level signal in this order at predetermined time intervals. be. When the read interface 12 receives a "1" level BLo signal and a "0" level XBLo signal, it first outputs a "1" level signal. The read interface 12 outputs a second "0" level signal when a "0" level BLo signal and a "1" level XBLo signal are input. The read interface 12 outputs a third "1" level signal when a "1" level BLo signal and a "0" level XBLo signal are input. The read interface 12 outputs the final "1" level signal when the "0" level BLo signal and the "1" level XBLo signal are input.

Each of the shift circuits 13 has the same configuration. The shift circuits 13 are arranged between the write interface 11 and the read interface 12 in the order of shift circuits 13-15, 13-14, . . . , 13-1, 13-0. The shift circuit 13 holds the level of the signal input to each shift circuit 13, as will be described later. Between two adjacent shift circuits 13, the shift circuit 13 located on the write interface 11 side shifts the level held by the shift circuit 13 to the shift circuit 13 located on the read interface 12 side.

The shift circuit 13-15 includes a pair of input terminals, a pair of output terminals, a gate G15, a latch L15, and a buffer B15. A pair of input terminals is connected to each output terminal of the write interface 11, respectively. A pair of output terminals are connected to respective input terminals of the shift circuits 13-14. The shift circuit 13-14 is a shift circuit after the shift circuit 13-15.

The gate G15 includes a first switching element g15-1 and a second switching element g15-2. Both the first switching element g15-1 and the second switching element g15-2 are, for example, known semiconductor transistors. Each of the first switching element g15-1 and the second switching element g15-2 becomes conductive when the clock signal CK rises, and becomes non-conductive when the clock signal CK falls.

The latch L15 holds two complementary levels that are input to the latch L15. For example, if the level input to latch L15 is "1" level, latch L15 holds "1" level. On the other hand, if the level input to latch L15 is "0" level, latch L15 holds "0" level.

The buffer B15 includes a first buffer b15-1 and a second buffer b15-2. The first buffer b15-1 and the second buffer b15-2 are composed of known semiconductor elements, for example. The first buffer b15-1 outputs one of the two complementary levels held by the latch L15 to one output terminal of the shift circuit 13-15. The second buffer b15-2 outputs the other of the two complementary levels held by the latch L15 to the other output terminal of the shift circuit 13-15. Both the first buffer b15-1 and the second buffer b15-2 shift the level only in the direction from the shift circuit 13-15 to the shift circuit 13-14.

The shift circuits 13-14 to 13-0 differ from the shift circuit 13-15 as follows. That is, each input terminal of each of the shift circuits 13-14 to 13-0 is connected to each output terminal of the shift circuit in the preceding stage of each of the shift circuits 13-14 to 13-0. For example, each input terminal of the shift circuits 13-14 is connected to each output terminal of a shift circuit 13-15, which is a shift circuit preceding the shift circuit 13-14.

However, the shift circuit 13-0 differs from the shift circuit 13-15 in the following points. That is, as described above, each output terminal of the shift circuit 13-0 is connected to each input terminal of the read interface 12, respectively.

Although FIG. 2 also shows members constituting each of the shift circuits 13-0 to 13-14, the description of each member is omitted. Also, each member whose explanation is omitted corresponds to each member of the shift circuits 13 to 15, with the number following the alphabet of the reference numeral attached to each corresponding to "15". Further, by such replacement, when understanding each member of the shift circuits 13-0 to 13-14, the above description of each member of the shift circuit 13-15 can be easily referred to. For example, in the case of a member with the code B14, by replacing the letter "B" followed by "14" with "15", the member is a buffer corresponding to the buffer B15 of the shift circuit 13-15. It is understood that

Also, when collectively referring to the members that make up the shift circuit 13, the letters attached to the members will be used. For example, the gates G0, G1, G14, and G15 of the shift circuit 13 are collectively referred to as a gate G.

(motion)
The operation of the control device 103 will be described below. The controller 103 has write and read operations. The write operation will be described first, and then the read operation will be described.

1. Write Operation The write operation of the control device 103 will be described with reference to FIG. A case where a spike train represented by "0000111101000001" (hereinafter referred to as "spike train A") is input to the write interface 11 will be described below as an example. Spike train A is a 16-bit spike train. A spike train A is a calculation result of the calculation device 101 . In addition, the writing interface 11 outputs the level of the first digit (=1), the level of the second digit (=0), the level of the third digit (=0), and the level of the spike train A at predetermined time intervals. . . , the level of the 15th digit (=0) and the level of the 16th digit (=0) are input in order.

(1) Input of the level of the first digit (=1) of the spike train A When the level of the first digit (=1) of the spike train A is input to the write interface 11, the write interface 11 outputs one signal. A "1" level BLi signal and a "0" level XBLi signal are output from each of the terminals.

Next, when the clock signal CK rises, the first switching element g15-1 and the second switching element g15-2 of the gate G15 of the shift circuit 13-15 become conductive. When the first switching element g15-1 and the second switching element g15-2 are turned on, the "1" level of the BLi signal and the "0" level of the XBLi signal are input to the latch L15. Latch L15 holds "1" level and "0" level. The clock signal CK falls again, and the first switching element g15-1 and the second switching element g15-2 become non-conductive again.

Note that the clock signal CK is normally stable in the falling state. The clock signal CK instantaneously rises and falls again in synchronization with the timing at which the level of each digit of the spike train A is input to the write interface 11 . In addition, the clock signal CK is normally stabilized in a rising state, momentarily falls in synchronization with the timing when the level of each digit of the spike train A is input to the write interface 11, and then falls again. can be However, in this case, the first switching element g15-1 and the second switching element g15-2 become conductive when the clock signal CK falls, and become non-conductive again when the clock signal CK rises.

When the clock signal CK rises, each of the first switching elements g0-1 to g14-1 and each of the second switching elements g0-2 of the gates 0 to 14 in each of the shift circuits 13-0 to 13-14. ∼g14-2 also become conductive. When the clock signal CK falls, each of the shift circuits 13-0 to 13-14 also switches between the first switching elements g0-1 to g14-1 and the second switching elements g0-1 of the gates G0 to G14. 2 to g14-2 also become non-conducting.

The first buffer b15-1 of the buffer B15 outputs the "1" level held in the latch L15 to one output terminal of the shift circuit 13-15. The second buffer b15-2 of the buffer B15 outputs the "0" level held in the latch L15 to the other output terminal of the shift circuit 13-15. Since the first switching element g14-1 and the second switching element g14-2 of the gate G14 of the shift circuit 13-14 are in a non-conducting state, each level output to each of the pair of output terminals of the shift circuit 13-15 is not input to the latch L14 of the shift circuit 13-14.

Thus, when the level of the first digit (=1) of the spike train A is input to the write interface 11, the latch L15 of the shift circuit 13-15 holds the "1" level and the "0" level. be. The level held in the latch L15 is originally the "1" level, which is the level of the first digit (=1) of the spike train A. The "0" level is the complementary level of the "1" level. In order to simplify the explanation, only the level of each digit of the spike train A will be used when describing the level held in the latch L15, and the complementary level will be omitted. . The same applies to latches L0-L14.

(2) Input of the level of the second digit (=0) of the spike train A Next, when the level of the second digit (=0) of the spike train A is input to the write interface 11, the write interface 11 A "0" level BLi signal and a "1" level XBLi signal are output from each of the single output terminals.

Next, when the clock signal CK rises, in the shift circuit 13-15, the first switching element g15-1 and the second switching element g15-2 of the gate G15 of the shift circuit 13-15 become conductive. When the first switching element g15-1 and the second switching element g15-2 become conductive, the "0" level of the BLi signal and the "1" level of the XBLi signal are input to the latch L15. Latch L15 holds "0" level and "1" level.

In addition, in the shift circuit 13-14, the first switching element g14-1 and the second switching element g14-2 of the gate G14 of the shift circuit 13-14 become conductive. When the first switching element g14-1 and the second switching element g14-2 become conductive, the "1" level and the "0" level output from the pair of output terminals of the shift circuit 13-15 are latched L14. is entered in Latch L14 holds "1" level and "0" level.

The clock signal CK falls again, the first switching element g15-1 and the second switching element g15-2 of the gate G15 of the shift circuit 13-15, and the first switching element g14- of the gate G14 of the shift circuit 13-14. 1 and the second switching element g14-2 become non-conducting again.

In this way, when the level of the second digit (=0) of the spike train A is input to the write interface 11, the latch L15 of the shift circuit 13-15 is set to level "0", that is, the two digits of the spike train A Eye level is maintained. Also, the latch L14 of the shift circuit 13-14 holds the "1" level, that is, the level of the first digit of the spike train A. FIG.

The operation of the control device 103 until the level of the second digit (=0) of the spike train A is input to the write interface 11 has been described above. The operation of the control device 103 when the third and subsequent digit levels of the spike train A are input to the write interface 11 is also performed in the same manner.

For example, when the level of the third digit of spike train A is input to write interface 11, the level of the third digit of spike train A is applied to latch L15 of shift circuit 13-15 and latch L14 of shift circuit 13-14. The level of the second digit of the spike train A is held in , and the level of the first digit of the spike train A is held in the latch L13 of the shift circuit 13-13.

Similarly, when the level of the (N)th digit (N: any natural number from 4 to 15) of the spike train A is input to the write interface 11, the spike train A is input to the latch L15 of the shift circuit 13-15. The (N-1)th digit level of the spike train A is applied to the latch L14 of the shift circuit 13-14. ) digit level is at the latch L(N-1) of the shift circuit 13-(N-1), and the level of the 2nd digit of the spike train A is at the latch L of the shift circuit 13-(N). (N) holds the level of the first digit of the spike train A, respectively.

In this way, when the levels of the digits of the spike train A are sequentially input to the write interface 11, the latches of the shift circuits 13-15 are not changed until the input of all the levels of the digits of the spike train A is completed. The level of the 16th digit of the spike train A is stored in L15, the level of the 15th digit of the spike train A is stored in the latch L14 of the shift circuit 13-14, and the level of the spike train A is stored in the latch L1 of the shift circuit 13-1. The level of the second digit and the level of the first digit of the spike train A are held in the latch L0 of the shift circuit 13-0. That is, the control device 103 holds all the levels of the digits of the spike train A.

After holding all the levels of the digits of the spike train A, the control device 103 stores the levels of the digits of the spike train A in each memory cell selected from the memory cell array 51 of the storage device 102 . Here, an example in which the level of each digit of the spike train A is stored in the memory cells c1-0 to c1-15 in the memory cell array 51 will be described.

Here, each frequency of the clock signal CK and the clock signal CK2 can be determined as follows, for example. Here, each configuration of the control device 103 and the storage device 102 shown in FIG. 2 will be described as an example.

In the example of FIG. 2, the control device 103 has 16 shift circuits 13 . Therefore, in order to hold the level in all the latches of each shift circuit 13, each first switching element g0-1 to g15-1 and each second switching element g0-2 to g15- of each gate G0 to G15 2 must be made conductive 16 times. That is, the clock signal CK rises 16 times.

On the other hand, the control device 103 executes a read operation, which will be described later, after all the latches of the shift circuits 13 of the control device 103 hold the levels. At this time, the read operation is executed for the storage device 102 at the rising timing of the clock signal CK2.

That is, in the example of FIG. 2, the clock signal CK2 rises once every time the clock signal CK rises 16 times. Therefore, the frequency of the clock signal CK needs to be 16 times the frequency of the clock signal CK2. It goes without saying that the present disclosure does not limit the ratio between the frequency of the clock signal CK and the frequency of the clock signal CK2 to "16 times". The above ratio is changed according to the number of shift circuits 13 of the control device 103 . Also, the above ratio is changed depending on the performance of the hardware that constitutes each of the control device 103 and the storage device 102 .

The address generation circuit 53 of the storage device 102 sets the row address WL1 to "1" level. On the other hand, the address generation circuit 53 sets the row addresses WL0 and WL2 to "0" level.

Here, first, the "0" level held in the latch L15 of the shift circuit 13-15 of the control device 103, that is, the level of the 16th digit of the spike train A is changed to the memory cell c1- of the memory cell array 51 of the storage device 102. 15 will be explained. As described above, the latch L15 holds the "0" level of the 16th digit of the spike train A as well as the "1" level, which is the complementary level of the "0" level.

The "0" level held in the latch L15 is input to the bit line BL15 via the write circuit W15. Also, the "1" level held in the latch L15 is input to the bit line XBL15 via the write circuit W15. Here, since the row address WL1 is at "1" level and the row addresses WL0 and WL2 are at "0" level, only the memory cell c1-15 among the memory cells c0-15 to c2 to 15 has the bit line BL15. "0" level is input from . A "1" level is input from the bit line XBL15 only to the memory cell c1-15. As a result, the "0" level and "1" level held in the latch L15, that is, the 16th digit level of the spike train A are stored in the memory cells c1-15.

Similarly, the level of the fifteenth digit of spike train A held in latch L14 is stored in memory cells c1-14, . . . The second level is stored in memory cell c1-1, and the level of the first digit of spike train A held in latch L0 is stored in memory cell c1-0.

As described above, according to the control device 103, the spike train input to the write interface 11 can be written to the storage device 102 as it is.

2. Read Operation Next, the read operation of the control device 103 will be described. In a nutshell, the read operation of the control device 103 is the reverse of the processing performed by the control device 103 in the write operation.

That is, when the control device 103 performs a write operation, the control device 103 holds the level of each digit of the spike train sequentially input to the write interface 11 in each shift circuit 13 . Then, the controller 103 stores the level held in each shift circuit 13 in each memory cell c selected from the memory cell array 51 .

On the other hand, when the control device 103 performs a read operation, the control device 103 reads the level stored in each memory cell c selected from the memory cell array 51 and holds it in each shift circuit 13 . do. Then, the control device 103 sequentially outputs each level held in each shift circuit 13 from the readout interface 12 .

The following description will focus on the differences between the read operation and the write operation.

The control device 103 reads the level stored in each memory cell selected from the memory cell array 51 of the storage device 102 . Here, an example in which the levels stored in the memory cells c2-0 to c2-15 in the memory cell array 51 are read will be described. It is also assumed that the levels stored in the memory cells c2-0 to c2-15 in the memory cell array 51 are the spike train A "0000111101000001". The memory cell c2-0 has the first digit level of the spike train A, the memory cell c2-1 has the second digit level, . However, the level of the 16th digit is stored in memory cells c2-15.

First, the address generation circuit 53 of the storage device 102 sets the row address WL2 to "1" level. On the other hand, the address generation circuit 53 sets the row addresses WL0 and WL1 to "0" level.

First, reading the level stored in the memory cell c2-15 of the memory cell array 51 of the storage device 102 and holding the read level in the latch L15 of the shift circuit 13-15 of the control device 103 will be described. . The memory cell c2-15 stores the "0" level of the 16th digit of the spike train A as well as the "1" level, which is the complementary level of the "0" level.

The "0" level stored in the memory cell c2-15 is input to the latch L15 of the shift circuit 15 via the read circuit R15. Also, the "1" level stored in the memory cell c2-15 is input to the latch L15 of the shift circuit 15 via the read circuit R15. Here, since the row address WL2 is at "1" level and the row addresses WL1 and WL1 are at "0" level, only the memory cell c2-15 among the memory cells c0-15 to c2 to 15 is connected to the bit line BL15. A "0" level is input to the readout circuit W15 via the . A "1" level is input to the read circuit W15 from only the memory cell c2-15 through the bit line XBL15. As a result, the "0" level and "1" level stored in the memory cell c2-15, that is, the level of the 16th digit of the spike train A is held in the latch L15.

Similarly, the level of the fifteenth digit of the spike train A stored in the memory cell c2-14 is held in the latch L14 of the shift circuit 13-14, and stored in the memory cell c2-1. The level of the second digit of the spike train A stored in the shift circuit 13-1 is held in the latch L1 of the shift circuit 13-1. 13-0 is held in latch L0. That is, the control device 103 holds all the levels of the digits of the spike train A.

When the control device 103 holds all the levels of the digits of the spike train A, next, the control device 103 successively changes the levels held in the latches L of the shift circuits 13 in the same manner as in the write operation described above. It is moved to the latch L of each shift circuit 13 located on the readout interface 12 side.

The latch L0 of the shift circuit 13-0 sequentially holds the level of the 2nd digit, the level of the 3rd digit, . A pair of output terminals of the shift circuit 13 - 0 are connected to a pair of input terminals of the readout interface 12 . The level of each digit of the spike train A sequentially held in the latch L0 of the shift circuit 13-0 is sequentially input to a pair of input terminals of the readout interface 12 as each level of the BLo signal and the XBLo signal. . The readout interface 12 sequentially outputs the level of each digit of the spike train A, which is sequentially input to the pair of input terminals, from the output terminal. That is, the control device 103 outputs the spike train A from the output terminal of the readout interface 12 .

As described above, according to the control device 103, the spike train stored in the storage device 102 can be read out from the readout interface 12 as it is.

<Effect of Embodiment 1>
According to the control device 103, the spike train can be written as it is to the storage device, and the spike train can be read as it is from the storage device. That is, according to the control device 103, a control device having a novel configuration can be realized.

In addition, according to the control device 103, it is possible to reduce hardware and increase the speed of data processing in the device that implements the SC calculation mechanism.

[Embodiment 2]
Embodiment 2 of the present disclosure will be described below. For convenience of description, members having the same functions as those of the members described in the above embodiments are denoted by the same reference numerals, and description thereof will not be repeated.

The second embodiment relates to the write operation of the control device 103 when a spike train with a number of digits exceeding the total number of shift circuits 13 is input to the write interface 11 . Further, the second embodiment relates to the readout operation of the control device 103 when outputting a spike train with a number of digits exceeding the total number of shift circuits 13 from the readout interface 12 .

First, the write operation of the control device 103 according to the second embodiment will be explained using FIG. Note that the total number of shift circuits 13 is 16 in the second embodiment as well, as shown in FIG. It is also assumed that the number of digits of the spike train input to the write interface 11 is 18, which is 16, which is the total number of the shift circuits 13 .

The write interface 11 is supplied with signals at the levels of each digit in order from the first digit of the spike train at predetermined time intervals. When the number of levels equal to the total number of shift circuits 13 is input to the write interface 11, that is, when the level signal of the 16th digit of the spike train is input, the control device 103 temporarily performs the write operation. stop inputting the spike train to the interface 11;

Here, the spikes that have not yet been input to the writing interface 11 at the time of this stop are the 17th and 18th digits of the spike train. The control device 103 also holds all the levels of the 1st to 16th digits of the spike train.

Also, the control device 103 may detect the time when the same number of levels as the total number of shift circuits 13 are input by counting the number of clocks of the clock signal CK. If the total number of shift circuits 13 is 16, 16 clocks are required until 16 spikes are input.

After stopping the input of the spike train to the write interface 11 , the control device 103 sets the levels of the 1st to 16th digits of the spike train to the levels selected from the memory cell array 51 of the storage device 102 . Store in memory cell c. As a result, the control device 103 writes the levels of the 1st to 16th digits of the spike train to the storage device 102 .

After writing the levels of the 1st to 16th digits of the spike train to the storage device 102, the control device 103 starts inputting the spike train to the write interface 11 again. The writing interface 11 is supplied with signals at the levels of the 17th and 18th digits of the spike train in order from the 17th digit at predetermined time intervals.

The control device 103 holds the levels of the 17th and 18th digits of the spike train. Then, the control device 103 stores the levels of the 17th and 18th digits of the spike train in each memory cell c selected from the memory cell array 51 of the storage device 102 . As a result, the control device 103 writes the levels of the 1st to 18th digits of the spike train to the storage device 102 .

The level of each digit from the 1st to 16th digits of the spike train is stored in each memory cell c connected to the same row address. Also, the levels of the 17th and 18th digits of the spike train are stored in each memory cell c connected to the same row address. However, the former row address and the latter row address are different. For example, the levels of the 1st to 16th digits of the spike train are stored in memory cells c0-0 to c0-15 connected to row address WL0. Also, the levels of the 17th and 18th digits of the spike train are stored in the memory cells c1-14 to c1-15 connected to the row address WL1. Similarly to the control device 103, the address generation circuit 53 of the storage device 102 may also detect when the same number of levels as the total number of the shift circuits 13 is input by counting the number of clocks of the clock signal CK. Thereby, the address generation circuit 53 can change the row address to be selected from the row address WL0 to the row address WL1 as described above.

Next, the read operation of the control device 103 according to the second embodiment will be explained using FIG. Note that the total number of shift circuits 13 is 16 in the second embodiment as well, as shown in FIG. Also, it is assumed that the number of digits of the spike train output from the readout interface 12 is 18, which is 16, which is the total number of the shift circuits 13 .

The control device 103 reads the level stored in each memory cell c selected from the memory cell array 51 of the storage device 102 . Controller 103 keeps track of each level that is read. Each level to be read out is the level of each digit from the 1st to 16th digits of the spike train output from the readout interface 12 .

The control device 103 sequentially outputs each held level from the readout interface 12 . As a result, the control device 103 reads from the storage device 102 the levels of the 1st to 16th digits of the spike train.

Subsequently, the control device 103 reads the level stored in each memory cell c selected from the memory cell array 51 of the storage device 102 . Controller 103 keeps track of each level that is read. Each level read out is the level of each of the 17th and 18th digits of the spike train output from the readout interface 12 .

The control device 103 sequentially outputs each held level from the readout interface 12 . As a result, the control device 103 reads from the storage device 102 the levels of the 1st to 18th digits of the spike train.

The level of each digit from the 1st to 16th digits of the spike train is read from each memory cell c connected to the same row address. Also, the levels of the 17th and 18th digits of the spike train are read from each memory cell c connected to the same row address. However, the former row address and the latter row address are different. For example, the levels of the 1st to 16th digits of the spike train are read from the memory cells c0-0 to c0-15 connected to the row address WL0. Also, the levels of the 17th and 18th digits of the spike train are read from the memory cells c1-14 to c1-15 connected to the row address WL1.

As described above, according to the control device 103, even if the number of digits of the spike train to be written to the storage device 102 exceeds the total number of shift circuits 13, the spike train can be written to the storage device 102 as it is.

Further, according to the control device 103, even if the number of digits of the spike train read from the storage device 102 exceeds the total number of shift circuits 13, the spike train can be read from the storage device 102 as it is.

It should be noted that in the second embodiment, both the write operation and the read operation of the control device 103 have been described with an example in which the spike train has 18 digits. However, Embodiment 2 is not limited to the case where the spike train has 18 digits.

[Embodiment 3]
A third embodiment of the present disclosure will be described below. For convenience of description, members having the same functions as those of the members described in the above embodiments are denoted by the same reference numerals, and description thereof will not be repeated.

FIG. 3 is a diagram showing the circuit configuration of the control device 103A according to Embodiment 3 of the present disclosure. Although various members of the storage device 102 are also shown in FIG. 3, descriptions of members unrelated to the control device 103A are omitted.

As shown in FIG. 3, the control device 103A differs from the control device 103 of the first embodiment in that it further includes a counter 14 and selectors 15-15_14 and 15-1_0. Hereinafter, as in the first embodiment, a case where a spike train A represented by "0000111101000001" is input to the write interface 11 will be described as an example.

The writing interface 11 receives the level of the first digit (=1), the level of the second digit (=0), the level of the third digit (=0), . , the level of the 15th digit (=0), and the level of the 16th digit (=0) are input in this order.

When the level of the BLi signal input from the write interface 11 to the latch L15 of the shift circuit 13-15 is "1" level, the counter 14 increases the count value held in the counter 14 by one. A clock signal CK is input to the counter 14 . The "1" level of the BLi signal is input to the latch L15 at the rising edge of the clock signal CK. After the "1" level of the BLi signal is input to the latch L15, the counter 14 increments the count value by one at the timing of the next rise of the clock signal CK.

Also, if the level of the signal input from the shift circuit 13-1 to the latch L0 of the shift circuit 13-0 is "1" level, the counter 14 decrements the count value held in the counter 14 by one. A "1" level is input from the shift circuit 13-1 to the latch L0 of the shift circuit 13-0 at the rising timing of the clock signal CK. After the "1" level is input to the latch L0, the counter 14 decrements the count value by one at the timing of the next rise of the clock signal CK.

Also, the level of the BLi signal input from the write interface 11 to the latch L15 of the shift circuit 13-15 matches the level of the signal input from the shift circuit 13-1 to the latch L0 of the shift circuit 13-0. If so, the counter 14 maintains the count value held in the counter 14 .

More specifically, when the level of the first digit (=1) of the spike train A is input from the write interface 11 to the latch L15 of the shift circuit 13-15, the counter 14 sets the count value to 1. Next, when the level of the second digit (=0) of the spike train A is input from the write interface 11 to the latch L15 of the shift circuit 13-15, the counter 14 maintains the count value. That is, the count value remains 1.

Similarly, the levels of the 3rd digit (=0) to the 16th digit (=0) of the spike train A are sequentially input from the write interface 11 to the latch L15 of the shift circuit 13-15. Among the 1st to 16th digits of the spike train A, the number of digits of "1" level is 6, so the count value held by the counter 14 is 6.

When the selector 15-15_14 of the selector 15-15_14 and the selector 15-1_0 is turned on, the counter 14 outputs the count value held by the counter 14 to the selector 15-15_14. The selector 15-15_14 outputs the count value input from the counter 14 to the write circuit W14 and the write circuit W15. When the selector 15-1_0 of the selectors 15-15_14 and 15-1_0 is turned on, the counter 14 outputs the count value held by the counter 14 to the selector 15-1_0. The selector 15-1_0 outputs the count value input from the counter 14 to the write circuit W0 and the write circuit W1.

The write circuit W14, write circuit W15, write circuit W0, and write circuit W1 store the count value of the counter 14 in the memory cell c connected to each. The address generation circuit 53 selects the memory cell c in which the count value is stored using the row addresses WL0 to WL2.

When the level of the 16th digit (=0) of the spike train A is input from the write interface 11 to the latch L15 of the shift circuit 13-15, the shift circuit 13-1 to the latch L0 of the shift circuit 13-0 The level of the input signal is the level of the first digit (=1) of the spike train A. Therefore, the counter 14 decrements the counter value by one. That is, the count value is 5. Similarly, when the levels of the 3rd digit (=0) to the 16th digit (=0) of the spike train A are sequentially input to the latch L0, the counter value of the counter 14 becomes 0 again. That is, when the levels of the 1st digit (=1) to the 16th digit (=0) of the spike train A are sequentially input to the latch L0, the counter value of the counter 14 finally returns to 0.

Therefore, even if a spike train different from the spike train A (herein referred to as a spike train B) is continuously input from the write interface 11 after the spike train A is input, the spike train B The process of resetting the counter value of the counter 14 once before the input is started, in other words, the process of resetting the count value to 0 is unnecessary. This is because when the levels of the digits of the spike train B are sequentially input to the latch L15, the levels of the digits of the spike train A are also sequentially input to the latch L0 at the same time. This is because, while counting the number of "1" levels of spike train B, the number of "1" levels of spike train A input to latch L0 can be reduced from the count value.

As described above, according to the control device 103A, the number of spikes in the spike train written to the storage device 102 can be counted, and only the count value can be written to the storage device 102. Therefore, according to the control device 103A, the amount of data written to the storage device 102 can be compressed more than when the spike train is written to the storage device 102 as it is.

[Embodiment 4]
Embodiment 4 of the present disclosure will be described below. For convenience of description, members having the same functions as those of the members described in the above embodiments are denoted by the same reference numerals, and description thereof will not be repeated.

FIG. 4 is a diagram showing the circuit configuration of the control device 103B according to Embodiment 4 of the present disclosure. Although various members of the storage device 102 are also shown in FIG. 4, descriptions of members unrelated to the control device 103B are omitted.

As shown in FIG. 4, the control device 103B differs from the control device 103 of the first embodiment in that the counter 14, registers 16-15_14 (first register), register 16-1_0 (second register), comparator 17-15_14 (first comparator), comparator 17-1_0 (second comparator), and AND circuit 18 are further provided.

The fourth embodiment is a modification of the third embodiment. The control device 103A according to the third embodiment counts the number of spikes in the spike train written to the storage device 102 and writes only the count value to the storage device 102 .

On the other hand, the control device 103B counts the number of spikes in the spike train input to the write interface 11 and compares the count value with the minimum and maximum values prewritten in the storage device 102 . The control device 103B determines whether or not the count value falls within a predetermined range defined by the minimum value and the maximum value based on the result of the size comparison. Note that the minimum and maximum values may be input from the write interface 11 or may be input from the memory interface 102 as a spike train.

As shown in FIG. 4, the counter 14 counts the number of spike trains input to the write interface 11 . The processing by which the counter 14 counts the number of spikes in the spike train is the same as the processing executed by the counter 14 of the third embodiment, and thus description thereof will not be repeated here.

The counter 14 outputs the count value to both comparators 17-15_14 and 17-1_0.

In FIG. 4, the maximum value is stored in the memory cell c respectively connected to the readout circuit R14 and the readout circuit R15. The address generation circuit 53 uses the row addresses WL0 to WL2 to select the memory cell c in which the maximum value is stored. The readout circuit R14 and the readout circuit R15 read out the maximum value from the memory cell c connected thereto. The readout circuit R14 and the readout circuit R15 output the maximum value read from the memory cell c to the register 16-15_14. Register 16-15_14 holds the maximum value.

The minimum value is stored in the memory cell c connected to each of the readout circuit R0 and the readout circuit R1. The address generation circuit 53 selects the memory cell c storing the minimum value using the row addresses WL0 to WL2. The readout circuit R0 and the readout circuit R1 read out the minimum value from the memory cell c connected thereto. The readout circuit R0 and the readout circuit R1 output the minimum value read from the memory cell c to the register 16-1_0. Register 16-1_0 holds the minimum value.

Regarding the value held in the register 16-15_14 and the value held in the register 16-1_0, the value held in the register 16-15_14 is the maximum value and the value held in the register 16-1_0 is the minimum value. , is a set of values defining a predetermined range.

When the count value is input from the counter 14, the comparator 17-15_14 acquires the maximum value held in the register 16-15_14 from the register 16-15_14. Comparators 17-15_14 compare the count value with the maximum value. If the count value is equal to or less than the maximum value, the comparator 17-15_14 outputs a "1" level signal to the AND circuit . If the count value is greater than the maximum value, the comparator 17-15_14 outputs a "0" level signal to the AND circuit .

When the count value is input from the counter 14, the comparator 17-1_0 acquires the minimum value held in the register 16-1_0 from the register 16-1_0. Comparator 17-1_0 compares the count value with the minimum value. If the count value is equal to or greater than the minimum value, comparator 17-1_0 outputs a signal of “1” level to AND circuit . If the count value is smaller than the minimum value, the comparator 17-1_0 outputs a “0” level signal to the AND circuit .

When a "1" level signal is input to the AND circuit 18 from the comparator 17-15_14 and a "1" level signal is input to the AND circuit 18 from the comparator 17-1_0, the AND circuit 18 outputs "1". ” level PASS signal is output. On the other hand, when a "0" level signal is input to the AND circuit 18 from at least one of the comparators 17-15_14 and 17-1_0, the AND circuit 18 outputs a "0" level PASS signal.

That is, if the count value is within a predetermined range defined by the minimum and maximum values, the AND circuit 18 outputs a "1" level PASS signal. On the other hand, if the count value does not fall within the predetermined range defined by the minimum and maximum values, the AND circuit 18 outputs a "0" level PASS signal.

The "1" level and "0" level output from the AND circuit 18 may be input to the write interface 11 of another control device 103. In this case, each level output from the AND circuit 18 constitutes a spike train input to the write interface 11 of the other control device 103 .

As described above, according to the control device 103B, it is possible to count the number of spikes in the spike train input to the write interface 11 and determine whether or not the count value falls within a predetermined range.

Therefore, comparison programs that were conventionally implemented in software can now be implemented in hardware. It should be noted that the process of determining whether or not a predetermined value falls within a predetermined range based on the results of magnitude comparison as described above is the essence of identification processing in AI (Artificial Intelligence).

[Embodiment 5]
A fifth embodiment of the present disclosure will be described below. For convenience of description, members having the same functions as those of the members described in the above embodiments are denoted by the same reference numerals, and description thereof will not be repeated.

FIG. 5 is a diagram showing a circuit configuration of a control device 103C according to Embodiment 5 of the present disclosure. Although various members of the storage device 102 are also shown in FIG. 5, description of members unrelated to the control device 103C is omitted.

As shown in FIG. 5, the controller 103C differs from the controller 103 of the first embodiment in that a counter 19-15_14 (first counter), a counter 19-1_0 (second counter), a register 20-15_14, The point is that it further includes a register 20-1_0.

The control device 103C performs multiplication and division. Hereinafter, as in the first embodiment, a case where a spike train A represented by "0000111101000001" is input to the write interface 11 will be described as an example.

The writing interface 11 receives the level of the first digit (=1), the level of the second digit (=0), the level of the third digit (=0), . , the level of the 15th digit (=0), and the level of the 16th digit (=0) are input in this order.

The initial count value of the counter 19-15_14 (hereinafter referred to as "first initial value") is held in the register 20-15_14. The initial count value of the counter 19-1_0 (hereinafter referred to as "second initial value") is held in the register 20-1_0.

The first initial value is stored in the memory cell c connected to each of the readout circuit R14 and the readout circuit R15. The address generation circuit 53 selects the memory cell c storing the first initial value using the row addresses WL0 to WL2. The readout circuit R14 and the readout circuit R15 read out the first initial value from the memory cell c connected thereto. The readout circuit R14 and the readout circuit R15 output the first initial value read from the memory cell c to the register 20-15_14. The register 20-15_14 holds the first initial value.

The second initial value is stored in the memory cell c connected to each of the readout circuit R0 and the readout circuit R1. The address generation circuit 53 uses the row addresses WL0 to WL2 to select the memory cell c storing the second initial value. The readout circuit R0 and the readout circuit R1 read out the second initial value from the memory cell c connected thereto. The readout circuit R0 and the readout circuit R1 output the second initial value read from the memory cell c to the register 20-1_0. The register 20-1_0 holds the second initial value.

Returning to the description of the counters 19-15_14 and 19-1_0.

A clock signal CK is input to the counter 19-15_14. Each time the clock signal CK rises, the counter 19-15_14 decrements the count value by one. That is, each time the level of each digit of the spike train A is input to the write interface 11, the counter 19-15_14 decrements the count value by one. Then, when the count value of the counter 19-15_14 reaches 0, the counter 19-15_14 rewrites the level of the signal held in the latch L14 of the shift circuit 13-14 at the time of arrival to "1" level. Specifically, if the level of the signal held in the latch L14 is "1" level, the counter 19-15_14 maintains the "1" level. On the other hand, if the level of the signal held in the latch L14 is "0" level, the counter 19-15_14 rewrites the "0" level to "1" level. When the count value held in the counter 19-15_14 reaches 0, the counter 19-15_14 again sets the count value as the first initial value held in the register 20-15_14.

Every time the count value of the counter 19-15_14 reaches 0, the counter 19-15_14 rewrites the level of the signal held in the latch L14 to "1" level, so that the spike train A corresponding to the multiplicand becomes Multiplication processing for multiplying the corresponding first initial value is executed.

A clock signal CK is input to the counter 19-1_0. Each time the clock signal CK rises, the counter 19-1_0 decrements the count value by one. That is, each time the level of each digit of the spike train A is input to the write interface 11, the counter 19-1_0 decrements the count value by one. Then, when the count value of the counter 19-1_0 reaches 0, the counter 19-1_0 rewrites the level of the signal held in the latch L0 of the shift circuit 13-0 to "0" level at the time of arrival. Specifically, if the level of the signal held in the latch L0 is "0" level, the counter 19-1_0 maintains the "0" level. On the other hand, if the level of the signal held in the latch L14 is "1" level, the counter 19-1_0 rewrites the "1" level to "0" level. When the count value held in the counter 19-1_0 reaches 0, the counter 19-1_0 again sets the count value as the second initial value.

Every time the count value of the counter 19-1_0 reaches 0, the counter 19-1_0 rewrites the level of the signal held in the latch L14 to "0" level, so that the spike train A corresponding to the dividend and the divisor A division process for dividing the corresponding second initial value is executed.

As described above, according to the control device 103C, multiplication and division can be performed.

[Embodiment 6]
A sixth embodiment of the present disclosure will be described below. For convenience of description, members having the same functions as those of the members described in the above embodiments are denoted by the same reference numerals, and description thereof will not be repeated.

As shown in FIG. 6, the sixth embodiment of the present disclosure differs from the first embodiment in that the control device 103 performs write and read operations on the storage device 102A instead of the storage device 102. FIG.

The memory device 102A has a configuration in which the memory cells c0-0 to c0-15 connected to the row address WL0 in the memory device 102 are replaced with memory cells D0-0 to D0-15, respectively. Similarly, memory cells c1-0 to c1-15 connected to row address WL1 and memory cells c2-0 to c2-15 connected to row address WL2 are the same as memory cells D0-0 to D0-15. It is replaced by a memory cell that is a configuration.

The memory cells D0-0 to D0-15 have the same configuration. Here, the configuration of the memory cells D0-15 will be described. The memory cell D0-15 is composed of a first cell D0-15-1 and a second cell D0-15-2. The first cell D0-15-1 has the same configuration as the memory cell c0-15 of the storage device 102. FIG. Also, the second cell D0-15-2 is a known associative memory cell.

The controller 103 receives from the write circuit W all the values stored in the first cells D0-0-1 to D0-15-1 of the memory cells D0-0 to D0-15 connected to the match line ML0. match line ML0 precharged to "1" level is held at "1" level. On the other hand, the controller 103 determines that at least one of the values stored in the first cells D0-0-1 to D0-15-1 of the memory cells D0-0 to D0-15 is different from the value input from the write circuit W. In this case, the match line ML0 is discharged to "0" level.

The "1" level and "0" level output from the match line ML0 may be input to the write interface 11 of another control device 103. In this case, each level output from the match line ML0 constitutes a spike train input to the write interface 11 of the other control device 103. FIG.

As described above, according to the sixth embodiment, when the control device 103 performs the write operation, the value stored in the memory cell array 51A of the storage device 102A is compared with the value input from the write circuit W. can be done.

[Embodiment 7]
Embodiment 7 of the present disclosure will be described below. For convenience of description, members having the same functions as those of the members described in the above embodiments are denoted by the same reference numerals, and description thereof will not be repeated.

FIG. 7 is a diagram showing a schematic configuration of a device 200 that implements an SC calculation mechanism according to Embodiment 7 of the present disclosure. As shown in FIG. 7, the device 200 has a configuration in which two sets of the control device 103 and the storage device 102 of the first embodiment are arranged.

According to the device 200, each control device 103 can simultaneously execute the write operation and the read operation of the first embodiment.

In the device 200, instead of the control device 103 and the storage device 102 of the first embodiment, the control device 103 and the storage device 102 of the second embodiment, the control device 103A and the storage device 102 of the third embodiment, and the Two sets of the control device 103B and the storage device 102 of the fourth embodiment, the control device 103C and the storage device 102 of the fifth embodiment, and the control device 103 and the storage device 102A of the fifth embodiment are arranged. can be

Also, the two sets constituting the device 200 may be different from each other. For example, the first set may be the control device 103 and the storage device 102 of the first embodiment, and the second set may be the control device 103A and the storage device 102 of the third embodiment. Also, the number of sets of control devices that constitute the device 200 is not limited to two.

[Embodiment 8]
An eighth embodiment of the present disclosure will be described below. For convenience of description, members having the same functions as those of the members described in the above embodiments are denoted by the same reference numerals, and description thereof will not be repeated.

FIG. 8 is a diagram for explaining the configuration of a control device according to Embodiment 8 of the present disclosure. As shown in FIG. 8, the control device according to the eighth embodiment replaces the latch L15 of the shift circuit 13-15 with the latch LR15 in the control device 103 of the first embodiment, and replaces the gate G14 of the shift circuit 13-14 with the gate G14. It has a configuration replaced with GR14.

The latch LR15 is composed of an inductor LR15-1 and a capacitor LR15-2. Gate GR14 is a delay element.

In the control device according to the eighth embodiment, the gates G except the gate G15 are replaced with the gate GR14 or gates having the same configuration as the gate GR14, and the latch L has the same configuration as the latch LR15 or the latch LR15. Replaced by some latches.

The write operation and read operation of the control device 103 of the first embodiment can also be performed by the control device of the eighth embodiment.

〔others〕
The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments is also included in the technical scope of the present disclosure.

100 device for realizing SC calculation mechanism, 101 arithmetic device, 102 storage device, 103 control device, 11 write interface, 12 read interface, 13-0, 13-1, 13-14, 13-15 shift circuit, 14 , 19-15_14, 19-1_0 counter, 51, 51A memory cell array, 15-1_0, 15-15_14 selector, 16-15_14, 16-1_0, 20-15_14, 20-1_0 register, 17-15_14, 17-1_0 comparison 18 AND circuit 52 peripheral circuit 53 address generation circuit 54 memory interface G0, G1, G14, G15 gate L0, L1, L14, L15 latch B0, B1, B14, B15 buffer

Claims (9)

1. A controller for a memory included in a device implementing a stochastic computing computing mechanism, comprising:
   a writing interface into which a spike train is input;
   a readout interface that outputs a spike train;
   a plurality of shift circuits each holding a level of a signal input thereto,
   the plurality of shift circuits are connected in series between the write interface and the read interface;
   Among the two adjacent shift circuits, the shift circuit located on the write interface side shifts the level held by the shift circuit to the shift circuit located on the read interface side,
   Each of the shift circuits is connected to a plurality of memory cells capable of writing and reading the level held in each of the shift circuits,
   (i) when a spike train is input from the write interface to the controller,
   each said shift circuit,
   shifting the level of each digit of the spike train sequentially input from the write interface between the two adjacent shift circuits from the write interface side toward the read interface side;
   After the level of each digit is held in the corresponding shift circuit, the level held by each shift circuit is written into the memory cell connected to each shift circuit;
   (ii) when the control device outputs a spike train from the readout interface,
   each said shift circuit,
   reading the level of each digit from the memory cells connected to each of the shift circuits;
   After the levels of the respective digits are held in the corresponding shift circuits, the levels held in the respective shift circuits are transferred from the write interface side to the read interface side to the two adjacent digits. A controller for moving between shift circuits.
2. (i) When a spike train with a number of digits exceeding the total number of the plurality of shift circuits is input from the write interface to the control device,
   The control device temporarily stops inputting the spike train to the write interface when the number of levels equal to the total number of the plurality of shift circuits is input to the write interface,
   each of the shift circuits writes the level held by each of the shift circuits into the memory cells connected to each of the shift circuits;
   The controller again initiates input of the levels of the remaining digits of the spike train to the write interface;
   (ii) when the control device outputs a spike train with a number of digits exceeding the total number of the plurality of shift circuits from the readout interface,
   each of the shift circuits reads out the level of each digit from the memory cells connected to each of the shift circuits;
   The control device temporarily stops outputting the spike train from the readout interface at the time when the readout interface outputs the same number of levels as the total number of the plurality of shift circuits,
   2. The control device according to claim 1, wherein each said shift circuit again reads the level of the remaining digits of the spike train from said memory cells connected to each said shift circuit.
3. further comprising a counter,
   The counter is
   When the level held in the shift circuit connected to the write interface matches the level held in the shift circuit connected to the read interface, the counter value held in the counter is changed to maintain and
   when only the level held in the shift circuit connected to the write interface is "1" level, the counter value is incremented by one;
   when only the level held in the shift circuit connected to the readout interface is "1" level, the counter value is decremented by one;
   3. The control device according to claim 1, wherein said counter value is written into said memory cell connected to each said shift circuit.
4. a first register holding a maximum value;
   a second register holding a minimum value;
   a first comparator that compares the count value held in the counter and the maximum value held in the first register;
   a second comparator that compares the count value held in the counter and the minimum value held in the second register;
   An AND circuit connected to the first comparator and the second comparator,
   the first comparator outputs a "1" level signal to the AND circuit when the count value held in the counter is equal to or less than the maximum value held in the first register;
   4. The second comparator outputs a "1" level signal to the AND circuit when the count value held in the counter is equal to or greater than the minimum value held in the second register. The control device according to .
5. a first counter;
   a second counter;
   a first register that holds a first initial value that is the initial value of the count value held in the first counter;
   a second register that holds a second initial value that is the initial value of the count value held in the second counter;
   (i) each time the level of each digit of the spike train is input to the write interface, the first counter decrements the count value held in the first counter by one;
   When the count value of the first counter reaches 0, at the time of arrival, the first counter
   rewriting the level held in the shift circuit connected to the write interface to "1"level;
   Again, with the count value as the first initial value,
   (ii) each time the level of each digit of the spike train is input to the write interface, the second counter decrements the count value held in the second counter by one;
   When the count value of the second counter reaches 0, at the time of arrival, the second counter
   rewriting the level held in the shift circuit connected to the readout interface to "0"level;
   5. The control device according to claim 1, wherein said count value is used as said second initial value again.
6. A plurality of associative memory cells are connected to each of the shift circuits,
   After the level of each said digit is held in said corresponding shift circuit,
   When all the levels held by the shift circuits match the levels held in the memory cells connected to the shift circuits, the match lines connected to the associative memory cells output "1" level. death,
   2. The match line outputs a "0" level when at least one of the levels held by each shift circuit is different from the level held in the memory cell connected to each shift circuit. 6. The control device according to any one of 5.
7. The control device according to any one of claims 1 to 6, wherein a plurality of said control devices are arranged.
8. The control device according to any one of claims 1 to 7, wherein each said shift circuit includes a gate, a latch and a buffer.
9. 8. A control device as claimed in any preceding claim, wherein each said shift circuit comprises a capacitor, an inductor and a delay element.
   
   

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