WO2014012202A1 - 一种改善复信号iq路正交性的方法、设备和系统 - Google Patents

一种改善复信号iq路正交性的方法、设备和系统 Download PDF

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Publication number
WO2014012202A1
WO2014012202A1 PCT/CN2012/078675 CN2012078675W WO2014012202A1 WO 2014012202 A1 WO2014012202 A1 WO 2014012202A1 CN 2012078675 W CN2012078675 W CN 2012078675W WO 2014012202 A1 WO2014012202 A1 WO 2014012202A1
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Prior art keywords
delay
adjustment
signal
digital signal
analog signal
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PCT/CN2012/078675
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English (en)
French (fr)
Inventor
于海生
石晓明
周卫荣
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2012/078675 priority Critical patent/WO2014012202A1/zh
Priority to CN201280031424.3A priority patent/CN103688503B/zh
Publication of WO2014012202A1 publication Critical patent/WO2014012202A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits
    • H04L27/3845—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier
    • H04L27/3854—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
    • H04L27/3863—Compensation for quadrature error in the received signal

Definitions

  • the present invention relates to the field of communication technologies, and in particular, to a method, device and system for improving the orthogonality of a complex signal IQ path.
  • the orthogonality of the orthogonal signal is improved mainly by selecting a quadrature demodulator with better orthogonal performance or by fine-tuning simulation and repeated tuning, but this will increase the cost of the system. And design difficulty, at the same time will increase the difficulty of debugging the system hardware.
  • Embodiments of the present invention provide a method, apparatus, and system for improving orthogonality of a complex signal IQ path, which reduces system implementation cost and design and commissioning difficulty while improving orthogonality between complex signal IQ paths.
  • a method for improving orthogonality of a complex signal IQ path comprising: an analog-to-digital converter (ADC) receiving an I-channel analog signal and a Q-channel analog signal;
  • ADC analog-to-digital converter
  • the ADC adjusts the first sampling clock according to the first adjustment delay to obtain a second sampling clock, and samples the I analog signal by using the second sampling clock to obtain an I analog signal sampling point, and simulates the I path
  • the signal sampling point is converted to an I digital signal; and/or,
  • the ADC adjusts the first sampling clock according to the second adjustment delay to obtain a third sampling clock, and samples the Q analog signal by using the third sampling clock to obtain a Q analog signal sampling point, and the Q is The analog signal sampling point is converted into a Q digital signal;
  • the first adjustment delay and the second adjustment delay are used to make the I analog signal sampling point orthogonal to the Q analog signal sampling point.
  • the method further includes receiving the first adjustment delay and/or the second adjustment delay.
  • the ADC adjusts the first sampling clock according to the first adjustment delay to obtain a second sampling clock,
  • the second sampling clock samples the I-channel analog signal to obtain an I-channel analog signal sampling point, and converts the I-channel analog signal sampling point into an I-channel digital signal; and/or, the ADC adjusts according to the second adjustment delay Adjusting the first sampling clock to obtain a third sampling clock, sampling the Q analog signal by using the third sampling clock to obtain a Q analog signal sampling point, and converting the Q analog signal sampling point into a Q path
  • the method further includes: the ADC outputting the I digital signal and the Q digital signal by a first in first out (FIFO) queue unit located inside the ADC, and outputting the digital signal to the operation control device to collect the The I channel digital signal and the Q channel digital signal receive a read pointer sent by the operation control device to adjust the I channel digital signal and/or the Q channel digital signal
  • FIFO first in first out
  • the ADC sets its own initial delay value to 0, so that the ADC can utilize the
  • the first sampling clock samples the I analog signal and the Q analog signal, and obtains a delay difference between the I analog signal and the Q analog signal, where the initial value of the delay may be the ADC pair
  • the delay adjustment time of the first sampling of the I road analog signal and the Q channel analog signal is described.
  • a method for improving quadrature of a complex signal IQ path comprising: an operation control device collecting an analog-to-digital converter (ADC) and sampling an I analog signal and a Q analog signal to output an I digital signal and a digital signal of the Q channel; the operation control device calculates a first adjustment delay according to the I digital signal and the Q digital signal, and sends the first adjustment delay to the ADC, where the ADC is Adjusting the first sampling clock to obtain a second sampling clock, and sampling the I analog signal by using the second sampling clock to obtain an I analog signal sampling point; and/or, The operation control device calculates a second adjustment delay according to the I digital signal and the Q digital signal, and the operation control device sends the second adjustment delay to the ADC, where the ADC is The second adjustment delay adjusts the first sampling clock to obtain a third sampling clock, and samples the Q analog signal by using the third sampling clock to obtain a Q analog signal sampling point.
  • ADC analog-to-digital converter
  • the method further includes: the operation control device acquiring the I digital signal and the Q digital signal by using a first in first out (FIFO) queue unit located in the ADC And determining, when determining that the signal data of the I digital signal and the Q digital signal acquired by the same read pointer address from the FIFO queue unit are offset at the same time, sending an adjustment instruction to the ADC to adjust the The read pointer address of the I digital signal and/or the Q digital signal.
  • FIFO first in first out
  • the first adjustment delay and/or the second adjustment delay are written to a nonvolatile Sex memory.
  • an analog-to-digital converter including: an input interface, configured to receive an I-channel analog signal and a Q-channel analog signal;
  • An input interface configured to receive an I analog signal and a Q analog signal
  • a first time delay adjustment unit configured to adjust a first sampling clock according to the first adjustment delay to obtain a second sampling clock
  • a second delay adjustment unit configured to adjust a first sampling clock according to the second adjustment delay to obtain a third sampling clock
  • a first core unit configured to sample an I analog signal received by the input interface by using the second sampling clock to obtain an I analog signal sampling point, and convert the I analog signal sampling point into an I digital signal ;
  • a second core unit configured to receive the input interface by using the third sampling clock
  • the Q-channel analog signal is sampled to obtain a Q-channel analog signal sampling point, and the Q-channel analog signal sampling point is converted into a Q-channel digital signal;
  • the first adjustment delay and the second adjustment delay are used to orthogonalize the I-channel analog signal sampling point and the Q-channel analog signal sampling point.
  • the first possible implementation manner of the third aspect further includes a first delay adjustment interface and a second delay adjustment interface.
  • the first delay adjustment interface is configured to receive a first adjustment delay;
  • the second delay adjustment interface is configured to receive a second adjustment delay.
  • the method further includes:
  • a first first in first out (FIFO) queue unit connected to the first core unit, configured to output the I channel digital signal, and output the signal to the operation control device to collect the I channel digital signal, and receive the operation And an adjustment instruction sent by the control device to adjust a read pointer address of the I digital signal and/or the Q digital signal;
  • FIFO first in first out
  • a second first-in first-out queue unit connected to the second core unit, configured to output the Q-channel digital signal, and output the signal to the operation control device to collect the Q-channel digital signal, and receive the operation control device And an adjustment instruction for adjusting a read pointer address of the I digital signal and/or the Q digital signal;
  • the adjustment command is issued when the operation control device shifts the signal data of the I-channel digital signal and the Q-channel digital signal acquired by the same FIFO queue unit at the same time.
  • the first delay adjustment unit and the second delay adjustment The initial delay value of the unit is 0, and the initial value of the delay may be a delay adjustment time for the ADC to first sample the I-channel analog signal and the Q-channel analog signal.
  • the method further includes: It is used to bypass the first delay adjustment unit and the second delay adjustment unit.
  • an arithmetic control device including:
  • the acquisition unit is configured to collect an I-channel digital signal and a Q-channel digital signal that are output after the analog-to-digital converter (ADC) samples the I-channel analog signal and the Q-channel analog signal;
  • ADC analog-to-digital converter
  • An operation unit configured to calculate a first adjustment delay and/or a second adjustment delay according to the I digital signal and the Q digital signal;
  • a sending unit configured to: when the computing unit calculates a first adjustment time delay, send the first adjustment delay to the ADC, so that the ADC adjusts the first according to the first adjustment delay Taking a sampling clock to obtain a second sampling clock, and sampling the I analog signal by using the second sampling clock to obtain an I analog signal sampling point; or
  • the computing unit calculates a second adjustment time delay, sending the second adjustment delay Up to the ADC, so that the ADC adjusts the first sampling clock according to the second adjustment delay to obtain a third sampling clock, and samples the Q analog signal by using the third sampling clock to obtain a Q path.
  • Analog signal sampling point or,
  • the I channel analog signal sampling is used to obtain an I channel analog signal sampling point
  • the Q channel analog signal is sampled by the third sampling clock to obtain a Q channel analog signal sampling point
  • the first adjustment delay and the second adjustment The delay is used to orthogonalize the I-channel analog signal sampling point and the Q-channel analog signal sampling point.
  • the sending unit is further configured to collect the I digital signal and the same read pointer address at the same time by a first in first out (FIFO) queue unit located in the ADC.
  • the Q-channel digital signal sends an adjustment command to the ADC to adjust the I-channel digital signal and/or when determining that the acquired I-channel digital signal and the Q-channel digital signal are offset by signal data.
  • the read pointer address of the Q digital signal is further configured to collect the I digital signal and the same read pointer address at the same time by a first in first out (FIFO) queue unit located in the ADC.
  • the Q-channel digital signal sends an adjustment command to the ADC to adjust the I-channel digital signal and/or when determining that the acquired I-channel digital signal and the Q-channel digital signal are offset by signal data.
  • the read pointer address of the Q digital signal is further configured to collect the I digital signal and the same read pointer address at the same time by a first in first out (FIFO) queue unit located in the ADC.
  • the method further includes: the operation control device is a field programmable gate array FPGA or a digital signal processor DSP; or
  • the acquisition unit of the operation control device is an FPGA or a DSP, and the operation unit and the transmission unit of the operation control device are included in a central processing unit (CPU) on a single board; or the acquisition control unit of the operation control device is an FPGA or The operation unit of the operation control device is a personal computer PC, and the transmission unit of the operation control device is included in a CPU on a single board.
  • CPU central processing unit
  • the acquisition control unit of the operation control device is an FPGA or
  • the operation unit of the operation control device is a personal computer PC, and the transmission unit of the operation control device is included in a CPU on a single board.
  • the sending unit when included in a CPU on a board, the first adjusting delay and/or the The second adjustment delay is written to the non-volatile memory.
  • a receiver comprising: the analog-to-digital converter provided in the above third aspect and the arithmetic control device provided in the fourth aspect.
  • a communication system including: the receiver provided in the foregoing fifth aspect.
  • the received I analog signal and the Q analog signal are sampled by the second sampling clock and the third sampling clock to obtain an I analog signal sampling point and a Q analog signal sampling point.
  • the I channel analog signal sampling point and the Q channel analog signal sampling point are converted into an I channel digital signal and a Q channel digital signal, thereby reducing the implementation cost and design and adjustment of the system while improving the orthogonality of the two signals. Difficulty in measuring.
  • FIG. 1 is a schematic diagram of a method for improving orthogonality of a complex signal IQ path according to an embodiment of the present invention
  • FIG. 2 is another schematic diagram of a method for improving orthogonality of a complex signal IQ path according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of another method for improving the orthogonality of a complex signal IQ path according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of an ADC according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another ADC according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another ADC according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an operation control device according to an embodiment of the present invention
  • FIG. 8 is a receiver according to an embodiment of the present invention
  • FIG. 9 is a reference schematic diagram of an analog signal sampling point according to an embodiment of the present invention
  • FIG. 9b is a schematic diagram of another analog signal sampling point according to an embodiment of the present invention
  • FIG. 10b is a schematic diagram of another reference for adjusting a read pointer address according to an embodiment of the present invention
  • FIG. 1 is a schematic diagram of a reference for calculating an adjustment delay according to an embodiment of the present invention.
  • the embodiment of the present invention provides a method for improving the orthogonality of a complex signal IQ path.
  • the execution body of the method is an ADC, and includes:
  • the ADC receives an I analog signal and a Q analog signal.
  • the ADC is used to convert analog signals of continuous variables into discrete digital signals that are easier to store, process, and transmit.
  • the ADC receives an I-channel analog signal and a Q-channel analog signal that are transmitted from a quadrature demodulator and passed through a digitally controlled attenuator and an anti-aliasing filter, respectively.
  • the ADC adjusts the first sampling clock according to the first adjustment delay to obtain a second sampling clock, and uses the second sampling clock to sample the I analog signal to obtain an I analog signal sampling point, and sample the I analog signal. Point conversion to I digital signal; and / or,
  • the ADC adjusts the first sampling clock according to the second adjustment delay to obtain a third sampling clock, and uses the third sampling clock to sample the Q analog signal to obtain a Q analog signal sampling point, and the Q analog signal sampling point Convert to Q digital signal.
  • the first adjustment delay and the second adjustment delay are used to make the I analog signal sampling point orthogonal to the Q analog signal sampling point.
  • the method may further include: receiving the first adjustment delay and/or the second adjustment delay.
  • the ADC sets its own initial delay value to 0, and samples the I analog signal and the Q analog signal by using the first sampling clock; wherein, the initial value of the delay is an analog signal of the ADC to the I channel.
  • the delay adjustment time of the first sampling of the Q analog signal for example, if the initial delay of the sampling of the analog signal of the I channel is 1 second, and the initial value of the sampling of the analog signal of the Q channel is 0, then the path of the I The clock sampled by the analog signal is delayed by one second than the clock sampled by the analog signal of the Q channel.
  • the present invention is not limited thereto.
  • the initial value of the delay in the ADC may be set to 0, or may be set to 0.
  • the other one is not set to 0, and may be other values, and if the initial values of the delays of the I-channel analog signal and the Q-channel analog signal sample are different, the clocks sampled by the I-channel analog signal and the Q-channel analog signal are also different, and the present invention is different.
  • This is not limited, but regardless of the initial value of the delay, the difference between the initial value delay of the I analog signal and the Q analog signal is offset in the subsequent delay adjustment, for example, the sampling of the I analog signal
  • the initial value of the delay is X.
  • the initial delay of the Q-channel analog signal sampling is Y.
  • X is delayed by one cycle from Y and cannot maintain the orthogonality of the two signals.
  • the embodiment of the present invention is not limited to this.
  • the embodiment of the present invention is described by taking an initial value of the delay in the ADC as an example.
  • the specific adjustment method may include the following two types:
  • One is to obtain a second sampling clock by adjusting the first sampling clock of the analog signal of the I, and the I digital signal that is sampled and converted by the second sampling clock, and the Q without delay adjustment
  • the analog signal is sampled and converted to obtain a Q-channel digital signal orthogonal.
  • the third sampling clock is obtained by adjusting the first sampling clock of the Q analog signal, and the Q digital signal is sampled and converted by the third sampling clock, and the I analog signal without delay adjustment is performed.
  • the I-channel digital signals obtained by sampling and conversion are orthogonal.
  • the other is to simultaneously adjust the first sampling clock of the I channel analog signal and the Q channel analog signal to obtain the second sampling clock and the third sampling clock respectively, and the I channel analog signal is sampled and converted by the second sampling clock.
  • the digital signal is orthogonal to the Q digital signal obtained by sampling and converting the Q analog signal through the third sampling clock.
  • the signal will generate different delays due to the action of some signal processing devices (such as signal attenuators, signal amplifiers, anti-aliasing filters, etc.), resulting in I-channel analog signals and Q-channels.
  • the analog signal is offset at the sampling point where the same sampling clock is sampled, for example, with reference to Fig. 9a, wherein the upward arrow shown in the figure indicates the time at which the I channel analog signal is sampled, and the downward arrow indicates Q.
  • the horizontal axis represents the sampling clock
  • points A and B represent the two sampling points of the I channel analog signal and the Q channel analog signal respectively sampled at the same sampling time
  • the sampling point of the analog signal of the sampling I is sampled at the same sampling time
  • the sampling point of the sampling analog signal is D point.
  • point C and point D Because the existence of signal delay is offset from point A and point B, respectively, the orthogonality between the converted I-channel digital signal and the Q-channel digital signal is affected.
  • the ADC adjusts the first sampling clock according to the obtained first adjustment delay to obtain a second sampling clock
  • the second adjustment delay adjusts the first sampling clock to obtain a third sampling clock, which is described with reference to FIG. 9b.
  • the upward arrow shown in the figure indicates the time at which the I channel analog signal is sampled
  • the downward arrow indicates the time at which the Q channel analog signal is sampled
  • the horizontal axis indicates the sampling clock
  • the points A and B indicate the I channel analog signal and Q, respectively.
  • the two analog points of the road analog signal are sampled at the same sampling time, and the C point and the D point respectively represent the sampling points at which the I sampling analog signal and the Q analog signal are sampled at the same sampling time, so that the operation control module is After collecting the I digital signal and the Q digital signal, the second sampling clock and the third sampling clock are respectively obtained according to the I digital signal and the Q digital signal, and are sent to the ADC, so that the ADC is in the second sampling clock pair I.
  • the sampling point of the I analog signal is adjusted to point A.
  • the Q analog signal is The sampling point of the sample is adjusted to point B, which ensures that the ADC samples the analog signal of the I at the second sampling clock at point A. Similarly, it also ensures that the ADC samples the analog signal of the Q at the third sampling clock at point B. . Further, the I digital signal and the Q digital signal obtained by the above method maintain the orthogonality of the I digital signal and the Q digital signal, but the clock is sampled by the I analog signal and the Q analog signal.
  • the second sampling clock and the third sampling clock are different, so that when the ADC reads the I digital signal and the Q digital signal at the same read pointer address at the same time, the analog signal of the I channel may not be simultaneously read in the second sampling.
  • the sampling point of the clock sampling and the sampling point of the Q-channel analog signal sampled at the third sampling clock cannot maintain the orthogonality of the I-channel digital signal and the Q-channel digital signal after the ADC output, and therefore, based on the above method steps If the operation control device determines that the acquired ADC is offset by the signal data of the I digital signal and the Q digital signal read by the same read pointer address at the same time, the method further includes:
  • the ADC outputs the I digital signal and the Q digital signal through a FIFO (First Input First Output) unit located inside the ADC, and outputs the digital signal to the operation control device to collect the I digital signal and the a digital signal of the Q channel, receiving the adjustment of the read pointer address sent by the operation control device to adjust the I digital signal and the Q digital signal Entire instruction,
  • FIFO First Input First Output
  • the adjustment instruction is that the ADC data collected by the operation control device is offset from the signal of the I digital signal and the Q digital signal read by the same read pointer address from the FIFO queue unit at the same time (ie, no).
  • the signal data offset is different for the number of sampling periods of the collected I-channel digital signal and the Q-channel digital signal, and may also be the I-channel digital signal and the Q-channel number of the operation control device according to the acquisition.
  • the phase difference of the signal is not 90 degrees, thereby determining that the I digital signal and the Q digital signal are not orthogonal, thereby determining the offset of the acquired digital signal of the I channel and the signal of the Q digital signal.
  • the two cases are explained: In the first case, as shown in FIG. 10a, the FIFO pointer adjustment is not required; in the second case, as shown in FIG. 10b, the fifo pointer adjustment is required.
  • the sampling clock of the digital signal of the I channel is the second sampling clock
  • the sampling clock of the digital signal of the Q channel is the third sampling clock, where I.
  • Ii, 1 2 are 3 signal data continuously sampled by the I channel digital signal according to the second sampling clock
  • Q Q , Q i, Q 2 are 3 signal data continuously sampled by the Q channel digital signal according to the third sampling clock
  • I - FIFO indicates the first FIFO queue unit corresponding to the I digital signal
  • Q-FIFO indicates the second FIFO queue unit corresponding to the Q digital signal
  • point a is the arrival time of the write start signal of the I-FIFO and Q-FIFO
  • b The point is the time when the digital signal of the I channel is received and the digital signal data of the I channel is started after the write start signal is received
  • the point c is the time when the digital signal of the Q channel starts to write the digital signal data of the Q channel after receiving the write start signal
  • n is the read pointer address.
  • the I digital signal data is the same as the subscript of the Q digital signal data.
  • the signal data is orthogonal.
  • the same read pointer address reads the signal data of the I digital signal and the Q digital signal, and finally obtains paired signal data such as I Q Q Q , IiQ i , and I 2 Q 2 . Therefore, no adjustment of the FIFO pointer is required.
  • the FIFO write start signal arrives at the point a, it is only an example.
  • the embodiment of the present invention is not limited thereto. In practical applications, as long as the arrival position of the FIFO write start signal can be guaranteed to be the same at the same time. It is within the scope of the present invention to read the pointer address to read the signal data of the I digital signal and the Q digital signal as a pair of orthogonal signal data.
  • the sampling clock of the digital signal of the I channel is the second sampling clock
  • the sampling clock of the digital signal of the Q channel is the third sampling clock
  • the three signal data continuously sampled by the sampling clock, Q Q , 0 2 are the three signal data continuously sampled by the Q digital signal according to the third sampling clock
  • the I-FIFO represents the first FIFO queue unit corresponding to the I digital signal
  • Q - FIFO indicates the second FIFO queue unit corresponding to the Q digital signal
  • point a is the arrival time of the write start signal of the I-FIFO and Q-FIFO
  • point b is the I signal after the digital signal receives the write start signal.
  • point c is the time at which the Q digital signal starts to write the Q digital signal data after receiving the write enable signal
  • n is the read pointer address, which is similar to I due to the delay adjustment.
  • Q Q , IjQ 1 2 ( ⁇ 2 is such that the signal data of the pair (the digital signal data of I is the same as the subscript of the digital signal of the Q channel) is orthogonal.
  • the same read pointer address reads the signal data of the I digital signal and the Q digital signal, and the result is similar to 1 ⁇ ., I 2 Q!
  • the Q-FIFO read pointer address can be adjusted so that when the signal data of the I channel digital signal is read When the Q-channel digital signal is read by the same read pointer address at the same time, the signal data is guaranteed to be read, thereby obtaining paired signal data with better orthogonality.
  • the Q-FIFO is adjusted in the above embodiment.
  • the read pointer address is only an example. The embodiment of the present invention is not limited thereto, and the paired orthogonal signal data can be obtained by adjusting the read pointer address of the I-FIFO. Adjusting the I-FIFO and Q-FIFO, can be obtained as long as the pair of adjustment orthogonal to the data signals are within the scope of the present invention.
  • the implementation body of the above method embodiment is an ADC.
  • the above method is used to improve the orthogonality of the two signals while reducing the implementation cost of the system and the difficulty of design and adjustment.
  • the embodiment of the present invention provides another method for improving the orthogonality of the complex signal IQ path.
  • the execution body of the method is an operation control device, and includes:
  • the arithmetic control device collects the I digital signal and the Q digital signal which are output after the ADC samples the analog signal of the I channel and the analog signal of the Q channel.
  • the operation control device calculates a first adjustment delay according to the I digital signal and the Q digital signal, and sends the first adjustment delay to the ADC, where the ADC adjusts the first according to the first adjustment delay.
  • the sampling clock obtains a second sampling clock, and the I sampling analog signal is sampled by the second sampling clock to obtain an I analog signal sampling point; and/or,
  • the operation control device calculates a second adjustment delay according to the I digital signal and the Q digital signal, and the operation control device sends the second adjustment delay to the ADC, and the ADC adjusts according to the second adjustment delay
  • the first sampling clock obtains a third sampling clock, and the Q sampling analog signal is sampled by the third sampling clock to obtain a Q analog signal sampling point.
  • the operation control device writes the first adjustment delay and/or the second adjustment delay into the non-volatile memory.
  • FIG. 11 shows the amplitude-frequency characteristic diagram of I+jQ
  • the horizontal axis represents the sampling frequency (F s ) of the ADC
  • the vertical axis represents the signal amplitude
  • the main signal region The area represents the energy of the signal itself
  • the area of the image signal area represents the energy of the image signal, wherein the image signal is generated because the I channel digital signal and the Q channel digital signal are not orthogonal, and the main signal region and the image signal region are related to the binary image.
  • the F s symmetry because the ratio of the main signal energy to the image signal energy corresponds to the delay of the orthogonal deviation of the I channel digital signal and the Q channel digital signal, therefore, the ratio of the main signal energy to the image signal energy can be obtained.
  • the delay of the orthogonal deviation of the I digital signal and the Q digital signal because the ratio of the main signal energy to the image signal energy corresponds to the delay of the orthogonal deviation of the I channel digital signal and the Q channel digital signal, therefore, the ratio of the main signal energy to the image signal energy can be obtained.
  • the delay of the orthogonal deviation of the I digital signal and the Q digital signal because the ratio of the main signal energy to the image signal energy corresponds to the delay of the orthogonal deviation of the I channel digital signal and the Q channel digital signal.
  • the first adjustment delay and the second adjustment delay may be determined by the delay of the orthogonal deviation of the I digital signal and the Q digital signal.
  • the operation control device may only determine the first adjustment delay, and The finally obtained I-channel analog signal sampling point is orthogonal to the Q-channel analog signal sampling point obtained without delay adjustment; or, the operation control device can only determine the second adjustment delay, and finally obtain the Q-channel analog signal sampling point.
  • the I-channel analog signal sampling point obtained by the delay adjustment is orthogonal to the I-channel analog signal sampling point; the arithmetic control device can also determine the first adjustment delay and the second adjustment delay, and adjust and obtain the I-channel analog signal sampling point and the Q-channel.
  • the analog signal sampling points are orthogonal.
  • the present invention is not limited thereto.
  • the operation control device sends the first adjustment delay to the ADC, and the ADC adjusts the first sampling clock according to the first adjustment delay to obtain a second sampling clock, and uses the second sampling clock to determine the I
  • the analog signal is sampled to obtain the I sample signal sampling point; or the operation control device sends the second adjustment delay to the ADC, and the ADC adjusts the first sampling clock according to the second adjustment delay to obtain the third sampling clock.
  • sampling the Q analog signal by using the third sampling clock to obtain a Q analog signal sampling point; or
  • the operation control device sends the first adjustment delay and the second adjustment delay to the An ADC, the ADC adjusts the first sampling clock according to the first adjustment delay to obtain a second sampling clock, adjusts the first sampling clock according to the second adjustment delay to obtain a third sampling clock, and uses the second sampling clock.
  • the I channel analog signal is sampled to obtain an I channel analog signal sampling point
  • the Q channel analog signal is sampled by the third sampling clock to obtain a Q channel analog signal sampling point.
  • the first adjustment delay and the second adjustment delay are used to make the I analog signal sampling point and the Q analog signal sampling point orthogonal.
  • the method further includes:
  • the operation control device acquires the I digital signal and the Q digital signal through a first in first out (FIFO) queue unit located in the ADC, and determines the I path collected from the same read pointer address at the same time from the FIFO queue unit.
  • FIFO first in first out
  • the execution body of the above method embodiment is an arithmetic control device.
  • Another embodiment of the present invention provides a method for improving the orthogonality of a complex signal IQ path. As shown in FIG. 3, the specific steps of the method include:
  • the ADC receives the I channel analog signal and the Q channel analog signal.
  • the ADC is used to convert analog signals of continuous variables into discrete digital signals that are easier to store, process, and transmit.
  • the ADC receives an I-channel analog signal and a Q-channel analog signal that are transmitted from a quadrature demodulator and passed through a digitally controlled attenuator and an anti-aliasing filter, respectively.
  • the operation control device collects the I channel digital signal and the Q channel digital signal which are output by the ADC after sampling the I channel analog signal and the Q channel analog signal by using the first sampling clock.
  • the operation control device calculates the digital signal according to the I channel and the digital signal of the Q channel.
  • the first adjustment delay and the second adjustment delay are sent to the ADC by the first adjustment delay and the second adjustment delay.
  • the ADC receives the first adjustment delay and the second adjustment delay, adjusts the first sampling clock according to the first adjustment delay to obtain a second sampling clock, and adjusts the first sampling according to the second adjustment delay.
  • the clock gets the third sample clock.
  • the ADC uses the second sampling clock to sample the I analog signal to obtain an I analog signal sampling point, and convert the I analog signal sampling point into an I digital signal, and use the third sampling clock to the Q
  • the analog signal of the road is sampled to obtain the Q-channel analog signal sampling point, and the Q-channel analog signal sampling point is converted into a Q-channel digital signal.
  • the first adjustment delay and the second adjustment delay are used to make the I analog signal sampling point orthogonal to the Q analog signal sampling point.
  • the operation control device collects the I digital signal and the Q digital signal by using the same read pointer address at the same time by the FIFO queue unit located in the ADC.
  • the operation control device sends an adjustment instruction to the ADC when determining that the I-channel digital signal collected from the FIFO queue unit and the signal data of the Q-channel digital signal are offset.
  • the adjustment instruction is that the ADC data collected by the operation control device is offset from the signal of the I digital signal and the Q digital signal read by the same read pointer address from the FIFO queue unit at the same time (ie, no The signal data offset is different for the sampling period of the collected I-channel digital signal and the Q-channel digital signal, and may also be the I-channel digital signal and the Q-channel digital signal of the operation control device according to the collected The phase difference is not 90 degrees, thereby determining that the I channel digital signal and the Q channel digital signal are not orthogonal, thereby determining the offset of the acquired I channel digital signal and the Q channel digital signal signal data.
  • the ADC adjusts the read pointer address of the I digital signal and the Q digital signal according to the adjustment instruction.
  • An embodiment of the present invention provides an analog-to-digital converter ADC40, as shown in FIG. 4, including: an input interface for receiving an I-channel analog signal and a Q-channel analog signal.
  • the first core unit 41 is configured to sample the I analog signal received by the input interface by using the second sampling clock to obtain an I analog signal sampling point, and convert the I analog signal sampling point into an I digital signal.
  • the second core unit 42 is configured to sample the Q analog signal received by the input interface by using the third sampling clock to obtain a Q analog signal sampling point, and convert the Q analog signal sampling point into a Q digital signal.
  • the first delay adjustment unit 43 is configured to adjust the first sampling clock according to the first adjustment delay to obtain the second sampling clock.
  • the second delay adjustment unit 44 is configured to adjust the first sampling clock according to the second adjustment delay to obtain the third sampling clock.
  • the first adjustment delay and the second adjustment delay are used to make the I analog signal sampling point and the Q analog signal sampling point orthogonal.
  • the initial delay value of the first delay adjustment unit 43 and the second delay adjustment unit 44 is 0, where the initial value of the delay may be performed by the ADC for the I analog signal and the Q analog signal. Delay adjustment time for the first sample.
  • the initial delay values of the first delay adjustment unit 43 and the second delay adjustment unit 44 may both be 0, or may be 0, the other is not 0, and may be other values, and if The initial value of the delay of the I-channel analog signal and the Q-channel analog signal sample is different, then the I path is The clocks of the analog signal and the Q-channel analog signal sample are also different.
  • the present invention does not limit this, but regardless of the initial value of the delay, the initial of the I-channel analog signal and the Q-channel analog signal will be used in subsequent delay adjustment. The difference of the value delay is offset.
  • the initial delay of the sampling of the analog signal of the I channel is X
  • the initial value of the delay of the sampling of the analog signal of the Q channel is ⁇
  • X is delayed by one cycle than Y
  • the positive of the two signals cannot be maintained.
  • Intercommunication now adjust the two signals to Z to maintain the orthogonality of the two signals, and X and Y both lag behind Z, then the second adjustment delay obtained in the subsequent direction is relative to the obtained third adjustment delay.
  • the two signals are orthogonal to each other.
  • the embodiment of the present invention is not limited thereto.
  • the ADC further includes: a first delay adjustment interface and a second delay adjustment interface, where the first delay adjustment interface is configured to receive the first adjustment delay.
  • the first delay adjustment interface receives the first adjustment delay sent by the operation control device.
  • the second delay adjustment interface is configured to receive a second adjustment delay.
  • the second delay adjustment interface receives the second adjustment delay sent by the operation control device. It should be noted that, in an actual application, the input interface, the first delay adjustment interface, and the second delay adjustment interface may be integrated into the same interface, or may be independent interfaces, or the input interface is independent.
  • the first time delay adjustment interface and the second time delay adjustment interface are integrated into one interface, which is not limited by the present invention.
  • the ADC 40 further includes: a first FIFO queue unit 45 connected to the first core unit 41, configured to output the I channel digital signal, and output the signal to the operation control device to collect the The I channel digital signal receives an adjustment instruction sent by the operation control device to adjust the I-channel digital signal and the read pointer address of the Q-channel digital signal.
  • the second FIFO queue unit 46 is connected to the second core unit 42 and configured to output the Q digital signal and output it to the operation control device to collect the Q digital signal, and receive the adjustment sent by the operation control device.
  • the adjustment instruction is that the ADC data collected by the operation control device is offset from the signal of the I digital signal and the Q digital signal read by the same read pointer address from the FIFO queue unit at the same time (ie, no The signal data offset is different for the sampling period of the collected I-channel digital signal and the Q-channel digital signal, and may also be the I-channel digital signal and the Q-channel digital signal of the operation control device according to the collected The phase difference is not 90 degrees, thereby determining that the I digital signal and the Q digital signal are not orthogonal, thereby determining the acquired I The digital signal of the road and the signal data of the digital signal of the Q are offset.
  • the ADC 40 further comprising a disposed on the first delay adjusting unit 43 where a first switch circuit K l and the next first delay unit adjusting a configuration register configuration where line 43
  • the circuit b and the second switch K 2 of the register configuration bypass b further include a third switch ⁇ 3 on the line c where the second delay adjustment unit 44 is located, and a line c configuration at the second delay adjustment unit 44
  • the register configuration bypasses d and the register configures the fourth switch K 4 of bypass d.
  • the register configuration bypass b is used to bypass the first delay adjustment unit;
  • the register configuration bypass d is used to bypass the second delay adjustment unit;
  • the first switch and the third may be used.
  • the switch K 3 is turned off, and the second switch ⁇ 2 and the fourth switch ⁇ 4 are closed, so that the sampling clocks of the two independent signals do not need to pass through the first delay adjusting unit 43 and the second delay adjusting unit 44.
  • the adjustment simplifies the sampling process, reduces the loss of the ADC during the adjustment of the ADC, and improves the performance of the ADC.
  • the ADC provided by this embodiment can also be applied to the process of sampling only one received signal. Similarly, the one signal does not need to be adjusted by the sampling clock.
  • the ADC provided by the above embodiment can sample the signal at different sampling clocks according to different signals received, and has strong flexibility in practical applications.
  • the two orthogonal channels are adjusted.
  • the sampling clock of the analog signal improves the implementation cost of the system and the difficulty of design and debugging while improving the orthogonality of the two signals.
  • the adjustment of the clock so the ADC can control the adjustment of the signal sampling clock through the opening and closing of the switch.
  • each unit in the embodiment of the present invention may be integrated into one processing unit, or each unit may be physically independent, or two or more units in each unit may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the embodiment of the present invention provides an operation control device 70, as shown in FIG. 7, comprising: an acquisition unit 71, configured to acquire an I-channel digital signal and a Q-channel number that are output after the ADC samples the I-channel analog signal and the Q-channel analog signal. signal.
  • the operation unit 72 is configured to calculate a first adjustment delay and/or a second adjustment delay according to the I digital signal and the Q digital signal.
  • the sending unit 73 is configured to calculate a first adjustment time delay in the operation unit 72, and send the first adjustment delay to the ADC, so that the ADC adjusts the first sampling clock according to the first adjustment delay. a second sampling clock, and sampling the I analog signal by using the second sampling clock to obtain an I analog signal sampling point; or
  • the operation unit 72 calculates a second adjustment time delay, and sends the second adjustment delay to the ADC, so that the ADC adjusts the first sampling clock according to the second adjustment delay to obtain a third sampling clock, and Using the third sampling clock to sample the Q analog signal to obtain a Q analog signal sampling point; or
  • the first adjustment delay and the second adjustment delay are calculated by the operation unit 72, and the first adjustment delay and the second adjustment delay are sent to the ADC, so that the ADC is adjusted according to the first adjustment. Adjusting the first sampling clock to obtain a second sampling clock, adjusting the first sampling clock according to the second adjustment delay to obtain a third sampling clock, and sampling the I analog signal by using the second sampling clock to obtain an I-channel simulation The signal sampling point is used to sample the Q analog signal by using the third sampling clock to obtain a Q analog signal sampling point.
  • the first adjustment delay and the second adjustment delay are used to make the I analog signal sampling point and the Q analog signal sampling point orthogonal.
  • the sending unit 73 is further configured to collect the I digital signal and the Q by using the same read pointer address at the same time by the FIFO queue unit (including the first FIFO queue unit and the second FIFO queue unit) located in the ADC.
  • Road digital signal in determining the acquired I
  • an adjustment command is sent to the ADC to adjust the read pointer address of the digital signal of the I channel and/or the digital signal of the Q channel.
  • the operation unit may only determine the first adjustment delay, and the finally obtained I-channel analog signal sampling point is orthogonal to the Q-channel analog signal sampling point obtained without delay adjustment; or, the operation unit may only determine the second Adjusting the delay, and the resulting Q-channel analog signal sampling point is orthogonal to the I-channel analog signal sampling point obtained without delay adjustment;
  • the arithmetic unit may also determine the first adjustment delay and the second adjustment delay at the same time, and the adjusted and obtained analog signal sampling points and the Q analog signal sampling points are orthogonal.
  • the invention is not limited thereto.
  • the operation control device can be an FPGA (Field - Programmable Gate Array) or a DSP (Digital Signal Processing), which can realize fast and continuous delay.
  • the acquisition unit of the operation control device is an FPGA or a DSP, and the operation unit and the transmission unit of the operation control device are included in a CPU (Central Processing Unit) on the board.
  • the CPU Central Processing Unit
  • the operation control device acquisition unit is an FPGA or a DSP
  • the operation unit of the operation control device is a personal computer PC (personal computer)
  • the transmission unit of the operation control device is included in the CPU, and the implementation manner is applicable to the operation method. More complicated, the CPU on the board is difficult to complete the operation.
  • the sending unit when included in the CPU on the board, the first adjusting delay and/or the second adjusting delay are also written into the non-volatile memory.
  • the orthogonality of the two signals is improved, and the realization cost of the system and the difficulty of designing and debugging are reduced. It will be apparent to those skilled in the art that, for the convenience and brevity of the description, the specific working process of the ADC and the operation control device described above may be referred to the corresponding process in the foregoing method embodiments, and details are not described herein again.
  • each unit in the embodiment of the present invention may be integrated into one processing unit, or each unit may be physically independent, or two or more units in each unit may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or Implemented in the form of hardware plus software functional units.
  • the embodiment of the present invention provides a receiver 80, as shown in FIG. 8, comprising: the ADC 40 described in the above embodiment and the arithmetic control device 70 described in the above embodiment.
  • the orthogonality of the two signals is improved, and the realization cost of the system and the difficulty of designing and adjusting the j are reduced.
  • the above ADC is applied to the above method for improving the orthogonality of the complex signal IQ path
  • each unit in the ADC also corresponds to each step in the method
  • the above operation control device is also applied to the above improved complex signal.
  • the method of IQ path orthogonality, and each unit in the arithmetic control device also corresponds to each step in the method.
  • Embodiments of the present invention provide a communication system including the above receiver.
  • the communication system may be a GSM (Global System for Mobile communications), a CDMA (Code Division Multiple Access) system, or a TDMA (Time Division Multiple Access) system.
  • WCDMA Wideband Code Division Multiple Access Wireless
  • FDMA Frequency Division Multiple Addressing
  • OFDMA Orthogonal Frequency-Division Multiple Access
  • SC-FDMA Single Carrier FDMA
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution

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Abstract

本发明实施例提供一种改善复信号IQ路正交性的方法、设备和系统,涉及通信技术领域，在提高两路信号之间的正交性的同时，降低系统实现成本以及设计和调测难度，该方法包括：ADC接收I路模拟信号和Q路模拟信号；该ADC根据第一调整时延调整第一采样时钟得到第二采样时钟，利用该第二采样时钟对该I路模拟信号采样得到I路模拟信号采样点，并将该I路模拟信号采样点转换为I路数字信号；和/或，该ADC根据第二调整时延调整该第一采样时钟得到第三采样时钟，利用该第三采样时钟对该Q路模拟信号采样得到Q路模拟信号采样点，并将该Q路模拟信号采样点转换为Q路数字信号。本发明实施例用于改善复信号IQ路正交性。

Description

一种改善复信号 IQ路正交性的方法、 设备和系统 技术领域
本发明涉及通信技术领域， 尤其涉及一种改善复信号 IQ路正交性的 方法、 设备和系统。
背景技术
在复中频系统中， 随着信号带宽的加大， 信号中频频率的提高， 对 信号的正交性要求也随之不断提高， 因此， 在模拟信号通过 ADC ( Analog-to-Digital Converter, 模数转换器） 转化为数字信号的场景下， 由正交解调器输出的两路正交信号 （通常称为 In-phase component (同相 相位分量, 简称 I路信号 ) 和 Quadrature phase component (正交相位分 量， 简称 Q路信号） ） 在信号传输的过程中要保持正交性， 但是正交解 调器是由模拟电路实现的， 无法做到绝对的正交， 即两路信号产生了信 号延迟， 并且， 在信号传输的过程中也会产生信号延时， 从而进一步恶 化了两路正交信号的正交性。
现有技术中，主要通过选用正交性能更好的正交解调器或者通过精细 化仿真和反复调测的方法来改善正交信号正交性恶化的情况， 但是这样做 会提高系统的成本和设计难度， 同时会增加系统硬件的调测难度。
发明内容
本发明的实施例提供一种改善复信号 IQ路正交性的方法、 设备和 系统， 在提高复信号 IQ路之间的正交性的同时， 降低系统实现成本以及设 计和调测难度。 第一方面， 提供一种改善复信号 IQ路正交性的方法， 包括： 模数转换器 ( ADC )接收 I路模拟信号和 Q路模拟信号；
所述 A D C根据第一调整时延调整第一采样时钟得到第二采样时钟， 利用所述第二采样时钟对所述 I路模拟信号采样得到 I路模拟信号采样 点， 并将所述 I路模拟信号采样点转换为 I路数字信号； 和 /或，
所述 ADC根据第二调整时延调整所述第一采样时钟得到第三采样时 钟， 利用所述第三采样时钟对所述 Q路模拟信号采样得到 Q路模拟信号 采样点， 并将所述 Q路模拟信号采样点转换为 Q路数字信号； 其中， 所 述第一调整时延和所述第二调整时延用于使所述 I 路模拟信号采样点与 所述 Q路模拟信号采样点正交。
第一方面的第一种可能的实现方式中， 还包括接收所述第一调整时 延和 /或所述第二调整时延。
结合第一方面或第一方面的第一种可能的实现方式， 在第二种可能 的实现方式中， 所述 A D C根据第一调整时延调整第一采样时钟得到第二 采样时钟，利用所述第二采样时钟对所述 I路模拟信号采样得到 I路模拟 信号采样点， 并将所述 I路模拟信号采样点转换为 I路数字信号； 和 /或， 所述 ADC根据第二调整时延调整所述第一采样时钟得到第三采样时钟， 利用所述第三采样时钟对所述 Q路模拟信号采样得到 Q路模拟信号采样 点， 并将所述 Q路模拟信号采样点转换为 Q路数字信号之后， 还包括： 所述 ADC通过位于所述 ADC内部的先入先出 （FIFO ) 队列单元将 所述 I路数字信号和所述 Q路数字信号输出， 并输出给运算控制设备以 采集所述 I路数字信号和所述 Q路数字信号， 接收所述运算控制设备所 发的调整所述 I路数字信号和 /或所述 Q路数字信号的读指针地址的调整 指令， 所述调整指令是在所述运算控制设备在同一时刻相同读指针地址 从所述 FIFO队列单元采集的所述 I路数字信号和所述 Q路数字信号的信 号数据偏移时发出的。
结合第一方面以及第一种可能的实现方式和第二种可能的实现方 式， 在第三种可能的实现方式中， 所述 ADC将自身的时延初始值置 0, 这样， ADC可以利用所述第一采样时钟对 I路模拟信号和 Q路模拟信号 采样， 进而获得 I路模拟信号和 Q路模拟信号之间的时延差， 其中， 所 述时延初始值可以为所述 ADC对所述 I路模拟信号和 Q路模拟信号进行 首次采样的时延调整时间。
第二方面， 提供一种改善复信号 IQ路正交性的方法， 包括： 运算控制设备采集模数转换器 ( ADC ) 对 I路模拟信号和 Q路模拟 信号采样后输出的 I路数字信号和 Q路数字信号； 所述运算控制设备根据所述 I路数字信号和所述 Q路数字信号计算 出第一调整时延并将所述第一调整时延发送至 ADC, 则所述 ADC根据 所述第一调整时延调整所述第一采样时钟得到第二采样时钟， 并利用所 述第二采样时钟对所述 I路模拟信号采样得到 I路模拟信号采样点； 和 / 或， 所述运算控制设备根据所述 I路数字信号和所述 Q路数字信号计算 出第二调整时延， 所述运算控制设备将所述第二调整时延发送至 ADC, 则所述 ADC根据所述第二调整时延调整所述第一采样时钟得到第三采样 时钟， 并利用所述第三采样时钟对所述 Q路模拟信号采样得到 Q路模拟 信号采样点。
第二方面的第一种可能的实现方式中， 还包括： 所述运算控制设备 通过位于所述 ADC内的先入先出 （FIFO ) 队列单元采集所述 I路数字信 号和所述 Q路数字信号，在确定从所述 FIFO队列单元在同一时刻相同读 指针地址采集的所述 I路数字信号和所述 Q路数字信号的信号数据偏移 时， 向所述 ADC发送调整指令， 以调整所述 I路数字信号和 /或所述 Q 路数字信号的读指针地址。
结合第二方面或第二方面的第一种可能的实现方式， 在第二种可能 的实现方式中， 将所述第一调整时延和 /或所述第二调整时延写入非易失 性存储器。
第三方面， 提供一种模数转换器， 包括： 输入接口， 用于接收 I路 模拟信号和 Q路模拟信号；
输入接口， 用于接收 I路模拟信号和 Q路模拟信号；
第一时延调整单元， 用于根据第一调整时延调整第一采样时钟得到 第二采样时钟；
第二时延调整单元， 用于根据第二调整时延调整第一采样时钟得到 第三采样时钟；
第一内核单元， 用于利用所述第二采样时钟对所述输入接口接收的 I路模拟信号采样得到 I路模拟信号采样点， 并将所述 I路模拟信号采样 点转换为 I路数字信号；
第二内核单元， 用于利用所述第三采样时钟对所述输入接口接收的
Q路模拟信号采样得到 Q路模拟信号采样点， 并将所述 Q路模拟信号采 样点转换为 Q路数字信号；
其中， 所述第一调整时延和所述第二调整时延用于使所述 I路模拟 信号采样点和所述 Q路模拟信号采样点正交。
第三方面第一种可能的实现方式中， 还包括第一时延调整接口和第 二时延调整接口，
所述第一时延调整接口， 用于接收第一调整时延； 所述第二时延调整接口， 用于接收第二调整时延。
结合第三方面或第三方面第一种可能的实现方式， 在第二种可能的 实现方式中， 还包括：
第一先入先出 （FIFO ) 队列单元， 与所述第一内核单元相连， 用于 将所述 I路数字信号输出，并输出给运算控制设备以采集所述 I路数字信 号， 接收所述运算控制设备所发的调整所述 I路数字信号和 /或所述 Q路 数字信号的读指针地址的调整指令；
第二先入先出队列单元， 与所述第二内核单元相连， 用于将所述 Q 路数字信号输出， 并输出给运算控制设备以采集所述 Q路数字信号， 接 收所述运算控制设备所发的调整所述 I路数字信号和 /或所述 Q路数字信 号的读指针地址的调整指令；
所述调整指令是在所述运算控制设备在同一时刻相同读指针地址从 所述 FIFO队列单元采集的所述 I路数字信号和所述 Q路数字信号的信号 数据偏移时发出的。
结合第三方面或第三方面第一种可能的实现方式或第二种可能的实 现方式， 在第三种可能的实现方式中， 所述第一时延调整单元和所述第 二时延调整单元的时延初始值为 0, 所述时延初始值可以为所述 ADC对 所述 I路模拟信号和 Q路模拟信号进行首次采样的时延调整时间。
结合第三方面以及第三方面第一种可能的实现方式、 第二种可能的 实现方式和第三种可能的实现方式， 在第四种可能的实现方式中， 还包 括： 寄存器配置旁路， 用于对第一时延调整单元和第二时延调整单元进 行旁路。
第四方面， 提供一种运算控制设备， 包括：
采集单元， 用于采集模数转换器 ( ADC ) 对 I路模拟信号和 Q路模 拟信号采样后输出的 I路数字信号和 Q路数字信号；
运算单元， 用于根据所述 I路数字信号和所述 Q路数字信号运算出 第一调整时延和 /或第二调整时延；
发送单元， 用于在所述运算单元运算出第一调整时延时， 将所述第 一调整时延发送至所述 ADC, 以使得所述 ADC根据所述第一调整时延 调整所述第一采样时钟得到第二采样时钟， 并利用所述第二采样时钟对 所述 I路模拟信号采样得到 I路模拟信号采样点； 或者，
在所述运算单元运算出第二调整时延时， 将所述第二调整时延发送 至所述 ADC, 以使得所述 ADC根据所述第二调整时延调整所述第一采 样时钟得到第三采样时钟， 并利用所述第三采样时钟对所述 Q路模拟信 号采样得到 Q路模拟信号采样点； 或者，
在所述运算单元运算出第一调整时延时和第二调整时延时， 将所述 第一调整时延和所述第二调整时延发送至所述 ADC, 以使得所述 ADC 根据所述第一调整时延调整所述第一采样时钟得到第二采样时钟， 根据 所述第二调整时延调整所述第一采样时钟得到第三采样时钟， 并利用所 述第二采样时钟对所述 I路模拟信号采样得到 I路模拟信号采样点，利用 所述第三采样时钟对所述 Q路模拟信号采样得到 Q路模拟信号采样点； 其中，所述第一调整时延和第二调整时延用于使所述 I路模拟信号采样点 和所述 Q路模拟信号采样点正交。
第四方面第一种可能的实现方式中， 所述发送单元， 还用于通过位 于所述 ADC内的先入先出 （FIFO )队列单元在同一时刻相同读指针地址 采集所述 I路数字信号和所述 Q路数字信号， 在确定采集的所述 I路数 字信号和所述 Q路数字信号的信号数据偏移时，向所述 ADC发送调整指 令， 以调整所述 I路数字信号和 /或所述 Q路数字信号的读指针地址。
结合第四方面或第四方面第一种可能的实现方式， 在第二种可能的 实现方式中， 还包括： 所述运算控制设备为现场可编程门阵列 FPGA或 者数字信号处理器 DSP; 或者，
所述运算控制设备的采集单元为 FPGA或者 DSP , 所述运算控制设 备的运算单元和发送单元包含在单板上的中央处理器 （CPU ) 中； 或者， 所述运算控制设备采集单元为 FPGA或者 DSP, 所述运算控制设备 的运算单元为个人计算机 PC, 所述运算控制设备的发送单元包含在单板 上的 CPU中。
结合第二种可能的实现方式， 在第三种可能的实现方式中， 所述发 送单元包含在单板上的 CPU中时，还用于将所述第一调整时延和 /或所述 第二调整时延写入非易失性存储器。
第五方面， 提供一种接收机， 包括： 上述第三方面的提供的模数转 换器和第四方面提供的运算控制设备。
第六方面， 提供一种通信系统， 包括： 上述第五方面提供的接收机。 通过上述方案，将接收的 I路模拟信号和 Q路模拟信号利用第二采样 时钟和第三采样时钟采样得到 I路模拟信号采样点和 Q路模拟信号采样点， 并将 I路模拟信号采样点和 Q路模拟信号采样点转换为 I路数字信号和 Q 路数字信号， 这样， 在提高两路信号正交性的同时， 降低了系统的实现成 本以及设计和调测难度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下 面将对实施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅是本发明的一些实施例， 对于 本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以 根据这些附图获得其他的附图。
图 1为本发明实施例提供的一种改善复信号 IQ路正交性的方法示意 图；
图 2为本发明实施例提供的另一种改善复信号 IQ路正交性的方法示 意图；
图 3为本发明实施例提供的另一种改善复信号 IQ路正交性的方法示 意图；
图 4为本发明实施例提供的一种 ADC的结构示意图；
图 5为本发明实施例提供的另一种 ADC的结构示意图；
图 6为本发明实施例提供的另一种 ADC的结构示意图；
图 7为本发明实施例提供的一种运算控制设备的结构示意图； 图 8为本发明实施例提供的一种接收机；
图 9a为本发明实施例提供的一种模拟信号采样点的参考示意图； 图 9b为本发明实施例提供的另一种模拟信号采样点的参考示意图； 图 10a为本发明实施例提供的一种调整读指针地址的参考示意图； 图 10b 为本发明实施例提供的另一种调整读指针地址的参考示意 图；
图 1 1为本发明实施例提供的一种计算调整时延的参考示意图。
具体实施方式 下面将结合本发明实施例中的附图， 对本发明实施例中的技术 方案进行清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明 一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本 领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他 实施例， 都属于本发明保护的范围。 本发明实施例提供一种改善复信号 IQ路正交性的方法，如图 1所示， 该方法的执行主体为 ADC, 包括：
5101、 ADC接收 I路模拟信号和 Q路模拟信号。
其中，该 ADC用于通过采样将连续变量的模拟信号转换为更容易储 存、 处理和发送的离散的数字信号。
例如， ADC接收从正交解调器发送并分别经过数控衰减器和抗混叠 滤波器后的 I路模拟信号和 Q路模拟信号。
5102、该 ADC根据第一调整时延调整第一采样时钟得到第二采样时 钟，利用该第二采样时钟对该 I路模拟信号采样得到 I路模拟信号采样点 , 并将该 I路模拟信号采样点转换为 I路数字信号； 和 /或，
该 ADC根据第二调整时延调整该第一采样时钟得到第三采样时钟， 利用该第三采样时钟对该 Q路模拟信号采样得到 Q路模拟信号采样点， 并将该 Q路模拟信号采样点转换为 Q路数字信号。
其中， 该第一调整时延和该第二调整时延用于使该 I路模拟信号采 样点与该 Q路模拟信号采样点正交。
进一步地， 在步骤 S102之前， 该方法还可以包括： 接收第一调整时 延和 /或第二调整时延。 可选地， ADC将自身的时延初始值置 0, 并利用该第一采样时钟对 I路模拟信号和 Q路模拟信号采样； 其中， 该时延初始值为该 ADC对该 I路模拟信号和 Q路模拟信号进行首次采样的时延调整时间， 例如， 若该 I路模拟信号采样的时延初始值为 1秒，而 Q路模拟信号采样的时延初始 值为 0,则对 I路模拟信号采样的时钟比对 Q路模拟信号采样的时钟延迟 1秒， 这里只是举例说明， 本发明对此不作限定。
需要说明的是， ADC中的时延初始值可以都置 0, 也可以一个置 0, 另一个不置 0, 还可以是其他值， 并且若 I路模拟信号和 Q路模拟信号采 样的时延初始值不同， 则对 I路模拟信号和 Q路模拟信号采样的时钟也 不同， 本发明对此不作限定， 但是不论时延初始值为何值， 在后续的时 延调整中都会将该 I路模拟信号和 Q路模拟信号的初始值时延的差值抵 消， 例如， I路模拟信号采样的时延初始值为 X, Q路模拟信号采样的 时延初始值为 Y, X比 Y滞后一个周期而无法保持两路信号的正交性， 现将两路信号调整至 Z才能保持两路信号的正交性， 且 X和 Y都滞后于 Z, 则在后续获得的第二调整时延相对于获得的第三调整时延向前多调整 一个周期， 从而保持两路信号的正交， 这里只是举例说明， 本发明实施 例并不局限于此， 本发明实施例是以 ADC中的时延初始值都置 0为例进 行说明的。
具体地调整方式可以包括以下两种：
一种是通过调整 I路模拟信号的第一采样时钟得到第二采样时钟， 通过该第二采样时钟对该 I路模拟信号采样并转换得到的 I路数字信号， 与没有进行时延调整的 Q路模拟信号采样并转换得到的 Q路数字信号正 交。 或者，
通过调整 Q路模拟信号的第一采样时钟得到第三采样时钟， 通过该 第三采样时钟对该 Q路模拟信号采样并转换得到的 Q路数字信号， 与没 有进行时延调整的 I路模拟信号采样并转换得到的 I路数字信号正交。 另一种是同时调整 I路模拟信号和 Q路模拟信号的第一采样时钟分 别得到第二采样时钟和第三采样时钟，通过该第二采样时钟对该 I路模拟 信号采样并转换得到的 I路数字信号， 与通过第三采样时钟对 Q路模拟 信号采样并转换得到的 Q路数字信号正交。 示例地， 在实际的信号传输过程中， 信号会由于一些信号处理设备 (例如信号衰减器、 信号放大器和抗混叠滤波器等） 的作用产生不同的 时延， 造成 I路模拟信号和 Q路模拟信号在同一采样时钟被采样的采样 点发生偏移， 示例地， 参考图 9a进行说明， 其中， 图中所示的向上的箭 头表示 I路模拟信号被采样的时刻， 向下的箭头表示 Q路模拟信号被采 样的时刻，横轴线表示采样时钟， A点和 B点分别表示 I路模拟信号和 Q 路模拟信号在同一采样时刻被采样的两个采样点， 当 I路模拟信号和 Q 路模拟信号发生延时时， 则 ADC在同一采样时刻采样 I路模拟信号的采 样点为 C点， 采样 Q路模拟信号的采样点为 D点， 由图中可以看出， C 点和 D点因为信号时延的存在分别与 A点和 B点发生了偏移， 从而影响 了转换后的 I路数字信号与 Q路数字信号的正交性。 本发明实施例中 ADC 根据得到的第一调整时延调整第一采样时钟 得到第二采样时钟， 第二调整时延调整第一采样时钟得到第三采样时钟， 参考图 9b进行说明， 其中， 图中所示的向上的箭头表示 I路模拟信号被 采样的时刻， 向下的箭头表示 Q路模拟信号被采样的时刻， 横轴线表示 采样时钟， A点和 B点分别表示 I路模拟信号和 Q路模拟信号在同一采 样时刻被采样的两个采样点， C点和 D点分别表示 I路模拟信号和 Q路 模拟信号发生延时时同一采样时刻被采样的采样点， 这样， 运算控制模 块在采集 I路数字信号和 Q路数字信号后， 根据该 I路数字信号和 Q路 数字信号分别得到第二采样时钟和第三采样时钟， 并发送至 ADC, 以便 于 ADC在第二采样时钟对 I路模拟信号采样时， I路模拟信号被采样的 采样点调整到了 A点， ADC在第三采样时钟对 Q路模拟信号采样时， Q 路模拟信号被采样的采样点调整到了 B点，保证了 ADC在第二采样时钟 对 I路模拟信号在 A点进行采样， 同样地， 也保证了 ADC在第三采样时 钟对 Q路模拟信号在 B点进行采样。 进一步地， 采用上述方法得到的 I路数字信号和 Q路数字信号， 虽 然保持了 I路数字信号和 Q路数字信号的正交性， 却由于对 I路模拟信 号和 Q路模拟信号采样的时钟（即第二采样时钟和第三采样时钟）不同， 使得 ADC在同一时刻相同读指针地址读取 I路数字信号和 Q路数字信号 时，可能无法同时读取对 I路模拟信号在第二采样时钟采样的采样点和对 Q路模拟信号在第三采样时钟采样的采样点， 也就无法保持该 ADC输出 后的 I路数字信号和 Q路数字信号的正交性， 因此，基于上述方法步骤， 若运算控制设备确定所采集的 ADC在同一时刻相同读指针地址读取的 I 路数字信号和 Q路数字信号的信号数据偏移时， 该方法还包括：
该 ADC通过位于该 ADC内部的 FIFO ( First Input First Output, 先 入先出队列） 单元将该 I路数字信号和该 Q路数字信号输出， 并输出给 运算控制设备以采集该 I路数字信号和该 Q路数字信号， 接收该运算控 制设备所发的调整该 I路数字信号和该 Q路数字信号的读指针地址的调 整指令，
其中，该调整指令是在该运算控制设备所采集的 ADC在同一时刻相 同读指针地址从该 FIFO队列单元读取的该 I路数字信号和该 Q路数字信 号的信号数据偏移 （也即不正交） 时发出的； 该信号数据偏移为所采集 的所述 I路数字信号和 Q路数字信号的采样周期数不同， 也可为运算控 制设备根据采集的 I路数字信号和 Q路数字信号的相位差不为 90度， 从 而确定该 I路数字信号和 Q路数字信号没有保持正交， 进而确定采集的 该 I路数字信号和该 Q路数字信号的信号数据偏移。
具体地， 在执行延时调整后， 分两种情况进行说明： 第一种情况如 图 10a所示， 不需要 FIFO指针调整； 第二种情况如图 10b所示， 需要进 行 fifo指针调整。 下面针对上述两种情况分别进行具体描述。 图 10a中， I路数字信号的采样时钟为第二采样时钟， Q路数字信号 的采样时钟为第三采样时钟， 其中， I。、 Ii、 12为 I路数字信号根据第二 采样时钟连续采样的 3个信号数据， QQ、 Q i、 Q 2为 Q路数字信号根据第 三采样时钟连续采样的 3个信号数据， I-FIFO表示 I路数字信号对应的 第一 FIFO队列单元， Q-FIFO表示 Q路数字信号对应的第二 FIFO队列 单元， a点为 I-FIFO和 Q-FIFO的写启动信号的到达时刻， b点为 I路数 字信号接收到写启动信号后开始写 I路数字信号数据的时刻， c点为 Q路 数字信号接收到写启动信号后开始写 Q路数字信号数据的时刻， n为读 指针地址， 由于进行了延时调整， 类似 I。 QQ、 IjQ I2Q 2这样成对 （I 路数字信号数据与 Q路数字信号数据的下标相同） 的信号数据正交， 当 FIFO写启动信号在 a点位置到达时， 只要在同一时刻相同读指针地址读 取 I路数字信号和 Q路数字信号的信号数据， 总能得到类似 IQ QQ、 IiQ i , I2Q 2这样成对的信号数据。 因此， 不需要进行 FIFO指针的调整。
需要说明的是，上述的当 FIFO写启动信号在 a点位置到达只是举例 说明， 本发明实施例并不局限于此， 在实际应用中， 只要 FIFO写启动信 号的到达位置能够保证在同一时刻相同读指针地址读取 I 路数字信号和 Q 路数字信号的信号数据为成对的正交的信号数据都在本发明的保护范 围内。
图 10b中， I路数字信号的采样时钟为第二采样时钟， Q路数字信号 的采样时钟为第三采样时钟， 其中， I。、 Ii、 12为 I路数字信号根据第二 采样时钟连续采样的 3个信号数据， QQ、 02为 Q路数字信号根据第 三采样时钟连续采样的 3个信号数据， I-FIFO表示 I路数字信号对应的 第一 FIFO队列单元， Q-FIFO表示 Q路数字信号对应的第二 FIFO队列 单元， a点为 I-FIFO和 Q-FIFO的写启动信号的到达时刻， b点为 I路数 字信号接收到写启动信号后开始写 I路数字信号数据的时刻， c点为 Q路 数字信号接收到写启动信号后开始写 Q路数字信号数据的时刻， n为读 指针地址， 由于进行了延时调整， 类似 I。 QQ、 IjQ 12(^ 2这样成对 （I 路数字信号数据与 Q路数字信号数据的下标相同） 的信号数据正交。 当 FIFO写启动信号在图示 a点位置到达， 则在同一时刻相同读指针地址读 取 I路数字信号和 Q路数字信号的信号数据， 得到的是类似 1^。、 I2Q！ 这样不成对 （即 I路数字信号数据与 Q路数字信号数据的下标不同） 的 信号数据， 也就无法得到正交的信号数据， 需要进行 FIFO指针的调整。 具体的， 可以调整 Q-FIFO的读指针地址， 使得当读取 I路数字信号的 信号数据时， 在同一时刻相同读指针地址读取 Q路数字信号时保证读取 到 信号数据， 从而得到了成对的正交性较好的信号数据。 需要说明的是， 上述实施例中调整 Q-FIFO 的读指针地址只是举例 说明， 本发明实施例并不局限于此， 还可以通过调整 I-FIFO的读指针地 址从而得到了成对的正交的信号数据， 当然， 也可以同时调整 I-FIFO和 Q-FIFO , 只要能够得到成对的正交的信号数据的调整方式都在本发明的 保护范围内。
上述的方法实施例的执行主体为 ADC, 采用上述方法， 在提高两路 信号正交性的同时， 降低了系统的实现成本以及设计和调测难度。
本发明实施例提供另一种改善复信号 IQ路正交性的方法，如图 2所 示， 该方法的执行主体为运算控制设备， 包括：
5201、运算控制设备采集 ADC对 I路模拟信号和 Q路模拟信号采样 后输出的 I路数字信号和 Q路数字信号。
5202、 运算控制设备根据该 I路数字信号和该 Q路数字信号计算出 第一调整时延并将该第一调整时延发送至 ADC, 则该 ADC根据该第一 调整时延调整该第一采样时钟得到第二采样时钟， 并利用该第二采样时 钟对该 I路模拟信号采样得到 I路模拟信号采样点； 和 /或， 该运算控制设备根据该 I路数字信号和该 Q路数字信号计算出第二 调整时延， 该运算控制设备将该第二调整时延发送至 ADC, 则该 ADC 根据该第二调整时延调整该第一采样时钟得到第三采样时钟， 并利用该 第三采样时钟对该 Q路模拟信号采样得到 Q路模拟信号采样点。 可选地， 运算控制设备将该第一调整时延和 /或该第二调整时延写入 非易失性存储器。
具体地计算过程参考图 11进行说明， 如图 11所示， 图 11表示 I+jQ 的幅频特性图， 横轴表示 ADC的采样频率 （Fs ) , 纵轴表示信号幅度， 主信号区域的面积表示信号本身的能量， 镜像信号区域的面积表示镜像 信号的能量， 其中， 镜像信号是由于 I路数字信号和 Q路数字信号不正 交产生的， 且主信号区域与镜像信号区域是关于二分之 Fs对称的， 由于 主信号能量与镜像信号能量的比值与 I路数字信号和 Q路数字信号距正 交偏差的时延相对应， 因此， 可以根据主信号能量与镜像信号能量的比 值得到 I路数字信号和 Q路数字信号距正交偏差的时延。
进一步地， 通过 I路数字信号和 Q路数字信号距正交偏差的时延可 以确定第一调整时延和第二调整时延， 具体地， 运算控制设备可以只确 定第一调整时延，且最终得到的 I路模拟信号采样点与没有进行时延调整 得到的 Q路模拟信号采样点正交； 或者， 运算控制设备可以只确定第二 调整时延， 且最终得到的 Q路模拟信号采样点与没有进行时延调整得到 的 I路模拟信号采样点正交； 运算控制设备还可以同时确定第一调整时延和第二调整时延， 且调 整并得到的 I路模拟信号采样点和 Q路模拟信号采样点正交。 本发明对 此不作限定。 可选地， 运算控制设备将该第一调整时延发送至 ADC, 则该 ADC 根据该第一调整时延调整该第一采样时钟得到第二采样时钟， 并利用该 第二采样时钟对该 I路模拟信号采样得到 I路模拟信号采样点； 或者， 运算控制设备将该第二调整时延发送至 ADC, 则该 ADC根据该第 二调整时延调整该第一采样时钟得到第三采样时钟， 并利用该第三采样 时钟对该 Q路模拟信号采样得到 Q路模拟信号采样点； 或者，
运算控制设备将该第一调整时延和该第二调整时延都发送至该 ADC , 则该 ADC根据该第一调整时延调整该第一采样时钟得到第二采样 时钟， 根据该第二调整时延调整该第一采样时钟得到第三采样时钟， 并 利用该第二采样时钟对该 I路模拟信号采样得到 I路模拟信号采样点，利 用该第三采样时钟对该 Q路模拟信号采样得到 Q路模拟信号采样点。 其中， 该第一调整时延和第二调整时延用于使该 I路模拟信号采样 点和该 Q路模拟信号采样点正交。
进一步地，为了保持 ADC在读取后输出的 I路数字信号和 Q路数字 信号的正交性， 该方法还包括：
该运算控制设备通过位于该 ADC 内的先入先出 （FIFO ) 队列单元 采集该 I路数字信号和该 Q路数字信号，在确定从该 FIFO队列单元在同 一时刻相同读指针地址采集的该 I路数字信号和该 Q路数字信号的信号 数据偏移时， 向该 ADC发送调整指令， 以调整该 I路数字信号和 /或该 Q 路数字信号的读指针地址。
需要说明的是， 对调整指针地址具体过程的说明， 参考上述实施例 中对图 10a和图 10b的说明， 此处就不再贅述了。 上述的方法实施例的执行主体为运算控制设备， 采用上述方法， 在 提高两路信号正交性的同时， 降低了系统的实现成本以及设计和调测难 度。
本发明实施例提供另一种改善复信号 IQ路正交性的方法，如图 3所 示， 该方法具体步骤包括：
S301、 ADC接收 I路模拟信号和 Q路模拟信号。
其中，该 ADC用于通过采样将连续变量的模拟信号转换为更容易储 存、 处理和发送的离散的数字信号。 例如， ADC接收从正交解调器发送并分别经过数控衰减器和抗混叠 滤波器后的 I路模拟信号和 Q路模拟信号。
5302、运算控制设备采集 ADC利用第一采样时钟对 I路模拟信号和 Q路模拟信号采样后输出的 I路数字信号和 Q路数字信号。
5303、 运算控制设备根据该 I路数字信号和该 Q路数字信号计算出 第一调整时延和第二调整时延， 并将该第一调整时延和第二调整时延发 送至 ADC。
具体的计算过程参考上述实施例对图 1 1 的说明， 在此就不再贅述 了。
5304、 该 ADC接收该第一调整时延和第二调整时延， 根据该第一调 整时延调整该第一采样时钟得到第二采样时钟， 并根据该第二调整时延 调整该第一采样时钟得到第三采样时钟。
5305、 该 ADC利用该第二采样时钟对该 I路模拟信号采样得到 I路 模拟信号采样点， 并将该 I路模拟信号采样点转换为 I路数字信号， 利用 该第三采样时钟对该 Q路模拟信号采样得到 Q路模拟信号采样点， 并将 该 Q路模拟信号采样点转换为 Q路数字信号。
其中， 该第一调整时延和该第二调整时延用于使该 I路模拟信号采 样点与该 Q路模拟信号采样点正交。
5306、 运算控制设备通过位于 ADC内的 FIFO队列单元在同一时刻 相同读指针地址采集该 I路数字信号和该 Q路数字信号。
5307、运算控制设备在确定从该 FIFO队列单元采集出的该 I路数字 信号和该 Q路数字信号的信号数据偏移时， 向该 ADC发送调整指令。
其中，该调整指令是在该运算控制设备所采集的 ADC在同一时刻相 同读指针地址从该 FIFO队列单元读取的该 I路数字信号和该 Q路数字信 号的信号数据偏移 （也即不正交） 时发出的； 该信号数据偏移为采集的 所述 I路数字信号和 Q路数字信号的采样周期数不同， 也可为运算控制 设备根据采集的 I路数字信号和 Q路数字信号的相位差不为 90度， 从而 确定该 I路数字信号和 Q路数字信号没有保持正交， 进而确定采集的该 I 路数字信号和该 Q路数字信号的信号数据偏移。
5308、 ADC根据该调整指令调整该 I路数字信号和该 Q路数字信号 的读指针地址。
其中， 对调整读指针地址具体过程的说明， 参考上述实施例中对图 10a和图 10b的说明， 此处就不再贅述了。 采用上述方法， 在提高两路信号正交性的同时， 降低了系统的实现 成本以及设计和调测难度， 同时， 保持了 ADC在同一时刻相同读指针地 址读取的两路信号的正交性。
需要说明的是， 对于前述的各方法实施例， 为了简单描述， 故将其 都表述为一系列的动作组合， 但是本领域技术人员应该知悉， 本发明并 不受所描述的动作顺序的限制， 其次， 本领域技术人员也应该知悉， 说 明书中所描述的实施例均属于优选实施例， 所涉及的动作和模块并不一 定是本发明所必须的。
本发明实施例提供一种模数转换器 ADC40, 如图 4所示， 包括： 输入接口， 用于接收 I路模拟信号和 Q路模拟信号。
例如， 接收从正交解调器发送并分别经过数控衰减器和抗混叠滤波 器后的 I路模拟信号和 Q路模拟信号。 第一内核单元 41 , 用于利用该第二采样时钟对该输入接口接收的 I 路模拟信号采样得到 I路模拟信号采样点，并将该 I路模拟信号采样点转 换为 I路数字信号。
第二内核单元 42, 用于利用该第三采样时钟对该输入接口接收的 Q 路模拟信号采样得到 Q路模拟信号采样点 , 并将该 Q路模拟信号采样点 转换为 Q路数字信号。
第一时延调整单元 43 , 用于根据第一调整时延调整第一采样时钟得 到第二采样时钟。 第二时延调整单元 44 , 用于根据第二调整时延调整第一采样时钟得 到第三采样时钟。 其中， 该第一调整时延和该第二调整时延用于使该 I路模拟信号采 样点和该 Q路模拟信号采样点正交。
可选地， 第一时延调整单元 43和第二时延调整单元 44的时延初始 值为 0 , 其中， 该时延初始值可以为该 ADC对该 I路模拟信号和 Q路模 拟信号进行首次采样的时延调整时间。
需要说明的是， 第一时延调整单元 43和第二时延调整单元 44的时 延初始值可以都为 0 , 也可以一个为 0, 另一个不为 0 , 还可以是其他值， 并且若 I路模拟信号和 Q路模拟信号采样的时延初始值不同， 则对 I路 模拟信号和 Q路模拟信号采样的时钟也不同， 本发明对此不作限定， 但 是不论时延初始值为何值，在后续的时延调整中都会将该 I路模拟信号和 Q路模拟信号的初始值时延的差值抵消， 例如， I路模拟信号采样的时延 初始值为 X , Q路模拟信号采样的时延初始值为 Υ , X比 Y滞后一个周 期而无法保持两路信号的正交性， 现将两路信号调整至 Z才能保持两路 信号的正交性， 且 X和 Y都滞后于 Z , 则在后续获得的第二调整时延相 对于获得的第三调整时延向前多调整一个周期， 从而保持两路信号的正 交， 这里只是举例说明， 本发明实施例并不局限于此。
进一步地，该 ADC还包括：第一时延调整接口和第二时延调整接口， 该第一时延调整接口， 用于接收第一调整时延。
其中，该第一时延调整接口接收运算控制设备发送的第一调整时延。 该第二时延调整接口， 用于接收第二调整时延。 其中，该第二时延调整接口接收运算控制设备发送的第二调整时延。 需要说明的是， 在实际应用中， 上述输入接口和上述第一时延调整 接口以及第二时延调整接口还可以集成为同一个接口， 也可以为各自独 立的接口， 或者， 输入接口为独立的接口， 第一时延调整接口和第二时 延调整接口集成为一个接口， 本发明对此不作限定。
可选地， 如图 5所示， 该 ADC40还包括： 第一 FIFO队列单元 45 , 与该第一内核单元 41相连， 用于将该 I路数字信号输出， 并输出给运算 控制设备以采集该 I 路数字信号， 接收该运算控制设备所发的调整该 I 路数字信号和该 Q路数字信号的读指针地址的调整指令。
第二 FIFO队列单元 46 , 与该第二内核单元 42相连， 用于将该 Q路 数字信号输出， 并输出给运算控制设备以采集该 Q路数字信号， 接收该 运算控制设备所发的调整该 I路数字信号和该 Q路数字信号的读指针地 址的调整指令；
其中，该调整指令是在该运算控制设备所采集的 ADC在同一时刻相 同读指针地址从该 FIFO队列单元读取的该 I路数字信号和该 Q路数字信 号的信号数据偏移 （也即不正交） 时发出的； 该信号数据偏移为采集的 所述 I路数字信号和 Q路数字信号的采样周期数不同， 也可为运算控制 设备根据采集的 I路数字信号和 Q路数字信号的相位差不为 90度， 从而 确定该 I路数字信号和 Q路数字信号没有保持正交， 进而确定采集的该 I 路数字信号和该 Q路数字信号的信号数据偏移。
优选地， 如图 6 所示， 该 ADC40 , 还包括在第一时延调整单元 43 所在线路 a上配置的第一开关 Kl 以及在第一时延调整单元 43所在线路 a配置的寄存器配置旁路 b和该寄存器配置旁路 b的第二开关 K2, 还包 括在第二时延调整单元 44所在线路 c上的第三开关 Κ3, 以及在第二时延 调整单元 44所在线路 c配置的寄存器配置旁路 d和该寄存器配置旁路 d 的第四开关 K4。
其中， 上述寄存器配置旁路 b用于对第一时延调整单元进行旁路； 上述寄存器配置旁路 d用于对第二时延调整单元进行旁路；
具体地， 当传输两路相互独立的信号 （即不存在正交性而独立传输 的信号） 时， 并不需要对该两路独立信号进行采样时钟的调整， 则可以 将第一开关 和第三开关 K3断开， 将第二开关 Κ2和第四开关 Κ4闭合， 这样， 该两路独立信号的采样时钟就不需要再通过第一时延调整单元 43 和第二时延调整单元 44进行调整， 简化了采样的过程， 降低了 ADC调 整时延时对设备的损耗， 提高了 ADC的性能。 该实施例提供的 ADC 还可以应用在只对接收的一路信号进行采样 的过程， 同样地， 该一路信号也不需要进行采样时钟的调整， 示例地， 当第一内核单元 41接收该一路信号时， 将第一开关 断开， 第二开关 K2闭合； 或者， 当第二内核单元 42接收该一路信号时， 将第三开关 Κ3 断开， 第四开关 Κ4闭合。 上述实施例提供的 ADC 能够根据接收的不同信号在不同的采样时 钟对信号进行采样， 在实际应用方面具有很强的灵活性， 当接收两路相 互正交的信号时， 通过调整两路正交的模拟信号的采样时钟， 在提高两 路信号正交性的同时， 降低了系统的实现成本以及设计和调测难度； 当 接收两路独立信号或者只接收到一路信号时， 由于不需要进行采样时钟 的调整， 所以该 ADC可以通过开关的断开与闭合来控制信号采样时钟的 调整。
所属本领域的技术人员可以清楚地了解到， 为描述的方便和简洁， 上述描述的 ADC和运算控制设备的具体工作过程， 可以参考前述方法实 施例中的对应过程， 在此不再贅述。 另外， 在本发明实施例中的各单元可以集成在一个处理单元中， 也 可以是各个单元物理独立， 也可以各单元中的两个或两个以上单元集成 在一个单元中。 上述集成的单元既可以采用硬件的形式实现， 也可以采 用硬件加软件功能单元的形式实现。
本发明实施例提供一种运算控制设备 70, 如图 7所示， 包括： 采集单元 71 , 用于采集 ADC对 I路模拟信号和 Q路模拟信号采样 后输出的 I路数字信号和 Q路数字信号。
运算单元 72, 用于根据该 I路数字信号和该 Q路数字信号计算出第 一调整时延和 /或第二调整时延。
具体的计算过程参考上述实施例对图 1 1 的说明， 在此就不再贅述 了。
发送单元 73 , 用于在该运算单元 72运算出第一调整时延时， 将该 第一调整时延发送至该 ADC, 以使得该 ADC根据该第一调整时延调整 该第一采样时钟得到第二采样时钟，并利用该第二采样时钟对该 I路模拟 信号采样得到 I路模拟信号采样点； 或者，
在该运算单元 72运算出第二调整时延时，将该第二调整时延发送至 该 ADC, 以使得该 ADC根据该第二调整时延调整该第一采样时钟得到 第三采样时钟， 并利用该第三采样时钟对该 Q路模拟信号采样得到 Q路 模拟信号采样点； 或者，
在该运算单元 72运算出第一调整时延时和第二调整时延时，将该第 一调整时延和该第二调整时延发送至该 ADC, 以使得该 ADC根据该第 一调整时延调整该第一采样时钟得到第二采样时钟， 根据该第二调整时 延调整该第一采样时钟得到第三采样时钟， 并利用该第二采样时钟对该 I 路模拟信号采样得到 I路模拟信号采样点， 利用该第三采样时钟对该 Q 路模拟信号采样得到 Q路模拟信号采样点。
其中， 该第一调整时延和第二调整时延用于使该 I路模拟信号采样 点和该 Q路模拟信号采样点正交。
进一步地， 该发送单元 73 , 还用于通过位于该 ADC内的 FIFO队列 单元 （包括第一 FIFO队列单元和第二 FIFO队列单元） 在同一时刻相同 读指针地址采集该 I路数字信号和该 Q路数字信号， 在确定采集的该 I 路数字信号和该 Q路数字信号的信号数据偏移时，向该 ADC发送调整指 令， 以调整该 I路数字信号和 /或该 Q路数字信号的读指针地址。
具体地， 运算单元可以只确定第一调整时延， 且最终得到的 I路模 拟信号采样点与没有进行时延调整得到的 Q路模拟信号采样点正交； 或 者， 运算单元可以只确定第二调整时延， 且最终得到的 Q路模拟信号采 样点与没有进行时延调整得到的 I路模拟信号采样点正交；
运算单元还可以同时确定第一调整时延和第二调整时延， 且调整并 得到的 I路模拟信号采样点和 Q路模拟信号采样点正交。 本发明对此不 作限定。
需要说明的是，该运算控制设备可以为 FPGA ( Field - Programmable Gate Array, 现场可编程门阵列 )或者 DSP ( Digital Signal Processing, 数 字信号处理器） ， 这种实现方式能够实现快速、 连续的时延调整； 或者， 该运算控制设备的采集单元为 FPGA或者 DSP, 该运算控制设备的 运算单元和发送单元包含在单板上的 CPU ( Central Processing Unit, 中央 处理器）中， 这种实现方式不占用逻辑或者 DSP资源， CPU只计算一次， 后续每次上电直接配置即可； 或者，
该运算控制设备采集单元为 FPGA或者 DSP , 该运算控制设备的运 算单元为个人计算机 PC ( personal computer, 个人计算机） ， 该运算控 制设备的发送单元包含在 CPU中， 这种实现方式适用于运算方法比较复 杂， 单板上的 CPU很难完成运算的情况。
进一步地， 该发送单元包含在单板上的 CPU中时， 还用于将该第一 调整时延和 /或该第二调整时延写入非易失性存储器。 采用上述的运算控制设备， 在提高两路信号正交性的同时， 降低了 系统的实现成本以及设计和调测难度。 所属本领域的技术人员可以清楚地了解到， 为描述的方便和简洁， 上述描述的 ADC和运算控制设备的具体工作过程， 可以参考前述方法实 施例中的对应过程， 在此不再贅述。 另外， 在本发明实施例中的各单元可以集成在一个处理单元中， 也 可以是各个单元物理独立， 也可以各单元中的两个或两个以上单元集成 在一个单元中。 上述集成的单元既可以采用硬件的形式实现， 也可以采 用硬件加软件功能单元的形式实现。
本发明实施例提供一种接收机 80 , 如图 8所示， 包括： 上述实施例 描述的 ADC40和上述实施例描述的运算控制设备 70。
采用上述的接收机， 在提高两路信号正交性的同时， 降低了系统的 实现成本以及设计和调 'j难度。
需要说明的是， 上述 ADC应用于上述改善复信号 IQ路正交性的方 法， 且该 ADC中的各个单元也与该方法中的各步骤相对应， 上述运算控 制设备也应用于上述改善复信号 IQ路正交性的方法， 且该运算控制设备 中的各个单元也与该方法中的各步骤相对应。 本发明实施例提供一种通信系统， 包括上述接收机。
需要说明的是， 该通信系统可以是 GSM ( Global System for Mobile communications , 全球移动通信系统), CDMA ( Code Division Multiple Access , 码分多址） 系统， TDMA ( Time Division Multiple Access , 时 分多址） 系统， WCDMA ( Wideband Code Division Multiple Access Wireless , 宽带码分多 址 ) , FDMA ( Frequency Division Multiple Addressing , 频分多址)系统, OFDMA ( Orthogonal Frequency-Division Multiple Access , 正交频分多址） 系统， 单载波 FDMA ( SC-FDMA ) 系 统， GPRS ( General Packet Radio Service , 通用分组无线业务 ) 系统， LTE ( Long Term Evolution , 长期演进） 系统， 以及其他此类通信系统。 采用上述的通信系统， 在提高两路信号正交性的同时， 降低了系统 的实现成本以及设计和调测难度。 本发明实施例中的 "和 /或" 指的是 "和" ， 或者， "或" ， 例如 A 和 /或 B , 代表的是 "A和 B" , 或者， "A或 B" , 也就是， A, B , A 和 B三种情况中的任意一种。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围 并不局限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技 术范围内， 可轻易想到变化或替换， 都应涵盖在本发明的保护范围 之内。 因此， 本发明的保护范围应所述以权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种改善复信号 IQ路正交性的方法， 其特征在于， 包括： 模数转换器 ( ADC )接收 I路模拟信号和 Q路模拟信号；
所述 A D C根据第一调整时延调整第一采样时钟得到第二采样时钟， 利用所述第二采样时钟对所述 I路模拟信号采样得到 I路模拟信号采样 点， 并将所述 I路模拟信号采样点转换为 I路数字信号； 和 /或，
所述 ADC根据第二调整时延调整所述第一采样时钟得到第三采样时 钟， 利用所述第三采样时钟对所述 Q路模拟信号采样得到 Q路模拟信号 采样点， 并将所述 Q路模拟信号采样点转换为 Q路数字信号； 其中， 所 述第一调整时延和所述第二调整时延用于使所述 I 路模拟信号采样点与 所述 Q路模拟信号采样点正交。
2、 根据权利要求 1所述的方法， 其特征在于， 还包括接收所述第一 调整时延和 /或所述第二调整时延。
3、 根据权利要求 1或 2所述的方法， 其特征在于， 所述 ADC根据 第一调整时延调整第一采样时钟得到第二采样时钟， 利用所述第二采样 时钟对所述 I路模拟信号采样得到 I路模拟信号采样点， 并将所述 I路模 拟信号采样点转换为 I路数字信号； 和 /或， 所述 ADC根据第二调整时延 调整所述第一采样时钟得到第三采样时钟， 利用所述第三采样时钟对所 述 Q路模拟信号采样得到 Q路模拟信号采样点， 并将所述 Q路模拟信号 采样点转换为 Q路数字信号之后， 还包括：
所述 ADC通过位于所述 ADC内部的先入先出 （FIFO ) 队列单元将 所述 I路数字信号和所述 Q路数字信号输出， 并输出给运算控制设备以 采集所述 I路数字信号和所述 Q路数字信号， 接收所述运算控制设备所 发的调整所述 I路数字信号和 /或所述 Q路数字信号的读指针地址的调整 指令， 所述调整指令是在所述运算控制设备在同一时刻相同读指针地址 从所述 FIFO队列单元采集的所述 I路数字信号和所述 Q路数字信号的信 号数据偏移时发出的。
4、 根据权利要求 1至 3任一项所述的方法， 其特征在于， 还包括： 所述 ADC将自身的时延初始值置 0, 并利用所述第一采样时钟对 I路模 拟信号和 Q路模拟信号采样， 所述时延初始值为所述 ADC对所述 I路模 拟信号和 Q路模拟信号进行首次采样的时延调整时间。
5、 一种改善复信号 IQ路正交性的方法， 其特征在于， 包括： 运算控制设备采集模数转换器 （ ADC ) 对 I路模拟信号和 Q路模拟 信号采样后输出的 I路数字信号和 Q路数字信号； 所述运算控制设备根据所述 I路数字信号和所述 Q路数字信号计算 出第一调整时延并将所述第一调整时延发送至 ADC,则所述 ADC根据所 述第一调整时延调整所述第一采样时钟得到第二采样时钟， 并利用所述 第二采样时钟对所述 I路模拟信号采样得到 I路模拟信号采样点； 和 /或， 所述运算控制设备根据所述 I路数字信号和所述 Q路数字信号计算 出第二调整时延， 所述运算控制设备将所述第二调整时延发送至 ADC, 则所述 ADC根据所述第二调整时延调整所述第一采样时钟得到第三采样 时钟， 并利用所述第三采样时钟对所述 Q路模拟信号采样得到 Q路模拟 信号采样点。
6、 根据权利要求 5所述的方法， 其特征在于， 还包括：
所述运算控制设备通过位于所述 ADC内的先入先出（FIFO )队列单 元采集所述 I路数字信号和所述 Q路数字信号，在确定从所述 FIFO队列 单元在同一时刻相同读指针地址采集的所述 I路数字信号和所述 Q路数 字信号的信号数据偏移时， 向所述 ADC发送调整指令， 以调整所述 I路 数字信号和 /或所述 Q路数字信号的读指针地址。
7、 根据权利要求 5或 6所述的方法， 其特征在于， 还包括： 将所述第一调整时延和 /或所述第二调整时延写入非易失性存储器。
8、 一种模数转换器 （ADC ) , 其特征在于， 包括：
输入接口， 用于接收 I路模拟信号和 Q路模拟信号；
第一时延调整单元， 用于根据第一调整时延调整第一采样时钟得到 第二采样时钟；
第二时延调整单元， 用于根据第二调整时延调整第一采样时钟得到 第三采样时钟；
第一内核单元， 用于利用所述第二采样时钟对所述输入接口接收的 I路模拟信号采样得到 I路模拟信号采样点， 并将所述 I路模拟信号采样 点转换为 I路数字信号；
第二内核单元， 用于利用所述第三采样时钟对所述输入接口接收的
Q路模拟信号采样得到 Q路模拟信号采样点， 并将所述 Q路模拟信号采 样点转换为 Q路数字信号； 其中， 所述第一调整时延和所述第二调整时延用于使所述 I路模拟 信号采样点和所述 Q路模拟信号采样点正交。
9、 根据权利要求 8 所述的 ADC, 其特征在于， 还包括第一时延调 整接口和第二时延调整接口，
所述第一时延调整接口， 用于接收第一调整时延；
所述第二时延调整接口， 用于接收第二调整时延。
10、 根据权利要求 8或 9所述的 ADC, 其特征在于， 还包括： 第一先入先出 （FIFO ) 队列单元， 与所述第一内核单元相连， 用于 将所述 I路数字信号输出，并输出给运算控制设备以采集所述 I路数字信 号， 接收所述运算控制设备所发的调整所述 I路数字信号和 /或所述 Q路 数字信号的读指针地址的调整指令；
第二先入先出队列单元， 与所述第二内核单元相连， 用于将所述 Q 路数字信号输出， 并输出给运算控制设备以采集所述 Q路数字信号， 接 收所述运算控制设备所发的调整所述 I路数字信号和 /或所述 Q路数字信 号的读指针地址的调整指令；
所述调整指令是在所述运算控制设备在同一时刻相同读指针地址从 所述 FIFO队列单元采集的所述 I路数字信号和所述 Q路数字信号的信号 数据偏移时发出的。
1 1、 根据权利要求 8至 10任一项所述的 ADC, 其特征在于， 所述 第一时延调整单元和所述第二时延调整单元的时延初始值为 0,所述时延 初始值为所述 ADC对所述 I路模拟信号和 Q路模拟信号进行首次采样的 时延调整时间。
12、 根据权利要求 8至 11 中任一项所述的 ADC, 其特征在于， 还 包括寄存器配置旁路， 用于对第一时延调整单元和 /或第二时延调整单元 进行旁路。
13、 一种运算控制设备， 其特征在于， 包括：
采集单元， 用于采集模数转换器 ( ADC ) 对 I路模拟信号和 Q路模 拟信号采样后输出的 I路数字信号和 Q路数字信号；
运算单元， 用于根据所述 I路数字信号和所述 Q路数字信号运算出 第一调整时延和 /或第二调整时延；
发送单元， 用于在所述运算单元运算出第一调整时延时， 将所述第 一调整时延发送至所述 ADC,以使得所述 ADC根据所述第一调整时延调 整所述第一采样时钟得到第二采样时钟， 并利用所述第二采样时钟对所 述 I路模拟信号采样得到 I路模拟信号采样点； 或者，
在所述运算单元运算出第二调整时延时， 将所述第二调整时延发送 至所述 ADC,以使得所述 ADC根据所述第二调整时延调整所述第一采样 时钟得到第三采样时钟， 并利用所述第三采样时钟对所述 Q路模拟信号 采样得到 Q路模拟信号采样点； 或者，
在所述运算单元运算出第一调整时延时和第二调整时延时， 将所述 第一调整时延和所述第二调整时延发送至所述 ADC , 以使得所述 ADC 根据所述第一调整时延调整所述第一采样时钟得到第二采样时钟， 根据 所述第二调整时延调整所述第一采样时钟得到第三采样时钟， 并利用所 述第二采样时钟对所述 I路模拟信号采样得到 I路模拟信号采样点，利用 所述第三采样时钟对所述 Q路模拟信号采样得到 Q路模拟信号采样点； 其中，所述第一调整时延和第二调整时延用于使所述 I路模拟信号采样点 和所述 Q路模拟信号采样点正交。
14、 根据权利要求 13所述的设备， 其特征在于， 所述发送单元， 还 用于通过位于所述 ADC内的先入先出 （FIFO )队列单元在同一时刻相同 读指针地址采集所述 I路数字信号和所述 Q路数字信号， 在确定采集的 所述 I路数字信号和所述 Q路数字信号的信号数据偏移时， 向所述 ADC 发送调整指令， 以调整所述 I路数字信号和 /或所述 Q路数字信号的读指 针地址。
15、 根据权利要求 13或 14所述的设备， 其特征在于， 所述运算控 制设备为现场可编程门阵列 （FPGA ) 或者数字信号处理器 （DSP ) ； 或 者，
所述运算控制设备的采集单元为 FPGA或者 DSP , 所述运算控制设 备的运算单元和发送单元包含在单板上的中央处理器 （CPU ) 中； 或者， 所述运算控制设备采集单元为 FPGA或者 DSP , 所述运算控制设备 的运算单元为个人计算机 PC, 所述运算控制设备的发送单元包含在单板 上的 CPU中。
16、 根据权利要求 15所述的设备， 其特征在于， 所述发送单元包含 在单板上的 CPU中时，还用于将所述第一调整时延和 /或所述第二调整时 延写入非易失性存储器。
17、 一种接收机， 其特征在于， 包括： 根据权利要求 8至 12任意一 项所述的模数转换器 （ADC ) 和根据权利要求 13至 16任意一项所述的 运算控制设备。
18、 一种通信系统， 其特征在于， 包括： 权利要求 17所述的接收机。
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