WO2014008674A1 - 阵列基板及液晶面板 - Google Patents

阵列基板及液晶面板 Download PDF

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Publication number
WO2014008674A1
WO2014008674A1 PCT/CN2012/078741 CN2012078741W WO2014008674A1 WO 2014008674 A1 WO2014008674 A1 WO 2014008674A1 CN 2012078741 W CN2012078741 W CN 2012078741W WO 2014008674 A1 WO2014008674 A1 WO 2014008674A1
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Prior art keywords
line
transmission line
data
data line
main
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English (en)
French (fr)
Inventor
徐亮
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/641,130 priority Critical patent/US20140016055A1/en
Publication of WO2014008674A1 publication Critical patent/WO2014008674A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133788—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by light irradiation, e.g. linearly polarised light photo-polymerisation
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G02F1/13775—Polymer-stabilized liquid crystal layers

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an alignment circuit of an array substrate and a liquid crystal panel.
  • liquid crystal display devices such as liquid crystal display devices, plasma display devices and OLEDs (Organic Light-Emitting Diode, organic light emitting diode) display device.
  • OLEDs Organic Light-Emitting Diode, organic light emitting diode
  • liquid crystal display devices are gradually replacing cold cathode display devices due to their advantages of low weight, small size, and low power consumption.
  • PSVA Polymer Stabilize Vertical Alignment (polymer stabilized vertical alignment mode) is widely used in liquid crystal displays.
  • a reactive monomer is added to the negative liquid crystal. After the liquid crystal cell is formed, by applying a voltage across the liquid crystal cell, the reactive monomer is polymerized under the excitation of ultraviolet light, thereby completing the light alignment of the liquid crystal.
  • FIG. 1 is a schematic structural diagram of a power-on circuit of a liquid crystal panel of a PSVA display mode in the prior art.
  • the liquid crystal panel has a data line 10 including a signal input module 20 and a transmission line 30.
  • the first end 10a of the data line 10 is connected to the transmission line 30.
  • the data line 10 is broken due to various factors. As shown in the figure, if the D point in the data line 10 is broken, when an electrical signal is input from the signal input module 20 to the data line 10 via the transmission line 30, the electrical signal reaches the D point through the first end 10a, due to the point D. There is an open circuit, and the electrical signal cannot be transmitted through the D point. Therefore, the data line 10 has no electrical signal except for the first end 10a to the point D, so that the corresponding liquid crystal molecules cannot be properly aligned, thereby causing display defects of the liquid crystal panel. The yield of the liquid crystal panel is lowered.
  • the main object of the present invention is to provide an array substrate, which aims to improve the alignment of liquid crystal molecules, improve display defects, and reduce the rejection rate of liquid crystal panels.
  • an array substrate includes a substrate, a plurality of data lines disposed in parallel on the substrate, a signal input module for inputting an alignment electrical signal, and at least one transmission line, wherein the data line has The first end and the second end, one end of the transmission line is connected to the signal input module, and is respectively connected to the first end and the second end of the data line.
  • the signal input module is disposed on a side of the substrate near the first end of the data line, and one end of the transmission line is connected to the signal input module, and is close to the data line from the substrate.
  • One side of the first end extends to a side of the substrate adjacent the second end of the data line.
  • the transmission line includes a first transmission line and a second transmission line
  • the plurality of data lines disposed on the substrate in parallel are composed of a plurality of data units
  • the data unit includes a first data line and a second data line
  • the first end and the second end of the first data line are both connected to the first transmission line
  • the first end and the second end of the second data line are both connected to the second transmission line.
  • the transmission line includes a first transmission line, a second transmission line, and a third transmission line
  • the plurality of data lines disposed on the substrate in parallel are composed of a plurality of data units
  • the data unit includes a first data line, a first data line and a third data line, wherein the first end and the second end of the first data line are both connected to the first transmission line, and the first end and the second end of the second data line are both
  • the second transmission line is connected, and the first end and the second end of the third data line are both connected to the third transmission line.
  • the signal input module comprises a main input unit and a synchronizing input unit of an alignment electric signal input synchronously with the main input unit, the transmission line comprising a main transmission line and a synchronous transmission line; the main input unit and the main transmission line a side of the main transmission line connected to the main input unit and connected to the first end of the data line; and the synchronization input unit and The synchronous transmission line is disposed on a side of the substrate adjacent to the second end of the data line, and one end of the synchronous transmission line is connected to the synchronization input unit and connected to the second end of the data line.
  • the main transmission line includes a first main transmission line and a second main transmission line
  • the synchronous transmission line includes a first synchronous transmission line and a second synchronous transmission line
  • the plurality of data lines arranged in parallel on the substrate are composed of data a unit comprising: a first data line and a second data line; a first end of the first data line is connected to the first main transmission line, and a second end is connected to the first synchronous transmission line; The first end of the second data line is connected to the second main transmission line, and the second end is connected to the second synchronous transmission line.
  • the main transmission line includes a first main transmission line, a second main transmission line, and a third main transmission line
  • the plurality of data lines disposed in parallel on the substrate are composed of a plurality of data units
  • the data unit includes the first a data line, a second data line, and a third data line
  • the first end of the first data line is connected to the first main transmission line
  • the second end of the first data line is connected to the first synchronous transmission line
  • a first end of the second data line is connected to the second main transmission line
  • a second end of the second data line is connected to the second synchronous transmission line to connect the first end of the third data line
  • the third main transmission line is connected, and the second end of the third data line is connected to the third synchronous transmission line.
  • the array substrate further includes a plurality of gate lines disposed in parallel on the substrate, a driving module for inputting a driving signal, a first conveying line and a second conveying line, the gate line having a first And a second end; the first transfer line is respectively connected to the first end of the gate line and the driving module, and the second transfer line is connected to the second end of the gate line.
  • the array substrate further includes a synchronous driving module of a driving signal input in synchronization with the driving module, and the synchronous driving module is connected to the second conveying line.
  • the alignment electrical signal is input to the data line from the first end and the second end of the data line through the transmission line.
  • the present invention also provides a liquid crystal panel comprising an array substrate, a color filter substrate, and liquid crystal molecules disposed between the array substrate and the color filter substrate, the array substrate including the substrate, and a plurality of parallel disposed in the liquid crystal panel a data line on the substrate, a signal input module for inputting an alignment electrical signal, and at least one transmission line, the data line having a first end and a second end, one end of the transmission line being connected to the signal input module, and Connected to the first end and the second end of the data line, respectively.
  • the signal input module is disposed on a side of the substrate near the first end of the data line, and one end of the transmission line is connected to the signal input module, and is close to the data line from the substrate.
  • One side of the first end extends to a side of the substrate adjacent the second end of the data line.
  • the transmission line includes a first transmission line and a second transmission line
  • the plurality of data lines disposed on the substrate in parallel are composed of a plurality of data units
  • the data unit includes a first data line and a second data line
  • the first end and the second end of the first data line are both connected to the first transmission line
  • the first end and the second end of the second data line are both connected to the second transmission line.
  • the transmission line includes a first transmission line, a second transmission line, and a third transmission line
  • the plurality of data lines disposed on the substrate in parallel are composed of a plurality of data units
  • the data unit includes a first data line, a first data line and a third data line, wherein the first end and the second end of the first data line are both connected to the first transmission line, and the first end and the second end of the second data line are both
  • the second transmission line is connected, and the first end and the second end of the third data line are both connected to the third transmission line.
  • the signal input module comprises a main input unit and a synchronizing input unit of an alignment electric signal input synchronously with the main input unit, the transmission line comprising a main transmission line and a synchronous transmission line; the main input unit and the main transmission line a side of the main transmission line connected to the main input unit and connected to the first end of the data line; and the synchronization input unit and The synchronous transmission line is disposed on a side of the substrate adjacent to the second end of the data line, and one end of the synchronous transmission line is connected to the synchronization input unit and connected to the second end of the data line.
  • the main transmission line includes a first main transmission line and a second main transmission line
  • the synchronous transmission line includes a first synchronous transmission line and a second synchronous transmission line
  • the plurality of data lines arranged in parallel on the substrate are composed of data a unit comprising: a first data line and a second data line; a first end of the first data line is connected to the first main transmission line, and a second end is connected to the first synchronous transmission line; The first end of the second data line is connected to the second main transmission line, and the second end is connected to the second synchronous transmission line.
  • the main transmission line includes a first main transmission line, a second main transmission line, and a third main transmission line
  • the plurality of data lines disposed in parallel on the substrate are composed of a plurality of data units
  • the data unit includes the first a data line, a second data line, and a third data line
  • the first end of the first data line is connected to the first main transmission line
  • the second end of the first data line is connected to the first synchronous transmission line
  • a first end of the second data line is connected to the second main transmission line
  • a second end of the second data line is connected to the second synchronous transmission line to connect the first end of the third data line
  • the third main transmission line is connected, and the second end of the third data line is connected to the third synchronous transmission line.
  • the array substrate further includes a plurality of gate lines disposed in parallel on the substrate, a driving module for inputting a driving signal, a first conveying line and a second conveying line, the gate line having a first And a second end; the first transfer line is respectively connected to the first end of the gate line and the driving module, and the second transfer line is connected to the second end of the gate line.
  • the array substrate further includes a synchronous driving module of a driving signal input in synchronization with the driving module, and the synchronous driving module is connected to the second conveying line.
  • the alignment electrical signal is input to the data line from the first end and the second end of the data line through the transmission line.
  • the invention connects the signal input module to the two ends of the data line through the transmission line, and the alignment electrical signal inputs the data line from the first end and the second end of the data line through the transmission line, so when there is power failure in the data line, the data
  • the parts on both sides of the line break point can normally input the matching electric signal, thereby improving the alignment of the liquid crystal molecules and reducing the scrap rate of the liquid crystal panel.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic structural view of a first embodiment of an array substrate according to the present invention.
  • FIG. 3 is a schematic structural view of a second embodiment of an array substrate according to the present invention.
  • FIG. 4 is a schematic structural view of a third embodiment of an array substrate according to the present invention.
  • FIG. 5 is a schematic structural view of a fourth embodiment of an array substrate according to the present invention.
  • FIG. 6 is a schematic structural view of a fifth embodiment of an array substrate according to the present invention.
  • FIG. 7 is a schematic structural view of a sixth embodiment of an array substrate according to the present invention.
  • FIG. 8 is a schematic structural view of a seventh embodiment of an array substrate according to the present invention.
  • FIG. 2 is a schematic structural view of a first embodiment of an array substrate according to the present invention.
  • the array substrate provided in this embodiment includes a substrate 40, a plurality of data lines 10 disposed in parallel on the substrate 40, a signal input module 20 for inputting an alignment electrical signal, and at least one transmission line 30; the data line has a first end 10a And the second end 10b, one end of the transmission line 30 is connected to the signal input module 20, and is respectively connected to the first end 10a and the second end 10b of the data line 10.
  • the data line 10 is input from the first end 10a and the second end 10b of the data line 10.
  • the signal input module 20 transmits the same alignment electrical signal to the first end 10a and the second end 10b of the same data line 10 through the output line 30, and when the A point of the data line 10 is broken, the liquid crystal is performed.
  • the alignment electrical signal is input from the signal input module 20 to the data line 10 via the transmission line 30. Since there is an open circuit at point A, the alignment electrical signal reaches the point A through the first end 10a, so that the first end 10a to A of the data line 10 There is an alignment electrical signal at the point; at the same time, the second end 10b reaches point A, so that there is an alignment electrical signal at the second end 10b to point A of the data line 10. Therefore, there is an alignment electrical signal outside the break point A of the data line 10, and the corresponding liquid crystal molecules can complete the alignment.
  • the invention is respectively connected to the two ends of the data line 10 through the transmission line 30, so that the alignment electric signal is transmitted from the two ends of the data line 10 to the break point A, respectively, so that the data line 10 has an alignment electric signal except the break point A, thereby
  • the alignment of the liquid crystal molecules is improved, and the display defects are improved, so that the present invention reduces the rejection rate of the liquid crystal panel.
  • the signal input module 20 is disposed on a side of the substrate 40 adjacent to the first end 10a of the data line 10, one end of the transmission line 30 is connected to the signal input module 20, and the substrate 40 is adjacent to the first end 10a of the data line 10.
  • One side extends to the side of the substrate 40 adjacent the second end 10b of the data line 10 and is coupled to the second end 10b of the data line 10.
  • the first end 10a and the second end 10b of the data line 10 are simultaneously connected through the transmission line 30, and the alignment electrical signals are respectively input to the first end 10a and the second end 10b of the data line 10.
  • the alignment electrical signal between the first end 10a of the data line 10 and the break point of the open circuit can be transmitted through the first end 10a of the data line 10;
  • the alignment electrical signal between the two ends 10b to the breakpoint of the open circuit can be transmitted through the second end 10b of the data line 10. Therefore, the normal alignment of the liquid crystal molecules corresponding to the entire data line 10 can be completed, and the rejection rate of the liquid crystal panel is reduced.
  • FIG. 3 is a schematic structural view of a second embodiment of an array substrate according to the present invention.
  • the array substrate provided in this embodiment is different from the array substrate in the first embodiment in that the signal input module in the alignment line includes a main input unit 201 and a synchronization input unit 202, and the transmission line includes a main transmission line 301 and a synchronous transmission line 302.
  • the main input unit 201 and the main transmission line 301 are disposed on a side of the substrate 40 adjacent to the first end 10a of the data line 10.
  • One end of the main transmission line 301 is connected to the main input unit 201, and is connected to the first end 10a of the data line 10.
  • the sync input unit 202 and the sync transfer line 302 are disposed on a side of the substrate 40 adjacent to the second end 10b of the data line 10, and one end of the sync transfer line 302 is connected to the sync input unit 202 and to the second end 10b of the data line 10.
  • the aligning electric signal autonomous input unit 201 transmits to the break point of the open circuit via the main transmission line 301 and the first end 10a of the data line 10; and the aligning electric signal self-synchronizing input unit 202 is transmitted to the breakpoint of the open circuit via the synchronous transmission line 302 and the second end 10b of the data line 10. Therefore, the normal alignment of the liquid crystal molecules corresponding to the entire data line 10 can be completed, and the rejection rate of the liquid crystal panel is reduced.
  • FIG. 4 is a schematic structural view of a third embodiment of an array substrate according to the present invention.
  • the transmission lines 30 are two.
  • the transmission line 30 includes a first transmission line 30a and a second transmission line 30b.
  • the plurality of data lines disposed in parallel on the substrate are composed of a data unit 100 including a first data line 101 and a second data line 102.
  • the first end 101a and the second end 101b of the first data line 101 are both connected to the first transmission line 30a; the first end 102a and the second end 102b of the second data line 102 are both connected to the second transmission line 30b.
  • the principle of the alignment electrical signal transmission of the array substrate provided in this embodiment can be referred to the foregoing, and details are not described herein again. Since the alignment electric signals are respectively transmitted from the first data line 101 and the second data line 102 to the middle through the first transmission line 30a or the second transmission line 30b, the alignment of the liquid crystal molecules is improved, and display defects are improved.
  • FIG. 5 is a schematic structural view of a fourth embodiment of an array substrate according to the present invention.
  • the main transmission line 301 includes a first main transmission line 301a and a second main transmission line 301b
  • the synchronization transmission line 302 includes an alignment electric signal that is synchronously transmitted with the first main transmission line 301a.
  • the first synchronous transmission line 302a and the second synchronous transmission line 302b that is synchronously transmitted with the second primary transmission line 301b.
  • the plurality of data lines disposed in parallel on the substrate are composed of a plurality of data units 100, and the data unit 100 includes a first data line 101 and a second data line 102.
  • the first end 101a of the first data line 101 is connected to the first main transmission line 301a
  • the second end 101b is connected to the first synchronous transmission line 302a
  • the first end 102a of the second data line 102 is connected to the second main transmission line 301b.
  • the two ends 102b are connected to the second synchronous transmission line 302b.
  • FIG. 6 is a schematic structural view of a fifth embodiment of an array substrate according to the present invention.
  • the transmission lines 30 are three.
  • the transmission line 30 includes a first transmission line 30a, a second transmission line 30b, and a third transmission line 30c.
  • the plurality of data lines disposed in parallel on the substrate are composed of a data unit 100 including a first data line 101, a second data line 102, and a third data line 103.
  • the first end 101a and the second end 101b of the first data line 101 are both connected to the first transmission line 30a; the first end 102a and the second end 102b of the second data line 102 are both connected to the second transmission line 30b; The first end 103a and the second end 103b of the line 103 are both connected to the third transmission line 30c.
  • the principle of the alignment electrical signal transmission of the array substrate provided in this embodiment can be referred to the foregoing, and details are not described herein again. Since the alignment electric signal is respectively transmitted from the first data line 101, the second data line 102, and the third data line 103 to the middle through the first transmission line 30a or the second transmission line 30b or the third transmission line 30c, the liquid crystal molecules are improved. Consistency of alignment improves display defects.
  • FIG. 7 is a schematic structural view of a sixth embodiment of an array substrate according to the present invention.
  • the main transmission line 301 includes a first main transmission line 301a, a second main transmission line 301b, and a third main transmission line 301c.
  • the synchronization transmission line 302 includes synchronization with the first main transmission line 301a.
  • the plurality of data lines disposed in parallel on the substrate are composed of a data unit 100 including a first data line 101, a second data line 102, and a third data line 103.
  • the first end 101a of the first data line 101 is connected to the first main transmission line 301a
  • the second end 101b is connected to the first synchronous transmission line 302a
  • the first end 102a of the second data line 102 is connected to the second main transmission line 301b.
  • the second end 102b is connected to the second synchronous transmission line 302b
  • the first end 103a of the third data line 103 is connected to the third main transmission line 301c
  • the second end 103b is connected to the third synchronous transmission line 302c.
  • FIG. 8 is a schematic structural view of a seventh embodiment of an array substrate according to the present invention.
  • the array substrate provided by the embodiment further includes a plurality of gate lines 50 disposed on the substrate 40 in parallel, a driving module 60 for inputting driving signals, a first conveying line 70 and a second conveying line 80,
  • the first transfer line 70 is connected to the first end of the gate line 50 and the driving module 60
  • the second transfer line is connected to the second end of the gate line 50.
  • first gate line 501, the second gate line 502, and the third gate line 503 in the gate line 50 are taken as an example.
  • the first ends of the first gate line 501, the second gate line 502, and the third gate line 503 are both connected to the first transfer line 70, and the second end is connected to the second transfer line 80;
  • a conveyor line 70 is coupled to the drive module 60 described above.
  • the driving signal is transmitted from the driving module 60 to the break point of the disconnection of the first gate line 501 via the first transfer line 70, the first end of the first gate line 501 a breakpoint transmitted to the first gate line 501 via the first transfer line 70, the second gate line 502 or the third gate line 503, the second transfer line 80, and the second end of the first gate line 501 At the office. Therefore, the alignment line provided by the embodiment of the present invention can better ensure a normal driving signal on the gate line 50, and reduce the rejection rate of the liquid crystal panel.
  • the array substrate further includes a synchronous driving module 90 that is driven in synchronization with the driving module 60, and the synchronous driving module 90 is connected to the second conveying line 80.
  • the synchronous driving module 90 When the synchronous driving module 90 is connected to the second transfer line, when the first gate line 501, the second gate line 502, and the third gate line 503 each have a break point, the first gate line 501, the second Drive signals on the lines from the first end of the gate line 502 and the third gate line 503 to the breakpoint are provided by the drive module 60, and the drive signal on the line from the first end to the breakpoint is provided by the synchronous drive module 90. .
  • the driving signal is transmitted from the driving module 60 to the first conveying line 70, and transmitted to the break point through the first end of the gate line 50; meanwhile, the driving signal is from The synchronous drive module 90 is transmitted to the second transfer line 80 and transmitted to the breakpoint via the second end of the gate line 50.
  • the first end of the gate line 50 is connected to the driving module 60 by using the first conveying line 70, and the second end is driven by the second conveying line 80 and the driving signal of the driving signal synchronized with the driving module 60. Connected, the drive signals are simultaneously loaded to both ends of the gate line 50. Therefore, the normal alignment of the liquid crystal can be better ensured, and the scrap rate of the liquid crystal panel can be reduced.
  • the present invention also provides a liquid crystal panel comprising an array substrate, a color filter substrate, and liquid crystal molecules disposed between the array substrate and the color filter substrate.
  • the array substrate is any one of the first to seventh embodiments described above, and details are not described herein again.

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Description

阵列基板及液晶面板
技术领域
本发明涉及液晶显示领域，特别涉及一种阵列基板的配向线路及液晶面板。
背景技术
随着电子技术的发展，平板显示器件得到了飞速的发展，如液晶显示器件、等离子体显示器件和OLED（Organic Light-Emitting Diode，有机发光二极管）显示器件。在平板显示器件当中，液晶显示器件由于其重量低、体积小、能耗低的优点，正在逐步取代冷阴极显示设备。而PSVA（Polymer Stabilize Vertical Alignment，高分子稳定垂直配向模式）广泛应用于液晶显示器中。
PSVA显示模式是在负性液晶中添加了反应单体，在液晶盒形成后，通过在液晶盒两端施加电压，在紫外光的激化下，反应单体发生聚合，从而完成液晶的光配向。
如图1所示，图1为现有技术中PSVA显示模式的液晶面板的加电电路的结构示意图。所述液晶面板具有数据线10，所述加电电路包括信号输入模块20和传输线30。其中该数据线10的第一端10a与该传输线30连接。然而，在形成数据线10的过程中，受各种因素的影响，常常会出现数据线10存在断线的情况。如图所示，若该数据线10中的D点发生断路，当电信号自该信号输入模块20经由传输线30输入到数据线10时，电信号经过第一端10a达到D点，由于D点存在断路，电信号无法通过D点传送，故数据线10除第一端10a至D点外的部分都没有电信号，故其相对应的液晶分子无法正常配向，从而造成液晶面板的显示缺陷，而降低了液晶面板的良率。
发明内容
本发明的主要目的在于提供一种阵列基板，旨在提高液晶分子配向的一致性，改善显示缺陷，降低液晶面板的报废率。
为了实现发明目的，本发明提供一种阵列基板，包括基板、若干条平行设置在所述基板上的数据线、用于输入一配向电信号的信号输入模块及至少一条传输线，所述数据线具有第一端及第二端，所述传输线的一端与所述信号输入模块连接，并分别与所述数据线的第一端和第二端连接。
优选地，所述信号输入模块设置在所述基板靠近所述数据线的第一端的一侧，所述传输线的一端与所述信号输入模块连接，并从所述基板靠近所述数据线的第一端的一侧延伸至所述基板靠近所述数据线的第二端的一侧。
优选地，所述传输线包括第一传输线和第二传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线和第二数据线，所述第一数据线的第一端和第二端均与所述第一传输线连接，所述第二数据线的第一端和第二端均与所述第二传输线连接。
优选地，所述传输线包括第一传输线、第二传输线和第三传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线、第二数据线和第三数据线，所述第一数据线的第一端和第二端均与所述第一传输线连接，所述第二数据线的第一端和第二端均与所述第二传输线连接，所述第三数据线的第一端和第二端均与所述第三传输线连接。
优选地，所述信号输入模块包括主输入单元和与所述主输入单元同步输入的配向电信号的同步输入单元，所述传输线包括主传输线和同步传输线；所述主输入单元和所述主传输线设置在所述基板靠近所述数据线的第一端的一侧，所述主传输线的一端与所述主输入单元连接，并与所述数据线的第一端连接；所述同步输入单元和所述同步传输线设置在所述基板靠近所述数据线的第二端的一侧，所述同步传输线的一端与所述同步输入单元连接，并与所述数据线的第二端连接。
优选地，所述主传输线包括第一主传输线和第二主传输线，所述同步传输线包括第一同步传输线及第二同步传输线；所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线和第二数据线；所述第一数据线的第一端与所述第一主传输线连接，第二端与所述第一同步传输线连接；所述第二数据线的第一端与所述第二主传输线连接，第二端与所述第二同步传输线连接。
优选地，所述主传输线包括第一主传输线、第二主传输线和第三主传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线、第二数据线和第三数据线，所述第一数据线的第一端与所述第一主传输线连接，所述第一数据线的第二端与所述第一同步传输线连接；所述第二数据线的第一端与所述第二主传输线连接，所述第二数据线的第二端与所述第二同步传输线连接所述第三数据线的第一端与所述第三主传输线连接，所述第三数据线的第二端与所述第三同步传输线连接。
优选地，所述阵列基板还包括若干条平行设置在所述基板上的栅极线、用于输入驱动信号的驱动模块、第一输送线和第二输送线，所述栅极线具有第一端及第二端；所述第一输送线分别与所述栅极线的第一端和所述驱动模块连接，所述第二输送线与所述栅极线的第二端连接。
优选地，所述阵列基板还包括与所述驱动模块同步输入的驱动信号的同步驱动模块，所述同步驱动模块与所述第二输送线连接。
优选地，所述配向电信号经过所述传输线自数据线的第一端及第二端输入所述数据线。
本发明还提供一种液晶面板，该液晶面板包括阵列基板、彩色滤光片基板及设置在阵列基板与彩色滤光片基板之间的液晶分子，该阵列基板包括基板、若干条平行设置在所述基板上的数据线、用于输入一配向电信号的信号输入模块及至少一条传输线，所述数据线具有第一端及第二端，所述传输线的一端与所述信号输入模块连接，并分别与所述数据线的第一端和第二端连接。
优选地，所述信号输入模块设置在所述基板靠近所述数据线的第一端的一侧，所述传输线的一端与所述信号输入模块连接，并从所述基板靠近所述数据线的第一端的一侧延伸至所述基板靠近所述数据线的第二端的一侧。
优选地，所述传输线包括第一传输线和第二传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线和第二数据线，所述第一数据线的第一端和第二端均与所述第一传输线连接，所述第二数据线的第一端和第二端均与所述第二传输线连接。
优选地，所述传输线包括第一传输线、第二传输线和第三传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线、第二数据线和第三数据线，所述第一数据线的第一端和第二端均与所述第一传输线连接，所述第二数据线的第一端和第二端均与所述第二传输线连接，所述第三数据线的第一端和第二端均与所述第三传输线连接。
优选地，所述信号输入模块包括主输入单元和与所述主输入单元同步输入的配向电信号的同步输入单元，所述传输线包括主传输线和同步传输线；所述主输入单元和所述主传输线设置在所述基板靠近所述数据线的第一端的一侧，所述主传输线的一端与所述主输入单元连接，并与所述数据线的第一端连接；所述同步输入单元和所述同步传输线设置在所述基板靠近所述数据线的第二端的一侧，所述同步传输线的一端与所述同步输入单元连接，并与所述数据线的第二端连接。
优选地，所述主传输线包括第一主传输线和第二主传输线，所述同步传输线包括第一同步传输线及第二同步传输线；所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线和第二数据线；所述第一数据线的第一端与所述第一主传输线连接，第二端与所述第一同步传输线连接；所述第二数据线的第一端与所述第二主传输线连接，第二端与所述第二同步传输线连接。
优选地，所述主传输线包括第一主传输线、第二主传输线和第三主传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线、第二数据线和第三数据线，所述第一数据线的第一端与所述第一主传输线连接，所述第一数据线的第二端与所述第一同步传输线连接；所述第二数据线的第一端与所述第二主传输线连接，所述第二数据线的第二端与所述第二同步传输线连接所述第三数据线的第一端与所述第三主传输线连接，所述第三数据线的第二端与所述第三同步传输线连接。
优选地，所述阵列基板还包括若干条平行设置在所述基板上的栅极线、用于输入驱动信号的驱动模块、第一输送线和第二输送线，所述栅极线具有第一端及第二端；所述第一输送线分别与所述栅极线的第一端和所述驱动模块连接，所述第二输送线与所述栅极线的第二端连接。
优选地，所述阵列基板还包括与所述驱动模块同步输入的驱动信号的同步驱动模块，所述同步驱动模块与所述第二输送线连接。
优选地，所述配向电信号经过所述传输线自数据线的第一端及第二端输入所述数据线。
本发明通过传输线将信号输入模块分别与数据线的两端连接，配向电信号经过所述传输线自数据线的第一端及第二端输入数据线，因此当数据线中存在断电时，数据线断点两侧的部分均可以正常输入配向电信号，从而提高了液晶分子配向的一致性，降低了液晶面板的报废率。
附图说明
图1为现有技术中阵列基板结构示意图；
图2为本发明阵列基板第一实施例的结构示意图；
图3为本发明阵列基板第二实施例的结构示意图；
图4为本发明阵列基板第三实施例的结构示意图；
图5为本发明阵列基板第四实施例的结构示意图；
图6为本发明阵列基板第五实施例的结构示意图；
图7为本发明阵列基板第六实施例的结构示意图；
图8为本发明阵列基板第七实施例的结构示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
参照图2，图2为本发明阵列基板的第一实施例的结构示意图。本实施例提供的阵列基板包括基板40、若干条平行设置在基板40上的数据线10、用于输入一配向电信号的信号输入模块20及至少一条传输线30；该数据线具有第一端10a及第二端10b，该传输线30的一端与信号输入模块20连接，并分别与数据线10的第一端10a和第二端10b连接。配向电信号经过信号输入模块20及传输线30后，自数据线10的第一端10a和第二端10b输入数据线10。
本实施例中，信号输入模块20通过输出线30将同一配向电信号输送至同一数据线10的第一端10a和第二端10b，当该数据线10的A点存在断路时，在进行液晶配向过程中，配向电信号从信号输入模块20经由传输线30输入到数据线10，由于A点存在断路，配向电信号经过第一端10a到达A点，使得数据线10的第一端10a至A点存在配向电信号；同时经过第二端10b到达A点，使得数据线10的第二端10b至A点存在配向电信号。因此，数据线10处断点A外均存在配向电信号，其对应的液晶分子可完成配向。
本发明通过传输线30分别与数据线10的两端连接，从而将配向电信号从数据线10两端分别向断点A处传输，使数据线10除断点A外均存在配向电信号，从而提高了液晶分子配向的一致性，进而改善了显示缺陷，因此本发明降低了液晶面板的报废率。
具体地，上述信号输入模块20设置在基板40靠近数据线10的第一端10a的一侧，传输线30的一端与信号输入模块20连接，并且从基板40靠近数据线10的第一端10a的一侧延伸至基板40靠近数据线10的第二端10b的一侧，且与数据线10的第二端10b连接。
本实施例中，通过传输线30同时连接数据线10的第一端10a和第二端10b，将配向电信号分别输入至数据线10的第一端10a和第二端10b。当该数据线10的某点存在断路时，数据线10的第一端10a至该断路的断点之间的配向电信号可通过数据线10的第一端10a进行传输；数据线10的第二端10b至该断路的断点之间的配向电信号可通过数据线10的第二端10b进行传输。因此，可完成整条数据线10对应的液晶分子的正常配向，降低了液晶面板的报废率。
参照图3，图3为本发明阵列基板第二实施例的结构示意图。
本实施例提供的阵列基板与第一实施例中的阵列基板的不同在于，配向线路中的信号输入模块包括主输入单元201、同步输入单元202，所述传输线包括主传输线301和同步传输线302。其中主输入单元201和主传输线301设置在基板40靠近数据线10的第一端10a的一侧，主传输线301的一端与主输入单元201连接，并与数据线10的第一端10a连接。同步输入单元202和同步传输线302设置在基板40靠近数据线10的第二端10b的一侧，同步传输线302的一端与同步输入单元202连接，并与数据线10的第二端10b连接。
当该数据线10的某点存在断路时，配向电信号自主输入单元201经由主传输线301和数据线10的第一端10a传输至该断路的断点处；同时该配向电信号自同步输入单元202经由同步传输线302和数据线10的第二端10b传输至该断路的断点处。因此，可完成整条数据线10对应的液晶分子的正常配向，降低了液晶面板的报废率。
参照图4，图4为本发明阵列基板的第三实施例的结构示意图。基于上述实施例，本实施例中，上述传输线30为两条。具体地，传输线30包括第一传输线30a和第二传输线30b。上述若干条平行设置在基板上的数据线由数据单元100组成，该数据单元100包括第一数据线101和第二数据线102。该第一数据线101的第一端101a和第二端101b均与第一传输线30a连接；第二数据线102的第一端102a和第二端102b均与第二传输线30b连接。本实施例提供的阵列基板的配向电信号传输原理可参照前述，在此不再赘述。由于通过第一传输线30a或第二传输线30b将配向电信号从第一数据线101和第二数据线102两端分别向中间传输，从而提高了液晶分子配向的一致性，进而改善了显示缺陷。
参照图5，图5为本发明阵列基板的第四实施例的结构示意图。基于上述实施例，本实施例中，上述传输线为两条时，则主传输线301包括第一主传输线301a和第二主传输线301b，同步传输线302包括与第一主传输线301a同步传输的配向电信号的第一同步传输线302a以及与第二主传输线301b同步传输的第二同步传输线302b。上述若干条平行设置在基板上的数据线由若干数据单元100组成，该数据单元100包括第一数据线101、第二数据线102。该第一数据线101的第一端101a与第一主传输线301a连接，第二端101b与第一同步传输线302a连接；第二数据线102的第一端102a与第二主传输线301b连接，第二端102b与第二同步传输线302b连接。本实施例提供的阵列基板的配向电信号传输原理可参照前述，在此不再赘述。
参照图6，图6为本发明阵列基板的第五实施例的结构示意图。基于上述实施例，本实施例中，上述传输线30为三条。具体地，传输线30包括第一传输线30a、第二传输线30b和第三传输线30c。上述若干条平行设置在基板上的数据线由数据单元100组成，该数据单元100包括第一数据线101、第二数据线102和第三数据线103。该第一数据线101的第一端101a和第二端101b均与第一传输线30a连接；第二数据线102的第一端102a和第二端102b均与第二传输线30b连接；第三数据线103的第一端103a和第二端103b均与第三传输线30c连接。本实施例提供的阵列基板的配向电信号传输原理可参照前述，在此不再赘述。由于通过第一传输线30a或第二传输线30b或第三传输线30c将配向电信号从第一数据线101、第二数据线102和第三数据线103两端分别向中间传输，从而提高了液晶分子配向的一致性，进而改善了显示缺陷。
参照图7，图7为本发明阵列基板的第六实施例的结构示意图。基于上述实施例，本实施例中，上述传输线为三条时，则主传输线301包括第一主传输线301a、第二主传输线301b和第三主传输线301c，同步传输线302包括与第一主传输线301a同步传输的配向电信号的第一同步传输线302a、与第二主传输线301b同步传输的第二同步传输线302b以及与第三主传输线301c同步传输的第三同步传输线302c。上述若干条平行设置在基板上的数据线由数据单元100组成，该数据单元100包括第一数据线101、第二数据线102和第三数据线103。该第一数据线101的第一端101a与第一主传输线301a连接，第二端101b与第一同步传输线302a连接；第二数据线102的第一端102a与第二主传输线301b连接，第二端102b与第二同步传输线302b连接；第三数据线103的第一端103a与第三主传输线301c连接，第二端103b与第三同步传输线302c连接。本实施例提供的阵列基板的配向电信号传输原理可参照前述，在此不再赘述。
参照图8，图8为本发明阵列基板第七实施例的结构示意图。基于上述实施例，本实施例提供的阵列基板还包括若干条平行设置在基板40上的栅极线50、用于输入驱动信号的驱动模块60、第一输送线70和第二输送线80，该第一输送线70分别与栅极线50的第一端和驱动模块60连接，第二输送线与栅极线50的第二端连接。
具体的，以上述栅极线50中的第一栅极线501、第二栅极线502和第三栅极线503为例。该第一栅极线501、第二栅极线502和第三栅极线503的第一端均与上述第一输送线70连接，第二端均与上述第二输送线80连接；该第一输送线70与上述驱动模块60连接。当第一栅极线501的中间存在断路时，驱动信号自驱动模块60经由第一输送线70、第一栅极线501的第一端传输至第一栅极线501的断路的断点处，同时经由第一输送线70、第二栅极线502或第三栅极线503、第二输送线80、第一栅极线501的第二端传输至第一栅极线501的断点处。因此，本发明实施例提供的配向线路能更好的保证栅极线50上有正常的驱动信号，降低了液晶面板的报废率。
进一步地，上述阵列基板还包括与驱动模块60同步输入的驱动信号的同步驱动模块90，该同步驱动模块90与上述第二输送线80连接。
通过在第二输送线上连接同步驱动模块90，当上述第一栅极线501、第二栅极线502和第三栅极线503均存在断点时，第一栅极线501、第二栅极线502和第三栅极线503的第一端至断点处的线路上的驱动信号由驱动模块60提供，第一端至断点处的线路上的驱动信号由同步驱动模块90提供。具体地，当栅极线50存在断点时，驱动信号从驱动模块60传输至所述第一输送线70，并经栅极线50的第一端传输至断点处；同时该驱动信号从同步驱动模块90传输至第二输送线80，并经栅极线50的第二端传输至断点处。
本实施例通过在栅极线50的第一端采用第一输送线70和驱动模块60连接，第二端采用第二输送线80和与该驱动模块60同步输入的驱动信号的同步驱动模块90连接，将驱动信号同时加载到栅极线50的两端。因此能更好的保证液晶正常的配向，降低了液晶面板的报废率。
本发明还提供一种液晶面板，该液晶面板包括阵列基板、彩色滤光片基板及设置在阵列基板与彩色滤光片基板之间的液晶分子。所述阵列基板为上述第一至第七实施例中的任一一种，在此不再赘述。
以上仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其特征在于，包括基板、若干条平行设置在所述基板上的数据线、用于输入一配向电信号的信号输入模块及至少一条传输线，所述数据线具有第一端及第二端，所述传输线的一端与所述信号输入模块连接，并分别与所述数据线的第一端和第二端连接。
  2. 如权利要求1所述的阵列基板，其特征在于，所述信号输入模块设置在所述基板靠近所述数据线的第一端的一侧，所述传输线的一端与所述信号输入模块连接，并从所述基板靠近所述数据线的第一端的一侧延伸至所述基板靠近所述数据线的第二端的一侧。
  3. 如权利要求2所述的阵列基板，其特征在于，所述传输线包括第一传输线和第二传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线和第二数据线，所述第一数据线的第一端和第二端均与所述第一传输线连接，所述第二数据线的第一端和第二端均与所述第二传输线连接。
  4. 如权利要求2所述的阵列基板，其特征在于，所述传输线包括第一传输线、第二传输线和第三传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线、第二数据线和第三数据线，所述第一数据线的第一端和第二端均与所述第一传输线连接，所述第二数据线的第一端和第二端均与所述第二传输线连接，所述第三数据线的第一端和第二端均与所述第三传输线连接。
  5. 如权利要求1所述的阵列基板，其特征在于，所述信号输入模块包括主输入单元和与所述主输入单元同步输入的配向电信号的同步输入单元，所述传输线包括主传输线和同步传输线；所述主输入单元和所述主传输线设置在所述基板靠近所述数据线的第一端的一侧，所述主传输线的一端与所述主输入单元连接，并与所述数据线的第一端连接；所述同步输入单元和所述同步传输线设置在所述基板靠近所述数据线的第二端的一侧，所述同步传输线的一端与所述同步输入单元连接，并与所述数据线的第二端连接。
  6. 如权利要求5所述的阵列基板，其特征在于，所述主传输线包括第一主传输线和第二主传输线，所述同步传输线包括第一同步传输线及第二同步传输线；所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线和第二数据线；所述第一数据线的第一端与所述第一主传输线连接，第二端与所述第一同步传输线连接；所述第二数据线的第一端与所述第二主传输线连接，第二端与所述第二同步传输线连接。
  7. 如权利要求5所述的阵列基板，其特征在于，所述主传输线包括第一主传输线、第二主传输线和第三主传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线、第二数据线和第三数据线，所述第一数据线的第一端与所述第一主传输线连接，所述第一数据线的第二端与所述第一同步传输线连接；所述第二数据线的第一端与所述第二主传输线连接，所述第二数据线的第二端与所述第二同步传输线连接所述第三数据线的第一端与所述第三主传输线连接，所述第三数据线的第二端与所述第三同步传输线连接。
  8. 如权利要求1所述的阵列基板，其特征在于，还包括若干条平行设置在所述基板上的栅极线、用于输入驱动信号的驱动模块、第一输送线和第二输送线，所述栅极线具有第一端及第二端；所述第一输送线分别与所述栅极线的第一端和所述驱动模块连接，所述第二输送线与所述栅极线的第二端连接。
  9. 如权利要求8所述的阵列基板，其特征在于，还包括与所述驱动模块同步输入的驱动信号的同步驱动模块，所述同步驱动模块与所述第二输送线连接。
  10. 如权利要求1所述的阵列基板，其特征在于，所述配向电信号经过所述传输线自数据线的第一端及第二端输入所述数据线。
  11. 一种液晶面板，其特征在于，包括阵列基板、彩色滤光片基板及设置在阵列基板与彩色滤光片基板之间的液晶分子，该阵列基板包括基板、若干条平行设置在所述基板上的数据线、用于输入一配向电信号的信号输入模块及至少一条传输线，所述数据线具有第一端及第二端，所述传输线的一端与所述信号输入模块连接，并分别与所述数据线的第一端和第二端连接。
  12. 如权利要求11所述的液晶面板，其特征在于，所述信号输入模块设置在所述基板靠近所述数据线的第一端的一侧，所述传输线的一端与所述信号输入模块连接，并从所述基板靠近所述数据线的第一端的一侧延伸至所述基板靠近所述数据线的第二端的一侧。
  13. 如权利要求12所述的液晶面板，其特征在于，所述传输线包括第一传输线和第二传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线和第二数据线，所述第一数据线的第一端和第二端均与所述第一传输线连接，所述第二数据线的第一端和第二端均与所述第二传输线连接。
  14. 如权利要求12所述的液晶面板，其特征在于，所述传输线包括第一传输线、第二传输线和第三传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线、第二数据线和第三数据线，所述第一数据线的第一端和第二端均与所述第一传输线连接，所述第二数据线的第一端和第二端均与所述第二传输线连接，所述第三数据线的第一端和第二端均与所述第三传输线连接。
  15. 如权利要求11所述的液晶面板，其特征在于，所述信号输入模块包括主输入单元和与所述主输入单元同步输入的配向电信号的同步输入单元，所述传输线包括主传输线和同步传输线；所述主输入单元和所述主传输线设置在所述基板靠近所述数据线的第一端的一侧，所述主传输线的一端与所述主输入单元连接，并与所述数据线的第一端连接；所述同步输入单元和所述同步传输线设置在所述基板靠近所述数据线的第二端的一侧，所述同步传输线的一端与所述同步输入单元连接，并与所述数据线的第二端连接。
  16. 如权利要求15所述的液晶面板，其特征在于，所述主传输线包括第一主传输线和第二主传输线，所述同步传输线包括第一同步传输线及第二同步传输线；所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线和第二数据线；所述第一数据线的第一端与所述第一主传输线连接，第二端与所述第一同步传输线连接；所述第二数据线的第一端与所述第二主传输线连接，第二端与所述第二同步传输线连接。
  17. 如权利要求15所述的液晶面板，其特征在于，所述主传输线包括第一主传输线、第二主传输线和第三主传输线，所述若干条平行设置在所述基板上的数据线由若干数据单元组成，所述数据单元包括第一数据线、第二数据线和第三数据线，所述第一数据线的第一端与所述第一主传输线连接，所述第一数据线的第二端与所述第一同步传输线连接；所述第二数据线的第一端与所述第二主传输线连接，所述第二数据线的第二端与所述第二同步传输线连接所述第三数据线的第一端与所述第三主传输线连接，所述第三数据线的第二端与所述第三同步传输线连接。
  18. 如权利要求11所述的液晶面板，其特征在于，还包括若干条平行设置在所述基板上的栅极线、用于输入驱动信号的驱动模块、第一输送线和第二输送线，所述栅极线具有第一端及第二端；所述第一输送线分别与所述栅极线的第一端和所述驱动模块连接，所述第二输送线与所述栅极线的第二端连接。
  19. 如权利要求18所述的液晶面板，其特征在于，还包括与所述驱动模块同步输入的驱动信号的同步驱动模块，所述同步驱动模块与所述第二输送线连接。
  20. 如权利要求11所述的液晶面板，其特征在于，所述配向电信号经过所述传输线自数据线的第一端及第二端输入所述数据线。
PCT/CN2012/078741 2012-07-10 2012-07-17 阵列基板及液晶面板 Ceased WO2014008674A1 (zh)

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