WO2013189283A1 - 具有电流扩展层的发光二极管及其制作方法 - Google Patents

具有电流扩展层的发光二极管及其制作方法 Download PDF

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WO2013189283A1
WO2013189283A1 PCT/CN2013/077409 CN2013077409W WO2013189283A1 WO 2013189283 A1 WO2013189283 A1 WO 2013189283A1 CN 2013077409 W CN2013077409 W CN 2013077409W WO 2013189283 A1 WO2013189283 A1 WO 2013189283A1
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layer
current spreading
nitride semiconductor
spreading layer
emitting diode
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English (en)
French (fr)
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叶孟欣
吴志强
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厦门市三安光电科技有限公司
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Publication of WO2013189283A1 publication Critical patent/WO2013189283A1/zh
Priority to US14/531,973 priority Critical patent/US9705033B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/002—Devices characterised by their operation having heterojunctions or graded gap
    • H01L33/0025—Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

Definitions

  • the invention belongs to the technical field of light emitting semiconductors, and relates to a gallium nitride based light emitting diode with a current spreading layer and a manufacturing method thereof.
  • substrate transfer techniques such as depositing GaN-based thin films by MOCVD on sapphire substrates, and then bonding GaN-based thin films to semiconductors or metals by wafer bonding or electroplating techniques.
  • the sapphire substrate is removed by laser stripping; or a GaN-based film is deposited on the SiC or Si substrate, and then the GaN-based film is bonded to the semiconductor or metal substrate by wafer bonding or electroplating, and then The SiC or Si substrate is removed by chemical etching.
  • the thin GaN chip has a higher surface.
  • the light-emitting efficiency and the transferred substrate have excellent thermal conductivity characteristics, so the GaN-based thin film chip transferred to the heat-dissipating substrate has a great advantage in high-current applications.
  • it in order to truly popularize semiconductor lighting, it still needs to continue to improve at the existing level of light efficiency.
  • a light emitting diode having a current spreading layer comprising: an n-side layer and a p-side layer respectively formed of a nitride semiconductor; having between the n-side layer and the p-side layer An active layer composed of a nitride semiconductor; wherein the n-side layer is formed by sequentially stacking an extrinsic doped buffer layer and a composite multi-current expansion layer; the composite multi-current expansion layer is composed of a first current expansion layer, The two current spreading layers and the third current spreading layer are sequentially stacked; the first current spreading layer and the third current spreading layer are formed by alternately laminating a u-type nitride semiconductor layer and an n-type nitride semiconductor layer, the second The current spreading layer is a distributed insulating layer formed on the n-type nitride semiconductor layer; the first current spreading layer is adjacent to the extrinsic doping buffer layer, and the third current spreading layer
  • a method of fabricating a light emitting diode having a current spreading layer comprising the steps of: providing a growth substrate on which an n-side layer is formed; Forming an active layer on the n side layer; forming a p side layer on the active layer to form an epitaxial structure; wherein the n The side layer is composed of a non-intrinsic doped buffer layer and a composite multi-current expansion layer; the composite multi-current expansion layer is sequentially stacked by the first current expansion layer, the second current expansion layer and the third current expansion layer;
  • the first current spreading layer and the third current spreading layer are The u-type nitride semiconductor layer and the n-type nitride semiconductor layer are alternately laminated, and the second current spreading layer is at n a distributed insulating layer formed of a type nitride semiconductor layer; the first current spreading layer is adjacent to the extrinsic doping buffer layer, and the third current spreading layer is adjacent to the
  • the light emitting diode disclosed by the invention has good N-
  • the type current spreading function can uniformly distribute the current to the entire light-emitting area in the composite multi-current expansion layer, thereby effectively improving the luminous efficiency of the nitride light-emitting diode assembly and increasing the electrostatic breakdown voltage.
  • FIG. 1 is a schematic structural view of a general gallium nitride-based vertical structure light emitting diode assembly.
  • FIG. 2 is a schematic diagram of a current path of the LED assembly shown in FIG. 1.
  • FIG. 3 is a schematic diagram showing an epitaxial structure of an LED of a gallium nitride-based vertical structure light-emitting diode according to Embodiment 1 of the present invention.
  • Figure 4 is a side cross-sectional view showing a gallium nitride-based vertical structure light-emitting diode assembly according to Embodiment 1 of the present invention.
  • Fig. 5 is a schematic view showing current expansion of a gallium nitride-based vertical structure light-emitting diode assembly according to Embodiment 1 of the present invention.
  • Figure 6 is a side cross-sectional view showing a gallium nitride-based vertical structure light-emitting diode assembly according to a second embodiment of the present invention.
  • Fig. 7 is a schematic view showing current expansion of a gallium nitride-based vertical structure light-emitting diode assembly of Embodiment 2 of the present invention.
  • Figure 8 is a graph showing the luminous output power of Embodiment 2 of the present invention.
  • Fig. 9 is a graph showing the rate of passage of an electrostatic breakdown voltage in Example 2 of the present invention.
  • 203a, 303a a first current spreading layer
  • 303c a graded silicon doped n-type nitride semiconductor layer
  • 106, 206, 306 p-type GaN layer
  • 111, 211, 311 P-side metal diffusion barrier layer and bonding layer
  • 112, 212, 312 a conductive substrate
  • the present invention proposes The LED structure will be modified according to the application field and the needs of the process process, and some of its structure and size will be modified within a certain range, and the material selection will be modified.
  • FIG. 1 it is a schematic structural diagram of a general gallium nitride-based vertical structure light emitting diode assembly, and the top and bottom thereof may include: N- a surface electrode metal layer 114, an extrinsic doped buffer layer 102, an N-type GaN layer 103, an active layer 104, an electron blocking layer 105, a P-type GaN layer 106, P-plane mirror and ohmic electrode layer 110, P-side metal diffusion barrier layer and bonding layer 111, conductive substrate 112, and lower electrode metal layer 113.
  • Figure 2 shows the LED Schematic diagram of the current path of the component, because the current flows from the N-side electrode metal layer 114 to the lower electrode metal layer 113, which will be biased toward the closer line, which will cause some parts of the current density to be too large, resulting in current crowding ( Current crowding ), thereby limiting the effective improvement of the level of light efficiency.
  • N-type current-expanding light-emitting diode and its manufacturing method are proposed below.
  • the epitaxial structure of a light-emitting diode having good N-type current spreading consists of an n-side layer, an active layer, and p Side layer composition, where n
  • the side layer is composed of a non-intrinsic doped buffer layer and a composite multi-current expansion layer in this order.
  • the composite multi-current expansion layer is formed by sequentially laminating the first current spreading layer, the second current spreading layer, and the third current spreading.
  • the first current spreading layer and the third current spreading layer are The u-type nitride semiconductor layer and the n-type nitride semiconductor layer are alternately laminated, and the second current spreading layer is at n A distributed insulating layer formed of a type nitride semiconductor layer.
  • the first current spreading layer is adjacent to the extrinsic doping buffer layer
  • the third current spreading layer is adjacent to the active layer of the light emitting diode.
  • the current-expanding LED further includes a conductive substrate on which the epitaxial structure is located, wherein the n-side layer is away from the conductive substrate, and the p-side layer is adjacent to the conductive substrate to form a vertical light-emitting structure.
  • the top surface of the side layer is generally provided with an electrode metal layer. Since the buffer layer is non-intrinsic doped, the electrode metal layer can be directly formed on the buffer layer.
  • the first current spreading layer in the composite multi-current spreading layer is designed as a u-type nitride semiconductor layer and An n-type nitride semiconductor layer is alternately laminated, the purpose of which is to introduce a current source from the N-side electrode metal layer, by a u-type layer and n
  • the interactive stacking of the layers forces the current sources everywhere to perform a two-dimensional horizontal expansion;
  • the second current spreading layer is designed to form a distributed insulating layer in the n-type nitride semiconductor layer to force a uniform current distribution ( Distribution) to form a uniformly distributed point current source (see Figure 3 or Figure 5);
  • the third current spreading layer is designed as a u-type nitride semiconductor layer and n
  • the nitride semiconductor layer is alternately laminated, and the purpose is to uniformly distribute the point current source formed by the second current spreading layer by the u type layer and n
  • the interactive stacking of the layers forces the point current sources everywhere to be two-dimensionally horizontal
  • the composite multi-current expansion layer in the n-side layer may have a film thickness of 1000 angstroms to 100,000 Ai.
  • the first current spreading layer and the third current spreading layer may each have a film thickness of 350 ⁇ to 45,000 ⁇ , wherein a film thickness ratio of the u-type nitride semiconductor layer to the n-type nitride semiconductor layer is greater than 0.8
  • the number of lamination cycles is 1 to 100; the thickness of the second current spreading layer may be 100 angstroms to 5000 The angstrom, wherein the distributed insulating layer may be composed of insulating portions spaced at predetermined intervals, the process of which may be formed by ion implantation.
  • the first current spreading layer may have a film thickness of 10,000 angstroms to 40,000
  • the film thickness ratio of the u-type nitride semiconductor layer and the n-type nitride semiconductor layer is 1.5:1, and the number of lamination cycles is 40.
  • the third current spreading layer has a film thickness of 4000 angstroms to 18,000 angstroms.
  • the film thickness ratio of the u-type nitride semiconductor layer and the n-type nitride semiconductor layer is 1:1, and the number of lamination cycles is 18.
  • the silicon doping concentration of the u-type nitride semiconductor layer is less than 5 ⁇ 10 17 Cm -3
  • the n-type nitride semiconductor layer has a silicon doping concentration greater than 1 ⁇ 10 18 Cm -3 .
  • a gradual silicon doping may be included between the second current spreading layer and the third current spreading layer.
  • Type nitride semiconductor layer the gradient silicon-doped n-type nitride semiconductor layer may have a film thickness of 200 angstroms to 5000 angstroms, formed by secondary growth epitaxy, wherein the silicon doping concentration is 1 ⁇ 10 17 Cm -3 Gradient to 5 ⁇ 10 19 Cm -3 More preferably, the doping concentration of silicon is 5 ⁇ 10 17 Cm -3 Gradient to 1 ⁇ 10 19 Cm -3 .
  • a gradual silicon doped n-type layer is added to the second current spreading layer and the third current spreading layer for the purpose of doping with a graded silicon
  • the nitride semiconductor layer is used to repair and improve the surface defect caused by the formation of the distributed insulating layer in the second current spreading layer, thereby maintaining the lattice quality of the nitride semiconductor layer after the secondary epitaxy, and can be used as the current guiding layer of the third current spreading layer.
  • FIG. 3 is a LED of a gallium nitride-based vertical structure light emitting diode according to Embodiment 1 of the present invention; Schematic diagram of an epitaxial structure containing a composite multi-current extension layer.
  • the nitride vertical structure light-emitting diode of the present embodiment has a structure in which the following layers are sequentially laminated on the sapphire substrate 201:
  • An extrinsic doped buffer layer composed of gallium nitride (GaN), aluminum nitride (AlN) or aluminum gallium nitride (GaAlN) 202, the film thickness of 200 angstroms to 500 angstroms.
  • the composite multi-current expansion layer 203 having a thickness of 15,000 angstroms to 100,000 angstroms is laminated in this order.
  • the first current spreading layer 203a has a film thickness of 10,000 angstroms to 40,000
  • the film thickness ratio of the u-type nitride semiconductor layer and the n-type nitride semiconductor layer is 1.5:1, and the number of lamination cycles is 40.
  • the second current spreading layer 203b is formed by ion implantation at n
  • the distributed insulating layer formed of the type nitride semiconductor layer is composed of insulating portions spaced apart at predetermined intervals, and has a film thickness of 100 ⁇ to 5000 ⁇ .
  • the third current spreading layer 203d has a film thickness of 4000 angstroms ⁇ At 18000 angstroms, the film thickness ratio of the u-type nitride semiconductor layer and the n-type nitride semiconductor layer is 1:1, and the number of lamination cycles is 18.
  • the u-type nitride semiconductor layer has a silicon doping concentration of less than 5 ⁇ 10 17 Cm -3 , n Type nitride semiconductor layer silicon doping concentration is greater than 1 ⁇ 10 18 Cm -3 .
  • An active layer of a multiple quantum well structure in which an InGaN layer is used as a well layer and a GaN layer is used as a barrier layer.
  • the film thickness of the well layer is 18 ⁇ to 30 ⁇
  • the film thickness of the barrier layer is 80 ⁇ to 200 ⁇ .
  • the film thickness is from 100 angstroms to 600 angstroms.
  • P-type GaN consisting of one of gallium nitride (GaN), indium gallium nitride (InGaN) or gallium nitride Layer 206 has a film thickness of 1000 angstroms to 3000 angstroms.
  • a side cross-sectional view of a vertically structured LED assembly obtained by a chip process is shown in Figure 4, with an extrinsic doped buffer layer 202.
  • the epitaxial structure formed by the composite multi-current expansion layer 203, the active layer 204, the electron blocking layer 205, and the P-type GaN layer 206 is reversely flip-chip mounted on the conductive substrate 212 On.
  • the conductive substrate 212 is generally selected from a heat dissipating material, and may be a silicon wafer, a ceramic wafer or the like.
  • the substrate 212 shown in the drawing It is made of a conductive material, and is not limited to such a material. A through-hole type substrate can also be used, and the heat dissipation effect is better.
  • P- is generally provided between the P-type GaN layer 206 and the conductive substrate 212.
  • the face mirror and the ohmic electrode layer 210 are bonded to the conductive substrate through the bonding layer 211.
  • a metal expansion barrier layer may be added to the bonding layer. 213
  • a lower electrode metal layer is formed on the back surface of the conductive substrate 212, and an N-side electrode metal layer 214 is directly deposited on the extrinsic doping buffer layer 202.
  • the aforementioned vertical structure of the LED assembly can be obtained by the following method.
  • the epitaxial wafer is mesa-etched by a dry etching process, and the epitaxial wafer is selectively patterned to complete the LED.
  • the chip is chip-level separated according to the size and spacing of the design, and the etch depth is at least through the epitaxial film.
  • P-plane mirror and ohmic electrode layer 210 are formed on the P-plane of the surface of the epitaxial wafer according to the pattern of the chip design. , P-side metal diffusion barrier layer and bonding layer 211 .
  • the epitaxial wafer is inverted onto the conductive substrate 212 by a metal bonding process.
  • the sapphire substrate 201 is formed by laser lift-off, grinding, wet etching, or a combination of two techniques. Remove. At this time, the sapphire substrate and the LED epitaxial film are separated, the LED epitaxial film remains on the conductive substrate 212, and the sapphire substrate is automatically detached to form a vertical structure LED. The structure of the device, the extrinsic doped buffer layer 202 is exposed to the surface.
  • N-side electrode metal layer 214 N-type surface texture, surface etching and lower electrode metal layer 213. Complete the fabrication of the vertical structure LED.
  • the N-side electrode metal layer 214 is used.
  • the current source is introduced, and the first two-dimensional horizontal expansion is performed by the alternating stack of the u-type layer and the n-type layer of the first current spreading layer 203a; and then passes through the second current spreading layer 203b.
  • the distributed current of the insulating layer is uniformly distributed to form a point-like current source with uniform distribution; finally, by the u-type layer and n of the third current spreading layer 203d
  • the interactive stacking of the layers forces the point current sources everywhere to be a second two-dimensional horizontal expansion, so that the current spreads very evenly to the entire light-emitting area, which is more than the conventional conventional currentless expansion layer or single current expansion.
  • the design is more capable of achieving current expansion.
  • the shape, size, distribution density of the second current spreading layer insulating layer and the first and third current spreading layers may be U-type layer and n
  • the film thickness ratio of the type layer and the number of lamination cycles are designed in combination.
  • the second current spreading layer insulating layer has a high distribution density, and the number of first and third current spreading laminated layers is small; on the contrary, when the second current spreading layer insulating layer has a low distribution density, the first is required.
  • the three current spreading layer has a large number of cycles, so that the current is distributed evenly to the entire light emitting area, so that the luminous efficiency of the nitride light emitting diode assembly can be effectively improved, and the electrostatic breakdown voltage can be increased.
  • Figure 5 and FIG. 2 are schematic diagrams showing current paths of a gallium nitride-based vertical structure light-emitting diode assembly according to an embodiment of the present invention.
  • Figure 6 is a side cross-sectional view showing a gallium nitride-based vertical structure light-emitting diode assembly according to a second embodiment of the present invention.
  • the composite multi-current expansion layer of the embodiment has a gradual silicon doped n-type layer 303c added between the second current spreading layer and the third current spreading layer.
  • the graded silicon doped n-type layer 303c is designed to have a silicon doping concentration from a low doping of 5 ⁇ 10 17 cm -3 to a high doping of 1 ⁇ 10 19 cm -3 n-type nitride semiconductor layer, which is performed by secondary epitaxy
  • the purpose of the method is to repair a second current spreading layer which is caused by ion implantation to cause surface defects by a graded silicon doped n-type nitride semiconductor layer, thereby maintaining the lattice quality of the nitride semiconductor layer after secondary epitaxy. And can be used as the current guiding layer of the third current spreading layer.
  • the beneficial effect of the composite multi-current expansion layer having the process of the present invention, for the process of the present invention and the conventional process ie, the composite multi-current expansion layer having the process of the present invention
  • the samples were evaluated for their luminous output power and electrostatic breakdown voltage characteristics.
  • the film thickness of each semiconductor layer was set as shown in Table 1.
  • Each layer of the process of the invention has a film thickness ⁇ and structure
  • Each layer of the traditional process, film thickness ( ⁇ ) and structure Extrinsic doped buffer layer 300
  • Interactive stack of composite multi-current expansion layers 303a film thickness: 20000; 303b film thickness: 1500; 103c film thickness: 3500; 303d film thickness: 10000; (303 total film thickness 35000) no (N-type GaN layer 35000) Active layer GaN(140)/InGaN(25) X10 cycle (last GaN layer) GaN(140)/InGaN(25) X10 cycle (last GaN layer)
  • Electronic barrier 600 600 P-type GaN layer 2000 2000 2000
  • FIG. 8 and Figure 9 show the results of its evaluation.
  • Figure 8 The graph of the illuminating output power of each sample of the embodiment of the present invention is shown, and the luminescence output power of the gallium nitride-based vertical structure light-emitting diode module sample of the present invention is higher than that of the conventional GaN-based vertical structure light-emitting diode module sample. Out 10 ⁇ 20% or so.
  • FIG. 9 The electrostatic breakdown voltage pass rate graph of each sample of the embodiment of the present invention is shown, and the electrostatic breakdown voltage of the gallium nitride-based vertical structure light-emitting diode module sample of the present invention is higher than that of the conventional gallium nitride-based vertical structure light-emitting diode Component sample.

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Abstract

提供一种具有电流扩展层的发光二极管。其至少包括：由氮化物半导体分别形成的n侧层和p侧层；在n侧层和p侧层之间、具有由氮化物半导体构成的活性层（204）；其中n侧层由非本征掺杂缓冲层（202）及复合式多电流扩展层（203）依次层叠构成；复合式多电流扩展层（203）由第一电流扩展层（203a）、第二电流扩展层（203b）及第三电流扩展层（203c）依次层叠构成；第一电流扩展层（203a）和第三电流扩展层（203c）由u型氮化物半导体层和n型氮化物半导体层交互叠层而成，第二电流扩展层（203b）是在n型氮化物半导体层形成的分布绝缘层；第一电流扩展层（203a）与非本征掺杂缓冲层（202）毗邻，第三电流扩展层（203c）与活性层（204）毗邻。

Description

具有电流扩展层的发光二极管及其制作方法
本申请主张如下优先权：中国发明专利申请号201210202007.2 ，题为 ' 具有电流扩展层的发光二极管及其制作方法 ' ，于 2013 年 6 月 19日 提交。 上述申请的全部内容通过引用结合在本申请中。
技术领域
本发明属于发光半导体技术领域，涉及一种具有电流扩展层的氮化镓系发光二极管及其制作方法。
背景技术
近年来，为了提高 GaN 芯片的发光效率，发展了衬底转移技术，例如在蓝宝石衬底上通过 MOCVD 沉积 GaN 基薄膜，然后把 GaN 基薄膜通过晶圆键合技术或电镀技术黏结到半导体或金属基板上，再把蓝宝石衬底用激光剥离方法去除；或者在 SiC 或者 Si 衬底上沉积 GaN 基薄膜，然后把 GaN 基薄膜通过晶圆键合技术或电镀技术黏结到半导体或金属基板上，再把 SiC 或者 Si 衬底用化学腐蚀方法去除。这样一方面可以通过在外延薄膜和基板之间加一个反射层，另一方面由于氮极性面的 GaN 上容易通过光化学腐蚀方法获取粗糙的出光面，以上两方面使薄膜 GaN 芯片具有更高的出光效率，同时转移后的基板具有优良的导热特性，因此转移到散热基板上的 GaN 基薄膜芯片在大电流应用上具有较大的优势。然而，要真正意义上普及半导体照明，仍然需要在现有的光效水平上继续提高。
发明内容
根据本发明的第一个方面，提供了一种具有电流扩展层的发光二极管，包含：由氮化物半导体分别形成的 n 侧层和 p 侧层；在 n 侧层和 p 侧层之间具有由氮化物半导体构成的活性层；其中，所述 n 侧层由非本征掺杂缓冲层及复合式多电流扩展层依次层叠构成；所述复合式多电流扩展层由第一电流扩展层、第二电流扩展层及第三电流扩展依次层叠构成；所述第一电流扩展层及第三电流扩展层由 u 型氮化物半导体层和 n 型氮化物半导体层交互叠层而成，所述第二电流扩展层是在 n 型氮化物半导体层形成的分布绝缘层；所述第一电流扩展层与所述非本征掺杂缓冲层毗邻，所述第三电流扩展层与所述活性层毗邻。
根据本发明的第二个方面，提供了一种具有电流扩展层的发光二极管的制作方法，包括步骤：提供一生长衬底上，在其上形成 n 侧层；在所述 n 侧层上形成活性层；在所述活性层上形成 p 侧层，构成外延结构；其中，所述 n 侧层由非本征掺杂缓冲层及复合式多电流扩展层依次层叠构成；所述复合式多电流扩展层由第一电流扩展层、第二电流扩展层及第三电流扩展依次层叠构成；所述第一电流扩展层及第三电流扩展层由 u 型氮化物半导体层和 n 型氮化物半导体层交互叠层而成，所述第二电流扩展层是在 n 型氮化物半导体层形成的分布绝缘层；所述第一电流扩展层与所述非本征掺杂缓冲层毗邻，所述第三电流扩展层与所述活性层毗邻。
本发明公开的发光二极管具有良好 N- 型电流扩展作用，在复合式多电流扩展层内能将电流非常均匀扩展分布至整个发光面积，因而可以有效提高氮化物发光二极管组件的发光效率，并且提高静电击穿电压。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其它优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
图 1 一般氮化镓系垂直结构发光二极管组件的结构示意图。
图 2 为图 1 所示的发光二极管组件的电流路径示意图。
图 3 为本发明实施例 1 的氮化镓系垂直结构发光二极管的 LED 外延结构示意图。
图 4 是本发明实施例 1 的氮化镓系垂直结构发光二极管组件的侧面剖视图。
图 5 是本发明实施例 1 的氮化镓系垂直结构发光二极管组件的电流扩展示意图。
图 6 是本发明实施例 2 的氮化镓系垂直结构发光二极管组件的侧面剖视图。
图 7 是本发明实施例 2 的氮化镓系垂直结构发光二极管组件的电流扩展示意图。
图 8 是本发明实施例 2 的发光输出功率的曲线图。
图 9 是本发明实施例 2 的静电击穿电压通过率图。
图中各标号表示：
201 ：蓝宝石衬底；
102 ， 202 ， 302 ：非本征掺杂缓冲层；
103 ： n 型 GaN 层；
203 ， 303 ：复合式多电流扩展层；
203a ， 303a ：第一电流扩展层；
203b ， 303b ：第二电流扩展层；
303c ：渐变式硅掺杂 n 型氮化物半导体层；
203d ， 303d ：第三电流扩展层；
104 ， 204 ， 304 ：活性层；
105 ， 205 ， 305 ：电子阻挡层；
106 ， 206 ， 306 ： p 型 GaN 层；
110 ， 210 ， 310 ： P- 面反光镜和欧姆电极层；
111 ， 211 ， 311 ： P- 面金属扩散阻挡层和键合层；
112 ， 212 ， 312 ：导电基板；
113 ， 213 ， 313 ：下电极金属层；
114 ， 214 ， 314 ： N- 面电极金属层。
具体实施方式
下面结合附图和优选的具体实施例对本发明做进一步说明。在具体的器件设计和制造中，本发明提出的 LED 结构将根据应用领域和工艺制程实施的需要，对其部分结构和尺寸在一定范围内作出修改，对材料的选取进行变通。
如图 1 所示，为一般氮化镓系垂直结构发光二极管组件的结构示意图，其至上而下可能包括： N- 面电极金属层 114 、非本征掺杂缓冲层 102 、 N 型 GaN 层 103 、活性层 104 、电子阻挡层 105 、 P 型 GaN 层 106 、 P- 面反光镜和欧姆电极层 110 、 P- 面金属扩散阻挡层和键合层 111 、导电基板 112 、下电极金属层 113 。图 2 为 LED 组件的电流路径示意图，因为电流从 N- 面电极金属层 114 流向下电极金属层 113 会偏向较近的线路，这样就会造成有些部分电流密度过大，导致电流拥挤现象（ current crowding ），从而限制光效水平的有效提高。
为解决上述氮化镓系垂直结构发光二极管中所存在的问题，有效提高发光效率，下面提出了一种具有良好 N- 型电流扩展的发光二极管及其制作方法。
下列各实施例公开的具有良好 N- 型电流扩展的发光二极管的外延结构由 n 侧层、活性层、 p 侧层构成，其中 n 侧层由非本征掺杂缓冲层和复合式多电流扩展层依次层叠构成。进一步地，复合式多电流扩展层由第一电流扩展层、第二电流扩展层及第三电流扩展依次层叠构成。第一电流扩展层及第三电流扩展层由 u 型氮化物半导体层和 n 型氮化物半导体层交互叠层而成，第二电流扩展层是在 n 型氮化物半导体层形成的分布绝缘层。第一电流扩展层与非本征掺杂缓冲层毗邻，第三电流扩展层与发光二极管的活性层毗邻。
在某些实施例中，具有良好 N- 型电流扩展的发光二极管还包括一导电基板，外延结构位于该导电基板上，其中 n 侧层远离导电基板， p 侧层靠近导电基板，构成了垂直的发光结构。在 n 侧层的顶面一般设置有电极金属层，由于缓冲层为非本征掺杂，可直接将该电极金属层形成该缓冲层上。复合式多电流扩展层中的第一电流扩展层设计为 u 型氮化物半导体层和 n 型氮化物半导体层交互叠层，其目的是将从 N- 面电极金属层导入的电流源，借由 u 型层和 n 型层的交互叠层，将各处的电流源强迫先做一次二维水平扩展；第二电流扩展层的设计为在 n 型氮化物半导体层形成分布绝缘层可强迫电流均匀分布（ distribution) ，形成分布均匀的点状电流源 ( 参看图 3 或图 5) ；第三电流扩展层的设计为 u 型氮化物半导体层和 n 型氮化物半导体层交互叠层而成，其目的是将第二电流扩展层所形成的均匀分布点状电流源，由 u 型层和 n 型层的交互叠层，将各处的点状电流源再次强迫做二维水平扩展，使电流非常均匀扩展至整个发光面积，比现有一般传统无电流扩展层或单电流扩展的设计更能达到电流扩展的效果，而无电流拥挤现象（ current crowding ）。
n 侧层中的复合式多电流扩展层膜厚可以为 1000 埃～ 100000 埃。第一电流扩展层、第三电流扩展层各自膜厚可以为 350 埃～ 45000 埃，其中 u 型氮化物半导体层与 n 型氮化物半导体层的膜厚比大于 0.8 ，叠层周期数为 1 ～ 100 ；第二电流扩展层膜厚可以为 100 埃～ 5000 埃，其中分布绝缘层可以由以预定间隔隔开的绝缘部组成，其制程可通过离子注入法形成。在一些优选实施例中，第一电流扩展层膜厚可以为 10000 埃～ 40000 埃， u 型氮化物半导体层和 n 型氮化物半导体层的膜厚比为 1.5 ： 1 ，叠层周期数为 40 。第三电流扩展层膜厚为 4000 埃～ 18000 埃， u 型氮化物半导体层和 n 型氮化物半导体层的膜厚比为 1 ： 1 ，叠层周期数为 18 。
在一些优选实施例中，第一电流扩展层、第三电流扩展层中， u 型氮化物半导体层硅掺杂浓度小于 5 × 1017cm-3 ， n 型氮化物半导体层硅掺杂浓度大于 1 × 1018cm-3 。
在某些优选的实施例中，在第二电流扩展层与第三电流扩展层之间还可以包括一渐变式硅掺杂 n 型氮化物半导体层。具体地，渐变式硅掺杂 n 型氮化物半导体层的膜厚可以为 200 埃～ 5000 埃，由二次成长外延所形成，其中硅掺杂浓度由 1 × 1017cm-3 渐变至 5 × 1019cm-3 ，更优地，所硅掺杂浓度由 5 × 1017cm-3 渐变至 1 × 1019cm-3 。
在第二电流扩展层与第三电流扩展层中加入渐变式硅掺杂 n 型层，其目的是借由渐变式硅掺杂的 n 型氮化物半导体层来修复改善第二电流扩展层因形成分布绝缘层而造成表层缺陷，进而维持二次外延后氮化物半导体层的晶格质量，并可作为第三电流扩展层的电流引导层。
下面结合实施例 1 、 2 及附图 3~9 对本发明具体实施的更多细节作说明。
实施例 1
图 3 为本发明实施例 1 的氮化镓系垂直结构发光二极管的 LED 外延结构示意图，其含有复合式多电流扩展层。本实施方式的氮化物垂直结构发光二极管具有在蓝宝石衬底 201 上依次叠层下述各层的结构：
(1) 由氮化镓 (GaN) 、氮化铝（ AlN ）或氮化镓铝（ GaAlN ） 构成的非本征掺杂缓冲层 202 ，其膜厚为 200 埃～ 500 埃。
(2) 由第一电流扩展层 203a 、第二电流扩展层 203b 、第三电流扩展层 203d 依次层叠构成的复合式多电流扩展层 203 ，其膜厚为 15000 埃～ 100000 埃间。第一电流扩展层 203a 膜厚为 10000 埃～ 40000 埃， u 型氮化物半导体层和 n 型氮化物半导体层的膜厚比为 1.5 ： 1 ，叠层周期数为 40 。第二电流扩展层 203b 为通过离子注入法在 n 型氮化物半导体层形成的分布式绝缘层，由预定间隔隔开的绝缘部组成，膜厚为 100 埃～ 5000 埃。第三电流扩展层 203d 膜厚为 4000 埃～ 18000 埃， u 型氮化物半导体层和 n 型氮化物半导体层的膜厚比为 1 ： 1 ，叠层周期数为 18 。在第一电流扩展层 203a 、第三电流扩展层 203d 中， u 型氮化物半导体层硅掺杂浓度小于 5 × 1017cm-3 ， n 型氮化物半导体层硅掺杂浓度大于 1 × 1018cm-3 。
(4) 以 InGaN 层作为阱层、 GaN 层作为势垒层的多量子阱结构的活性层 204 ；其中阱层的膜厚为 18 埃～ 30 埃，势垒层的膜厚为 80 埃～ 200 埃。
(5) 由掺杂了 Mg 的氮化铝铟镓 (AlInGaN) 构成的电子阻挡层 205 ，其膜厚为 100 埃～ 600 埃。
(6) 由氮化镓 (GaN) 、氮化铟镓 (InGaN) 或氮化镓系之一构成的 P 型 GaN 层 206 ，其膜厚为 1000 埃～ 3000 埃。
通过芯片制程获得的垂直结构的 LED 组件的侧面剖视图如图 4 所示，由非本征掺杂缓冲层 202 、复合式多电流扩展层 203 、活性层 204 、电子阻挡层 205 、 P 型 GaN 层 206 构成的外延结构反转倒装在导电基板 212 上。导电基板 212 一般选择散热性材料，可为硅片、陶瓷片等。在附图中所示的基板 212 为导电型的材料构成，并不局限于此类材料，也可选用通孔型基板，其散热效果更佳。在 P 型 GaN 层 206 与导电基板 212 之间一般设有 p- 面反射镜和欧姆电极层 210 ，并通过键合层 211 键合在导电基板上，为了防止金属扩展，还可以在键合层中加入金属扩展阻挡层。 213 下电极金属层形成于导电基板 212 的背面上， N- 面电极金属层 214 直接沉积在非本征掺杂缓冲层 202 上。
前述的垂直结构的 LED 组件可通过下面方法制作获得。
（ 1 ）在蓝宝石衬底 201 上通过 MOCVD 外延生长非本征掺杂缓冲层 202 及复合式多电流扩展层 203 中的第一及第二电流扩展层，并通过离子注入法在第二电流扩展层形成预定间隔隔开的分布绝缘层。
（ 2 ）在第二电流扩展层 203b 上二次外延生长第三电流扩展层 203d 、活性层 204 、电子阻挡层 205 、 P 型 GaN 层 206 ，完成外延生长。
（ 3 ）然后通过干法蚀刻工艺对外延片进行台面蚀刻，对外延片进行选择性图形蚀刻，完成 LED 芯片按照设计的尺寸和间隔进行的芯片级分离，蚀刻深度至少透过外延层薄膜。
（ 4 ）在外延片表面的 P- 面按照芯片设计的图形制作 P- 面反光镜和欧姆电极层 210 、 P- 面金属扩散阻挡层和键合层 211 。
（ 5 ）将外延片通过金属键合工艺反转到导电基板 212 上。
（ 6 ）通过透过激光剥离、研磨、湿法腐蚀或结合其中两种技术，将蓝宝石衬底 201 去除。此时，蓝宝石衬底和 LED 外延层薄膜分开， LED 外延层薄膜保留在导电基板 212 上，而蓝宝石衬底自动脱落，形成可制作垂直结构 LED 器件的结构，非本征掺杂缓冲层 202 暴露在表面。
（ 7 ）制作 N- 面电极金属层 214 、 N- 型表面织构化、表面刻蚀与下电极金属层 213 ，完成垂直结构 LED 的制作。
请参看附图 5 ，在本实施例中，从 N- 面电极金属层 214 导入的电流源，借由第一电流扩展层 203a 的 u 型层和 n 型层的交互叠层做第一次二维水平扩展；接着通过第二电流扩展层 203b 的分布绝缘层的强迫电流均匀分布 (distribution) 作用，形成分布均匀的点状电流源；最后借由第三电流扩展层 203d 的由 u 型层和 n 型层的交互叠层，将各处的点状电流源强迫做第二次二维水平扩展，从而使电流非常均匀扩展至整个发光面积，比现有一般传统无电流扩展层或单电流扩展的设计更能达到电流扩展的效果。进一步地，可借由第二电流扩展层绝缘层的的形状、大小、分布密度与第一、三电流扩展层 u 型层与 n 型层的膜厚比、叠层周期数做搭配设计。例如：第二电流扩展层绝缘层的分布密度高，所需第一、三电流扩展层叠层周期数则少；反之，当第二电流扩展层绝缘层的分布密度低，则所需第一、三电流扩展层叠层周期数则多，使电流非常均匀分布至整个发光面积，因此可以有效提高氮化物发光二极管组件的发光效率，并且提高静电击穿电压。图 5 和图 2 是有无本发明实施方式的氮化镓系垂直结构发光二极管组件的电流路径示意图。
实施例 2
图 6 是示出本发明实施例 2 的氮化镓系垂直结构发光二极管组件的侧面剖视图。本实施例与实施例 1 的相比，其复合式多电流扩展层为在第二电流扩展层与第三电流扩展层之间多加入一渐变式硅掺杂 n 型层 303c 。该渐变式硅掺杂 n 型层 303c 的设计为硅掺杂浓度由低掺 5 × 1017cm-3 渐变至高掺 1 × 1019cm-3 的 n 型氮化物半导体层，是由二次外延所形成，其目的是借由渐变式硅掺杂的 n 型氮化物半导体层来修复改善因离子注入造成表层缺陷的第二电流扩展层，进而维持二次外延后氮化物半导体层的晶格质量，并可作为第三电流扩展层的电流引导层。
在本实施例中，为更好地说明本发明相较于传统的氮化镓系垂直结构发光二极管 ( 即有无本发明工艺的复合式多电流扩展层 ) 的有益效果，针对本发明工艺与传统的工艺 ( 即有无本发明工艺的复合式多电流扩展层 ) ，制作 2 种样品，分别评价其发光输出功率与静电击穿电压特性。
在本实施例中，按表 1 所示那样设定各半导体层的膜厚。
表 1
层 本发明工艺的各层 膜厚埃（ À ）及结构 传统工艺的各层 膜厚埃（ À ）及结构
非本征掺杂缓冲层 300 300
复合式多电流扩展层 的交互叠层 303a 膜厚 :20000 ； 303b 膜厚 :1500 ； 103c 膜厚 :3500 ；
303d 膜厚 :10000 ；
(303 总膜厚 35000)		 无
(N 型 GaN 层 35000)
活性层 GaN(140)/InGaN(25)
X10 周期 ( 最后是 GaN 层 )		 GaN(140)/InGaN(25)
X10 周期 ( 最后是 GaN 层 )
电子阻挡层 600 600
P 型 GaN 层 2000 2000
图 8 、图 9 示出了它的评价结果。
如图 8 所示的本发明实施例的各样品的发光输出功率的曲线图，本发明的氮化镓系垂直结构发光二极管组件样品的发光输出功率比传统工艺的氮化镓系垂直结构发光二极管组件样品高出 10~20 ％左右。
如图 9 所示的本发明实施例的各样品的静电击穿电压通过率图，本发明的氮化镓系垂直结构发光二极管组件样品的静电击穿电压高于传统工艺的氮化镓系垂直结构发光二极管组件样品。

Claims (22)

  1. 具有电流扩展层的发光二极管，包含：
    由氮化物半导体分别形成的 n 侧层和 p 侧层；
    在 n 侧层和 p 侧层之间具有由氮化物半导体构成的活性层；
    其特征在于：所述 n 侧层由非本征掺杂缓冲层及复合式多电流扩展层依次层叠构成；所述复合式多电流扩展层由第一电流扩展层、第二电流扩展层及第三电流扩展依次层叠构成；所述第一电流扩展层及第三电流扩展层由 u 型氮化物半导体层和 n 型氮化物半导体层交互叠层而成，所述第二电流扩展层是在 n 型氮化物半导体层形成的分布绝缘层；所述第一电流扩展层与所述非本征掺杂缓冲层毗邻，所述第三电流扩展层与所述活性层毗邻。
  2. 根据权利要求 1 所述的具有电流扩展层的发光二极管，其特征在于：所述复合式多电流扩展层还包括一渐变式硅掺杂 n 型氮化物半导体层，其位于所述第二电流扩展层与所述第三电流扩展层之间。
  3. 根据权利要求 1 或 2 所述的具有电流扩展层的发光二极管，其特征在于：还包括一导电基板，由所述 p 侧、活性层和 n 侧层构成的外延结构位于所述导电基板之上，构成垂直的发光结构。
  4. 根据权利要求 1 或 2 所述的具有电流扩展层的发光二极管，其特征在于：所述分布绝缘层由以预定间隔隔开的绝缘部组成。
  5. 根据权利要求 2 所述的具有电流扩展层的发光二极管，其特征在于：所述复合式多电流扩展层膜厚为 1000 埃～ 100000 埃。
  6. 根据权利要求 1 或 2 所述的具有电流扩展层的发光二极管，其特征在于：所述第二电流扩展层膜厚为 100 埃～ 5000 埃。
  7. 根据权利要求 2 所述的具有电流扩展层的发光二极管，其特征在于：所述渐变式硅掺杂 n 型氮化物半导体层膜厚为 200 埃～ 5000 埃。
  8. 根据权利要求 2 所述的具有电流扩展层的发光二极管，其特征在于：所述渐变式硅掺杂 n 型氮化物半导体层由二次成长外延所形成，其中硅掺杂浓度由 1 × 1017cm-3 渐变至 5 × 1019cm-3 。
  9. 根据权利要求 8 所述的具有电流扩展层的发光二极管，其特征在于：所述渐变式硅掺杂 n 型氮化物半导体层由二次成长外延所形成，其中硅掺杂浓度由 5 × 1017cm-3 渐变至 1 × 1019cm-3 。
  10. 根据权利要求 1 或 2 所述的具有电流扩展层的发光二极管，其特征在于：所述第一电流扩展层、第三电流扩展层各自膜厚为 350 埃～ 45000 埃，其中 u 型氮化物半导体层与 n 型氮化物半导体层的膜厚比大于 0.8 ，叠层周期数为 1 ～ 100 。
  11. 根据权利要求 10 所述的具有电流扩展层的垂直结构发光二管，其特征在于：所述第一电流扩展层膜厚为 10000 埃～ 40000 埃， u 型氮化物半导体层和 n 型氮化物半导体层的膜厚比为 1.5 ： 1 ，叠层周期数为 40 。
  12. 根据权利要求 10 或 11 所述的具有电流扩展层的发光二极管，其特征在于：所述第三电流扩展层膜厚为 4000 埃～ 18000 埃， u 型氮化物半导体层和 n 型氮化物半导体层的膜厚比为 1 ： 1 ，叠层周期数为 18 。
  13. 根据权利要求 1 或 2 所述的具有电流扩展层的发光二极管，其特征在于：所述第一电流扩展层、第三电流扩展层中， u 型氮化物半导体层硅掺杂浓度小于 5 × 1017cm-3 ， n 型氮化物半导体层硅掺杂浓度大于 1 × 1018cm-3 。
  14. 具有电流扩展层的发光二极管的制作方法，包括步骤：
    提供一生长衬底上，在其上形成 n 侧层；
    在所述 n 侧层上形成活性层；
    在所述活性层上形成 p 侧层，构成外延结构；
    其中，所述 n 侧层由非本征掺杂缓冲层及复合式多电流扩展层依次层叠构成；所述复合式多电流扩展层由第一电流扩展层、第二电流扩展层及第三电流扩展依次层叠构成；所述第一电流扩展层及第三电流扩展层由 u 型氮化物半导体层和 n 型氮化物半导体层交互叠层而成，所述第二电流扩展层是在 n 型氮化物半导体层形成的分布绝缘层；所述第一电流扩展层与所述非本征掺杂缓冲层毗邻，所述第三电流扩展层与所述活性层毗邻。
  15. 根据权利要求 14 所述的具有电流扩展层的发光二极管的制作方法，所述 n 侧层通过下列步骤形成：
    在所述生长衬底上依次外延生长非本征掺杂缓冲层及第一及第二电流扩展层，并通过离子注入法在所述第二电流扩展层形成预定间隔隔开的分布绝缘层；
    在所述第二电流扩展层上二次外延生长第三电流扩展层。
  16. 根据权利要求 15 所述的具有电流扩展层的发光二极管的制作方法，还包括步骤：
    在所述第二电流扩展层与所述第三电流扩展层之间形成一渐变式硅掺杂 n 型氮化物半导体层。
  17. 根据权利要求 15 或 16 所述的具有电流扩展层的发光二极管的制作方法，还包括步骤：
    提供一导电基板；
    将所述外延结构所述导电基板连结；
    移除所述生长衬底；
    制作 p 、 n 电极，形成垂直结构的发光二极管。
  18. 根据权利要求 17 所述的具有电流扩展层的发光二极管的制作方法，其特征在于：所述复合式多电流扩展层膜厚为 1000 埃～ 100000 埃。
  19. 根据权利要求 17 所述的具有电流扩展层的发光二极管的制作方法，其特征在于：所述第一电流扩展层、第三电流扩展层各自膜厚为 350 埃～ 45000 埃，其中 u 型氮化物半导体层与 n 型氮化物半导体层的膜厚比大于 0.8 ，叠层周期数为 1 ～ 100 。
  20. 根据权利要求 19 所述的具有电流扩展层的发光二极管的制作方法，其特征在于：所述第一电流扩展层膜厚为 10000 埃～ 40000 埃， u 型氮化物半导体层和 n 型氮化物半导体层的膜厚比为 1.5 ： 1 ，叠层周期数为 40 。
  21. 根据权利要求 19 所述的具有电流扩展层的发光二极管的制作方法，其特征在于：所述第三电流扩展层膜厚为 4000 埃～ 18000 埃， u 型氮化物半导体层和 n 型氮化物半导体层的膜厚比为 1 ： 1 ，叠层周期数为 18 。
  22. 根据权利要求 17 所述的具有电流扩展层的发光二极管的制作方法，其特征在于：所述第一电流扩展层、第三电流扩展层中， u 型氮化物半导体层硅掺杂浓度小于 5 × 1017cm-3 ， n 型氮化物半导体层硅掺杂浓度大于 1 × 1018cm-3 。
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