WO2013166895A1 - 一种无源射频识别上电复位电路及无源射频识别标签 - Google Patents

一种无源射频识别上电复位电路及无源射频识别标签 Download PDF

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WO2013166895A1
WO2013166895A1 PCT/CN2013/073881 CN2013073881W WO2013166895A1 WO 2013166895 A1 WO2013166895 A1 WO 2013166895A1 CN 2013073881 W CN2013073881 W CN 2013073881W WO 2013166895 A1 WO2013166895 A1 WO 2013166895A1
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type mos
mos transistor
unit
twenty
switch tube
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PCT/CN2013/073881
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English (en)
French (fr)
Inventor
梁海浪
韩富强
吴边
漆射虎
罗远明
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卓捷创芯科技（深圳）有限公司
无锡智速科技有限公司
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Publication of WO2013166895A1 publication Critical patent/WO2013166895A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0701—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management

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  • the invention belongs to the field of radio frequency, and particularly relates to a passive radio frequency identification power-on reset circuit and a passive radio frequency identification tag.
  • Radio Frequency Identification (Radio Frequency Identification, RFID) is a non-contact automatic identification technology that can be applied to various fields such as warehouse management, identification, transportation, food and medical, animal management, etc. Due to its wide application, RFID technology has been more and more in recent years. The more you pay attention.
  • the RFID tags are mainly divided into passive tags and active tags.
  • the passive passive RFID tag system generates energy from the RF energy emitted by the reader. It does not need a built-in power supply. It receives RF signals through the antenna and is internally rectified. And the voltage stabilizing circuit generates a stable power supply.
  • the power-on reset circuit detects and determines whether the power supply voltage reaches the starting voltage, and outputs a reset signal when the power supply voltage reaches the starting voltage, to the digital circuit and other working circuits. Realize reset and start.
  • Figure 1 shows the structure of a conventional power-on reset circuit, including an N-type MOS transistor M1, an N-type MOS transistor M2, a capacitor C11, an inverter NOT11, a delay device D11, and an exclusive OR gate XOR11;
  • the gate and the drain of the N-type MOS transistor M1 are simultaneously connected to the power supply voltage VDDA, the source of the N-type MOS transistor M1 is connected to the drain of the N-type MOS transistor M2, and the gate of the N-type MOS transistor M2 and the N-type
  • the drain of the MOS transistor M2 is connected, the source of the N-type MOS transistor M2 is grounded through the capacitor C11, the connection point of the N-type MOS transistor M2 and the capacitor C11 is the node J, and the source of the N-type MOS transistor M2 is simultaneously with the inverter NOT11
  • the input terminal is connected, and the output terminal of the inverter NOT11 is simultaneously connected with the input terminal of the delay device D11 and the XOR11 terminal of the exclusive OR gate.
  • connection point of the inverter NOT11 with the delay device D11 and the exclusive OR gate XOR11 is the node K1, and the delay is delayed.
  • the output of the D11 is connected to the other end of the XOR11, and the output of the XOR11 is the output of the power-on reset signal for outputting a reset signal.
  • the N-type MOS transistor M1 and the N-type MOS transistor M2 form two unidirectional conduction devices.
  • the power supply voltage VDDA is greater than the sum of the threshold voltages of the N-type MOS transistor M1 and the N-type MOS transistor M2
  • the N-type The MOS transistor M1 and the N-type MOS transistor M2 are turned on, the power supply voltage VDDA charges the capacitor C11, and the voltage of the capacitor C11 is outputted as a reset signal POR by the reverse and delay processing.
  • FIG. 3 shows the structure of another form of power-on reset circuit, including a P-type MOS transistor M3, a P-type MOS transistor M4, a P-type MOS transistor M5, a capacitor C12, an inverter NOT12, a delay device D12, and XOR gate XOR12;
  • the source of the P-type MOS transistor M3 and the source of the P-type MOS transistor M4 are simultaneously connected to the power supply voltage VDDA, the gate of the P-type MOS transistor M3 is connected to the drain thereof, and the drain of the P-type MOS transistor M3 is connected to the P.
  • the source of the MOS transistor M5 is connected, the gate of the P-type MOS transistor M5 is simultaneously grounded with its drain, the gate of the P-type MOS transistor M4 is connected to the gate of the P-type MOS transistor M3, and the drain of the P-type MOS transistor M4
  • the capacitor P12 is grounded, the drain of the P-type MOS transistor M4 is also connected to the input terminal of the inverter NOT12, and the output terminal of the inverter NOT12 is simultaneously connected to the input terminal of the delay device D12 and the second input terminal of the XOR gate XOR12.
  • the output of the delay D12 is connected to the first input of the exclusive OR gate XOR12, and the output of the exclusive OR gate XOR12 is the output of the power-on reset signal for outputting a reset signal.
  • the P-type MOS transistor M3 and the P-type MOS transistor M4 constitute a pair of capacitors C12 A mirrored current source for charging. After charging, the voltage of the capacitor C12 is outputted as a reset signal POR by the reverse and delay processing. Compared with the first prior art example, only the delay capacitor C12 is charged in a slightly different manner. During the dynamic fast power-on process, the power supply voltage is not high enough, and the input terminal of the inverter NOT12 is in the absence. Driven state, thus no determined level input, resulting inverter NOT12 The output is not controlled by the input voltage, making the inverter NOT12 The output voltage is not determined to follow the power supply voltage, and there is always a certain voltage difference from the power supply voltage.
  • the waveform S5 i.e., the output reset signal POR
  • the waveform S4 also has a short-term problem of not being able to follow the waveform S4, that is, the rise of the power supply voltage input to the reset circuit, resulting in the generation of a false pulse.
  • the existing power-on reset circuit has the above-mentioned pseudo-pulse signal
  • the amplitude variation range of the pseudo-pulse signal is usually between 0.3V and 1.5V when VDDA is 1.8V, however, in the RFID system.
  • triggering the digital circuit due to ignoring the above false pulse, which directly leads to a decrease in the sensitivity of the RFID tag, so that the power-on flip level is raised, and the power-on reset cannot be realized under the low power supply voltage. Very big.
  • the power-on reset voltage in the low-power RFID system is lower than the conventional reset voltage.
  • the existing power-on reset circuit structure is prone to generate false pulses, resulting in the system being The false pulse triggers and enters the working mode by mistake, and the power supply at this time does not satisfy the trigger condition of the power-on reset circuit, thereby reducing the sensitivity of the radio frequency tag and even causing the system to be unstable.
  • An object of the present invention is to provide a passive radio frequency identification power-on reset circuit, which aims to solve the problem that the system is abnormally reset due to the occurrence of a false pulse signal during power-on reset.
  • a passive radio frequency identification power-on reset circuit the circuit comprising:
  • a detecting unit wherein the input end of the detecting unit is connected to an output end of the power management module, configured to detect, by the power management module, a magnitude of a power supply voltage to be tested, and output a power detecting signal and a follow control signal;
  • the first input of the following control unit is connected to the output of the power management module, and the second input of the following control unit is connected to the first output of the detection unit, the following a control end of the control unit is coupled to the second output end of the detecting unit, configured to generate a power supply following signal following the power detection signal and the power voltage according to the following control signal;
  • a delay unit an input end of the delay unit is connected to an output end of the following control unit, and an output end of the delay unit is connected to a digital circuit for delaying and deglitching the power following signal , generate a reset signal.
  • Another object of embodiments of the present invention is to provide a passive radio frequency identification tag using the above passive radio frequency identification power-on reset circuit.
  • False triggering ensures the reliability of the system, enabling power-on reset under low power supply voltage conditions, avoiding high power consumption caused by preventing flip-flops due to false triggering, and more suitable for low-power demand radio frequency identification. System, and only one switch is turned on after reset to achieve a low power reset.
  • FIG. 1 is a structural diagram of a conventional power-on reset circuit
  • FIG. 2 is a signal waveform diagram of the power-on reset circuit corresponding to FIG. 1;
  • FIG. 3 is another structural diagram of a conventional power-on reset circuit
  • FIG. 4 is a signal waveform diagram of the power-on reset circuit corresponding to FIG. 3;
  • FIG. 5 is a structural diagram of a passive radio frequency identification power-on reset circuit according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram showing an example of a passive radio frequency identification power-on reset circuit according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of signal changes of a passive radio frequency identification power-on reset circuit according to an embodiment of the present invention.
  • Figure 8 is an expanded view of each signal line in Figure 7.
  • the power supply following signal closely follows the power supply voltage, effectively suppressing the generation of the false pulse signal and ensuring the reliability of the reset signal.
  • FIG. 5 shows the structure of a passive radio frequency identification power-on reset circuit according to an embodiment of the present invention. For convenience of description, only parts related to the present invention are shown.
  • the passive radio frequency identification power-on reset circuit 1 provided as an embodiment of the present invention can be applied to various passive radio frequency identification tags 4, and the passive radio frequency identification power-on reset circuit 1 is connected to the power supply unit 2 (for example, low voltage) Differential linear regulator low Between dropout regulator, LDO) and digital circuits, including:
  • the power supply unit 2 for example, low voltage
  • Differential linear regulator low Between dropout regulator, LDO Differential linear regulator low Between dropout regulator, LDO
  • digital circuits including:
  • the detecting unit 11 and the output end of the detecting unit 11 and the output end of the power management module in the passive radio frequency identification tag are configured to detect the output of the power supply voltage VDDA to be tested by the power management module 2, and output a power detecting signal. And following control signals;
  • the first input of the following control unit is connected to the output of the power management module 2 in the passive radio frequency identification tag, and the second input of the following control unit is connected to the first output of the detection unit 11, followed by The control end of the control unit is connected to the second output end of the detecting unit 11 for generating a power following signal following the power detecting signal and the power voltage according to the following control signal;
  • the delay unit 13 is connected to the output end of the follow-up control unit 12, and the output end of the delay unit 13 is connected to the digital circuit 3 in the passive RFID tag for performing the power follow signal Delay and deburring processing to generate a reset signal.
  • False triggering ensures the reliability of the system, enabling power-on reset under low power supply voltage conditions, avoiding high power consumption caused by preventing flip-flops due to false triggering, and more suitable for low-power demand radio frequency identification. System, and only one switch is turned on after reset to achieve a low power reset.
  • FIG. 6 shows an example circuit structure of a passive radio frequency identification power-on reset circuit according to an embodiment of the present invention. For convenience of description, only parts related to the present invention are shown.
  • the detecting unit 11 includes:
  • a resistor R1 a first one-way unit 111, a second one-way unit 112, and a capacitor C1;
  • One end of the resistor R1 is an input end of the detecting unit 11, and the other end of the resistor R1 is a first output end of the detecting unit 11 connected to an input end of the first one-way conducting unit, and an output end of the first one-way conducting unit 111
  • the input end of the second unidirectional conduction unit 112 is connected, the output end of the second unidirectional conduction unit 112 is grounded, and the second output end of the capacitor C1 is connected to the output end of the first unidirectional conduction unit, and the capacitor C1 is connected.
  • the other end is grounded.
  • the first unidirectional conduction unit 111 and the second unidirectional conduction unit 112 can be implemented by using a plurality of diodes in series, and the anode of the first diode D1 is the input end of the first unidirectional conduction unit 111.
  • the cathode of the first diode D1 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the anode of the diode connected in series, and so on, and the cathode of the diode of the last series is the first
  • the output of one single-pass unit 111, the plurality of diodes of the second one-way unit 112 are the same as the first one-way unit 111, and are not described herein again, and the first one-way unit 111 and the second
  • the number of diodes selected in series by the one-way conduction unit 112 is guaranteed to avoid diode forward conduction and to properly adjust the diode sub-threshold leakage current to ensure temporary follow-up behavior of node A with respect to the power supply.
  • the first unidirectional conduction unit 111 and the second unidirectional conduction unit 112 can also be implemented by using a plurality of diode-connected MOS tubes in series.
  • the series structure of three MOS tubes is used.
  • the first one-way pass unit 111 includes: an eleventh P-type MOS transistor M11, a twelfth P-type MOS transistor M12, and a thirteenth P-type MOS transistor M13;
  • the source of the eleventh P-type MOS transistor M11 is the input end of the first unidirectional conduction unit 111, and the gate of the eleventh P-type MOS transistor M11 is connected to the drain of the eleventh P-type MOS transistor M11, and the tenth
  • the drain of a P-type MOS transistor M11 is connected to the source of the twelfth P-type MOS transistor M12, and the gate of the twelfth P-type MOS transistor M12 is connected to the drain of the twelfth P-type MOS transistor M12.
  • the drain of the twelve P-type MOS transistor M12 is further connected to the source of the thirteenth P-type MOS transistor M13, and the gate of the thirteenth P-type MOS transistor M13 is connected to the drain of the thirteenth P-type MOS transistor M13.
  • the drain of the thirteenth P-type MOS transistor M13 is the output terminal of the first one-way conduction unit 111.
  • the second unidirectional pass unit 112 includes: a fourteenth N-type MOS transistor M14, a fifteenth N-type MOS transistor M15, and a sixteenth N-type MOS transistor M16;
  • the drain of the fourteenth N-type MOS transistor M14 is the input end of the second unidirectional conduction unit 112, and the gate of the fourteenth N-type MOS transistor M14 is connected to the drain of the fourteenth N-type MOS transistor M14, and the tenth
  • the source of the four N-type MOS transistor M14 is further connected to the drain of the fifteenth N-type MOS transistor M15, and the gate of the fifteenth N-type MOS transistor M15 is connected to the drain of the fifteenth N-type MOS transistor M15,
  • the source of the fifteen-type N-type MOS transistor M15 is further connected to the drain of the sixteenth N-type MOS transistor M16, and the gate of the sixteenth N-type MOS transistor M16 is connected to the drain of the sixteenth N-type MOS transistor M16.
  • the source of the sixteenth N-type MOS transistor M16 is the output of the second one-way conduction unit 112.
  • first one-way unit 111 and the second one-way unit 112 are not limited to include three MOS tubes, and the number of specific MOS tubes may be selected according to the output voltage of the power management module (5V, 3V, or 1.8V). That is, under normal working conditions, the voltage of the cascaded MOS tube series branch is turned on higher than the system power supply voltage to avoid the forward conduction of the MOS tube, and when the pulse of the reset signal POR has not been formed, multiple The MOS tube branch of the series connection provides a sub-threshold leakage path from the power supply to node A.
  • the size and number ratio of the MOS transistors in the first one-way conduction unit 111 and the second one-way conduction unit 112 determine the magnitude of the charging current to the capacitor C1, the magnitude of the constant DC current after stabilization, and the voltage on the stabilized C1 capacitor. High and low. From the viewpoint of low power consumption, the number of MOS transistors in the first one-way conduction unit 111 and the second one-way conduction unit 112 is preferably 7-15.
  • the following control unit 12 includes:
  • a first switching unit 121 a second switching unit 122, a third unidirectional conduction unit 123, a fourth unidirectional conduction unit 124, and a resistor R2;
  • the input end of the first switch unit 121 is the second input end of the following control unit 12, the output end of the first switch unit 121 is connected to the input end of the second switch unit 122, and the output end of the second switch unit 122 is grounded, first The control end of the switch unit 121 is grounded through the resistor R2, the control end of the second switch unit 122 is the control end of the following control unit 12, and the input end of the third unidirectional pass unit 123 is the first input end of the follow control unit 12, The output of the three-way conduction unit 123 is connected to the input end of the fourth unidirectional conduction unit 124, and the output end of the fourth unidirectional conduction unit 124 is the output of the following control unit 12, and the output of the fourth unidirectional conduction unit 124.
  • the terminal is connected to the input of the second switching unit 122.
  • the first switch unit 121 and the second switch unit 122 can be implemented by using a plurality of switch tubes connected in series.
  • the first switch unit 121 includes a twenty-first switch tube 1211, a twenty-second switch tube 1212, a twenty-third switch tube 1213;
  • the input end of the 21st switch tube 1211 is the input end of the first switch unit 121, the output end of the 21st switch tube 1211 is connected to the input end of the 22nd switch tube 1212, and the 22nd switch tube
  • the output end of the 1212 is connected to the input end of the twenty-third switch tube 1213, the output end of the twenty-third switch tube 1213 is the output end of the first switch unit 121, and the control end of the twenty-first switch tube 1211 is second.
  • the control end of the twelve switch tube 1212 and the control end of the twenty-third switch tube 1213 are simultaneously connected to the control end of the first switch unit 121.
  • the twenty-first switch tube 1211, the second switch tube 1212, and the twenty-third switch tube 1213 can be implemented by using a PNP type transistor, and the base of the PNP type transistor is a twenty-first switch.
  • the control end of the tube 1211, the twenty-second switch tube 1212, the twenty-third switch tube 1213, the emission of the PNP type transistor is extremely the twenty-first switch tube 1211, the twenty-second switch tube 1212, the twenty-third switch tube
  • the collector of the PNP type transistor is the output end of the twenty-first switch tube 1211, the twenty-second switch tube 1212, and the twenty-third switch tube 1213.
  • the twenty-first switch tube 1211, the second switch tube 1212, and the twenty-third switch tube 1213 can also be implemented by using a P-type MOS tube M21, a P-type MOS tube M22, and a P-type MOS tube M23, respectively.
  • the gates of the P-type MOS transistors M21, M22, and M23 are respectively the control ends of the twenty-first switch tube 1211, the twenty-second switch tube 1212, the twenty-third switch tube 1213, and the P-type MOS tubes M21, M22, and M23.
  • the sources of the P1 MOS transistors M21, M22, and M23 are respectively the 21st.
  • the output ends of the switch tube 1211, the twenty-second switch tube 1212, and the twenty-third switch tube 1213 are respectively.
  • the second switch unit 122 includes: a twenty-fourth switch tube 1221, a twenty-fifth switch tube 1222, and a twenty-six switch tube 1223;
  • the input end of the twenty-fourth switch tube 1221 is the input end of the second switch unit 122, the output end of the twenty-fourth switch tube 1221 is connected to the input end of the twenty-fifth switch tube 1222, and the twenty-fifth switch tube
  • the output end of the 1222 is connected to the input end of the twenty-six switch tube 1223, the output end of the twenty-six switch tube 1223 is the output end of the second switch unit 122, and the control end of the twenty-fourth switch tube 1221 is second.
  • the control end of the fifteen switch tube 1222 and the control end of the twenty-six switch tube 1223 are simultaneously connected to the control end of the second switch unit 122.
  • the twenty-fourth switch tube 1221, the twenty-fifth switch tube 1222, and the twenty-six switch tube 1223 can all be implemented by using an NPN type transistor, and the base of the NPN type transistor is the twenty-fourth switch.
  • the control end of the tube 1221, the twenty-fifth switch tube 1222, the twenty-six switch tube 1223, the collector of the NPN type transistor is the twenty-fourth switch tube 1221, the twenty-fifth switch tube 1222, and the twenty-sixth switch
  • the input end of the tube 1223, the emitter of the NPN type transistor is the output end of the twenty-fourth switch tube 1221, the twenty-fifth switch tube 1222, and the twenty-six switch tube 1223.
  • the twenty-fourth switch tube 1221, the twenty-fifth switch tube 1222, and the twenty-six switch tube 1223 can also be implemented by using an N-type MOS tube M24, an N-type MOS tube M25, and an N-type MOS tube M26, respectively.
  • the gates of the N-type MOS transistors M24, M25, and M26 are the control terminals of the twenty-fourth switch tube 1221, the twenty-fifth switch tube 1222, and the twenty-six switch tube 1223, respectively, and the N-type MOS tubes M24, M25, and M26.
  • the drains are respectively the input ends of the twenty-fourth switch tube 1221, the twenty-fifth switch tube 1222, and the twenty-six switch tube 1223, and the drains of the N-type MOS transistors M24, M25, and M26 are respectively the twenty-fourth.
  • the third unidirectional conduction unit 123 and the fourth unidirectional conduction unit 124 may each be implemented by using a plurality of diodes in series, and the anode of the fourth diode D4 is an input end of the third unidirectional conduction unit 123.
  • the cathode of the fourth diode D4 is connected to the anode of the fifth diode D5, the cathode of the fifth diode D5 is connected to the anode of the diode connected in series, and so on, and the cathode of the diode of the last series is the first
  • the output of the three-way conduction unit 123, the plurality of diodes of the fourth one-way unit 124 are the same as the third one-way unit 123, and are not described herein again, and the third one-way unit 123, the fourth The number of diodes connected in series by the one-way conduction unit 124 is guaranteed to avoid diode forward conduction and to properly adjust the leakage current of the diode sub-threshold to ensure the temporary following behavior of the node B with respect to the power supply.
  • the third unidirectional conduction unit 123 and the fourth unidirectional conduction unit 124 can also be implemented by using a plurality of diode-connected MOS tubes in series.
  • the series structure of three MOS tubes is used.
  • the third one-way pass unit 123 includes: a thirty-first P-type MOS transistor M31, a thirty-second P-type MOS transistor M32, and a thirty-third P-type MOS transistor M33;
  • the source of the 31st P-type MOS transistor M31 is the input end of the third unidirectional conduction unit 123, and the gate of the 31st P-type MOS transistor M31 is connected to the drain of the 31st P-type MOS transistor M31.
  • the drain of the thirty-first P-type MOS transistor M31 is further connected to the source of the thirty-second P-type MOS transistor M32, the gate of the thirty-second P-type MOS transistor M32 and the thirty-second P-type MOS transistor
  • the drain of the M32 is connected, the drain of the thirty-second P-type MOS transistor M32 is connected to the source of the thirty-third P-type MOS transistor M33, and the gate of the thirty-third P-type MOS transistor M33 is the thirty
  • the drain of the triple P-type MOS transistor M33 is connected, and the drain of the thirty-third P-type MOS transistor M33 is the output terminal of the third unidirectional conduction unit 123.
  • the fourth one-way pass unit 124 includes: a thirty-fourth P-type MOS transistor M34, a thirty-fifth P-type MOS transistor M35, and a thirty-sixth P-type MOS transistor M36;
  • the source of the thirty-fourth P-type MOS transistor M34 is the input end of the fourth one-way conduction unit 124, and the gate of the thirty-fourth P-type MOS transistor M34 is connected to the drain of the thirty-fourth P-type MOS transistor M34.
  • the drain of the thirty-fourth P-type MOS transistor M34 is further connected to the source of the thirty-fifth P-type MOS transistor M35, the gate of the thirty-fifth P-type MOS transistor M35 and the thirty-fifth P-type MOS transistor
  • the drain of the M35 is connected, the drain of the thirty-fifth P-type MOS transistor M35 is connected to the source of the thirty-sixth P-type MOS transistor M36, and the gate of the thirty-sixth P-type MOS transistor M36 is the thirty
  • the drain of the six P-type MOS transistor M36 is connected, and the drain of the thirty-sixth P-type MOS transistor M36 is the output terminal of the fourth unidirectional conduction unit 124.
  • the third unidirectional conduction unit 123 and the fourth unidirectional conduction unit 124 are not limited to include three MOS tubes, and the number of specific MOS tubes may be selected according to the output voltage of the power management module (5V, 3V, or 1.8V). That is, under normal working conditions, the voltage of the cascaded MOS tube series branch is turned on higher than the system power supply voltage to avoid the forward conduction of the MOS tube, and when the pulse of the reset signal POR has not been formed, multiple The MOS tube branch of the series connection provides a sub-threshold leakage path from the power supply to node A.
  • the number of MOS transistors in the third one-way conduction unit 123 and the fourth one-way conduction unit 124 is preferably 7-15.
  • the delay unit 13 includes:
  • first inverter 131 a first inverter 131, a second inverter 132, a third inverter 133;
  • the input end of the first inverter 131 is the input end of the delay unit 13
  • the output end of the first inverter 131 is connected to the input end of the second inverter 132
  • the output end of the second inverter is the third
  • the input of the inverter 133 is connected, and the output of the third inverter 133 is the output of the delay unit 13.
  • the number of the delay units 13 including the inverters is not limited to three, and may be set to any number as needed.
  • the power supply voltage VDDA starts to be powered on, and the C point voltage (power supply detection signal) follows VDDA rise, and when the voltage at point C reaches the threshold voltage of the first one-way conduction unit 111 and the second one-way conduction unit 112.
  • the first one-way conduction unit 111 and the second one-way conduction unit 112 are turned on, the capacitor C1 starts to be charged, and the voltage at the point A (following the control signal) follows the voltage at the point C.
  • the first switching unit 121 Before the voltage at point A rises to the threshold voltage of the second switching unit 122, after the power supply voltage VDDA starts to be powered on, the first switching unit 121 is turned on, and the voltage at point B (power following signal) follows the voltage at point C, when the power supply voltage VDDA When rising to the sum of the threshold voltages of the third one-way conduction unit 123 and the fourth one-way conduction unit 124, the third one-way conduction unit 123 and the fourth one-way conduction unit 124 are turned on, and the voltage at point B (power supply follow-up signal) Following the rise of the supply voltage VDDA to achieve good supply voltage follow-up, the follow-up tightness is greatly improved. And after the second switching unit 122 is turned on, since the on current is small, the power consumption is low.
  • the voltage at point A rises to the threshold voltage of the second switching unit 122
  • the voltage at point B rises to the highest, and is greater than the inversion voltage of the inverter, and the reset signal POR is at a low level, at which time the second switching unit 122 is turned on.
  • the voltage at point B (power supply follow-up signal) is rapidly pulled low, and a high-level reset signal POR is output through the first inverter 131, the second inverter 132, and the third inverter 133.
  • FIG. 7 and FIG. 8 show waveform changes of a part of signals in the circuit, wherein the curve 301 is a simulated schematic waveform of the power supply follow-up signal, and the curve 302 is a signal waveform of the voltage at point B passing through the first inverter, before the time t1,
  • the power supply voltage VDDA and the reset signal POR are both low.
  • the power supply starts to be powered up, and the power supply voltage VDDA gradually rises.
  • the power supply follow signal follows the power supply detection signal, that is, the voltage difference is kept small with the power supply voltage VDDA.
  • the power supply follow signal begins to closely follow the power supply voltage VDDA until the second switch unit 122 is turned on, and the power supply follow signal is rapidly dropped to the ground voltage.
  • the time of the power supply follow signal output can be adjusted by adjusting the size of the capacitor C1, and the output time of the reset signal can be adjusted by increasing the number of inverters to output a reset signal at the time when the power supply is completed.
  • False triggering ensures the reliability of the system, enabling power-on reset under low power supply voltage conditions, avoiding high power consumption caused by preventing flip-flops due to false triggering, and more suitable for low-power demand radio frequency identification. System, and only one switch is turned on after reset to achieve a low power reset.

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Abstract

本发明适用于射频领域，提供了一种无源射频识别上电复位电路及无源射频识别标签，所述电路包括：检测单元，用于对电源电压的幅值进行检测，输出电源检测信号和跟随控制信号；跟随控制单元，用于根据所述跟随控制信号生成跟随所述电源检测信号和所述电源电压的电源跟随信号；延时单元，用于对所述电源跟随信号进行延迟及去毛刺处理，生成复位信号。本发明在上电的过程中，通过使电源跟随信号紧紧跟随电源电压，有效抑制了假脉冲信号的产生，有效地避免了由于存在假脉冲信号而导致上电复位信号对系统的误触发，保证了系统的可靠性，并且在复位后仅有一个开关管导通，实现低功耗复位。

Description

一种无源射频识别上电复位电路及无源射频识别标签 技术领域
本发明属于射频领域，尤其涉及一种无源射频识别上电复位电路及无源射频识别标签。
 背景技术
射频识别（Radio Frequency Identification，RFID）是一种非接触式的自动识别技术，其可以应用于仓库管理、身份识别、交通运输、食品医疗、动物管理等多种领域，由于其广泛的应用，RFID技术在近年来越来越受到重视。
RFID标签主要分为无源标签和有源标签两种类型，无源式被动射频识别标签系统的能量来自读写器发射的射频能量，无须内置电源，通过天线接收到射频信号，在内部经过整流及稳压电路产生稳定的电源，在电源上电的过程中，上电复位电路检测并判断电源电压是否达到启动电压，当电源电压达到启动电压时输出复位信号，以对数字电路以及其他工作电路实现复位、启动。
图1所示为现有的上电复位电路的结构，包括N型MOS管M1、N型MOS管M2、电容C11、反相器NOT11、延迟器D11以及异或门XOR11；
其中，N型MOS管M1的栅极和漏极同时与电源电压VDDA连接，N型MOS管M1的源极与N型MOS管M2的漏极连接，N型MOS管M2的栅极与N型MOS管M2的漏极连接，N型MOS管M2的源极通过电容C11接地，N型MOS管M2与电容C11的连接点为节点J，N型MOS管M2的源极同时与反相器NOT11的输入端连接，反相器NOT11的输出端同时与延迟器D11的输入端、异或门XOR11的一端连接，反相器NOT11与延迟器D11、异或门XOR11的连接点为节点K1，延迟器D11的输出端与异或门XOR11的另一端连接，异或门XOR11的输出端为上电复位信号的输出端，用于输出复位信号。
在上述结构中，N型MOS管M1与N型MOS管M2形成了两个单向导通器件，当电源电压VDDA大于N型MOS管M1与N型MOS管M2的阈值电压之和时，N型MOS管M1和N型MOS管M2导通，电源电压VDDA对电容C11充电，电容C11的电压通过反向以及延迟处理后作为复位信号POR输出。
在动态快速上电过程中，由于反相器NOT11输出端，即节点K1的输出电压VK1因反相器NOT11输入端没有确定的电平驱动，因此电压VK1的变化延迟于电源电压VDDA的变化，即在上电瞬间节点K1的电压VK1不能很好的跟随电源电压VDDA，而始终与电源电压VDDA存在一定压差，详见图2中的信号波形，在图2中，S1为电源电压VDDA随时间变化的波形，S2为节点K1的电压VK1随时间变化的波形，S3为通过现有技术产生的复位信号POR随时间变化的波形。
在图2中可以明显看出，在电源电压VDDA已上升到高电平的临界值后，此时节点K1上的电压VK1依然还处于低电平的范围，此时经过反向、延迟后输出一个约为1.087V假脉冲复位信号FA，该假脉冲FA的幅值比较高，在电源电压VDDA为1.8V时，最高幅值可以达到1.3V，远高于数字电路以及其他工作电路中MOS管导通所需的阈值电压，从而导致系统在电源并没有上电完成时非正常启动，造成系统运行不稳定。
图3所示为现有另一种形式的上电复位电路的结构，包括P型MOS管M3、P型MOS管M4、P型MOS管M5、电容C12、反相器NOT12、延迟器D12以及异或门XOR12；
其中，P型MOS管M3的源极和P型MOS管M4的源极同时与电源电压VDDA连接，P型MOS管M3的栅极与其漏极连接，P型MOS管M3的漏极又与P型MOS管M5的源极连接，P型MOS管M5的栅极与其漏极同时接地，P型MOS管M4的栅极与P型MOS管M3的栅极连接，P型MOS管M4的漏极通过电容C12接地，P型MOS管M4的漏极还与反相器NOT12的输入端连接，反相器NOT12的输出端同时与延迟器D12的输入端、异或门XOR12的第二输入端连接，延迟器D12的输出端与异或门XOR12的第一输入端连接，异或门XOR12输出端为上电复位信号的输出端，用于输出复位信号。
上述结构中, P型MOS管M3和P型MOS管M4构成了对电容C12 充电的镜像电流源。充电后电容C12的电压通过反向以及延迟处理后作为复位信号POR输出。此处与第一个现有技术实例相比，仅仅是对延迟电容C12的充电方式稍有不同，在动态快速上电过程中，电源电压没有足够高，反相器NOT12的输入端是处于未被驱动的状态，因而没有确定的电平输入，导致反相器NOT12 的输出端不受输入端的控制电压，使得反相器NOT12 的输出电压没有确定的跟随电源电压，始终与电源电压存在一定的电压差，经过由反相器组成的延迟器D12以及异或门XOR12之后，最终产生了一个不期望出现的假脉冲信号。在图4中可以明显看出，波形S5即输出的复位信号POR同样有着短暂的不能跟随波形S4即复位电路输入的电源电压上升的问题，从而导致了假脉冲的产生。
由于现有的上电复位电路中，均具有上述的假脉冲信号，在VDDA为1.8V的情况下假脉冲信号的幅值变化范围通常在0.3V~1.5V之间，然而，在RFID系统中，经常出现由于忽略上述假脉冲而错误的触发数字电路，从而直接导致了射频识别标签的灵敏度降低，因此将上电翻转电平调高，无法在低电源电压条件下实现上电复位，功耗很大。
然而目前，随着RFID标签的低功耗需求，在极弱场条件下进入工作状态是射频标签产品的竞争性所在，而且深亚微米芯片制造工艺可以生产出阈值电压很低的数字逻辑器件，即意味着允许系统在很低的电源电压下完成数字逻辑功能。然而由于极弱场的缘故，低功耗的RFID系统中上电复位电压比传统的复位电压更低，在此情形下，现有的上电复位电路结构容易产生假脉冲，以导致系统由于被假脉冲触发而误进入工作模式的，而此时的电源并没有满足上电复位电路的触发条件，进而使得射频标签的灵敏度降低，甚至造成系统运行不稳定。
 技术问题
本发明实施例的目的在于提供一种无源射频识别上电复位电路，旨在解决上电复位时由于出现假脉冲信号而导致系统非正常复位的问题。
 技术解决方案
本发明实施例是这样实现的，一种无源射频识别上电复位电路，所述电路包括：
检测单元，所述检测单元的输入端与电源管理模块的输出端连接，用于对所述电源管理模块输出待测的电源电压的幅值进行检测，输出电源检测信号和跟随控制信号；
跟随控制单元，所述跟随控制单元的第一输入端与所述电源管理模块的输出端连接，所述跟随控制单元的第二输入端与所述检测单元的第一输出端连接，所述跟随控制单元的控制端与所述检测单元的第二输出端连接，用于根据所述跟随控制信号生成跟随所述电源检测信号和所述电源电压的电源跟随信号；
延时单元，所述延时单元的输入端与所述跟随控制单元的输出端连接，所述延时单元的输出端与数字电路连接，用于对所述电源跟随信号进行延迟及去毛刺处理，生成复位信号。
本发明实施例的另一目的在于提供一种采用上述无源射频识别上电复位电路的无源射频识别标签。
 有益效果
本发明实施例在上电的过程中，通过使电源跟随信号紧紧跟随电源电压，有效抑制了假脉冲信号的产生，进而有效地避免了由于存在假脉冲信号而导致上电复位信号对系统的误触发，保证了系统的可靠性，得以在低电源电压条件下有效实现上电复位，避免了因防止误触发而提高翻转电平导致的高功耗，更加适用于低功耗需求的射频识别系统，并且在复位后仅有一个开关管导通，实现低功耗复位。
 附图说明
图1为现有上电复位电路的一结构图；
图2为图1对应的上电复位电路的信号波形图；
图3为现有上电复位电路的另一结构图；
图4为图3对应的上电复位电路的信号波形图；
图5为本发明一实施例提供的无源射频识别上电复位电路的结构图；
图6为本发明一实施例提供的无源射频识别上电复位电路的示例电路结构图；
图7为本发明一实施例提供的无源射频识别上电复位电路的信号变化示意图；
图8 为图7中各个信号线展开图。
 本发明的最佳实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明实施例在上电的过程中，通过使电源跟随信号紧紧跟随电源电压，有效抑制了假脉冲信号的产生，保证了复位信号的可靠性。
图5示出本发明实施例提供的无源射频识别上电复位电路的结构，为了便于说明，仅示出了与本发明相关的部分。
作为本发明一实施例提供的无源射频识别上电复位电路1可以应用于各种无源射频识别标签4中，该无源射频识别上电复位电路1连接于电源提供单元2（例如：低压差线性稳压器low dropout regulator，LDO）与数字电路之间3，包括：
检测单元11，该检测单元11的输入端与无源射频识别标签中的电源管理模块的输出端，用于对电源管理模块2输出待测的电源电压VDDA的幅值进行检测，输出电源检测信号和跟随控制信号；
跟随控制单元12，该跟随控制单元的第一输入端与无源射频识别标签中电源管理模块2的输出端连接，跟随控制单元的第二输入端与检测单元11的第一输出端连接，跟随控制单元的控制端与检测单元11的第二输出端连接，用于根据跟随控制信号生成跟随电源检测信号和电源电压的电源跟随信号；
延时单元13，该延时单元13的输入端与跟随控制单元12的输出端连接，延时单元13的输出端与无源射频识别标签中的数字电路3连接，用于对电源跟随信号进行延迟及去毛刺处理，生成复位信号。
本发明实施例在上电的过程中，通过使电源跟随信号紧紧跟随电源电压，有效抑制了假脉冲信号的产生，进而有效地避免了由于存在假脉冲信号而导致上电复位信号对系统的误触发，保证了系统的可靠性，得以在低电源电压条件下有效实现上电复位，避免了因防止误触发而提高翻转电平导致的高功耗，更加适用于低功耗需求的射频识别系统，并且在复位后仅有一个开关管导通，实现低功耗复位。
以下结合具体实施例对本发明的实现进行详细说明。
图6示出本发明实施例提供的无源射频识别上电复位电路的示例电路结构，为了便于说明，仅示出了与本发明相关的部分。
作为本发明一实施例，检测单元11包括：
电阻R1、第一单向导通单元111、第二单向导通单元112以及电容C1；
电阻R1的一端为检测单元11的输入端，电阻R1的另一端为检测单元11的第一输出端与第一单向导通单元的输入端连接，第一单向导通单元111的输出端与第二单向导通单元112的输入端连接，第二单向导通单元112的输出端接地，电容C1的一端为检测单元11的第二输出端与第一单向导通单元的输出端连接，电容C1的另一端接地。
作为本发明一实施例，第一单向导通单元111和第二单向导通单元112均可以采用多个二极管串联实现，第一二极管D1的阳极为第一单向导通单元111的输入端，第一二极管D1的阴极与第二二极管D2的阳极连接，第二二极管D2的阴极与下一串联的二极管的阳极连接，依次类推，最后一个串联的二极管的阴极为第一单向导通单元111的输出端，第二单向导通单元112的多个二极管串联结构与第一单向导通单元111相同，此处不再赘述，而第一单向导通单元111和第二单向导通单元112所选取的串联的二极管的数量需保证避免二极管正向导通，并且使二极管亚阈值的漏电流调整适当，以保证节点A相对于电源的暂时跟随行为。
作为本发明一优选实施例，第一单向导通单元111和第二单向导通单元112还均可以采用多个二极管接法的MOS管串联实现，参考图6，以三个MOS管的串联结构为例，第一单向导通单元111包括：第十一P型MOS管M11、第十二P型MOS管M12和第十三P型MOS管M13；
其中第十一P型MOS管M11的源极为第一单向导通单元111的输入端，第十一P型MOS管M11的栅极与第十一P型MOS管M11的漏极连接，第十一P型MOS管M11的漏极又与第十二P型MOS管M12的源极连接，第十二P型MOS管M12的栅极与第十二P型MOS管M12的漏极连接，第十二P型MOS管M12的漏极又与第十三P型MOS管M13的源极连接，第十三P型MOS管M13的栅极与第十三P型MOS管M13的漏极连接，第十三P型MOS管M13的漏极为第一单向导通单元111的输出端。
第二单向导通单元112包括：第十四N型MOS管M14、第十五N型MOS管M15和第十六N型MOS管M16；
其中第十四N型MOS管M14的漏极为第二单向导通单元112的输入端，第十四N型MOS管M14的栅极与第十四N型MOS管M14的漏极连接，第十四N型MOS管M14的源极又与第十五N型MOS管M15的漏极连接，第十五N型MOS管M15的栅极与第十五N型MOS管M15的漏极连接，第十五N型MOS管M15的源极又与第十六N型MOS管M16的漏极连接，第十六N型MOS管M16的栅极与第十六N型MOS管M16的漏极连接，第十六N型MOS管M16的源极为第二单向导通单元112的输出端。
应当理解地，第一单向导通单元111和第二单向导通单元112不限于包括三个MOS管，具体MOS管数量可以根据电源管理模块的输出电压（5V、3V或1.8V）进行选取，即在正常的工作状态下，使叠加后MOS管串联支路的电压导通高于系统的电源电压，以避免MOS管发生正向导通，进而在复位信号POR的脉冲尚未形成的时候，多个串联接法的MOS管支路提供了电源到节点A的亚阈值漏电通道，只有皮安级，不到纳安级的电流，确保了复位信号POR的脉冲形成之前，节点A可以暂时跟随电源电压的升高而适当升高，从而避免了假脉冲信号的形成，即利用二极管或MOS管导通前的亚阈值态的漏电流消除假脉冲，以提高射频标签的灵敏度。
第一单向导通单元111以及第二单向导通单元112中MOS管的尺寸和数量比决定了对电容C1的充电电流大小、稳定后恒定直流电流的大小、以及稳定后的C1电容上电压的高低。从低功耗的角度考虑，第一单向导通单元111以及第二单向导通单元112中MOS管的数量均优选为7-15个。
跟随控制单元12包括：
第一开关单元121、第二开关单元122、第三单向导通单元123、第四单向导通单元124以及电阻R2；
第一开关单元121的输入端为跟随控制单元12的第二输入端，第一开关单元121的输出端与第二开关单元122的输入端连接，第二开关单元122的输出端接地，第一开关单元121的控制端通过电阻R2接地，第二开关单元122的控制端为跟随控制单元12的控制端，第三单向导通单元123的输入端为跟随控制单元12的第一输入端，第三单向导通单元123的输出端与第四单向导通单元124的输入端连接，第四单向导通单元124的输出端为跟随控制单元12的输出端，第四单向导通单元124的输出端与第二开关单元122的输入端连接。
作为本发明一实施例，第一开关单元121和第二开关单元122均可以采用多个串联的开关管实现，参考图6，以三个开关管的串联结构为例，第一开关单元121包括：第二十一开关管1211、第二十二开关管1212、第二十三开关管1213；
其中第二十一开关管1211的输入端为第一开关单元121的输入端，第二十一开关管1211的输出端与第二十二开关管1212的输入端连接，第二十二开关管1212的输出端与第二十三开关管1213的输入端连接，第二十三开关管1213的输出端为第一开关单元121的输出端，第二十一开关管1211的控制端、第二十二开关管1212的控制端、第二十三开关管1213的控制端连接同时为第一开关单元121的控制端。
作为本发明一实施例，第二十一开关管1211、第二十二开关管1212、第二十三开关管1213均可以采用PNP型三极管实现，该PNP型三极管的基极为第二十一开关管1211、第二十二开关管1212、第二十三开关管1213的控制端，PNP型三极管的发射极为第二十一开关管1211、第二十二开关管1212、第二十三开关管1213的输入端，PNP型三极管的集电极为第二十一开关管1211、第二十二开关管1212、第二十三开关管1213的输出端。
优选地，第二十一开关管1211、第二十二开关管1212、第二十三开关管1213还可以分别采用P型MOS管M21、P型MOS管M22、P型MOS管M23实现，该P型MOS管M21、M22、M23的栅极分别为第二十一开关管1211、第二十二开关管1212、第二十三开关管1213的控制端，P型MOS管M21、M22、M23的源极分别为第二十一开关管1211、第二十二开关管1212、第二十三开关管1213的输入端，P型MOS管M21、M22、M23的漏极分别为第二十一开关管1211、第二十二开关管1212、第二十三开关管1213的输出端。
第二开关单元122包括：第二十四开关管1221、第二十五开关管1222、第二十六开关管1223；
其中第二十四开关管1221的输入端为第二开关单元122的输入端，第二十四开关管1221的输出端与第二十五开关管1222的输入端连接，第二十五开关管1222的输出端与第二十六开关管1223的输入端连接，第二十六开关管1223的输出端为第二开关单元122的输出端，第二十四开关管1221的控制端、第二十五开关管1222的控制端、第二十六开关管1223的控制端连接同时为第二开关单元122的控制端。
作为本发明一实施例，第二十四开关管1221、第二十五开关管1222、第二十六开关管1223均可以采用NPN型三极管实现，该NPN型三极管的基极为第二十四开关管1221、第二十五开关管1222、第二十六开关管1223的控制端，NPN型三极管的集电极为第二十四开关管1221、第二十五开关管1222、第二十六开关管1223的输入端，NPN型三极管的发射极为第二十四开关管1221、第二十五开关管1222、第二十六开关管1223的输出端。
优选地，第二十四开关管1221、第二十五开关管1222、第二十六开关管1223还可以分别采用N型MOS管M24、N型MOS管M25、N型MOS管M26实现，该N型MOS管M24、M25、M26的栅极分别为第二十四开关管1221、第二十五开关管1222、第二十六开关管1223的控制端，N型MOS管M24、M25、M26的漏极分别为第二十四开关管1221、第二十五开关管1222、第二十六开关管1223的输入端，N型MOS管M24、M25、M26的漏极分别为第二十四开关管1221、第二十五开关管1222、第二十六开关管1223的输出端。
作为本发明一实施例，第三单向导通单元123、第四单向导通单元124均可以采用多个二极管串联实现，第四二极管D4的阳极为第三单向导通单元123的输入端，第四二极管D4的阴极与第五二极管D5的阳极连接，第五二极管D5的阴极与下一串联的二极管的阳极连接，依次类推，最后一个串联的二极管的阴极为第三单向导通单元123的输出端，第四单向导通单元124的多个二极管串联结构与第三单向导通单元123相同，此处不再赘述，而第三单向导通单元123、第四单向导通单元124所选取的串联的二极管的数量需保证避免二极管正向导通，并且使二极管亚阈值的漏电流调整适当，以保证节点B相对于电源的暂时跟随行为。
作为本发明一优选实施例，第三单向导通单元123、第四单向导通单元124还均可以采用多个二极管接法的MOS管串联实现，参考图6，以三个MOS管的串联结构为例，第三单向导通单元123包括：第三十一P型MOS管M31、第三十二P型MOS管M32和第三十三P型MOS管M33；
其中第三十一P型MOS管M31的源极为第三单向导通单元123的输入端，第三十一P型MOS管M31的栅极与第三十一P型MOS管M31的漏极连接，第三十一P型MOS管M31的漏极又与第三十二P型MOS管M32的源极连接，第三十二P型MOS管M32的栅极与第三十二P型MOS管M32的漏极连接，第三十二P型MOS管M32的漏极又与第三十三P型MOS管M33的源极连接，第三十三P型MOS管M33的栅极与第三十三P型MOS管M33的漏极连接，第三十三P型MOS管M33的漏极为第三单向导通单元123的输出端。
第四单向导通单元124包括：第三十四P型MOS管M34、第三十五P型MOS管M35和第三十六P型MOS管M36；
其中第三十四P型MOS管M34的源极为第四单向导通单元124的输入端，第三十四P型MOS管M34的栅极与第三十四P型MOS管M34的漏极连接，第三十四P型MOS管M34的漏极又与第三十五P型MOS管M35的源极连接，第三十五P型MOS管M35的栅极与第三十五P型MOS管M35的漏极连接，第三十五P型MOS管M35的漏极又与第三十六P型MOS管M36的源极连接，第三十六P型MOS管M36的栅极与第三十六P型MOS管M36的漏极连接，第三十六P型MOS管M36的漏极为第四单向导通单元124的输出端。
应当理解地，第三单向导通单元123、第四单向导通单元124不限于包括三个MOS管，具体MOS管数量可以根据电源管理模块的输出电压（5V、3V或1.8V）进行选取，即在正常的工作状态下，使叠加后MOS管串联支路的电压导通高于系统的电源电压，以避免MOS管发生正向导通，进而在复位信号POR的脉冲尚未形成的时候，多个串联接法的MOS管支路提供了电源到节点A的亚阈值漏电通道，只有皮安级，不到纳安级的电流，确保了复位信号POR的脉冲形成之前，节点B可以暂时跟随电源电压的升高而适当升高，从而避免了假脉冲信号的形成，即利用二极管或MOS管导通前的亚阈值态的漏电流消除假脉冲，以提高射频标签的灵敏度。从低功耗的角度考虑，第三单向导通单元123、第四单向导通单元124中MOS管的数量均优选为7-15个。
延时单元13包括：
第一反相器131、第二反相器132、第三反相器133；
第一反相器131的输入端为延时单元13的输入端，第一反相器131的输出端与第二反相器132的输入端连接，第二反向器的输出端与第三反相器133的输入端连接，第三反相器133的输出端为延时单元13的输出端。
可以理解，延时单元13包括反相器的数量并不限定为三个，可以根据需要设置为任意多个。
在本发明实施例中，电源电压VDDA开始上电，C点电压（电源检测信号）跟随VDDA上升，当C点电压达到第一单向导通单元111和第二单向导通单元112的阈值电压之和时，第一单向导通单元111和第二单向导通单元112导通，电容C1开始充电，A点电压（跟随控制信号）跟随C点电压上升。
在A点电压上升到第二开关单元122的阈值电压之前，电源电压VDDA开始上电后，第一开关单元121导通，B点电压（电源跟随信号）跟随C点电压上升，当电源电压VDDA上升到第三单向导通单元123、第四单向导通单元124的阈值电压之和时，第三单向导通单元123、第四单向导通单元124导通，B点电压（电源跟随信号）跟随电源电压VDDA上升，以实现良好的电源电压跟随，大幅提高了跟随紧密性。并且在第二开关单元122导通后，由于导通电流很小，所以功耗很低。
在A点电压上升到第二开关单元122的阈值电压时，B点电压升到最高，并且大于反相器的翻转电压，复位信号POR为低电平，此时第二开关单元122导通，B点电压（电源跟随信号）迅速被拉低，并通过第一反相器131、第二反相器132、第三反相器133输出高电平的复位信号POR。
图7和图8示出了电路中部分信号的波形变化，其中，曲线301为电源跟随信号的仿真示意波形，曲线302为B点电压经过第一反相器的信号波形，在t1时刻以前，电源电压VDDA和复位信号POR均为低电平，在t1时刻，电源开始上电，电源电压VDDA逐渐升高，此时，电源跟随信号跟随电源检测信号，即与电源电压VDDA保持较小压差的跟随，在t2时刻，电源继续上电，第三单向导通单元123、第四单向导通单元124、第五单向导通器件125、第六单向导通器件126、第七单向导通器件127和第八单向导通器件128导通，结合图6，电源跟随信号开始紧紧跟随电源电压VDDA，直到t3时刻，第二开关单元122导通后，电源跟随信号迅速下降为地电压，同时经过第一反相器131的信号从低电平跳变为高电平，并经过第二反相器132、第三反相器133的延时后，于t4时刻输出高电平的复位信号，电源也完成上电。
在本发明实施例中，可以通过调节电容C1的大小来调节电源跟随信号输出的时间，以及通过增加反相器的数量调节复位信号的输出时间，以实现在电源上电完成的时刻输出复位信号。
本发明实施例在上电的过程中，通过使电源跟随信号紧紧跟随电源电压，有效抑制了假脉冲信号的产生，进而有效地避免了由于存在假脉冲信号而导致上电复位信号对系统的误触发，保证了系统的可靠性，得以在低电源电压条件下有效实现上电复位，避免了因防止误触发而提高翻转电平导致的高功耗，更加适用于低功耗需求的射频识别系统，并且在复位后仅有一个开关管导通，实现低功耗复位。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种无源射频识别上电复位电路，其特征在于，所述电路包括：
    检测单元，所述检测单元的输入端与电源管理模块的输出端连接，用于对所述电源管理模块输出待测的电源电压的幅值进行检测，输出电源检测信号和跟随控制信号；
    跟随控制单元，所述跟随控制单元的第一输入端与所述电源管理模块的输出端连接，所述跟随控制单元的第二输入端与所述检测单元的第一输出端连接，所述跟随控制单元的控制端与所述检测单元的第二输出端连接，用于根据所述跟随控制信号生成跟随所述电源检测信号和所述电源电压的电源跟随信号；
    延时单元，所述延时单元的输入端与所述跟随控制单元的输出端连接，所述延时单元的输出端与数字电路连接，用于对所述电源跟随信号进行延迟及去毛刺处理，生成复位信号。
  2. 如权利要求1所述的电路，其特征在于，所述检测单元包括：
    电阻R1、第一单向导通单元、第二单向导通单元以及电容C1；
    所述电阻R1的一端为所述检测单元的输入端，所述电阻R1的另一端为所述检测单元的第一输出端与所述第一单向导通单元的输入端连接，所述第一单向导通单元的输出端与第二单向导通单元的输入端连接，第二单向导通单元的输出端接地，所述电容C1的一端为所述检测单元的第二输出端与所述第一单向导通单元的输出端连接，所述电容C1的另一端接地。
  3. 如权利要求2所述的电路，其特征在于，所述第一单向导通单元包括：第十一P型MOS管、第十二P型MOS管和第十三P型MOS管；
    所述第十一P型MOS管的源极为所述第一单向导通单元的输入端，所述第十一P型MOS管的栅极与所述第十一P型MOS管的漏极连接，所述第十一P型MOS管的漏极又与所述第十二P型MOS管的源极连接，所述第十二P型MOS管的栅极与所述第十二P型MOS管的漏极连接，所述第十二P型MOS管的漏极又与所述第十三P型MOS管的源极连接，所述第十三P型MOS管的栅极与所述第十三P型MOS管的漏极连接，所述第十三P型MOS管的漏极为所述第一单向导通单元的输出端。
  4. 如权利要求2所述的电路，其特征在于，所述第二单向导通单元包括：第十四N型MOS管、第十五N型MOS管和第十六N型MOS管；
    所述第十四N型MOS管的漏极为所述第二单向导通单元的输入端，所述第十四N型MOS管的栅极与所述第十四N型MOS管的漏极连接，所述第十四N型MOS管的源极又与所述第十五N型MOS管的漏极连接，所述第十五N型MOS管的栅极与所述第十五N型MOS管的漏极连接，所述第十五N型MOS管的源极又与所述第十六N型MOS管的漏极连接，所述第十六N型MOS管的栅极与所述第十六N型MOS管的漏极连接，所述第十六N型MOS管的源极为所述第二单向导通单元的输出端。
  5. 如权利要求1所述的电路，其特征在于，所述跟随控制单元包括：
    第一开关单元、第二开关单元、第三单向导通单元、第四单向导通单元以及电阻R2；
    所述第一开关单元的输入端为所述跟随控制单元的第二输入端，所述第一开关单元的输出端与所述第二开关单元的输入端连接，所述第二开关单元的输出端接地，第一开关单元的控制端通过所述电阻R2接地，所述第二开关单元的控制端为所述跟随控制单元的控制端，所述第三单向导通单元的输入端为所述跟随控制单元的第一输入端，所述第三单向导通单元的输出端与所述第四单向导通单元的输入端连接，所述第四单向导通单元的输出端为所述跟随控制单元的输出端，所述第四单向导通单元的输出端与所述第二开关单元的输入端连接。
  6. 如权利要求5所述的电路，其特征在于，所述第一开关单元包括：第二十一开关管、第二十二开关管、第二十三开关管；
    所述第二十一开关管的输入端为所述第一开关单元的输入端，所述第二十一开关管的输出端与所述第二十二开关管的输入端连接，所述第二十二开关管的输出端与所述第二十三开关管的输入端连接，所述第二十三开关管的输出端为所述第一开关单元的输出端，所述第二十一开关管的控制端、所述第二十二开关管的控制端以及所述第二十三开关管的控制端连接且同时为所述第一开关单元的控制端；
    所述第二开关单元包括：第二十四开关管、第二十五开关管、第二十六开关管；
    所述第二十四开关管的输入端为所述第二开关单元的输入端，所述第二十四开关管的输出端与所述第二十五开关管的输入端连接，所述第二十五开关管的输出端与所述第二十六开关管的输入端连接，所述第二十六开关管的输出端为所述第二开关单元的输出端，所述第二十四开关管的控制端、所述第二十五开关管的控制端、所述第二十六开关管的控制端连接同时为所述第二开关单元的控制端。
  7. 如权利要求6所述的电路，其特征在于，所述第二十一开关管、所述第二十二开关管、所述第二十三开关管分别为P型MOS管M21、P型MOS管M22、P型MOS管M23，所述P型MOS管M21、所述P型MOS管M22、所述P型MOS管M23的栅极分别为所述第二十一开关管、所述第二十二开关管、所述第二十三开关管的控制端，所述P型MOS管M21、所述P型MOS管M22、所述P型MOS管M23的源极分别为所述第二十一开关管、所述第二十二开关管、所述第二十三开关管的输入端，所述P型MOS管M21、所述P型MOS管M22、所述P型MOS管M23的漏极分别为所述第二十一开关管、所述第二十二开关管、所述第二十三开关管的输出端；
    所述第二十四开关管、所述第二十五开关管、所述第二十六开关管分别为N型MOS管M24、N型MOS管M25、N型MOS管M26实现，所述N型MOS管M24、所述N型MOS管M25、所述N型MOS管M26的栅极分别为所述第二十四开关管、所述第二十五开关管、所述第二十六开关管的控制端，所述N型MOS管M24、所述N型MOS管M25、所述N型MOS管M26的漏极分别为所述第二十四开关管、所述第二十五开关管、所述第二十六开关管的输入端，所述N型MOS管M24、所述N型MOS管M25、所述N型MOS管M26的漏极分别为所述第二十四开关管、所述第二十五开关管、所述第二十六开关管的输出端。
  8. 如权利要求5所述的电路，其特征在于，所述第三单向导通单元包括：第三十一P型MOS管、第三十二P型MOS管和第三十三P型MOS管；
    所述第三十一P型MOS管的源极为所述第三单向导通单元的输入端，所述第三十一P型MOS管的栅极与所述第三十一P型MOS管的漏极连接，所述第三十一P型MOS管的漏极又与所述第三十二P型MOS管的源极连接，所述第三十二P型MOS管的栅极与所述第三十二P型MOS管的漏极连接，所述第三十二P型MOS管的漏极又与所述第三十三P型MOS管的源极连接，所述第三十三P型MOS管的栅极与所述第三十三P型MOS管的漏极连接，所述第三十三P型MOS管的漏极为所述第三单向导通单元的输出端；
    所述第四单向导通单元包括：第三十四P型MOS管、第三十五P型MOS管和第三十六P型MOS管；
    所述第三十四P型MOS管的源极为所述第四单向导通单元的输入端，所述第三十四P型MOS管的栅极与所述第三十四P型MOS管的漏极连接，所述第三十四P型MOS管的漏极又与所述第三十五P型MOS管的源极连接，所述第三十五P型MOS管的栅极与所述第三十五P型MOS管的漏极连接，所述第三十五P型MOS管的漏极又与所述第三十六P型MOS管的源极连接，所述第三十六P型MOS管的栅极与所述第三十六P型MOS管的漏极连接，所述第三十六P型MOS管的漏极为所述第四单向导通单元的输出端。
  9. 如权利要求1所述的电路，其特征在于，所述延时单元包括：
    第一反相器、第二反相器、第三反相器；
    所述第一反相器的输入端为所述延时单元的输入端，所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反向器的输出端与所述第三反相器的输入端连接，所述第三反相器的输出端为所述延时单元的输出端。
  10. 一种无源射频识别标签，其特征在于，所述无源射频识别标签中的无源射频识别上电复位电路为如权利要求1至9任一项所述的电路。
PCT/CN2013/073881 2012-05-08 2013-04-08 一种无源射频识别上电复位电路及无源射频识别标签 WO2013166895A1 (zh)

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