WO2013139148A1

WO2013139148A1 - Array substrate and manufacturing method thereof, and display device

Info

Publication number: WO2013139148A1
Application number: PCT/CN2012/086215
Authority: WO
Inventors: 朱佩誉; 牛菁
Original assignee: 京东方科技集团股份有限公司
Priority date: 2012-03-19
Filing date: 2012-12-07
Publication date: 2013-09-26
Also published as: CN102655156A; CN102655156B

Abstract

An array substrate and a manufacturing method thereof, and a display device. The array substrate (20) comprises: a substrate (209); a gate line (201) and a data line (202) that are arranged on the substrate (209) and crossed with each other; and a thin-film transistor (204) and a pixel electrode (203) that are arranged in a pixel unit defined by the gate line (201) and the data line (202). A gate (205) of the thin-film transistor (204) is connected to the gate line (201), a source (206) of the thin-film transistor (204) is connected to the data line (202), and a drain (207) of the thin-film transistor (204) is connected to the pixel electrode (203); and the thickness of the gate (205) of the thin-film transistor (204) in an area opposite to the drain (207) is smaller than the thickness of the gate (205) of the thin-film transistor (204) in an area opposite to a channel of the thin-film transistor (204).

Description

Array substrate, manufacturing method thereof and display device

5 Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique

Referring to the top view of the array substrate shown in FIG. 1 and the cross-sectional view in the AA direction shown in FIG. 2, the array substrate 10 of the prior art has a structure in which a vertical cross-over gate 10 line and data are formed on the transparent substrate 109. a thin film transistor 104 and a pixel electrode 103 are disposed in the pixel unit defined by the gate line and the data line; wherein the thin film transistor 104 includes: a gate electrode 105, a source electrode 106 and a drain electrode 107, and the drain electrode 107 passes through The hole and the pixel electrode 103 are electrically connected. As can be seen from a top view, the gate 105 and the drain 107 have overlapping regions, which generate a parasitic capacitance C _gd . Since the drain 107 has a capacitive coupling effect with the C _{gd of the} gate 105, an induced voltage AV is generated:

AV=V *C / (C +C + C )

i ~> a gd gd st LC

Where ν _α is the amplitude of the pulse voltage of the drive array substrate applied to the gate line bus, and ^G _st is the storage capacitor.

The appearance of the induced voltage causes the asymmetry of the driving voltage, resulting in fluctuations in the light transmittance, causing low-frequency brightness changes and avatar jitter, that is, flicker. In order to reduce the influence of the induced voltage, a larger storage capacitor C _st is usually used for 0, but a conventional method of increasing the storage capacitor C _st , such as increasing the area of the storage capacitor, causes the aperture ratio to decrease. In addition, although it can be seen from the above formula that the parasitic capacitance can be reduced, the induced voltage can be reduced. However, since the specification of the thin film transistor is relatively strict in the prior art, it is difficult to realize the design of reducing the parasitic capacitance by changing the overlap area. 5 Summary of the content

An embodiment of the present invention provides an array substrate, including: a substrate; gate lines and data lines crossing each other disposed on the substrate; a thin film transistor and a pixel electrode disposed on the gate line and the data line a pixel unit, wherein a gate of the thin film transistor is connected to the gate line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor is connected to the pixel electrode; And wherein the thickness of the gate of the thin film transistor is in a region facing the drain The thickness is smaller than the thickness of the region facing the channel of the thin film transistor.

Another embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a gate metal film on a substrate, patterning the gate metal film by a patterning process to form a gate metal layer; and forming a gate metal layer a gate insulating layer, an active layer, a source/drain metal layer and a common electrode line are formed on the substrate, wherein the gate metal layer comprises a gate line and a gate, and the source/drain metal layer comprises a source, a drain and a data line, The gate, the active layer, the source, and the drain constitute a thin film transistor, and wherein a thickness ratio of the gate in a region facing the drain is in a trench with the thin film transistor The thickness of the area where the road is facing is small.

Still another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a schematic structural view of an array substrate provided in the prior art;

2 is a schematic cross-sectional structural view of an array substrate provided in the prior art;

3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

4 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional view of another array substrate according to an embodiment of the present invention; FIG. 7 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present invention; FIG. A flowchart of a method for fabricating an array substrate; and FIG. 9 is a flowchart of still another method for fabricating an array substrate according to an embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. Based on the described embodiments of the present invention, those of ordinary skill in the art can obtain without the need for creative labor. All other embodiments obtained are within the scope of the invention.

An array substrate provided by an embodiment of the present invention, for example, the array substrate 20 shown in FIG. 3, the source 206 of the thin film transistor 204 of the substrate has an arc shape, and the drain 207 is viewed from a top view. One end is on the centripetal side of the curved source 206. The array substrate 20 includes a substrate (e.g., a transparent substrate). A gate line 201 and a data line 202 which are vertically and horizontally intersected are disposed on the substrate. A thin film transistor 204 and a pixel electrode 203 are disposed in the pixel unit defined by the gate line 201 and the data line 202. The gate 205 of the thin film transistor 204 is connected to the gate line 201, the source 206 is connected to the data line 202, and the drain 207 is connected to the pixel electrode 203. The thickness of the gate electrode 205 of the thin film transistor 204 in a region facing the drain electrode 207 is smaller than the thickness of a region facing the channel of the thin film transistor 204.

In order to clearly describe the structure in which the thickness of the gate electrode 205 of the thin film transistor 204 in the region facing the drain 207 is smaller than the thickness of the region facing the channel of the thin film transistor 204, reference may be made to FIG. 3 along the BB direction. Cut section view. As shown in Fig. 4, the thickness of the gate electrode 205 in the region facing the drain electrode 207 is smaller than that of the other regions, and exhibits a concave structure.

Optionally, on the basis of reducing the thickness of the gate in a region facing the drain, the thickness of the gate of the thin film transistor in a region facing the source may be further reduced, so that the gate of the thin film transistor The thickness of the pole in the region facing the source is smaller than the thickness in the region facing the channel of the thin film transistor. This not only increases the distance between the gate and the drain but also increases the distance between the gate and the source, and can reduce the parasitic capacitance of the drain and the gate, thereby also reducing the induced voltage. Further, the thickness of the source may be equal to the thickness of the drain.

Optionally, as shown in FIG. 3 and FIG. 4, the common electrode line 302 is further formed on the array substrate 20 provided by the embodiment of the present invention, and the common electrode line 302 is disposed in the same layer as the data line 202, and between the two Electrically insulated from each other. In this way, the two plates (the common electrode line and the pixel electrode) of the storage capacitor are separated by only one protective layer. Compared with the prior art, the two insulating plates are separated by a gate insulating layer and a protective layer. The distance between the storage capacitors is reduced, thereby increasing the storage capacitance, further reducing the induced voltage, improving screen flicker, and improving product quality. In order to ensure electrical insulation between the common electrode line and the data line set in the same layer, the common electrode line and the data line can be arranged in parallel, so that the arrangement of multiple via holes can be avoided relative to other setting modes, and the process is simplified.

Further, an active layer portion pattern may be formed under the common electrode line 302, and the active layer portion pattern supports the common electrode line, and the common electrode line and the pixel may be further reduced. The distance between the electrodes. Optionally, the active layer portion pattern coincides with the shape of the common electrode line.

An embodiment of the present invention provides an array substrate in which a thickness of a gate of a thin film transistor in a region facing the drain is smaller than a thickness of a region facing the channel of the thin film transistor, compared to the prior art. In addition, the distance between the gate and the drain is increased, and the parasitic capacitance generated by the overlap region of the gate and the drain can be reduced, thereby reducing the induced voltage, thereby improving the screen flicker and improving the screen display of the product. quality. Further, the common electrode line is disposed in the same layer as the data line, and has no electrical connection, which can reduce the distance between the common electrode line and the pixel electrode, increase the storage capacitance, and reduce the induced voltage, thereby improving The screen flickers to improve the quality of the product screen display.

The embodiment of the present invention further provides an array substrate, exemplarily, the array substrate 20 shown in FIG. 5. The source 206 and the drain 207 of the thin film transistor 204 may also have a rectangular shape when viewed from above. The array substrate 20 includes a substrate (e.g., a transparent substrate). A gate line 201 and a data line 202 which are vertically and horizontally intersected are disposed on the substrate. A thin film transistor 204 and a pixel electrode 203 are disposed in the pixel unit defined by the gate line 201 and the data line 202. The gate 205 of the thin film transistor 204 is connected to the gate line 205 and the gate line 201, the source 206 is connected to the data line 202, and the drain 207 is connected to the pixel electrode 203. The thickness of the gate electrode 205 of the thin film transistor 204 in a region facing the drain electrode 207 is smaller than the thickness of a region facing the channel of the thin film transistor 204, as shown in Fig. 6.

A cross-sectional view taken along the BB direction of the array substrate shown in FIG. 5, that is, as shown in FIG. 6, can reduce the thickness of the gate 205 in the region facing the drain 207, and further reduce the gate 205. The thickness of the region facing the source 206 is such that the thickness of the gate of the thin film transistor in a region facing the source is smaller than the thickness of a region facing the channel of the thin film transistor. This not only increases the distance between the gate and the drain but also increases the distance between the gate and the source, so that the parasitic capacitance C _gd decreases and c _gs also decreases, thereby further reducing the parasitic capacitance. The induced voltage is reduced, the screen flicker is improved, and the display quality of the product screen is improved.

On the array substrate shown in FIGS. 5 and 6 above, the common electrode line remains in conformity with the position in the prior art. Referring to the position of the common electrode line described in the previous embodiment, in the embodiment of the present invention, the common electrode line may also be disposed in the same layer as the data line, and electrically insulated between the two. In this way, the two plates (the common electrode line and the pixel electrode) of the storage capacitor are separated by only one protective layer. Compared with the prior art, the two insulating plates are separated by a gate insulating layer and a protective layer. The distance between the storage capacitors is reduced, thereby increasing the storage capacitance, reducing the induced voltage, improving screen flicker, and improving product quality. In order to ensure electrical insulation between the common electrode line and the data line set in the same layer, public electricity can be used. The pole line is arranged in parallel with the data line, and the data line and the common electrode line can be simultaneously formed by one photolithography process, which simplifies the process.

Further, an active layer portion pattern may be formed under the common electrode line, and the active layer portion pattern supports the common electrode line to further reduce the distance between the common electrode and the pixel electrode, thereby increasing the storage capacitance Reduce the induced voltage. Alternatively, the active layer portion pattern coincides with the shape of the common electrode line. 5 and FIG. 6 only describe the improvement on the gate. For other structures of the array substrate provided according to the embodiment, reference may be made to the description of the above embodiments (for example, FIG. 3 and FIG. 4), and details are not described herein again. .

An embodiment of the present invention provides an array substrate in which a thickness of a gate of a thin film transistor in a region facing the drain is smaller than a thickness of a region facing the channel of the thin film transistor, compared to the prior art. In addition, the distance between the gate and the drain is increased, and the parasitic capacitance generated by the overlap region of the gate and the drain can be reduced, thereby reducing the induced voltage, thereby improving the screen flicker and improving the product quality.

A method for fabricating an array substrate according to an embodiment of the present invention, as shown in FIG. 7, includes: S401, forming a gate metal film on a substrate (for example, a transparent substrate), and patterning the gate metal film by a patterning process a gate metal layer; the gate metal layer includes: a gate line, and a gate having a region opposite to the drain and having a smaller thickness than a region facing the channel.

This increases the distance between the gate and the drain compared to the prior art, and can reduce the parasitic capacitance generated by the overlapping regions of the gate and the drain, thereby reducing the induced voltage and improving the screen. Blinking, improving product quality.

S402, sequentially forming a gate insulating layer, an active layer, a source/drain metal layer, a protective layer, and a pixel electrode layer on the transparent substrate on which the gate metal layer is formed.

Preferably, the process of forming the active layer and the source/drain metal layer is specifically: forming a semiconductor film and a source/drain metal film on a transparent substrate on which a gate insulating layer is formed, and the semiconductor is patterned by a single mask patterning process. The thin film and the source/drain metal film are patterned to form an active layer and a source/drain metal layer; the source/drain metal layer includes: a data line, a source and a drain of the thin film transistor, and a common electrode line. The common electrode line and the data line are electrically insulated from each other. Since the common electrode line and the pixel electrode are separated by only one protective layer, the distance between the common electrode line and the pixel electrode is reduced as compared with the prior art, and the storage capacitance is increased, thereby further reducing on the basis of step S401. Induced voltage.

Next, for the array substrate shown in Fig. 3 (or Fig. 4), as shown in Fig. 8, a manufacturing method thereof will be provided. A gate metal film is deposited on the substrate (for example, a transparent substrate) by sputtering, and the material of the metal film may be molybdenum, titanium, chromium, aluminum, aluminum germanium or a combination thereof. Secondly, after the photoresist is coated, the transparent substrate is subjected to a halftone or gray tone mask half exposure, and after development, the photoresist shown in FIG. 8(a) is in an IHJ-like structure (including a photoresist completely removed region). , the photoresist partially retained area and the photoresist completely reserved area). The photoresist completely removed region includes a region outside the region where the gate metal layer is to be formed, the photoresist portion remaining region corresponds to a region corresponding to the gate and the drain, and the photoresist completely reserved region corresponds to the other region i or.

The gate metal film (corresponding to the gate metal film of the photoresist completely removed region) which is not covered by the photoresist is etched away by a wet etching process to obtain the structure shown in Fig. 8(b).

The photoresist is ashed, and the photoresist at the thinner position (retained portion of the photoresist portion) is completely ashed, and the underlying metal film is exposed, as shown in Fig. 8(c).

The exposed gate metal film is wet-etched to obtain the structure of Fig. 8 (d).

The photoresist is stripped to obtain a patterned gate metal layer, and the gate metal layer includes: a gate of the thin film transistor, as shown in FIG. 8(e). In this step, a gate line can also be formed together with the gate electrode. For example, the gate line may have the same thickness as at the thicker portion of the gate.

On the surface of the substrate on which the gate insulating layer 300 is deposited, a semiconductor film (the material is a semiconductor and a doped semiconductor) and a source/drain metal film are sequentially deposited, a photoresist is applied, and then a second exposure is performed. In this process, first, after exposure and development using a gray tone mask or a halftone mask, the source/drain metal film is first etched, and then the photoresist is ashed to remove the light corresponding to the channel region. After etching, the active layer is etched, and then a second source/drain metal film is etched, the source and drain metal layers in the trench are engraved, and the active layer at the channel of the array substrate is etched. The semiconductor doped layer is removed, and the patterned active layer, the data line, the source 206 and the drain 207 of the thin film transistor, and the common electrode line 302 are obtained after stripping the photoresist, as shown in FIG. 8(f). The common electrode line 302 is arranged in parallel with the data line. Since when the data line and the common electrode line are disposed in the same layer, if the arrangement direction of the common electrode line is the same as the original technology, that is, perpendicular to the data line, in order to avoid short circuit between the data line and the common electrode line, it is necessary to make a discontinuous setting. The common electrode line, each of the common electrode lines needs to be connected in series with each other. This structure requires that a via hole be provided on the protective layer at a position corresponding to both ends of each small common electrode line. In order to simplify the process, it is preferable in the embodiment of the present invention to arrange the common electrode lines in parallel with the data lines, thereby avoiding a manufacturing process of providing a plurality of via holes.

Subsequently, the protective layer is continuously deposited, exposed through a mask, and then etched after development to be disposed thereon. The via hole whose drain is connected to the pixel electrode is as shown in Fig. 8(g), and since all the drawings in Fig. 8 are based on the cross section in the BB direction in Fig. 3, Fig. 8 (g) The via holes formed in the ) are not identified, but those skilled in the art can unambiguously determine the position of the via holes according to the structure diagram shown in FIG.

After the protective layer having via holes is formed, patterning of the pixel electrodes is performed, as shown in FIG. 8(h), for example, depositing a transparent conductive layer on the protective layer, the conductive layer may be indium tin oxide ITO, The conductive layer is subjected to mask exposure, and after development and etching, a patterned pixel electrode is obtained. The pixel electrode portion covers the common electrode line, and the overlapping portion of the front projection portion is the storage capacitor covering position. Since the active layer portion pattern is formed under the common electrode line, the distance between the common electrode line and the pixel electrode is reduced, thereby increasing the storage capacitance, further reducing the induced voltage, improving the screen flicker, and improving product quality.

Next, the array substrate shown in Fig. 5 (or Fig. 6) is provided as shown in Fig. 9, and its manufacturing method is provided. As shown in Fig. 9 (a), a gate metal film and a photoresist are deposited on the transparent substrate 209.

As shown in Fig. 9(b), for example, a halftone mask or a gray tone mask is used to expose the photoresist, and a photoresist having a convex structure is obtained after development.

As shown in Fig. 9(c), the metal not covered by the photoresist is etched by wet etching.

As shown in Fig. 9(d), the photoresist is ashed into the dry etching apparatus to expose a part of the gate metal film.

As shown in Fig. 9(e), a part of the metal of the exposed gate metal film is etched away by dry etching, and the photoresist is removed to form a stepped gate electrode 205, as shown in Fig. 9(f).

As shown in Fig. 9(g), a gate insulating layer 301, a semiconductor film 208 (which may include a semiconductor and a doped semiconductor film), and a negative photoresist are deposited on the gate electrode.

The gate is used as a photomask, and self-aligned exposure is applied from the back surface of the substrate (the light is incident from the bottom to the top as shown in FIG. 9(g)), developed, and then dry-etched to form the active layer 208. . The self-aligned exposure refers to a process in which light is incident from the back surface of the array substrate with a gate metal as a mask, and the photoresist used is a negative photoresist when self-aligned exposure is used. . According to Fig. 9 (h), the light incident direction is the bottom-up exposure. Thus, the pattern of the gate can be used as a pattern of the mask, and the pattern of the active layer can be formed without using an additional mask, and the mask can be saved. Moreover, since this back exposure process can make a pattern consistent with the gate without calibrating the position of the mask, such a back exposure process can be referred to as a self-alignment process. The photoresist is removed to form the structure shown in Fig. 9(i).

As shown in FIG. 9(j), a source-drain metal film is deposited on the active layer, and the metal in the surrounding and the channel is first etched by wet etching through a third patterning process, and is engraved by dry etching. The doped semiconductor in the channel is etched away to form source and drain electrodes 206, 207 and the channel. Thereafter, a protective layer 300 is deposited, and via holes are formed by the fourth patterning process. Finally, a transparent conductive film is deposited, and the pixel electrode 203 is formed by the fifth patterning process.

In this way, the stepped gate formed increases the distance between the gate and the drain, and between the gate and the source, so that the parasitic capacitance C _gd decreases and the C _gs also decreases, which can be further reduced. Parasitic capacitance, which reduces the effect of screen flicker. In addition, the active layer is separately prepared from the source and drain electrodes, and the gate electrode is used as a mask to back-expose the active layer. Such a patterning process can obtain an active layer that is completely blocked by the gate, thereby avoiding active under the influence of the backlight. The layer produces photocurrent, which improves the quality of the process.

A method for fabricating an array substrate according to an embodiment of the present invention, wherein a thickness ratio of a gate of the thin film transistor in a region facing the drain is smaller than a thickness of a region facing the channel of the thin film transistor, In the prior art, the distance between the gate and the source and the drain is increased, and the parasitic capacitance generated by the overlap region of the gate and the drain can be reduced, thereby reducing the induced voltage, thereby improving the screen flicker and improving the screen. product quality.

Further, an embodiment of the present invention further provides a display device including an array substrate according to any of the embodiments of the present invention or an array substrate fabricated by the above method. The display device may be a liquid crystal display, an organic light emitting display (OLED) or an electronic paper display or the like. Since the above array substrate is used, the display device according to the embodiment of the present invention can also reduce the parasitic capacitance generated by the overlapping regions of the gate and the drain, thereby reducing the induced voltage, thereby improving the screen flicker and improving Product quality.

(1) An array substrate comprising:

Substrate

Grid lines and data lines crossing each other disposed on the substrate;

a thin film transistor and a pixel electrode disposed in the pixel unit defined by the gate line and the data line,

The gate of the thin film transistor is connected to the gate line, the source of the thin film transistor is connected to the data line, and the drain of the thin film transistor is connected to the pixel electrode; Wherein the thickness of the gate of the thin film transistor in a region facing the drain is smaller than a thickness of a region facing the channel of the thin film transistor.

(2) The array substrate according to (1), wherein a thickness of a gate of the thin film transistor in a region facing the source is smaller than a thickness of a region facing a channel of the thin film transistor.

(3) The array substrate according to (1) or (2), wherein a thickness of a source and a drain of the thin film transistor are equal.

The array substrate according to any one of (1) to (3), wherein, in a plan view, a source of the thin film transistor has an arc shape, and one end of a drain of the thin film transistor On the centripetal side of the curved source.

The array substrate according to any one of (1) to (3), wherein the source and the drain of the thin film transistor have a rectangular shape as seen from a plan view.

The array substrate according to any one of (1) to (5) further comprising: a common electrode line, wherein the common electrode line is disposed in the same layer as the data line, and the two are electrically connected to each other insulation.

(7) The array substrate according to (6), wherein the common electrode line is parallel to the data line.

(8) The array substrate according to (6) or (7), wherein an active layer portion pattern is formed under the common electrode line, and the active layer portion pattern supports the common electrode line.

The array substrate according to any one of (1), wherein the substrate is a transparent substrate.

(10) A method for fabricating an array substrate, comprising:

Forming a gate metal film on the substrate, patterning the gate metal film by a patterning process to form a gate metal layer;

Forming a gate insulating layer, an active layer, a source/drain metal layer, and a common electrode line on the substrate on which the gate metal layer is formed,

The gate metal layer includes a gate line and a gate, the source/drain metal layer includes a source, a drain, and a data line, and the gate, the active layer, the source, and the drain constitute a thin film transistor, and wherein a thickness of the gate in a region facing the drain is smaller than a thickness of a region facing a channel of the thin film transistor.

(11) The manufacturing method according to (10), wherein the step of forming the gate metal layer comprises: Depositing a gate metal film;

Forming a photoresist, developing and exposing it to form a photoresist completely removed region, a photoresist portion remaining region and a photoresist completely remaining region, wherein the photoresist completely removed region includes to form the a region outside the region of the gate metal layer, the photoresist portion remaining region corresponding to the region where the gate and the drain face, the photoresist completely reserved region corresponding to other regions; using an etching process Etching the gate metal film of the photoresist completely removed region; ashing the photoresist to remove the photoresist of the photoresist portion remaining region;

Etching a portion of the gate metal film in the remaining portion of the photoresist portion by an etching process; and

The remaining photoresist is stripped.

(12) The manufacturing method according to (10) or (11), wherein the common electrode line is formed in the same layer as the source/drain metal layer.

(13) The manufacturing method according to any one of (10) to (12), after the gate insulating layer, the active layer, the source/drain metal layer, and the common electrode line are formed, A step of sequentially forming a protective layer and a pixel electrode layer is included.

(14) The manufacturing method according to any one of (10), wherein the forming the active layer, the source/drain metal layer comprises:

Forming a semiconductor thin film and a source/drain metal thin film on a transparent substrate on which a gate insulating layer is formed, patterning the semiconductor thin film and the source/drain metal thin film by a single mask patterning process to form the active layer and the source/drain metal layer .

The manufacturing method according to any one of (10), wherein the thickness ratio of the gate to a region facing the source is opposite to a channel of the thin film transistor. The thickness of the area is small.

(16) A display device comprising the array substrate according to any one of (1) to (9).

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

1. An array substrate comprising:

Substrate

Grid lines and data lines crossing each other disposed on the substrate;

The gate of the thin film transistor is connected to the gate line, the source of the thin film transistor is connected to the data line, and the drain of the thin film transistor is connected to the pixel electrode;

Wherein the thickness of the gate of the thin film transistor in a region facing the drain is smaller than a thickness in a region facing the channel of the thin film transistor.

The array substrate according to claim 1, wherein a gate of the thin film transistor has a thickness smaller than a thickness of a region facing the source of the thin film transistor.

The array substrate according to claim 1 or 2, wherein a thickness of a source and a drain of the thin film transistor are equal.

The array substrate according to any one of claims 1 to 3, wherein a source of the thin film transistor has an arc shape, and one end of a drain of the thin film transistor is curved. The centripetal side of the source.

The array substrate according to any one of claims 1 to 3, wherein the source and the drain of the thin film transistor have a rectangular shape as seen from a plan view.

The array substrate according to any one of claims 1 to 5, further comprising: a common electrode line, wherein the common electrode line is disposed in the same layer as the data line, and is electrically insulated from each other.

The array substrate according to claim 6, wherein the common electrode line is parallel to the data line.

The array substrate according to claim 6 or 7, wherein an active layer portion pattern is formed under the common electrode line, and the active layer portion pattern supports the common electrode line.

The array substrate according to any one of claims 1 to 8, wherein the substrate is a transparent substrate.

10. A method of fabricating an array substrate, comprising:

Forming a gate metal film on the substrate, patterning the gate metal film by a patterning process to form a gated metal layer;

11. The fabricating method according to claim 10, wherein the step of forming the gate metal layer comprises:

Depositing a gate metal film;

The remaining photoresist is stripped.

The manufacturing method according to claim 10 or 11, wherein the common electrode line is formed in the same layer as the source/drain metal layer.

The manufacturing method according to any one of claims 10 to 12, after forming the gate insulating layer, the active layer, the source/drain metal layer, and the common electrode line, further comprising sequentially forming The steps of protecting the layer and the pixel electrode layer.

The manufacturing method according to any one of claims 10 to 13, wherein the step of forming the active layer, the source/drain metal layer comprises:

The manufacturing method according to any one of claims 10 to 14, wherein the gate is in The thickness of the region facing the source is greater than the thickness of the region facing the channel of the thin film transistor

A display device comprising the array substrate according to any one of claims 1-9.