CN112635574A - Liquid crystal display panel, thin film transistor and preparation method thereof - Google Patents
Liquid crystal display panel, thin film transistor and preparation method thereof Download PDFInfo
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- CN112635574A CN112635574A CN202011639252.0A CN202011639252A CN112635574A CN 112635574 A CN112635574 A CN 112635574A CN 202011639252 A CN202011639252 A CN 202011639252A CN 112635574 A CN112635574 A CN 112635574A
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- 239000010409 thin film Substances 0.000 title claims abstract description 56
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 29
- 150000004767 nitrides Chemical class 0.000 claims abstract description 28
- 238000001039 wet etching Methods 0.000 claims abstract description 23
- 238000001312 dry etching Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000002161 passivation Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 230000002035 prolonged effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 192
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/78669—
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/80—Etching
-
- H01L29/66765—
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- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
Abstract
The application is applicable to the technical field of display, and provides a liquid crystal display panel, a thin film transistor and a preparation method thereof, wherein a source drain layer and a photoresist layer which comprise a first nitride conducting layer, a metal layer and a second nitride conducting layer are prepared in a first photomask process; and/or, in the second photomask manufacturing process, the duration time of the second wet etching is shortened to 85S-95S; and/or in the second photomask manufacturing process, the duration time of the second dry etching is prolonged to 40S-50S, so that the trailing size of the contact layer can be effectively reduced, the channel length between the grid layer and the drain-source electrode layer and the length of a channel region can be increased, the off-state current of the thin film transistor is normal, the reliability reduction of the liquid crystal display panel realized based on the thin film transistor is improved, and the probability of generating abnormal pictures is reduced.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a liquid crystal display panel, a thin film transistor and a preparation method of the thin film transistor.
Background
With the continuous development of display technology, various types of display panels are developed, which brings great convenience to daily production and life of people. A liquid crystal display panel is a display panel which is widely used at present, and a Thin Film Transistor (TFT) is generally used to drive a liquid crystal pixel. In the manufacturing process of the thin film transistor, an amorphous silicon (a-Si) tail fiber is formed in a channel region by a contact layer below a source drain layer, so that off-state current (Ioff) of the thin film transistor is increased, Reliability (RA) of a liquid crystal display panel realized based on the thin film transistor is reduced, and abnormal pictures are easy to generate.
Disclosure of Invention
In view of this, embodiments of the present application provide a liquid crystal display panel, a thin film transistor and a method for manufacturing the same, so as to solve the problem that in a manufacturing process of the thin film transistor, an amorphous silicon tail fiber is formed in a channel region by a contact layer below a source drain layer, which increases an off-state current of the thin film transistor, thereby reducing reliability of the liquid crystal display panel implemented based on the thin film transistor and easily causing an abnormal picture phenomenon.
A first aspect of an embodiment of the present application provides a method for manufacturing a thin film transistor, including:
preparing a grid layer on a glass substrate layer and patterning the grid layer in a first photomask process; preparing a gate insulating layer, an active layer, a contact layer, a source drain layer and a photoresist layer on one surface of the gate layer away from the glass substrate layer;
in the second photo-mask process, the photo-resist layer is exposed and developed; carrying out first wet etching, and patterning the source drain layer to form metal lead structures of a source drain region and an active region; carrying out first dry etching, and patterning the active layer and the contact layer to form island-shaped structures of the active layer and the contact layer; carrying out oxygen ashing, and reducing the thickness of the photoresist layer to expose the source drain layer of the channel region; carrying out second wet etching to pattern the drain-source electrode layer; performing second dry etching to etch the active layer and the contact layer to form a thin film transistor structure;
the source drain layer comprises a first nitride conducting layer, a metal layer and a second nitride conducting layer;
and/or the duration of the second wet etching is 85S-95S;
and/or the duration of the second dry etching is 40S-50S.
In one embodiment, after the second dry etching, the size of the tail of the contact layer at the edge of the drain-source electrode layer is 0.15 μm to 0.35 μm, the channel length between the gate layer and the drain-source electrode layer is 4.2 μm to 5.2 μm, and the length of the channel region is greater than 3.4 μm.
In one embodiment, the initial thickness of the contact layer is 3900A.
In one embodiment, the initial thickness of the drain-source electrode layer is 4350A, the size of the photoresist layer after exposure and development is 5.0 μm to 5.3 μm, the total duration of the first wet etching and the second wet etching is 145S to 150S, and the thickness of the drain-source electrode layer after the second wet etching is 3800A.
In one embodiment, the method for manufacturing a thin film transistor further includes:
in the third photomask manufacturing process, preparing a passivation layer on one surface of the source drain electrode layer far away from the contact layer and patterning the passivation layer;
in the fourth photo-mask process, a transparent electrode layer is prepared on the surface of the passivation layer away from the source/drain layer and patterned.
A second aspect of the embodiments of the present application provides a thin film transistor, which is manufactured based on the method for manufacturing a thin film transistor provided in the first aspect of the embodiments of the present application, and includes a glass substrate layer, a gate electrode layer, a gate insulating layer, an active layer, a contact layer, and a source drain layer, which are sequentially disposed;
the source drain layer comprises a first nitride conducting layer, a metal layer and a second nitride conducting layer.
In one embodiment, the first nitride conductive layer or the second nitride conductive layer is one of a molybdenum nitride layer and a titanium nitride layer.
In one embodiment, the metal layer or the gate layer is one of an aluminum material layer, a copper material layer, and a silver material layer.
In one embodiment, the thin film transistor further includes a passivation layer disposed on a side of the source/drain electrode layer away from the contact layer, and a transparent electrode layer disposed on a side of the passivation layer away from the source/drain electrode layer.
A third aspect of the embodiments of the present application provides a liquid crystal display panel, including:
a liquid crystal pixel;
a source driver;
a gate driver; and
in the thin film transistor according to the second aspect of the embodiments of the present application, the drain layer, the source layer, and the gate layer of the thin film transistor are respectively connected to the pixel electrode, the source driver, and the gate driver of the liquid crystal pixel.
In the method for manufacturing a thin film transistor provided in the first aspect of the embodiment of the present application, a source drain layer and a photoresist layer including a first nitride conductive layer, a metal layer, and a second nitride conductive layer are prepared in a first photomask process; and/or, in the second photomask manufacturing process, the duration time of the second wet etching is shortened to 85S-95S; and/or in the second photomask manufacturing process, the duration time of the second dry etching is prolonged to 40S-50S, so that the trailing size of the contact layer can be effectively reduced, the channel length between the grid layer and the drain-source electrode layer and the length of a channel region can be increased, the off-state current of the thin film transistor is normal, the reliability reduction of the liquid crystal display panel realized based on the thin film transistor is improved, and the probability of generating abnormal pictures is reduced.
It is understood that, the beneficial effects of the second aspect and the third aspect can be referred to the related description of the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a first schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a thin film transistor according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present application;
fig. 4 is a schematic structural diagram of a source drain layer provided in the embodiment of the present application;
fig. 5 is a second schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
As shown in fig. 1, fig. 2, fig. 3, or fig. 4, a method for manufacturing a thin film transistor provided in an embodiment of the present application includes:
step S101, in a first photo-mask process, preparing a gate layer 12 on a glass substrate layer 11 and patterning the gate layer 12; preparing a gate insulating layer 13, an active layer 14, a contact layer 15, a source drain layer 16 and a photoresist layer 17 on one surface of the gate layer 12 away from the glass substrate layer 11;
step S102, in the second photo-mask process, exposing and developing the photo-resist layer 17; carrying out first wet etching to pattern the source drain layer 16 and form metal lead structures of a source drain region and an active region; carrying out first dry etching, and patterning the active layer 14 and the contact layer 15 to form island-shaped structures of the active layer 14 and the contact layer 15; performing oxygen ashing to reduce the thickness of the photoresist layer to expose the source/drain layer 16 in the channel region; performing a second wet etching to pattern the drain-source electrode layer 16; performing second dry etching to etch the active layer 14 and the contact layer 15 to form a thin film transistor structure;
wherein the source drain layer 16 includes a first nitride conductive layer 161, a metal layer 162, and a second nitride conductive layer 163;
and/or the duration of the second wet etching is 85S-95S (seconds);
and/or the duration of the second dry etching is 40S-50S.
In application, the method for manufacturing a thin film transistor provided in the embodiment of the present application is implemented based on 4Mask processes, and only two of the Mask processes are exemplarily shown in fig. 1 and fig. 2.
In application, in the first photomask manufacturing process, the method for preparing the source and drain electrode layer can be to prepare a first nitride conducting layer, a metal layer and a second nitride conducting layer on one surface, far away from the active layer, of the contact layer, and the side, close to the photoresist layer, of the source and drain electrode layer is set as the second nitride conducting layer, so that the characteristic of slow etching rate of nitride can be utilized, the coverage of the source and drain electrode layer on the contact layer is increased, and the trailing size of the contact layer is reduced.
In the application, in the second photo-mask process, the duration of the second wet etching can be shortened from 95S-105S to 85S-95S; and/or prolonging the duration of the second dry etching from 10S to 40S-50S. By shortening the time of the second wet etching, the etched area of the drain source layer can be reduced, and the Critical Dimension (CD) of the drain source layer after etching is increased, so that the coverage of the drain source layer on the contact layer is increased, and the tailing size of the contact layer is reduced. By extending the time of the second dry etch, the area of the tail etched can be increased, thereby reducing the size of the tail of the contact layer.
In application, the initial thickness of the contact layer may be set to 3900A (angstroms) so that the tail size of the contact layer after the second dry etching can meet the requirement of less than 0.35 μm.
In application, the initial thickness of the drain-source electrode layer is 4350A, the size of the photoresist layer after exposure and development is 5.0-5.3 μm, and the total duration time of the first wet etching and the second wet etching is controlled within 145-150S, so that the thickness of the drain-source electrode layer after the second wet etching is reduced from 4350A to 3800A.
Fig. 3 exemplarily shows a structure of a thin film transistor manufactured based on the manufacturing method shown in fig. 1, which includes a glass substrate layer 11, a gate electrode layer 12, a gate insulating layer 13, an active layer 14, a contact layer 15, and a source drain layer 16, which are sequentially disposed;
drain-source layer 16 includes a drain layer 164 and a source layer 165, with drain layer 164 and source layer 165 separated by a channel region 166.
In application, the first nitride conductive layer, the second nitride conductive layer may be a molybdenum nitride (MoN) layer, a titanium nitride (TiN) layer, or the like. The metal layer and the gate layer may be an aluminum (Al) material layer, a copper (Au) material layer, a silver (Ag) material layer, or the like.
In application, the contact layer is used to form a good ohmic contact between the source, drain and active layers, and may be formed of a semiconductor material, for example, an N-type hydrogenated amorphous silicon (N + a-Si: H) layer. The active layer, which is used as a channel when the thin film transistor is turned on, may be formed using a semiconductor material, for example, a hydrogenated amorphous silicon (a-Si: H) layer,
in application, the gate insulating layer may be made of any electrically poor conductor material, such as a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, or a combination of silicon nitride and silicon oxide. The gate insulating layer serves as a dielectric and has an insulating effect.
In application, the passivation layer (PVX) may be made of any electrically poor conductor material, such as a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer or a combination of silicon nitride and silicon oxide. The passivation layer serves as a protective layer having a certain strength and also has an insulating function.
In application, according to the method for manufacturing the thin film transistor provided by the embodiment of the application, after the second dry etching, the size of the tail of the contact layer at the edge of the drain-source layer can be reduced from 0.7 μm (micrometer) to 0.8 μm to less than 0.35 μm (for example, 0.15 μm to 0.35 μm), the channel length between the gate layer and the drain-source layer is 4.7 μm ± 0.5 μm, that is, 4.2 μm to 5.2 μm, and the length of the channel region can be increased to more than 3.4 μm.
As shown in fig. 5, in an embodiment, after step S102, the method further includes:
step 103, preparing a passivation layer 18 on the surface of the source/drain layer 16 away from the contact layer 15 and patterning the passivation layer 18 in a third photomask process;
step S104, in the fourth photo-masking process, a transparent electrode layer 19 is prepared on the surface of the passivation layer 18 away from the source/drain layer 16, and the transparent electrode layer 19 is patterned.
According to the preparation method of the thin film transistor, the source drain layer and the photoresist layer which comprise the first nitride conducting layer, the metal layer and the second nitride conducting layer are prepared in the first photomask manufacturing process; and/or, in the second photomask manufacturing process, the duration time of the second wet etching is shortened to 85S-95S; and/or in the second photomask manufacturing process, the duration time of the second dry etching is prolonged to 40S-50S, so that the trailing size of the contact layer can be effectively reduced, the channel length between the grid layer and the drain-source electrode layer and the length of a channel region can be increased, the off-state current of the thin film transistor is normal, the reliability reduction of the liquid crystal display panel realized based on the thin film transistor is improved, and the probability of generating abnormal pictures is reduced.
Embodiments of the present application further provide a thin film transistor (for example, the thin film transistor shown in fig. 3) prepared based on the above preparation method, and by configuring the drain-source layer to include the first nitride conductive layer, the metal layer, and the second nitride conductive layer, the tail size of the contact layer can be effectively reduced, the channel length between the gate layer and the drain-source layer and the length of the channel region can be increased, and the off-state current of the thin film transistor can be normal.
As shown in fig. 6, an embodiment of the present application further provides a liquid crystal display panel, including:
a liquid crystal pixel 100;
a source driver 200;
a gate driver 300; and
in the tft 400, a drain layer, a source layer, and a gate layer of the tft 400 are respectively connected to a pixel electrode of the liquid crystal pixel 300, the source driver 400, and the gate driver 500.
In application, the number of the liquid crystal pixels, the source drivers, the gate drivers, and the thin film transistors included in the liquid crystal display panel, and the driving manner of the gate drivers may be set according to actual needs, and the structure of the liquid crystal display panel shown in fig. 6 and the adopted dual-gate driving manner are only exemplary.
In the embodiment corresponding to fig. 6, by using the thin film transistor provided in the foregoing embodiment, the reliability of the liquid crystal display panel can be effectively improved, and the probability of generating abnormal pictures is reduced, so that different areas of pictures displayed by the liquid crystal display panel can be close to each other, thereby improving the display effect.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method for manufacturing a thin film transistor includes:
preparing a grid layer on a glass substrate layer and patterning the grid layer in a first photomask process; preparing a gate insulating layer, an active layer, a contact layer, a source drain layer and a photoresist layer on one surface of the gate layer away from the glass substrate layer;
in the second photo-mask process, the photo-resist layer is exposed and developed; carrying out first wet etching, and patterning the source drain layer to form metal lead structures of a source drain region and an active region; carrying out first dry etching, and patterning the active layer and the contact layer to form island-shaped structures of the active layer and the contact layer; carrying out oxygen ashing, and reducing the thickness of the photoresist layer to expose the source drain layer of the channel region; carrying out second wet etching to pattern the drain-source electrode layer; performing second dry etching to etch the active layer and the contact layer to form a thin film transistor structure;
the source drain layer comprises a first nitride conducting layer, a metal layer and a second nitride conducting layer;
and/or the duration of the second wet etching is 85S-95S;
and/or the duration of the second dry etching is 40S-50S.
2. The method of manufacturing a thin film transistor according to claim 1, wherein after the second dry etching, a size of a tail of the contact layer at an edge of the drain-source layer is 0.15 μm to 0.35 μm, a channel length between the gate layer and the drain-source layer is 4.2 μm to 5.2 μm, and a length of a channel region is greater than 3.4 μm.
3. The method for manufacturing a thin film transistor according to claim 1, wherein an initial thickness of the contact layer is 3900A.
4. The method of manufacturing a thin film transistor according to claim 1, wherein the initial thickness of the drain-source electrode layer is 4350A, the size of the photoresist layer after exposure and development is 5.0 μm to 5.3 μm, the total duration of the first wet etching and the second wet etching is 145S to 150S, and the thickness of the drain-source electrode layer after the second wet etching is 3800A.
5. The method for manufacturing a thin film transistor according to any one of claims 1 to 4, further comprising:
in the third photomask manufacturing process, preparing a passivation layer on one surface of the source drain electrode layer far away from the contact layer and patterning the passivation layer;
in the fourth photo-mask process, a transparent electrode layer is prepared on the surface of the passivation layer away from the source/drain layer and patterned.
6. A thin film transistor prepared by the method of any one of claims 1 to 5, comprising a glass substrate layer, a gate electrode layer, a gate insulating layer, an active layer, a contact layer and a source drain layer arranged in this order;
the source drain layer comprises a first nitride conducting layer, a metal layer and a second nitride conducting layer.
7. The thin film transistor according to claim 6, wherein the first nitride conductive layer or the second nitride conductive layer is one of a molybdenum nitride layer and a titanium nitride layer.
8. The thin film transistor of claim 6, wherein the metal layer or the gate layer is one of an aluminum material layer, a copper material layer, and a silver material layer.
9. The thin film transistor according to any one of claims 6 to 8, further comprising a passivation layer disposed on a side of the source drain layer remote from the contact layer and a transparent electrode layer disposed on a side of the passivation layer remote from the source drain layer.
10. A liquid crystal display panel, comprising:
a liquid crystal pixel;
a source driver;
a gate driver; and
the thin film transistor according to any one of claims 6 to 9, wherein the drain, source and gate electrode layers of the thin film transistor are connected to the pixel electrode, the source driver and the gate driver of the liquid crystal pixel, respectively.
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