KR20080038593A - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

An LCD panel and a manufacturing method thereof are provided to increase transformation force by an uneven portion on a fixing groove when the uneven portion of the fixing groove contacts a column spacer, thereby preventing smear faults and light leakage faults generated when the LCD panel is pressurized while increasing a liquid crystal margin. An LCD(Liquid Crystal Display) panel comprises a TFT(Thin Film Transistor) substrate, a color filter substrate, a column spacer(280) and a fixing groove(281). A TFT array is formed on the TFT substrate. A color filter array is formed on the color filter substrate and is opposite to the TFT substrate. The column spacer is formed on the color filter substrate and holds a cell gap between the TFT substrate and the color filter substrate. The fixing groove is formed on the TFT substrate, and the lower end of the column space is inserted into the fixing groove. The fixing groove has an uneven surface.

Description

Liquid crystal display panel and its manufacturing method {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}

1 is a plan view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along lines II ′ and II-II ′ of the thin film transistor substrate illustrated in FIG. 1.

3 to 8 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate of FIG. 1.

9 is a plan view illustrating a mask pattern according to a first exemplary embodiment of the present invention.

10 is a plan view illustrating a mask pattern according to a second exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

20 liquid crystal 30 thin film transistor substrate

40: lower substrate 50: gate line

60: data line 70: thin film transistor

80 gate electrode 90 source electrode

100 drain electrode 110 active layer

120: ohmic contact layer 130: pixel electrode

210: gate insulating film 220: protective film

225 contact hole 250 color filter

280: column spacer 281,282: fixing groove

290: slit mask 291: transparent substrate

292: transmission part 293: blocking part

295: photoresist layer 296, 297, 298, 299: mask pattern

The present invention relates to a liquid crystal display panel and a method for manufacturing the same, and more particularly, to a liquid crystal panel and a method for manufacturing the same, which can prevent smear defects and light leakage defects that may occur when the liquid crystal panel is pressed while increasing the liquid crystal margin.

In general, a liquid crystal display is a display device that displays a desired image by individually supplying data signals according to image information to pixels arranged in a matrix, and adjusting light transmittance of the pixels.

The liquid crystal display panel is bonded to a thin film transistor substrate on which a thin film transistor (TFT) array is formed and a color filter substrate on which a color filter (CF) array is formed to maintain a uniform cell gap, and a cell gap between the thin film transistor substrate and a color filter substrate. Liquid crystal is inherent.

The common electrode and the pixel electrode are formed in the liquid crystal display panel in which the thin film transistor substrate and the color filter substrate are opposed to each other to apply an electric field to the liquid crystal layer. That is, by controlling the voltage applied to the pixel electrode in the state where the voltage is applied to the common electrode, the light transmittance of the pixels can be adjusted individually. As such, in order to control the voltage applied to the pixel electrode for each pixel, a thin film transistor used as a switching element is formed in each pixel.

An alignment film is formed on opposing surfaces of the thin film transistor substrate and the color filter substrate, and rubbing is performed to arrange the liquid crystals in a constant direction.

Column spacers are used to maintain the cell gap, which is generally formed on the color filter substrate and is in surface contact with the thin film transistor substrate when the thin film transistor substrate and the color filter substrate are bonded together.

The cross-sectional area and density of the column spacers determine the pressure resistance of the column spacers and also influence the liquid crystal margin. However, the pressure resistance of the column spacer and the liquid crystal margin have a relationship opposite to the cross-sectional area and density of the column spacer.

For example, when the density of the column spacer is increased to improve the pressure resistance of the column spacer, the compressive strain of the column spacer is reduced. As a result, the liquid crystal margin is reduced.

On the other hand, when the density of the column spacer is reduced to improve the liquid crystal margin, the pressure resistance of the column spacer is reduced.

In addition, when the liquid crystal panel is pressurized, the color filter substrate is shifted in one direction, resulting in a touch unevenness or a deterioration of touch. This is because the friction force due to the surface contact between the column spacers and the thin film transistor substrate is large, and the color filter substrate is returned to its original position. This is because it takes a long time. For this reason, the image display quality of a liquid crystal display panel falls.

Accordingly, the technical problem of the present invention is to form first and second fixing grooves for fixing the column spacer to the protective layer, and to prevent smear defects and light leakage defects that may occur when the liquid crystal panel is pressed while increasing the liquid crystal margin of the liquid crystal panel. The present invention provides a liquid crystal display panel and a method of manufacturing the same.

In order to achieve the above technical problem, the liquid crystal display panel of the present invention comprises a thin film transistor substrate formed with a thin film transistor array; A color filter substrate on which a color filter array is formed and which faces the thin film transistor substrate; A column spacer formed on the color filter substrate and maintaining a cell gap between the thin film transistor substrate and the color filter substrate; and a lower end of the column spacer inserted into the thin film transistor substrate and having a concave-convex surface. It features.

The fixing groove may include a first fixing groove having a first depth for each pixel; And a second fixing groove formed to a second depth.

The density of the irregularities formed in the second fixing groove is greater than the density of the irregularities formed in the first fixing groove.

The first depth is formed to less than 2000Å, the second depth is greater than the first depth is characterized in that formed to 5000Å or less.

In order to achieve the above technical problem, a method of manufacturing a liquid crystal display panel of the present invention comprises the steps of providing a thin film transistor substrate having a thin film transistor array including a fixing groove is inserted into the bottom of the column spacer; Providing a color filter substrate comprising the column spacer and having a color filter array formed thereon; Bonding the thin film transistor substrate and the color filter substrate to each other, wherein preparing the thin film transistor substrate comprises: forming a gate pattern including a gate line and a gate electrode on an insulating substrate; Forming a gate insulating layer, an active layer, and an ohmic contact layer after forming the gate pattern; Forming a data pattern including a data line, a source electrode, and a drain electrode after forming the gate insulating layer, the active layer, and the ohmic contact layer; Forming a passivation layer after forming the data pattern; Forming a contact hole penetrating through the passivation layer and a fixing groove into which a lower end of the column spacer is inserted; And forming a pixel electrode connected to the thin film transistor on the passivation layer.

The forming of the fixing groove may include forming a first fixing groove having a first depth and a second fixing groove having a second depth for each pixel using a slit mask.

The depth of the first fixing groove is formed to less than 2000Å, the depth of the second fixing groove is greater than the first depth characterized in that it comprises a step of forming to less than 5000Å.

The density of the irregularities formed in the second fixing groove is greater than the density of the irregularities formed in the first fixing groove.

By using the slit mask is characterized in that the irregularities formed on the lower surface of the first and second fixing groove.

The unevenness may be formed using any one of a mask pattern formed in a stripe shape or a lattice shape.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a plan view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along lines II ′ and II-II ′ of the thin film transistor substrate illustrated in FIG. 1.

1 and 2, a liquid crystal display panel according to an exemplary embodiment of the present invention includes a thin film transistor substrate 30 and a color filter substrate bonded to each other by a predetermined interval with a liquid crystal 20 therebetween.

The liquid crystal 20 is rotated by a voltage difference between the common voltage of the common electrode of the color filter substrate and the pixel voltage of the pixel electrode 130 of the thin film transistor substrate 30 to adjust the amount of light transmitted from the backlight assembly. To this end, the liquid crystal 20 is made of a material having dielectric anisotropy light refractive index anisotropy.

The thin film transistor substrate may include a gate line 50 and a data line 60 formed on the first substrate 40 to cross each other, a thin film transistor 70 connected to the gate line 50 and the data line 60, and A pixel electrode 130 connected to the thin film transistor 70, a storage line formed in parallel with the gate line 50, a storage electrode protruding from the storage line, and a region overlapping the column spacer 280. And first and second fixing grooves 281 and 282 formed therein. Here, the gate line 50 and the data line 60 are insulated by the gate insulating film 210 formed on the entire surface.

The gate line 50 has a material such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy, and is formed of a single layer or multiple layers. The gate line 50 supplies the gate on / off voltage from the gate driving circuit to the gate electrode 80 of the thin film transistor 70 connected thereto.

The data line 60 has a material such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy, Ti or Ti alloy, and is formed of a single layer or multiple layers. The data line 60 supplies the data voltage from the data driving circuit to the source electrode 90 of the thin film transistor 70 connected thereto.

The thin film transistor 70 receives a data voltage from the data line 60 in response to the gate on / off voltage from the gate line 50 to supply the pixel voltage to the pixel electrode 130. To this end, the thin film transistor 70 is formed to face the gate electrode 80 connected to the gate line 50, the source electrode 90 connected to the data line 60, and the source electrode 90. A drain electrode 100 connected to the pixel electrode 130 and an active layer 110 and an ohmic contact layer 120 overlapping the gate electrode 80 with the gate insulating layer 210 interposed therebetween.

The gate electrode 80 is formed of the same material as the gate line 50 on the same plane as the gate line 50 and protrudes from the gate line 50. The gate electrode 80 turns the thin film transistor 70 on / off using the gate on / off voltage from the gate line 50.

The source electrode 90 is formed of the same material as the data line 60 on the same plane as the data line 60 and protrudes from the data line 60. The source electrode 90 supplies the data voltage from the data line 60 to the drain electrode 100 via the channel of the thin film transistor 70.

The drain electrode 100 is formed of the same material as the data line 60 on the same plane as the data line 60. The drain electrode 100 receives a data voltage from the source electrode 90 and supplies the pixel voltage to the pixel electrode 130 connected to the pixel electrode 130 through the contact hole 225 penetrating through the passivation layer 220. Here, the protective film 220 is formed to cover the thin film transistor 70 so as to protect the thin film transistor 70 and is formed on the entire surface.

The active layer 110 is formed of amorphous silicon and forms a channel of the thin film transistor 70.

The ohmic contact layer 120 is formed of impurity doped amorphous silicon, and is formed for ohmic contact between the source electrode 90, the drain electrode 100, and the active layer 110.

The pixel electrode 130 is formed of a transparent metal such as ITO or IZO, and applies the pixel voltage from the drain electrode 100 to the liquid crystal 20.

The storage line is formed of the same material as the gate line 50 on the same plane as the gate line 50. The storage line supplies the storage voltage from the storage voltage generator to the storage electrode.

The storage electrode is formed of the same material as the gate line 50 on the same plane as the gate line 50. The storage electrode overlaps the pixel electrode 130 with the gate insulating layer 210 and the passivation layer 220 therebetween. That is, the storage electrode uses the storage voltage from the storage line to maintain the pixel voltage supplied to the pixel electrode 130 for one frame.

The first and second fixing grooves 281 and 282 are formed on the passivation layer 220 such that the lower ends of the column spacers 280 may be inserted at positions corresponding to the column spacers 280.

The first fixing groove 281 is formed to have a first depth H1 and has an uneven surface therein.

The second fixing groove 282 is formed to the second depth (H2), and has a concave-convex density greater than the density of the concave-convex formed in the first fixing groove 281 therein. At this time, it is preferable that the first depth H1 is formed to be 2000 mPa or less, and the second depth H2 is formed to be larger than the first depth H2 to 5000 mPa or less. For example, when the first depth H1 is formed larger than 2000 kPa, the liquid crystal margin becomes small. When the second depth H2 is formed to be greater than 5000 mW, the gate line 50 may be exposed to cause defects, and the restoring force may be weakened during the liquid crystal panel pressurization test.

The passivation layer 220 may be formed of an inorganic passivation layer or an organic passivation layer. For example, in the case of forming the inorganic protective film, the protective film 220 is formed to have a thickness of 2000 μs along the step of the metal wires formed on the thin film transistor substrate 30. Accordingly, the first fixing groove 281 is formed on the passivation layer 220, and the second fixing groove 282 is formed on the gate insulating layer 210 through the protective layer 220 and the gate insulating layer 210.

On the other hand, when formed of an organic passivation layer, the passivation layer 220 is formed to have a larger thickness than that of the inorganic passivation layer, and eliminates the step of the metal lines formed on the thin film transistor substrate 30. Therefore, the first fixing grooves and the second fixing grooves 281 and 282 are formed on the organic protective film. For this reason, even if overetched, it does not affect the gate line 50. FIG.

The first and second fixing grooves 281 and 282 are formed to insert the lower ends of the column spacers 280 at positions corresponding to the column spacers 280 on the organic passivation layer.

The first fixing groove 281 is formed to have a first depth H1 and has an uneven surface therein.

The second fixing groove 282 is formed to the second depth (H2), and has a concave-convex density greater than the density of the concave-convex formed in the first fixing groove 281 therein. At this time, it is preferable that the first depth H1 is formed to be 2000 Pa or less, and the second depth H2 is formed to be greater than or equal to the first depth H2 to 5000 Pa or less. For example, when the first depth H1 is formed larger than 2000 kPa, the liquid crystal margin becomes small. When the second depth H2 is formed to be greater than 5000 mW, the gate line 50 may be exposed to cause defects, and the restoring force may be weakened during the liquid crystal panel pressurization test.

The column spacers contacting the first fixing grooves 281 when the thin film transistor substrate 30 having the first and second fixing grooves 281 and 282 thus formed and the color filter substrate having the column spacers 280 are bonded to each other ( 280 primarily maintains the cell gap. Therefore, the density of the column spacer 280 in contact with the thin film transistor substrate 30 may be lowered to improve the liquid crystal margin.

Then, the column spacer 280 fixed to the second fixing groove 282 is secondarily when a load is applied to the liquid crystal panel, a local part is pressed by the user, or bent by using a flexible plastic substrate. The cell gap between the thin film transistor substrate 30 and the color filter substrate is supported. Accordingly, when the pressure applied to the liquid crystal panel is increased, the density of the column spacer 280 contacting the thin film transistor substrate 30 may be increased, thereby improving pressure resistance of the liquid crystal panel. As a result, smear defects caused by the column spacer 280 collapsing due to the pressure applied to the liquid crystal panel or the lower layer thereof may be prevented may be prevented.

In addition, by forming the first and second fixing grooves 281 and 282 in the form of irregularities, the cross-sectional area of contact between the first and second fixing grooves 281 and 282 and the column spacer 280 in contact with each other increases, thereby increasing the width of the column spacer 280. The strain force is increased. The second fixing groove 282 in which the unevenness is formed more densely has a greater deformation force in contact with the column spacer 280 than the first fixing groove 281.

The first and second fixing grooves 281 and 282 are alternately formed by horizontal lines, alternately formed by vertical lines, or have a first depth H1 and a first depth in the remaining adjacent pixel areas based on one pixel area. It is formed with the 2nd depth H2 different from 1 depth H1.

Accordingly, by forming the first and second fixing grooves 281 and 282 having the uneven surface, it is possible to increase the liquid crystal margin and to prevent smear defects generated when the liquid crystal panel is pressed.

The color filter substrate includes a color filter formed in a black matrix and a region partitioned by the black matrix for preventing light leakage on the upper substrate, an overcoat formed to cover the black matrix and the color filter, a common electrode formed on the overcoat, and a common electrode. It includes a column spacer 280 formed on the top to maintain the cell gap.

The black matrix is opaque organic to prevent the light leakage current of the thin film transistor 70 by blocking the light transmitted through the region that can not control the liquid crystal 20 and direct light irradiation to the channel of the thin film transistor 70. It is formed of a material or an opaque metal.

The color filter includes red, green, and blue color filters R, G, and B to implement color. The red, green, and blue color filters R, G, and B each have red, green, and blue colors by absorbing or transmitting light of a specific wavelength through the red, green, and blue pigments they contain. In this case, various colors are realized through additive mixing colors of red, green, and blue light transmitted through the red, green, and blue color filters R, G, and B, respectively. This color filter arrangement has a stripe shape in which each of the red, green, and blue color filters R, G, and B is formed in a row. That is, the red, green, and blue color filters R, G, and B are alternately formed based on the data line 60 of the thin film transistor substrate 30.

The overcoat is formed of a transparent organic material and protects the color filter and is formed for good step coverage of the common electrode.

The common electrode is formed of a transparent metal such as ITO or IZO and applies a common voltage to the liquid crystal 20.

The column spacer 280 is formed of an organic material and overlaps with the black matrix to maintain a cell gap.

3 to 8 are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate of FIG. 1.

Referring to FIG. 3, a gate pattern including a gate line 50, a gate electrode 80, a storage line, and a storage electrode is formed in a single layer or multiple layers on a lower substrate 40 such as glass or plastic. .

Specifically, a gate metal layer such as Cr or Cr alloy, Al or Al alloy, Mo or Mo alloy, Ag or Ag alloy on the lower substrate 40 using a method such as sputtering as a single layer or multiple layers. Deposit. The gate metal layer is patterned through a photolithography process using the gate mask to form a gate pattern of a single layer or multiple layers.

Referring to FIG. 4, after the gate pattern is formed, the gate insulating layer 210, the active layer 110, and the ohmic contact layer 120 are formed.

Specifically, after the gate pattern is formed, a gate insulating film 210 such as SiNx or SiOx and an active layer 110 such as a-Si and n-doped a-Si using a method such as plasma enhanced chemical vapor deposition (PECVD) An ohmic contact layer 120, such as continuously deposited. Then, the active layer 110 and the ohmic contact layer 120 are formed through a photolithography process using an active mask.

Referring to FIG. 5, after the gate insulating layer 210, the active layer 110, and the ohmic contact layer 120 are formed, the data line 60, the source electrode 90, and the drain electrode 100 are included. The data pattern is formed into a single layer or multiple layers.

Specifically, Cr or Cr alloys, Al or Al alloys, Mo or Mo alloys, Ag or Ag alloys, Ti or Ti alloys, etc. may be formed on the gate insulating layer 210 and the ohmic contact layer 120 by using a sputtering method. The data metal layer is deposited in a single layer or multiple layers. Subsequently, the data metal layer is patterned through a photolithography process using a data mask to form a single or multiple data pattern. Thereafter, the ohmic contact layer 120 exposed between the source electrode 90 and the drain electrode 100 is dry etched to expose the active layer 110. In this case, the active layer 110 may also be slightly etched and overetched. The thickness of the gate insulating layer 210, the active layer 110, and the ohmic contact layer 120 is, for example, 4500 kV for the gate insulating film 210, 2000 kV for the active layer 110, and 3000 kPa for the ohmic contact layer 120. It is preferable to form.

Referring to FIG. 7, after forming the data pattern, the passivation layer 220, the contact hole 225, and the first and second fixing grooves 281 and 282 are formed.

The process of FIGS. 6A to 6C is performed to form FIG. 7.

Referring to FIG. 6A, after forming a data pattern, a protective film 220 such as SiNx or SiOx is deposited using a method such as PECVD. The thickness of the protective film 220 is preferably formed at 2000 kPa.

Then, a photoresist layer 295 for the photolithography process is applied as shown in FIG. 6B. Next, referring to FIG. 6C, first and second fixing grooves in which the column electrode 280 is fixed while exposing the drain electrode 100 by forming a contact hole 225 through a photolithography process using a protective film mask ( 281,282).

In order to form the contact holes 225 and the first and second fixing grooves 281 and 282 on the passivation layer 220, the slit mask 290 is formed in one patterning process.

Specifically, the protection layer 220 is formed by patterning the photolithography process using the slit mask 290. When patterning the passivation layer 220, a positive or negative method may be applied. Here, a case in which the negative method is applied will be described.

The negative slit mask 290 includes a transparent substrate 291, a transparent portion 291 through which the transparent substrate 291 is exposed, and a blocking portion 293 in which a slit and a blocking film are formed on the transparent substrate 291. In the photolithography process using the slit mask 290, only a portion where the exposure amount is insufficient is etched by the slit and the blocking film of the blocking part 293, and thus, the contact hole 225 and the first and second fixing grooves ( 281,282 are formed. At this time, the first fixing groove 281 is formed to the first depth (H1) and the second fixing groove 282 is formed to the second depth (H2). Preferably, the first depth H1 is formed to be 2000 mPa or less, and the second depth H2 is formed to be greater than the first depth H1 to 5000 mPa or less. In addition, unevenness is formed in the first and second fixing grooves 281 and 282 corresponding to the shape and width of each slit. For example, when forming 1st depth H1 larger than 2000 micrometers, liquid crystal margin will become small. When the second depth H2 is formed to be larger than 5000 mW, the gate line 50 may be exposed and defects may occur, and the restoring force may be weakened during the liquid crystal panel pressurization test.

The column spacers contacting the first fixing grooves 281 when the thin film transistor substrate 30 having the first and second fixing grooves 281 and 282 thus formed and the color filter substrate having the column spacers 280 are bonded to each other ( 280 primarily maintains the cell gap. Therefore, the density of the column spacer 280 in contact with the thin film transistor substrate 30 may be lowered to improve the liquid crystal margin.

Then, the column spacer 280 fixed to the second fixing groove 282 is secondarily when a load is applied to the liquid crystal panel, a local part is pressed by the user, or bent by using a flexible plastic substrate. The cell gap between the thin film transistor substrate 30 and the color filter substrate is supported. Accordingly, when the pressure applied to the liquid crystal panel increases, the density of the column spacer 280 in contact with the thin film transistor substrate 30 may increase, thereby improving pressure resistance of the liquid crystal panel. As a result, smear defects caused by the column spacer 280 collapsing due to the pressure applied to the liquid crystal panel or the lower layer thereof may be prevented may be prevented.

In addition, by forming the first and second fixing grooves 281 and 282 in the form of irregularities, the cross-sectional area of contact between the first and second fixing grooves 281 and 282 and the column spacer 280 in contact with each other increases, thereby increasing the width of the column spacer 280. The strain force is increased. The second fixing groove 282 in which the unevenness is formed more densely has a greater deformation force in contact with the column spacer 280 than the first fixing groove 281.

Referring to FIG. 8, after forming the passivation layer 220, the pixel electrode 130 is formed.

Specifically, after forming the protective film, a transparent conductive metal layer such as ITO or IZO is formed by using a method such as sputtering. Subsequently, the pixel electrode 130 is formed by patterning the transparent conductive metal layer through a photolithography process using a pixel electrode mask.

9 is a plan view illustrating a mask pattern according to a first exemplary embodiment of the present invention.

9, the first and second mask patterns 296 and 297 according to the first embodiment of the present invention are formed in a stripe shape.

In the above-described manufacturing method of the thin film transistor substrate 30, the pattern of the slit mask 290 is formed as the stripe-shaped first and second mask patterns 296 and 297 when the process of FIG. 6C is performed.

The column spacers contacting the first fixing grooves 281 when the thin film transistor substrate 30 having the first and second fixing grooves 281 and 282 formed as described above and the color filter substrate having the column spacer 280 are bonded to each other ( 280 primarily maintains the cell gap. Therefore, the density of the column spacer 280 in contact with the thin film transistor substrate 30 may be lowered to improve the liquid crystal margin.

Then, the column spacer 280 fixed to the second fixing groove 282 is secondarily when a load is applied to the liquid crystal panel, a local part is pressed by the user, or bent by using a flexible plastic substrate. The cell gap between the thin film transistor substrate 30 and the color filter substrate is supported. Accordingly, when the pressure applied to the liquid crystal panel is increased, the density of the column spacer 280 contacting the thin film transistor substrate 30 may be increased, thereby improving pressure resistance of the liquid crystal panel. As a result, smear defects caused by the column spacer 280 collapsing due to the pressure applied to the liquid crystal panel or the lower layer thereof may be prevented may be prevented.

In addition, by forming the first and second fixing grooves 281 and 282 in the form of irregularities, the cross-sectional area of contact between the first and second fixing grooves 281 and 282 and the column spacer 280 is increased, thereby increasing the The strain force is increased. The second fixing groove 282 in which the unevenness is formed more densely has a greater deformation force in contact with the column spacer 280 than the first fixing groove 281.

10 is a plan view illustrating a mask pattern according to a second exemplary embodiment of the present invention.

Referring to FIG. 10, the third and fourth mask patterns 298 and 299 according to the second embodiment of the present invention are formed in a matrix form.

In the above-described manufacturing method of the thin film transistor substrate 30, the pattern of the slit mask 290 is formed as the third and fourth mask patterns 296 and 297 in matrix form when the process of FIG. 6C is performed.

Since the method and effect of manufacturing the liquid crystal display panel using the third and fourth mask patterns 298 and 299 are the same as those of using the first and second mask patterns 296 and 297, detailed descriptions thereof will be omitted.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention include first and second fixing grooves capable of preventing the movement of the column spacer. Unevenness is formed in these fixing grooves, so that the deformation force is increased when contacting the column spacer. Accordingly, smear defects and light leakage defects, which may occur when pressing the liquid crystal panel while increasing the liquid crystal margin, may be prevented, thereby improving display quality of the liquid crystal display panel.

Although the detailed description of the present invention described above has been described with reference to a preferred embodiment of the present invention, those skilled in the art or those with ordinary knowledge in the technical field, the present invention described in the claims to be described later It is apparent that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention.

Claims (10)

A thin film transistor substrate on which a thin film transistor array is formed; A color filter substrate on which a color filter array is formed and which faces the thin film transistor substrate; A column spacer formed on the color filter substrate and maintaining a cell gap between the thin film transistor substrate and the color filter substrate; and a lower end of the column spacer inserted into the thin film transistor substrate and having a concave-convex surface. A liquid crystal display panel characterized by the above. The method of claim 1, The fixing groove may include a first fixing groove having a first depth for each pixel; And a second fixing groove formed to a second depth. The method of claim 2, The density of the unevenness formed in the second fixing groove is greater than the density of the unevenness formed in the first fixing groove. The method of claim 2, And the first depth is less than or equal to 2000 microns, and the second depth is greater than or equal to the first depth and less than or equal to 5000 microns. Providing a thin film transistor substrate having a thin film transistor array including a fixing groove into which a bottom of the column spacer is inserted; Providing a color filter substrate comprising the column spacer and having a color filter array formed thereon; In the bonding of the thin film transistor substrate and the color filter substrate, Preparing the thin film transistor substrate Forming a gate pattern including a gate line and a gate electrode on the insulating substrate; Forming a gate insulating layer, an active layer, and an ohmic contact layer after forming the gate pattern; Forming a data pattern including a data line, a source electrode, and a drain electrode after forming the gate insulating layer, the active layer, and the ohmic contact layer; Forming a passivation layer after forming the data pattern; Forming a contact hole penetrating through the passivation layer and a fixing groove into which a lower end of the column spacer is inserted; And forming a pixel electrode connected to the thin film transistor on the protective film. The method of claim 5, wherein Forming the fixing groove And forming a first fixing groove having a first depth and a second fixing groove having a second depth for each pixel using a slit mask. The method of claim 6, And forming a depth of the first fixing groove less than or equal to 2000 μs, and forming a depth of the second fixing groove larger than the first depth and less than or equal to 5000 μs. The method of claim 7, wherein The density of the irregularities formed in the second fixing groove is greater than the density of the irregularities formed in the first fixing groove. The method of claim 8, A method of manufacturing a liquid crystal display panel using the slit mask to form irregularities in the lower surfaces of the first and second fixing grooves. The method of claim 9, The unevenness of the liquid crystal display panel comprising the step of forming using any one of the mask pattern formed in the form of a stripe or lattice.

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