CN107132710B - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
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- CN107132710B CN107132710B CN201710347790.4A CN201710347790A CN107132710B CN 107132710 B CN107132710 B CN 107132710B CN 201710347790 A CN201710347790 A CN 201710347790A CN 107132710 B CN107132710 B CN 107132710B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
Abstract
The invention provides an array substrate, a preparation method thereof and a display panel, belongs to the technical field of display, and can solve the problem that light leakage is generated at intervals of an existing storage capacitor electrode line and a data line in the horizontal direction. In the array substrate, the data line and the shading metal line which are mutually insulated are arranged on the same layer on the insulating layer, so that even if the data line has deviation in the photoetching process, the light leakage phenomenon can not be generated due to the shading metal line; the shading metal lines on the insulating layer are formed on two sides of the data line, which is equivalent to a step-shaped transition structure, improves the section difference of the two sides of the data line, is beneficial to forming a uniform alignment film, and further prevents the light leakage phenomenon of the two sides of the data line; in addition, the shading metal wire independently exists between the pixel electrode and the storage capacitor electrode wire, so that the size of the storage capacitor can be increased, and the image display quality is improved. The array substrate is suitable for various display devices.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to an array substrate, a preparation method of the array substrate and a display panel.
Background
With the development of display technology, Liquid Crystal Display (LCD) panels are becoming more popular because of their advantages of portability, low radiation, etc. The liquid crystal display panel includes a color filter substrate (CF substrate) and an array substrate (TFT substrate) which are opposed to each other, and a liquid crystal layer (LC layer) interposed therebetween.
Fig. 1 is a schematic plan view of a liquid crystal display panel, fig. 2 is a schematic cross-sectional view taken along line AB in fig. 1, and fig. 3 is a schematic cross-sectional view taken along line CD in fig. 1. the liquid crystal display panel has a glass substrate 100 of an array substrate provided with a plurality of scan lines 112 and data lines 151, the plurality of scan lines 112 and the plurality of data lines 151 are arranged to intersect with each other to define a plurality of pixel regions, and a Thin Film Transistor (TFT) is provided near the intersection of the scan lines 112 and the data lines 151, the TFT is composed of a gate electrode 102, a source electrode 105, a drain electrode 106 and an active layer 104, wherein the source electrode 105 is electrically connected to the data lines 151, the drain electrode 106 is electrically connected to the pixel electrode 108 through a via 171, and the gate electrode 102.
Each pixel electrode 108 is controlled by a thin film transistor, when the thin film transistor is turned on, the pixel electrode 108 is charged in the turn-on time, and after the charging is finished, the voltage of the pixel electrode 108 is maintained until the next scanning is carried out for recharging. Since the liquid crystal capacitance (Clc) is not large and the voltage of the pixel electrode 108 cannot be maintained only by the liquid crystal capacitance, it is necessary to provide a storage capacitance (Cs) for maintaining the voltage of the pixel electrode 108. The liquid crystal display panel further includes a storage capacitor electrode line 121 on the glass substrate 100 of the array substrate, and the storage capacitor electrode line 121 functions as a storage capacitor with the pixel electrode 108 to maintain a voltage applied to the pixel electrode 108. In general, there are two main types of storage capacitors: namely, the storage point is connected to the Gate line (Cs on Gate) and the storage capacitor is connected to the common electrode line (Cs on common), which shows the structure of the storage capacitor on the common electrode line.
As shown in fig. 1 to 3, the storage capacitor electrode line 121, the gate electrode 102 of the TFT and the scan line 112 are in the same layer, and they may be made of the same material in the same process. In the figure, a gate insulating layer 3 is disposed between the storage capacitor electrode line 121 and the data line 151, the storage capacitor electrode line 121 extends along the direction of the data line 151, and a groove is formed in the storage capacitor at a position corresponding to the data line 151, as shown in fig. 4, the storage capacitor electrode line 121 is disposed on the left and right sides of the data line 151 and does not overlap with the data line 151 (refer to fig. 2), so as to reduce the parasitic capacitance between the storage capacitor electrode line 121 and the data line 151. In this way, since the storage capacitor electrode lines 121 and the data lines 151 are spaced apart from each other in the horizontal direction, in order to prevent light from the backlight from passing through, the liquid crystal display panel needs to fabricate a wider light shielding layer 21 on the color film substrate 20.
The inventor finds that at least the following problems exist in the prior art: as shown in fig. 2, assuming that the storage capacitor electrode lines 121 and the data lines 151 are spaced apart from each other by a distance d in the horizontal direction, since alignment is required in the photolithography process between different layers in the manufacturing process of the array substrate and there is alignment deviation, in the actual manufacturing process, the distance between the storage capacitor electrode lines 121 and the data lines 151 spaced apart from each other in the horizontal direction may be deviated, and if the deviation is large, the leaked light will be observed when the human eye is located at G. Meanwhile, as shown in fig. 2, since the data line 151 has a certain level difference, the passivation layer 107 also has a level difference on both sides of the data line 151, and when the alignment film is formed subsequently, the alignment film at the bottom of the level difference (e.g., at the region E) on both sides of the data line 151 is not easily brushed out of the alignment groove, which may aggravate the light leakage phenomenon of the display panel on both sides of the data line 151, and thus the brightness and chromaticity of the display panel are not uniform, which may affect the image quality.
In order to avoid light leakage and reduce the width of the light-shielding layer 21, a structure as shown in fig. 5 is proposed in the prior art, in fig. 5, the storage capacitor electrode lines 121 extending along the data lines 151 span the width of the entire data lines 151, the data lines 151 are located right above the storage capacitor electrode lines 121, and the line width of the data lines 151 is smaller than the line width of the storage capacitor electrode lines 121, so that the data lines 151 are overlapped right above the storage capacitor electrode lines 121. The pixel structure can reduce the width of the light-shielding layer 21, which is beneficial to improving the aperture ratio of the pixel, but the signal delay is increased due to the large parasitic capacitance generated between the data line 151 and the storage capacitor electrode line 121, which has a negative effect on the display image quality.
Disclosure of Invention
The invention provides an array substrate, a preparation method thereof and a display panel, aiming at the problem that light leakage is generated at the interval of the existing storage capacitor electrode wire and the existing data wire in the horizontal direction.
The technical scheme adopted for solving the technical problem of the invention is as follows:
an array substrate comprises a substrate, wherein a storage capacitor electrode wire and an insulating layer covering the storage capacitor electrode wire are arranged on the substrate, a data wire and a shading metal wire which are mutually insulated are arranged on the same layer on the insulating layer, and the shading metal wire is arranged on two sides of the data wire.
Preferably, an orthogonal projection of the data line on the substrate and an orthogonal projection of the storage capacitor electrode line on the substrate have no overlapping area.
Preferably, the data line includes a plurality of layers of conductive structures sequentially arranged, wherein a material of the conductive structure close to the insulating layer is easily etched by a dry method compared with a material of the conductive structure far away from the insulating layer, and the conductive structure close to the insulating layer is on the same layer as the light-shielding metal line.
Preferably, the data line includes a first conductive line and a second conductive line sequentially disposed, the first conductive line being disposed closer to the insulating layer than the second conductive line; the first conductive line is composed of Al, and the second conductive line is composed of Mo.
Preferably, the data line is disposed in parallel with the light shielding metal line.
Preferably, in a plane on which the same side of the data line and parallel to the substrate are located, a distance from a side of the light-shielding metal line far away from the data line to the data line is smaller than a distance from a side of the storage capacitor electrode line far away from the data line to the data line.
Preferably, in a direction parallel to a plane of the substrate and extending perpendicular to the data lines, a dimension between the light-shielding metal line and the data lines is d1, a dimension between the storage capacitor electrode line and the data lines is d, and d1 ≦ d.
The invention also provides a preparation method of the array substrate, which comprises the following preparation steps:
forming a storage capacitor electrode line on a substrate;
forming an insulating layer covering the storage capacitor electrode line on the substrate;
forming a data line and a light shielding metal line insulated from each other on the insulating layer; wherein, the shading metal wire is arranged at two sides of the data wire.
Preferably, the forming of the data line and the light shielding metal line insulated from each other includes:
forming a first conductive layer on the insulating layer;
forming a second conductive layer on the first conductive layer;
and forming a shading metal line and a first conductive line on the first conductive layer by adopting a half-tone process, and forming a second conductive line on the second conductive layer.
The invention also provides a display panel which comprises a color film substrate and the array substrate.
Preferably, a shading layer is arranged on the color film substrate, and the orthographic projection of the shading metal wire on the substrate falls within the orthographic projection range of the shading layer on the substrate.
In the array substrate, the data line and the shading metal line which are mutually insulated are arranged on the same layer on the insulating layer, so that even if the data line has deviation in the photoetching process, the light leakage phenomenon can not be generated due to the shading metal line; the shading metal lines on the insulating layer are formed on two sides of the data line, which is equivalent to a step-shaped transition structure, improves the section difference of the two sides of the data line, is beneficial to forming a uniform alignment film, and further prevents the light leakage phenomenon of the two sides of the data line; in addition, the shading metal wire independently exists between the pixel electrode and the storage capacitor electrode wire, so that the size of the storage capacitor can be increased, and the image display quality is improved. The array substrate is suitable for various display devices.
Drawings
FIGS. 1-5 are schematic diagrams of a conventional LCD panel structure;
fig. 6 is a schematic structural view of an array substrate according to embodiment 1 of the present invention;
fig. 7 and 8 are schematic structural views of an array substrate according to embodiment 2 of the present invention;
fig. 9 and 10 are schematic views illustrating a process for manufacturing an array substrate according to embodiment 3 of the present invention;
fig. 11 is a schematic view of a display panel structure according to embodiment 4 of the present invention;
wherein the reference numerals are: 100. a glass substrate; 102. a gate electrode; 103. an insulating layer; 104. an active layer; 105. a source electrode; 106. a drain electrode; 107. a passivation layer; 108. a pixel electrode; 112. scanning a line; 151. a data line; 121. a storage capacitor electrode line; 171. a via hole; 20. a color film substrate; 21. a light-shielding layer; 40. a photoresist film layer; 41. a light-shielding metal wire; 421. a first conductive line; 422. a second conductive line; 431. a first conductive layer; 432. a second conductive layer.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Example 1:
the embodiment provides an array substrate, as shown in fig. 6, the array substrate includes a substrate, the substrate is a glass substrate 100, a storage capacitor electrode line 121 is disposed on the substrate, and an insulating layer 103 covering the storage capacitor electrode line 121, a data line 151 and a light-shielding metal line 41 that are insulated from each other are disposed on the insulating layer 103 at the same layer, and the light-shielding metal line 41 is disposed on two sides of the data line 151.
In the array substrate of the embodiment, the data line 151 and the light-shielding metal line 41 which are insulated from each other are arranged on the insulating layer 103 in the same layer, so that even if the data line 151 has an offset in the photolithography process, the light leakage phenomenon cannot be generated due to the light-shielding metal line 41; the shading metal lines 41 on the insulating layer 103 are formed on both sides of the data line, which is equivalent to a step-shaped transition structure, so that the step difference between both sides of the data line 151 is improved, a uniform alignment film is formed, and the light leakage phenomenon generated on both sides of the data line 151 is further prevented; in addition, the light-shielding metal line 41 is independently present between the pixel electrode 108 and the storage capacitor electrode line 121, so that the size of the storage capacitor can be increased, and the image display quality can be improved, because the metal layer is added to the two electrode plates of the capacitor, which is equivalent to two capacitors connected in series, and the distance between the two capacitor electrodes is smaller than that between the two capacitor electrodes, so that the capacitance value is increased. Therefore, the array substrate of the embodiment can greatly improve the brightness and the chromaticity of the display panel, thereby improving the image quality.
Example 2:
the embodiment provides an array substrate, as shown in fig. 7, the array substrate includes a substrate, the substrate is a glass substrate 100, two storage capacitor electrode lines 121 and an insulating layer 103 covering the storage capacitor electrode lines 121 are disposed on the glass substrate 100, a data line 151 and two light-shielding metal lines 41 that are insulated from each other are disposed on the insulating layer 103 at the same layer, the two light-shielding metal lines 41 are disposed on two sides of the data line 151, a passivation layer 107 covers the data line 151 and the light-shielding metal lines 41, and a pixel electrode 108 is disposed on the passivation layer 107. Wherein, the orthographic projection of the data line 151 on the substrate and the orthographic projection of the storage capacitor electrode line 121 on the substrate have no overlapping area.
Referring to the cross-sectional view of fig. 7, for clarity, simplified drawings are adopted in the drawings, film layers of irrelevant parts are omitted, only film layers of relevant parts are shown, and there is no overlapping area between the data lines 151 and the orthographic projections of the storage capacitor electrode lines 121 on the glass substrate 100, so that no parasitic capacitance is generated between the data lines 151 and the storage capacitor electrode lines 121, signal delay is not increased, and negative effects on display image quality are not caused.
As an alternative implementation in this embodiment, the thickness of the data line 151 is different from the thickness of the light-shielding metal line 41 (herein, the dimension in the direction perpendicular to the substrate), the thickness of the data line 151 may be 400nm to 500nm, and the thickness of the light-shielding metal line 41 can achieve the purpose of shielding light; the thickness of the light-shielding metal line 41 lower than that of the data line 151 functions to: firstly, reduce material cost, secondly constitute the transition structure of step form, improve data line 151 both sides section difference, do benefit to and form even alignment film, further prevent that the part on data line 151 both sides from producing the phenomenon of light leak.
Preferably, the data line 151 includes a plurality of conductive structures sequentially arranged, wherein a material of the conductive structure close to the insulating layer 103 is easier to be dry etched than a material of the conductive structure far from the insulating layer 103, and the conductive structure close to the insulating layer 103 is on the same layer as the light-shielding metal line 41.
That is, the data line 151 may be formed of two, three or more layers, and a preferred embodiment is given here: the scheme with different thicknesses is realized by using different dry etching degrees of different materials, that is, the material of the conductive structure close to the insulating layer 103 is easy to be dry etched, the material of the conductive structure far away from the insulating layer 103 is relatively difficult to be dry etched, and the conductive structure close to the insulating layer 103 and the light-shielding metal wire 41 are formed in the same layer, so that the preparation process is saved.
Preferably, referring to fig. 8, the data line 151 includes a first conductive line 421 and a second conductive line 422 sequentially disposed, the first conductive line 421 being disposed closer to the insulating layer 103 than the second conductive line 422; the first conductive line 421 is made of Al, and the second conductive line 422 is made of Mo.
That is, the second conductive line 422 of the upper metal layer is a metal Mo layer having a thickness of about 250nm, and the first conductive line 421 of the lower metal layer is a metal Al layer having a thickness of about 250 nm. It should be noted that, the metal Al layer has very strong dry etching resistance, because in the oxygen plasma environment, a layer of Al is generated on the surface of the metal Al layer2O3Layer of Al2O3Is a ceramic material and is hardly dry etched, so that the metal Al of the bottom layer can be protected from being damaged by plasma.
Preferably, the data line 151 is disposed in parallel with the light shielding metal line 41.
That is, the data lines 151 and the light-shielding metal lines 41 are wired in parallel in a plan view.
Preferably, on the same side of the data line 151 and in a plane parallel to the substrate, a distance from a side of the light-shielding metal line 41 away from the data line 151 to the data line 151 is smaller than a distance from a side of the storage capacitor electrode line 121 away from the data line 151 to the data line 151.
That is, d2 is greater than or equal to 0 in fig. 8, that is, the edge of the outer side of the light-shielding metal line 41 is not beyond the outer side of the storage capacitor electrode line 121, so that the aperture ratio is not increased.
Preferably, in a direction parallel to a plane of the substrate and extending perpendicular to the data lines 151, a dimension between the light-shielding metal line 41 and the data lines 151 is d1, a dimension between the storage capacitor electrode line 121 and the data lines 151 is d, and d1 ≦ d.
When d1 < d, the shielding effect for the bottom backlight is better, and the coupling capacitance between the data line 151 and the storage capacitor electrode line 121 is not increased.
Example 3:
the embodiment provides a method for manufacturing an array substrate, as shown in fig. 9 and 10, including the following steps:
s01, forming storage capacitor electrode lines 121 on the glass substrate 100 as a substrate;
s02, forming an insulating layer 103 on the substrate to cover the storage capacitor electrode line 121;
s03, forming a data line 151 and a light-shielding metal line 41 insulated from each other on the insulating layer 103 by magnetron sputtering; wherein the light-shielding metal lines 41 are disposed at both sides of the data lines 151.
Specifically, the formation of the data line 151 and the light-shielding metal line 41 insulated from each other includes the steps of:
s03a, forming a first conductive layer 431 over the insulating layer 103; the first conductive layer 431 is a metal Al layer which is not easily etched by a dry method, and has a thickness of about 250 nm;
s03b, forming a second conductive layer 432 over the first conductive layer 431; the second conductive layer 432 is a metal Mo layer which is easy to be etched by a dry method, and the thickness is about 250 nm;
s03c, the light-shielding metal line 41 and the first conductive line 421 are formed on the first conductive layer 431 by using a halftone process, and the second conductive line 422 is formed on the second conductive layer 432. The specific steps of S03c are as follows:
and coating a photoresist film layer 40 on the upper surface of the metal Mo layer by a coating method.
The method comprises the steps of utilizing a Halftone process (Halftone Mask) technology to manufacture photoresist Mask patterns of the data lines 151 in an exposure and development mode, wherein the photoresist Mask patterns of the data lines 151 comprise photoresist complete retention areas, photoresist semi-retention areas and photoresist complete removal areas, and the photoresist semi-retention areas are symmetrically distributed on two sides of the photoresist complete retention areas and are mutually disconnected. It should be noted that the photoresist mask pattern also includes the photoresist mask pattern of the source and drain electrodes of the TFT area in the array substrate, and the photoresist mask pattern of the source and drain electrodes of the TFT area does not include the photoresist half-reserved area. That is, the photoresist mask pattern in the region of the data line 151 in fig. 9 is only a portion of the photoresist mask pattern.
And performing wet etching on the metal layer by taking the photoresist mask pattern as an anti-etching layer, namely etching the metal Mo layer and the metal Al layer by using an etching solution at the same time, wherein the area where the metal Mo and the metal Al are overlapped after the etching is finished forms a data line 151 of the array substrate.
Using an ICP etching apparatus, using O2And performing ashing treatment to ash the photoresist mask pattern, wherein after the ashing is completed, the photoresist semi-reserved area is completely removed, and only the photoresist completely-reserved area is left in the data line 151 area of the photoresist mask pattern.
Adopting ICP equipment cavity, taking photoresist complete reserved area as anti-etching layer, taking SF as anti-etching layer6And O2In order to etch the Mo metal layer by the etching gas, the light-shielding metal lines 41 on both sides of the data line 151 are only left with the bottom Al metal layer after the etching. It should be noted that, in this step, the layer of Al is formed on the surface of the metal Al in the plasma environment because the layer of Al is very resistant to dry etching2O3Layer of Al2O3Is a ceramic material and is hardly dry etched, so that the metal Al of the bottom layer can be protected from being damaged by plasma.
The photoresist mask pattern of the entire array substrate is stripped off, including the photoresist full-remaining region in the data line 151 region.
S04, depositing and growing the silicon nitride passivation layer 107 by PECVD, patterning the silicon nitride passivation layer 107, and then sequentially fabricating and patterning the transparent pixel electrode 108, wherein the transparent pixel electrode 108 is electrically connected to the drain electrode (not shown) of the TFT through the via 171 (not shown) of the passivation layer 107. At this time, because the two sides of the data line 151 formed by overlapping the metal Mo and the metal Al are provided with the independent metal Al layers, the two sides of the data line 151 form a step-shaped transition structure, so that the step difference between the two sides of the data line 151 formed by overlapping the metal Mo and the metal Al is reduced, the friction alignment of the alignment film at the bottom of the step difference between the two sides of the data line 151 is facilitated, and the phenomenon that the display panel generates light leakage at the two sides of the data line 151 is improved; meanwhile, the distance between the independent metal Al layers on the two sides of the data line 151 and the data line 151 (formed by overlapping metal Mo and metal Al) is d1, and d1 is less than or equal to d, so that the data line 151 manufactured in the groove of the storage capacitor electrode line 121 cannot generate serious light leakage even if the data line deviates in the photolithography process due to shielding of the independent metal Al layers on backlight light. Finally, the independent metal aluminum layer between the pixel electrode 108 and the storage capacitor line, which is the storage capacitor, can increase the size of the storage capacitor and improve the image display quality, because the metal layer is added to the two electrode plates of the capacitor, which is equivalent to reducing the distance between the capacitor electrodes, so the capacitance value will increase. The three points are superposed together, so that the brightness and the chromaticity of the display panel can be greatly improved, and the image quality is further improved.
Example 4:
the present embodiment provides a display panel, as shown in fig. 11, including a color film substrate 20 and the array substrate.
Preferably, a light-shielding layer 21 is arranged on the color filter substrate 20, and an orthographic projection of the light-shielding metal line 41 on the substrate falls within an orthographic projection range of the light-shielding layer 21 on the substrate.
Obviously, many variations are possible in the specific implementation of the above-described embodiments; for example: the specific material of shading metal wire can be selected according to actual need, and the specific size of shading metal wire can be changed according to product actual conditions.
Example 5:
the present embodiment provides a display device including any one of the display panels described above. The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal display panel, electronic paper, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (7)
1. An array substrate is characterized by comprising a substrate, wherein a storage capacitor electrode wire and an insulating layer covering the storage capacitor electrode wire are arranged on the substrate, a data wire and a shading metal wire which are mutually insulated are arranged on the same layer on the insulating layer, the shading metal wire is arranged on two sides of the data wire, the data wire comprises a plurality of layers of conductive structures which are sequentially arranged, wherein the material of the conductive structure close to the insulating layer is not easy to be etched by a dry method compared with the material of the conductive structure far away from the insulating layer, and the conductive structure close to the insulating layer and the shading metal wire are on the same layer; the orthographic projection of the data line on the substrate and the orthographic projection of the storage capacitor electrode line on the substrate do not have an overlapping area;
in the direction parallel to the plane of the substrate and perpendicular to the extension direction of the data lines, the size between the light-shielding metal line and the data lines is d1, the size between the storage capacitor electrode line and the data lines is d, and d1 is not less than d.
2. The array substrate of claim 1, wherein the data lines comprise a first conductive line and a second conductive line sequentially disposed, and the first conductive line is disposed closer to the insulating layer than the second conductive line; the first conductive line is composed of Al, and the second conductive line is composed of Mo.
3. The array substrate of claim 1, wherein the data lines are disposed parallel to the light-shielding metal lines.
4. The array substrate of claim 3, wherein a distance from a side of the light-shielding metal line far away from the data line to the data line is smaller than a distance from a side of the storage capacitor electrode line far away from the data line to the data line in a plane parallel to the substrate on the same side of the data line.
5. The preparation method of the array substrate is characterized by comprising the following preparation steps of:
forming a storage capacitor electrode line on a substrate;
forming an insulating layer covering the storage capacitor electrode line on the substrate;
forming a data line and a light shielding metal line insulated from each other on the insulating layer; the shading metal lines are arranged on two sides of the data line, the data line comprises a plurality of layers of conductive structures which are sequentially arranged, the material of the conductive structure close to the insulating layer is difficult to dry-etch compared with the material of the conductive structure far away from the insulating layer, and the conductive structure close to the insulating layer and the shading metal lines are on the same layer; in the direction parallel to the plane of the substrate and perpendicular to the extension direction of the data lines, the size between the light-shielding metal line and the data lines is d1, the size between the storage capacitor electrode line and the data lines is d, and d1 is not less than d;
the data line includes a first conductive line and a second conductive line which are sequentially arranged, the first conductive line is arranged closer to the insulating layer than the second conductive line, and the forming of the data line and the light-shielding metal line which are insulated from each other includes the steps of:
forming a first conductive layer on the insulating layer;
forming a second conductive layer on the first conductive layer;
and forming a shading metal line and a first conductive line on the first conductive layer by adopting a half-tone process, and forming a second conductive line on the second conductive layer.
6. A display panel comprising a color filter substrate and the array substrate according to any one of claims 1 to 4.
7. The display panel according to claim 6, wherein a light-shielding layer is disposed on the color filter substrate, and an orthogonal projection of the light-shielding metal line on the substrate falls within an orthogonal projection range of the light-shielding layer on the substrate.
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| CN107918234B (en) * | 2017-11-17 | 2020-08-04 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, liquid crystal display panel and liquid crystal display device |
| CN108039339A (en) | 2017-12-21 | 2018-05-15 | 惠科股份有限公司 | Production method, array base palte and the liquid crystal display panel of array base palte |
| CN107942595B (en) | 2017-12-21 | 2024-03-29 | 惠科股份有限公司 | Array substrate and manufacturing method thereof, liquid crystal display panel and manufacturing method thereof |
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| TWI728909B (en) * | 2020-09-02 | 2021-05-21 | 凌巨科技股份有限公司 | Structure of pixel |
| CN112185891B (en) * | 2020-09-28 | 2023-05-30 | 成都京东方显示科技有限公司 | Manufacturing method of array substrate, array substrate and display panel |
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| KR20060059481A (en) * | 2004-11-29 | 2006-06-02 | 삼성전자주식회사 | Array substrate having enhanced aperture ratio, method of manufacturing the same and liquid crystal display apparatus having the same |
| KR20080015696A (en) * | 2006-08-16 | 2008-02-20 | 삼성전자주식회사 | Liquid crystal display |
| CN101398585B (en) * | 2007-09-27 | 2011-06-01 | 北京京东方光电科技有限公司 | Array substrate of LCD |
| CN101840116B (en) * | 2009-03-16 | 2014-02-26 | 北京京东方光电科技有限公司 | TFT-LCD (Thin Film Transistor-Liquid Crystal Diode) array substrate and manufacture method thereof |
| CN105629612B (en) * | 2016-03-14 | 2019-04-05 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and preparation method thereof |
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