CN111490055A

CN111490055A - Pixel array substrate

Info

Publication number: CN111490055A
Application number: CN202010150797.9A
Authority: CN
Inventors: 吴炘儒; 陈韦洁; 杨智钧; 李冠谊
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-09-11
Filing date: 2020-03-06
Publication date: 2020-08-04
Anticipated expiration: 2040-03-06
Also published as: TW202111397A; TWI699581B; CN111490055B

Abstract

A pixel array substrate including a substrate, a first signal line, a first pixel, an insulating layer, an organic layer, and a light blocking pattern is provided. The first pixel comprises a first active element and a first pixel electrode which are electrically connected with each other. The first active element is electrically connected with the first signal line. The insulating layer has a first opening overlapping the first signal line. The first signal line has a first surface defining a first opening. The organic layer has a second opening connected to the first opening, a bottom surface defining the first opening, and a sidewall defining the second opening. The shading pattern covers the first surface, the side wall and the bottom surface and is provided with a first part positioned in the first opening and a second part positioned in the second opening and protruding out of the organic layer. The first portion and the second portion have a first width and a second width, respectively, and the first width is greater than the second width.

Description

Pixel array substrate

Technical Field

The invention relates to a display panel, and more particularly to a pixel array substrate.

Background

With the rapid development of the technology industry, display devices such as mobile phones (mobile phones), tablet computers (tablet computers), and electronic books (ebooks) have been widely used in daily life. In particular, in recent years, with the advent of multimedia applications such as stereoscopic display (stereoscopic display) and virtual reality (visual reality), there has been an increasing demand for display panels having ultra-high resolution in order to provide an amazing visual effect.

However, as the resolution of the display panel is continuously increased, the layout space of the driving circuit is not sufficient, and the aperture ratio of the pixel is decreased. Therefore, how to maintain the existing cost advantage while improving the resolution and the pixel aperture ratio of the display panel is one of the difficulties that the related manufacturers have attempted to overcome.

Disclosure of Invention

The invention provides a pixel array substrate with a high pixel aperture ratio.

The pixel array substrate comprises a substrate, a first signal line, a first pixel, an insulating layer, an organic layer and a shading pattern. The first signal line and the first pixel are arranged on the substrate. The first pixel comprises a first active element and a first pixel electrode which are electrically connected with each other. The first active element is electrically connected with the first signal line. The insulating layer covers the substrate and has a first opening overlapping the first signal line. The first signal line has a first upper surface defining a first opening. The organic layer is disposed on the insulating layer and has a second opening communicated with the first opening. The organic layer has a bottom surface defining the first opening and a sidewall defining the second opening, and the bottom surface is connected to the sidewall. The shading pattern covers the first upper surface of the first signal line and the side wall and the bottom surface of the organic layer, and is provided with a first part positioned in the first opening and a second part positioned in the second opening and protruding out of the organic layer. The first portion and the second portion have a first width and a second width, respectively, and the first width is greater than the second width.

In an embodiment of the invention, the first portion and the second portion of the light shielding pattern of the pixel array substrate are made of the same material.

In an embodiment of the invention, the pixel array substrate further includes a spacer disposed on the substrate. A first height is formed between the first top surface of the shading pattern and the upper surface of the substrate. A second height is formed between the spacer and the upper surface of the substrate, and the first height is smaller than the second height.

In an embodiment of the invention, the light-shielding pattern of the pixel array substrate and the spacer belong to the same film layer.

In an embodiment of the invention, the organic layer of the pixel array substrate is a stacked structure of a color filter layer and an organic insulating layer. The organic insulating layer covers the color filter layer and is provided with a side wall for defining the second opening.

In an embodiment of the invention, the insulating layer of the pixel array substrate is a laminated structure of a first sub-insulating layer and a second sub-insulating layer. The first sub-insulating layer is located between the substrate and the first signal line. The second sub-insulating layer is located between the first signal line and the organic layer, and the first opening penetrates through the second sub-insulating layer.

In an embodiment of the invention, the first opening of the pixel array substrate further penetrates through the first sub-insulating layer. The first signal line further has a first lower surface defining the first opening and a first side surface connecting the first upper surface and the first lower surface, and the light shielding pattern further covers the first lower surface and the first side surface of the first signal line.

In an embodiment of the invention, the pixel array substrate further includes a second signal line and a second pixel. The second signal line is adjacent to the first signal line and arranged on the substrate in parallel. The second signal line has a second upper surface defining the first opening, and the light shielding pattern further covers the second upper surface of the second signal line. The second pixel comprises a second active element and a second pixel electrode which are electrically connected with each other. The second active element is electrically connected with the second signal wire. The first signal line and the second signal line are positioned between the first pixel and the second pixel, and the shading pattern is positioned between the first signal line and the second signal line.

In an embodiment of the invention, the first opening of the pixel array substrate further penetrates through the first sub-insulating layer. The first signal line also has a first lower surface defining a first opening and a first side surface connecting the first upper surface and the first lower surface. The second signal line further has a second lower surface defining the first opening and a second side surface connecting the second upper surface and the second lower surface, and the light shielding pattern further covers the first lower surface and the first side surface of the first signal line and the second lower surface and the second side surface of the second signal line.

In an embodiment of the invention, the organic layer of the pixel array substrate is a color filter layer.

In view of the above, in the pixel array substrate according to an embodiment of the invention, the insulating layer and the organic layer respectively have the first opening and the second opening which are communicated, and the first signal line electrically connected to the active element of the pixel overlaps with the two openings. By making the width of the second portion of the light-shielding pattern in the second opening smaller than the width of the first portion of the light-shielding pattern in the first opening, the space for laying out the pixel electrode of the pixel can be increased, which is helpful to improve the Aperture Ratio (AR) of the pixel.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

Fig. 1 is a top view of a pixel array substrate according to a first embodiment of the invention.

Fig. 2A to 2E are cross-sectional views illustrating a manufacturing process of the pixel array substrate of fig. 1.

Fig. 2F is a cross-sectional view of a display panel using the pixel array substrate of fig. 2E.

Fig. 3 is a cross-sectional view of a pixel array substrate according to a second embodiment of the present invention.

Fig. 4 is a cross-sectional view of a pixel array substrate according to a third embodiment of the present invention.

Fig. 5 is a top view of a pixel array substrate according to a fourth embodiment of the invention.

Fig. 6 is a cross-sectional view of the pixel array substrate of fig. 5.

Fig. 7 is a cross-sectional view of a pixel array substrate according to a fifth embodiment of the present invention.

Wherein, the reference numbers:

1: display panel

10. 11, 12, 20, 21: pixel array substrate

101. 201: substrate

101 s: upper surface of

110: insulating layer

110a, 110 a-1: first opening

111: first sub-insulating layer

112: second sub-insulating layer

115: contact window

120: organic layer

120a, 120 a-1: second opening

120s 1: side wall

120s 2: bottom surface

121: color filter layer

121 a: slotting

121 b: opening holes

1211. 1212: color filter pattern

122: organic insulating layer

122M: layer of organic insulating material

130. 130A, 130B, 130C, 130D: shading pattern

130As, 130Ds, 135 s: the top surface

130M: light-shielding material layer

131. 131A, 131B: the first part

132. 132A, 132B: the second part

135: spacer

210: driving electrode

C L shared line

D. D1, D2: drain electrode

D L, D L1, D L2 data line

D L a, D L1 a, D L2 a upper surface

D L b, D L1 b, D L2 b lower surface

D L c, D L1 c, D L2 c side

DM: display medium layer

G: grid electrode

H1: first height

H2: second height

OC: ohmic contact layer

PE: pixel electrode

PEa: the first sub-part

PEb: the second sub-part

PX, PX1, PX 2: pixel

S: source electrode

SC: semiconductor pattern

S L scanning line

T, T': active element

W1, W': first width

W2: second width

X, Y: direction of rotation

A-A ', B-B ', C-C ': cutting line

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

as used herein, "about," "approximately," "essentially," or "substantially" includes the average of the stated value and a specified value within an acceptable range of deviation from the stated value, as determined by one of ordinary skill in the art, given the particular number of measurements in question and the errors associated with the measurements (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated values, or, for example, ± 30%, ± 20%, ± 15%, ± 10%, ± 5%. Further, as used herein, "about", "approximately", "essentially", or "substantially" may be selected based on the measured property, cleavage property, or other property to select a more acceptable range of deviation or standard deviation, and not one standard deviation may apply to all properties.

In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected" to another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, an "electrical connection" may be the presence of other elements between the two elements.

Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "above" or "below" may include both an orientation of above and below.

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1 is a top view of a pixel array substrate according to a first embodiment of the invention. Fig. 2A to 2E are cross-sectional views illustrating a manufacturing process of the pixel array substrate of fig. 1. FIG. 2E corresponds to section line A-A' of FIG. 1. Fig. 2F is a cross-sectional view of a display panel using the pixel array substrate of fig. 2E. For clarity, fig. 1 omits the illustration of the insulating layer 110, the organic insulating layer 122, the light-shielding pattern 130 and the spacers 135 of fig. 2E. In particular, the pixel array substrate 10 of fig. 2E can be applied to the display panel 1 (as shown in fig. 2F).

Referring to fig. 1 and 2E, the pixel array substrate 10 includes a substrate 101, a plurality of signal lines including a plurality of scan lines S L and a plurality of data lines D L, and a plurality of pixels PX., in the present embodiment, the plurality of signal lines S L intersect with the plurality of data lines D L and define a plurality of pixel regions, a plurality of pixels PX are respectively disposed in the pixel regions and are respectively electrically connected to a corresponding scan line S L and a corresponding data line D L, for example, the plurality of data lines D L are arranged on the substrate 101 along a direction X and extend in the direction Y, wherein the direction X may be substantially perpendicular to the direction Y, the plurality of scan lines S L are arranged on the substrate 101 along the direction Y and extend in the direction X, in the present embodiment, one pixel PX may be disposed between any two adjacent data lines D L, and the pixel PX may be electrically connected to one of the two adjacent data lines D L, but the present invention is not limited thereto.

In the present embodiment, the pixel array substrate 10 may further optionally include a plurality of common lines C L, for example, the common lines C L may be arranged on the substrate 101 along the direction Y and extend in the direction X, that is, the common lines C L0 may be selectively parallel to the scan lines S L, for example, based on the consideration of conductivity, the data lines D L, S L, and C L are generally made of a metal material, however, the present invention is not limited thereto, and according to other embodiments, the data lines D L, S L, and C L may also be made of other conductive materials, such as an alloy, a nitride of a metal material, an oxide of a metal material, or other suitable materials, or a stack layer of a metal material and other conductive materials.

Further, the pixel PX includes an insulating layer 110, an active device T, and a pixel electrode PE., wherein the insulating layer 110 includes a first sub-insulating layer 111 and a second sub-insulating layer 112, the first sub-insulating layer 111 covers the scan line S L, the second sub-insulating layer 112 covers a portion of the surface of the first sub-insulating layer 111, the data line D L, and the active device T, in this embodiment, the first sub-insulating layer 111 and the second sub-insulating layer 112 may be one or more inorganic insulating layers, and the material of the inorganic insulating layer includes silicon oxide (SiO2), silicon nitride (SiNx), silicon nitride oxide (SiOxNy; x > y), silicon oxynitride (SiNxOy; x > y), or other suitable inorganic insulating materials.

For example, the method of forming the active device T may include sequentially forming a gate G, a first sub-insulating layer 111, a semiconductor pattern SC, an ohmic contact layer OC, a source S and a drain D on the substrate 101, wherein the source S and the drain D are electrically connected to two different regions of the semiconductor pattern SC through the ohmic contact layer OC (e.g., two ohmic contact patterns), respectively, the source S and the drain D of the active device T are electrically connected to the data line D L and the pixel electrode PE., respectively.

On the other hand, the material of the semiconductor pattern SC is, for example, Amorphous silicon semiconductor (Amorphous silicon semiconductor) material, that is, the active element T may be an Amorphous silicon thin film Transistor (a-Si TFT), however, the invention is not limited thereto, and in other embodiments, the active element may also be a low temperature polysilicon thin film Transistor (L TPS TFT), a micro silicon thin film Transistor (micro-Si TFT) or a metal oxide Transistor (metal oxide Transistor).

In the present embodiment, the source S and the drain D of the active device T and the data line D L may be selectively made of the same material, and the gate G and the scan line S L of the active device T may be selectively made of the same material, that is, the source S and the drain D of the active device T and the data line D L of the active device T may be formed on the same film, and the gate G and the scan line S L of the active device T may be formed on the same film.

The pixel array substrate 10 further includes an organic layer 120 and a light-shielding pattern 130, the organic layer 120 is disposed on the insulating layer 110, and the light-shielding pattern 130 overlaps the data line D L in the normal direction of the substrate 101. that is, the light-shielding pattern 130 may be disposed between two adjacent pixels PX arranged in the direction X. in this embodiment, the light-shielding pattern 130 may selectively penetrate through the organic layer 120 and the insulating layer 110 to cover the data line D L and a portion of the upper surface 101s of the substrate 101. accordingly, the Optical Density (OD) of the light-shielding pattern 130 in the normal direction of the substrate 101 may be increased, which is helpful to reduce the reflection of the external ambient light (ambient light) by the data line D L, thereby improving the dark state appearance of the display panel.

Further, the insulating layer 110 and the organic layer 120 respectively have a first opening 110a and a second opening 120a overlapping the data line D L, the light-shielding pattern 130 is disposed in the first opening 110a and the second opening 120a and covers the upper surface D L a, the lower surface D L b, and the side surface D L c of the data line D L, wherein the upper surface D L a is opposite to the lower surface D L b, and the side surface D L c is connected between the upper surface D L a and the lower surface D L b, from another point of view, the light-shielding pattern 130 has a first portion 131 located in the first opening 110a and a second portion 132 located in the second opening 120a and protruding out of the organic layer 120, the first portion 131 and the second portion 132 of the light-shielding pattern 130 respectively have a first width W1 and a second width W2 in a direction perpendicular to the substrate normal 101, and the first width W1 of the first portion 131 is greater than the second width W2 of the second portion 132.

It should be noted that, by the disposition relationship between the first portion 131 and the data line D L (for example, in the direction perpendicular to the normal line of the substrate 101, the width of the first portion 131 is greater than the width of the data line D L), the light-shielding effect of the light-shielding pattern 130 (for example, in the direction normal to the substrate 101, the light leakage caused by the poor arrangement of the plurality of liquid crystal molecules in the overlapping region of the pixel electrode PE and the data line D L due to the configuration of the second portion 132 on the surface of the organic layer 120) can be ensured, and therefore, the second width W2 of the second portion 132 of the light-shielding pattern 130 can be effectively reduced, which is helpful to increase the layout space of the pixel electrode PE, and further increase the Aperture Ratio (AR) of the pixel PX.

First, referring to fig. 2A and 2B, after the organic insulating material layer 122M is formed, an etching step is performed to remove a portion of the organic insulating material layer 122M overlapped with the data line D L to form the organic insulating layer 122 of the pixel array substrate 10, and the organic insulating layer 122 is provided with the second opening 120 a. in the present embodiment, the organic layer 120 may be a stacked structure of the color filter layer 121 and the organic insulating layer 122.

In the present embodiment, the material of the organic insulating layer 122 may be a polymer (polymer) or other suitable materials, wherein the polymer includes acrylic resin (acrylic resin), photosensitive resin (photosensitive resin), polyimide (polyimide), or a composite material with the above-mentioned materials as main components, or other suitable materials, or a combination thereof, on the other hand, the color filter layer 121 may have a plurality of color filter patterns, and the color filter patterns are arranged on the substrate 101 along the direction X separately from each other (as shown in fig. 1), in other words, the color filter layer 121 has a slot 121a between any two adjacent color filter patterns (e.g., the first color filter pattern 1211 and the second color filter pattern 1212), and the slot 121a overlaps the data line D L and the second opening 120a in the normal direction of the substrate 101.

Referring to fig. 2B and 2C, after the organic insulating layer 122 is formed, another etching step is performed to remove a portion of the insulating layer 110 overlapping the data line D L in the normal direction of the substrate 101 to form a first opening 110a of the insulating layer 110. in the present embodiment, the first opening 110a of the insulating layer 110 may expose the upper surface D L a, the lower surface D L B and the side surface D L C of the data line D L, but the invention is not limited thereto.

For example, the etching step may be a dry etching (dry etching) process, such as: the portion of the insulating layer 110 exposed by the second opening 120a is etched by using a reactive gas (etching gas) or ions or radicals, and the etching selectivity of the etching gas to the material of the insulating layer 110 is higher than that to the material of the organic layer 120. In other words, the organic layer 120 is less easily etched by the etching gas during the etching of the insulating layer 110. However, the invention is not limited thereto, and according to other embodiments, the etching step of the insulating layer 110 may be performed by wet etching.

During the etching of the insulating layer 110, since the etching gas contacts the insulating layer 110 through the second opening 120a of the organic layer 120 and an etching reaction occurs. Therefore, the first opening 110a etched in the insulating layer 110 is connected to the second opening 120a of the organic layer 120. Particularly, a vertical projection area of the region occupied by the first opening 110a of the insulating layer 110 on the substrate 101 is larger than a vertical projection area of the region occupied by the second opening 120a of the organic layer 120 on the substrate 101.

Referring to fig. 2D, after the etching step of the insulating layer 110 is completed, a light-shielding material layer 130M is formed on the organic layer 120, and the light-shielding material layer 130M fills the first opening 110a of the insulating layer 110 and the second opening 120a of the organic layer 120. specifically, the organic layer 120 has a bottom surface 120s2 defining the first opening 110a and a sidewall 120s1 defining the second opening 120a and connected to the bottom surface 120s2, and the light-shielding material layer 130M covers the sidewall 120s1 and the bottom surface 120s2 of the organic layer 120 and the upper surface D L a, the lower surface D L b and the side surface D L c of the data line D L after filling the first opening 110a and the second opening 120 a.

Then, a photolithography process is performed on the light-shielding material layer 130M to form the light-shielding pattern 130, as shown in fig. 2E, for example, in the step of forming the light-shielding pattern 130, a spacer 135 overlapped on the active device T may be simultaneously formed, that is, the light-shielding pattern 130 and the spacer 135 may belong to the same layer.

It should be noted that the present invention is not limited to the manufacturing method of the light-shielding pattern 130 disclosed in fig. 2A to 2E, but it should be understood by those skilled in the art that the light-shielding pattern 130 of the present embodiment can also be formed through a more complicated manufacturing process, for example, after the insulating layer 110 is formed, the first portion 131 of the light-shielding pattern 130 is first fabricated, and the first portion 131 penetrates through the insulating layer 110 and covers the lower surface D L b of the data line D L, then the organic layer 120 having the second opening 120a is formed, and the second portion 132 of the light-shielding pattern 130 is formed in the second opening 120a, and the material of the first portion 131 and the second portion 132 connected to each other can be the same.

In the present embodiment, the pixel array substrate 10 includes a substrate 101, a data line D L, a pixel PX, an insulating layer 110, an organic layer 120, and a light shielding pattern 130, the data line D L and the pixel PX are disposed on the substrate 101, the pixel PX includes an active device T and a pixel electrode PE electrically connected to each other, and the active device T is electrically connected to a data line D L, the insulating layer 110 has a first opening 110a overlapping with the data line D L, the data line D L has an upper surface D L a defining the first opening 110a, the organic layer 120 is disposed on the insulating layer 110, and has a second opening 120a communicating with the first opening 110a, a bottom 120s2 defining the first opening 110a, and a sidewall 120s s1. and sidewall 120s1 defining the second opening 120a and is connected to the bottom 120s2, the light shielding pattern 130 covers the upper surface D L a of the data line D L and the sidewalls 120s 3985 and 120s 3638 of the organic layer 120, and has a width greater than the width of the first opening 120a, and the width of the second opening 120W 58131 and the width of the first opening 132.

In particular, in the present embodiment, the area occupied by the second opening 120a of the organic layer 120 may completely overlap the data line D L in the normal direction of the substrate 101, and the first opening 110a is mirror-symmetric with respect to the data line D L, but the present invention is not limited thereto.

For example, as shown in fig. 1, a plurality of signal lines (e.g., two data lines D L, a scan line S L, and a common line C L) defining an opening area of a pixel PX may be disposed at a position adjacent to or overlapping a pixel electrode PE of the pixel PX.

Further, the pixel array substrate 10 may be applied to the display Panel 1, as shown in fig. 2F, the display Panel 1 further includes a substrate 201, a driving electrode 210, a display medium layer DM., the substrate 201 is disposed opposite to the pixel array substrate 10, and the driving electrode 210 is disposed on a side surface of the substrate 201 facing the pixel array substrate 10, the display medium layer DM is sandwiched between the driving electrode 210 and the pixel array substrate 10, in this embodiment, the display medium layer DM may include a plurality of liquid crystal molecules, i.e., the display Panel 1 is, for example, a liquid crystal display Panel (liquid crystal display Panel, L CD Panel).

The present invention will be described in detail below with reference to other embodiments, wherein like components are denoted by like reference numerals, and descriptions of the same technical contents are omitted, and reference is made to the foregoing embodiments for omitting details. In particular, the pixel array substrate of the following embodiments can be used to replace the pixel array substrate 10 in the display panel 1.

Fig. 3 is a cross-sectional view of a pixel array substrate according to a second embodiment of the present invention. Referring to fig. 3, the main differences between the pixel array substrate 11 of the present embodiment and the pixel array substrate 10 of fig. 2E are: the configuration of the light shielding pattern is different. In the present embodiment, the light-shielding pattern 130A (or the second portion 132A) and the spacer 135 respectively have a top surface 130As and a top surface 135 s. The top surface 130As of the light shielding pattern 130A and the upper surface 101s of the substrate 101 have a first height H1 therebetween, the top surface 135s of the spacer 135 and the upper surface 101s of the substrate 101 have a second height H2 therebetween, and the first height H1 is smaller than the second height H2.

It should be noted that, when forming the light-shielding material layer, since the insulating layer 110 and the organic layer 120 are respectively provided with the first opening 110a and the second opening 120a, a portion of the film surface of the light-shielding material layer overlapping the second opening 120a may be recessed into another portion of the film surface. Thus, in the patterning process of the light-shielding material layer, the height difference between the light-shielding pattern 130A and the spacer 135 can be formed without using a half-tone (half-tone) mask for exposure. More specifically, in the present embodiment, the light shielding pattern 130A may also have a function of an auxiliary spacer. That is, the height difference between the light-shielding pattern 130A and the spacer 135 can improve the thickness uniformity of the display medium layer, increase the process tolerance (process yield) of the display panel, and contribute to the improvement of the production yield of the display panel.

Referring to fig. 4, the pixel array substrate 12 of the present embodiment is different from the pixel array substrate 10 of fig. 2E in the configuration of the light-shielding pattern, in which the first opening 110a-1 only penetrates through the second sub-insulating layer 112, and the first portion 131 of the light-shielding pattern 130B only covers the upper surface D L a of the data line D L. in other words, the first width W1' of the first portion 131A of the light-shielding pattern 130B is smaller than the first width W1 of the first portion 131 of the light-shielding pattern 130 of the pixel array substrate 10, but still larger than the second width W2 of the second portion 132. accordingly, the second width W2 of the second portion 132 of the light-shielding pattern 130B can be effectively reduced without damaging the light-shielding effect of the light-shielding pattern 130B, which is beneficial for increasing the layout space of the pixel electrode PE, and further increasing the Aperture Ratio (Aperture Ratio AR) of the pixel PX.

Referring to fig. 5 and 6, the main differences between the pixel array substrate 20 of the present embodiment and the pixel array substrate 10 of fig. 1 are that the signal lines and the pixels have different arrangement relationships and the first portion of the light shielding pattern has different configurations, in the present embodiment, two signal lines, namely, a first data line D L1 and a second data line D L2, are disposed between two adjacent pixels (for example, a first pixel PX1 and a second pixel PX2) arranged in the direction X, wherein the first data line D L1 and the second data line D L2 are arranged adjacent to and parallel to the substrate 101, and the first pixel PX1 and the second pixel PX2 are electrically connected to the first data line D L1 and the second data line D L2, respectively.

In the embodiment, the first portion 131B of the light-shielding pattern 130C covers the upper surface D L1 a, the lower surface D L01B, and the side surface D L11C of the first data line D L1, and the upper surface D L2 a, the lower surface D L2B, and the side surface D L2C of the second data line D L2 at the same time, that is, the light-shielding pattern 130C is disposed in the region between the first data line D L1 and the second data line D L2. the first portion 131B covers part of the first data line D L1, part of the second data line D L2, and the region between the two data lines, so as to block light leakage caused by backlight emitting from the region between the two data lines, and increase the layout space of the pixel electrode by shortening the width of the second portion 132 in the direction perpendicular to the substrate normal 101, thereby increasing the Aperture Ratio (AR) of the pixel.

On the other hand, the pixel electrode of each pixel of the present embodiment may be divided into the first sub-portion PEa and the second sub-portion PEb, and the active device T 'may have two drains, i.e. the drain D1 and the drain D2, respectively, wherein the first sub-portion PEa and the second sub-portion PEb of the pixel electrode are electrically connected to the drain D1 and the drain D2 of the active device T', but the invention is not limited thereto.

Fig. 7 is a cross-sectional view of a pixel array substrate according to a fifth embodiment of the present invention. Referring to fig. 7, the main differences between the pixel array substrate 21 of the present embodiment and the pixel array substrate 20 of fig. 6 are: the composition of the organic layers is different. In the present embodiment, the organic layer 120 only includes the color filter layer 121, and an inorganic insulating layer 140 is disposed between the spacers 135 (or the pixel electrodes) and the color filter layer 121. More specifically, the groove 121a of the color filter layer 121 may define a second opening 120A-1 of the organic layer 120A, and the width of the second portion 132B of the light shielding pattern 130D in the direction perpendicular to the normal of the substrate 101 is gradually reduced from the inside of the second opening 120A-1 toward the top surface 130Ds of the light shielding pattern 130D. Particularly, since the bottom aperture of the second opening 120a-1 located at one side of the insulating layer 110 is larger, the reaction time can be shortened in the etching process of the insulating layer 110, which is helpful for improving the etching efficiency. In the present embodiment, the material of the inorganic insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the above materials.

In summary, in the pixel array substrate according to an embodiment of the invention, the insulating layer and the organic layer have a first opening and a second opening respectively, and the first signal line electrically connected to the active element of the pixel overlaps the two openings. By making the width of the first portion of the light-shielding pattern in the first opening larger than the width of the second portion of the light-shielding pattern in the second opening, the space for laying out the pixel electrode of the pixel can be increased, which is helpful for increasing the Aperture Ratio (AR) of the pixel.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A pixel array substrate, comprising:

a substrate;

a first signal line disposed on the substrate;

a first pixel disposed on the substrate, the first pixel comprising:

a first active element electrically connected to the first signal line; and

a first pixel electrode electrically connected to the first active element;

an insulating layer covering the substrate, the insulating layer having a first opening overlapping the first signal line, wherein the first signal line has a first upper surface defining the first opening;

an organic layer disposed on the insulating layer, the organic layer having a second opening communicated with the first opening, wherein the organic layer has a bottom surface defining the first opening and a sidewall defining the second opening, and the bottom surface is connected to the sidewall; and

a light-shielding pattern covering the first upper surface of the first signal line and the sidewall and the bottom surface of the organic layer, and having a first portion located in the first opening and a second portion located in the second opening and protruding out of the organic layer, wherein the first portion and the second portion have a first width and a second width respectively, and the first width is greater than the second width.

2. The pixel array substrate of claim 1, wherein the first portion and the second portion of the light-shielding pattern are made of the same material.

3. The pixel array substrate of claim 1, further comprising:

and a spacer disposed on the substrate, wherein a first height is provided between a first top surface of the light-shielding pattern and an upper surface of the substrate, a second height is provided between a second top surface of the spacer and the upper surface of the substrate, and the first height is smaller than the second height.

4. The pixel array substrate of claim 3, wherein the light-shielding pattern and the spacer belong to a same layer.

5. The pixel array substrate of claim 1, wherein the organic layer is a laminate of a color filter layer and an organic insulating layer covering the color filter layer and having the sidewalls defining the second opening.

6. The pixel array substrate of claim 1, wherein the insulating layer is a stacked structure of a first sub-insulating layer and a second sub-insulating layer, the first sub-insulating layer is disposed between the substrate and the first signal line, the second sub-insulating layer is disposed between the first signal line and the organic layer, and the first opening penetrates the second sub-insulating layer.

7. The pixel array substrate of claim 6, wherein the first opening further penetrates the first sub-insulating layer, the first signal line further has a first lower surface defining the first opening and a first side surface connecting the first upper surface and the first lower surface, and the light shielding pattern further covers the first lower surface and the first side surface of the first signal line.

8. The pixel array substrate of claim 1, further comprising:

a second signal line arranged on the substrate adjacent to the first signal line in parallel, wherein the second signal line has a second upper surface defining the first opening, and the light-shielding pattern further covers the second upper surface of the second signal line; and

a second pixel disposed on the substrate, the second pixel comprising:

a second active element electrically connected to the second signal line; and

a second pixel electrode electrically connected to the second active device,

the first signal line and the second signal line are positioned between the first pixel and the second pixel, and the shading pattern is positioned between the first signal line and the second signal line.

9. The pixel array substrate of claim 8, wherein the insulating layer is a stacked structure of a first sub-insulating layer and a second sub-insulating layer, the first sub-insulating layer is disposed between the substrate and the first signal line, the second sub-insulating layer is disposed between the first signal line and the organic layer, and the first opening penetrates the second sub-insulating layer.

10. The pixel array substrate of claim 9, wherein the first opening further penetrates the first sub-insulating layer, the first signal line further has a first lower surface defining the first opening and a first side surface connecting the first upper surface and the first lower surface, the second signal line further has a second lower surface defining the first opening and a second side surface connecting the second upper surface and the second lower surface, and the light shielding pattern further covers the first lower surface and the first side surface of the first signal line and the second lower surface and the second side surface of the second signal line.

11. The pixel array substrate of claim 1, wherein the organic layer is a color filter layer.