KR101297357B1 - Vertical alignment mode liquid crystal display device - Google Patents

Abstract

The present invention comprises a first substrate; A gate line and a data line formed on the first substrate and intersecting with each other to define a pixel region; A thin film transistor formed in the pixel region; A protective layer covering the thin film transistor and having a plurality of holes in the pixel region; A pixel electrode formed on the protective layer and having recesses in the plurality of holes in the pixel area, and dividing the pixel area into a plurality of partial pixel areas, and including a plurality of partial pixel electrodes formed one for each of the partial pixel areas; and; A second substrate facing the first substrate; A black matrix formed on the inner surface of the second substrate; A color filter layer formed on the inner surface exposed to the outside of the black matrix; A common electrode formed on an entire surface under the color filter layer; Provided is a vertical alignment mode liquid crystal display including a liquid crystal layer interposed between the pixel electrode and the common electrode.

Vertical alignment mode, rivet free, process simplicity, multi domain

Description

[0001] The present invention relates to a vertical alignment mode liquid crystal display device,

1 is a cross-sectional view showing a portion of a conventional vertical alignment mode liquid crystal display device.

2 is a plan view of one pixel area of a vertical alignment mode liquid crystal display according to a first embodiment of the present invention;

Fig. 3 is a cross-sectional view of a portion cut along the cutting line III-III of Fig. 2; Fig.

4A through 4E are cross-sectional views illustrating manufacturing processes of one pixel area of an array substrate for a vertical alignment mode liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is cut along the cutting line III-III. Manufacturing process cross section for.

5 is a plan view of one pixel area of a vertical alignment mode liquid crystal display according to a second embodiment of the present invention;

FIG. 6 is a cross-sectional view of a portion cut along the cutting line VI-VI in FIG. 5; FIG.

7A to 7C are cross-sectional views illustrating manufacturing processes of one pixel area of an array substrate for a vertical alignment mode liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 5 is cut along the cutting line VI-VI. Manufacturing process cross section for.

<Description of the symbols for the main parts of the drawings>

100: vertical alignment mode liquid crystal display device

103: array substrate 108: gate electrode

113: first storage electrode 117: gate insulating film

120: semiconductor layer 120a: active layer

120b: ohmic contact layer 122a: first pattern (of pure amorphous silicon)

122b: second pattern (of impurity amorphous silicon)

125: data wiring 127: source electrode

129: drain electrode 132: second storage electrode

140: protective layers 142, 146: first and second holes

151, 153, and 155: first, second and third partial pixel electrodes

158: pixel electrode 171: color filter substrate

174: black matrix 177: color filter layer

177a, 177b, 177c: Red, Green, Blue Color Filter Pattern

180: overcoat layer 183: common electrode

190: liquid crystal layer

h1, h3: Depth of the first and third holes P: Pixel area

P1, P2, and P3: first, second and third partial pixel areas

StgA: Storage Area StgC: Storage Capacitor

Tr: Thin Film Transistor TrA: Switching Area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a surface driving liquid crystal display having fast response speed, excellent transmittance and viewing angle.

Recently, as the age of information society is rapidly progressing, a display field for processing and displaying a large amount of information has been developed.

In particular, in recent years, in order to respond to the era of thinning, light weight, and low power consumption, a need has arisen for a plate panel display, and accordingly, a thin film transistor liquid crystal display crystal display) has been developed.

The display method of such a liquid crystal display device uses optical anisotropy and polarization of liquid crystal molecules, because the structure of the liquid crystal molecules is thin and long and has a pre-tilt angle having directionality in the arrangement thereof. By artificially applying a voltage to the liquid crystal, the direction of alignment of the liquid crystal molecules can be controlled by changing the inclination angle of the liquid crystal molecules. Therefore, by applying an appropriate voltage to the liquid crystal layer, the alignment direction of the liquid crystal molecules can be arbitrarily adjusted to control the molecules of the liquid crystal. The desired image information is expressed by changing the arrangement and arbitrarily modulating the light polarized by the optical anisotropy of the liquid crystal.

Currently, an active matrix LCD in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and image realization ability.

In the liquid crystal panel, which is a basic element of a general liquid crystal display device, an upper color filter substrate and a lower array substrate face each other and are spaced apart at a predetermined interval, and a liquid crystal including liquid crystal molecules is filled between the two substrates. More specifically, a polymer alignment layer for controlling the initial arrangement of the filled liquid crystal and the movement according to the voltage is further formed covering the electrodes inside the respective substrates.

In this case, the electrodes for applying voltage to the liquid crystal become the common electrodes located on the color filter substrate and the pixel electrodes located on the array substrate. When a voltage is applied to these two electrodes, A vertical electric field is used to control the direction of the liquid crystal molecules located therebetween.

However, since the common electrode and the pixel electrode are horizontally formed in the liquid crystal display device having the above-described structure and the liquid crystal is driven by the vertical electric field generated in the vertical direction, the advantage of the excellent characteristics such as the transmittance and the aperture ratio However, it has a disadvantage that the viewing angle characteristic is not excellent.

Therefore, a vertical alignment (VA) mode liquid crystal display device has been proposed to improve the viewing angle characteristics.

The conventional vertical alignment mode liquid crystal display device 1 includes a gate electrode 42, a gate insulating film 43, a semiconductor layer 45, and source and drain electrodes 47 and 49, as shown in FIG. 1. A first substrate 40 comprising a thin film transistor Tr, which is a switching element, a protective layer 52 and a pixel electrode 55 thereon, disposed above the thin film transistor Tr, and a black matrix 61; A second substrate 60 including a color filter layer 63 including red, green, and blue color filter patterns, a common electrode 67, a rivet 78, and a column spacer 81; It consists of the liquid crystal layer 90 which has negative dielectric anisotropy interposed between (40, 60).

On the other hand, in the above-described vertical alignment mode liquid crystal display device 1, in order to have a wide viewing angle, a technique for constructing a multi-domain in one pixel region P is required. In order to form such a multi-domain, the first Pixel electrodes 55 provided on the substrate 40 are electrically connected to each other in the pixel region P, and partially formed, and each pixel region is disposed under the common electrode 67 of the second substrate 60 on the upper portion. The rivets 78 form the plurality of rivets 78 in the form of convex protrusions corresponding to the central portions of the pixel electrodes 55a, 55b, 55c partially formed in (P). By inducing distortion of the vertical electric field between the electrodes 55a, 55b, 55c and the common electrode 67, a multi-domain is formed to widen the viewing angle.

In manufacturing the vertical alignment mode liquid crystal display device 1 having such a structure, a total of six exposure masks are required for manufacturing the color filter substrate 60 for the vertical alignment mode liquid crystal display device having the rivet 78. A six mask process using the six exposure masks, that is, a black matrix 61 (# 1), a color filter layer 63 (# 2 to # 4) including a red, green, and blue color filter pattern; Compared with the manufacture of a color filter substrate for a general liquid crystal display device manufactured by a six mask process for patterning the rivet 78 (# 5) and the column spacer 81 (# 6), respectively, which are usually manufactured through five mask processes. Further needs a meeting mask process, there is a problem of productivity decrease and increase in production cost by increasing the number of processes.

In addition, the rivet 78 should be positioned at the center of each pixel electrode 55a, 55b, 55c partially formed in each pixel region P of the lower array substrate 40. In this case, the color filter substrate 60 ) And a larger bonding margin between the array substrate 40 is required, which causes a problem of lowering the aperture ratio.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a first object of the present invention is to reduce the number of mask steps in its manufacture and to improve productivity.

In addition, a second object of the present invention is to provide a vertical alignment mode liquid crystal display device which can induce distortion of vertical electric fields while omitting rivets formed on a color filter substrate to induce distortion of an electric field to form a multi-domain. Further, a third object of the present invention is to realize a high opening rate by reducing the bonding margin by omitting the rivet.

In order to achieve the above object, the vertical alignment mode liquid crystal display device according to the first aspect of the present invention comprises: a first substrate; A gate line and a data line formed on the first substrate and intersecting with each other to define a pixel region; A thin film transistor formed in the pixel region; A protective layer covering the thin film transistor and having a plurality of holes in the pixel region; A pixel electrode formed on the protective layer and having recesses in the plurality of holes in the pixel area, and dividing the pixel area into a plurality of partial pixel areas, and including a plurality of partial pixel electrodes formed one for each of the partial pixel areas; and; A second substrate facing the first substrate; A black matrix formed on the inner surface of the second substrate; A color filter layer formed on the inner surface exposed to the outside of the black matrix; A common electrode formed on an entire surface under the color filter layer; It includes a liquid crystal layer interposed between the pixel electrode and the common electrode.

In this case, each of the plurality of holes and the plurality of partial pixel electrodes includes first to third holes and first to third partial pixel electrodes, and the first to third holes each include first to third partial pixel electrodes. The first hole exposes one electrode of the thin film transistor, and the first to third holes are positioned at the center of the first to third partial pixel electrodes, respectively. to be.

A vertical alignment mode liquid crystal display device according to a second aspect of the present invention, comprising: a first substrate; A gate line and a data line formed on the first substrate and intersecting with each other to define a pixel region; A thin film transistor formed in the pixel region; A protective layer having a drain contact hole exposing a part of one electrode of the thin film transistor on the front surface of the thin film transistor and a plurality of convex portions in the pixel region; The pixel area is divided into a plurality of partial pixel areas over the passivation layer, and the plurality of partial pixel electrodes are formed to cover the plurality of convex parts so that a part of the pixel areas is convex. A pixel electrode; A second substrate facing the first substrate; A black matrix formed on the inner surface of the second substrate; A color filter layer formed on the inner surface exposed to the outside of the black matrix; A common electrode formed on an entire surface under the color filter layer; It includes a liquid crystal layer interposed between the pixel electrode and the common electrode.

 In this case, the plurality of partial pixel electrodes may include first to third partial pixel electrodes, and the first to third convex portions may be formed to correspond to the first to third partial pixel electrodes, respectively. The third convex portions are located at the centers of the first to third partial pixel electrodes, respectively.

In addition, in the vertical alignment mode liquid crystal display device according to the first and second features, the protective layer is formed of an organic insulating material, the surface of which is flat, and the gate wiring or the data wiring of the second substrate It further includes a plurality of column spacers formed at regular intervals corresponding to some. The apparatus may further include an overcoat layer having a flat surface formed between the color filter layer and the common electrode, and an alignment layer formed on inner surfaces of each of the first and second substrates in contact with the liquid crystal layer.

Further, in the vertical alignment mode liquid crystal display device according to the first and second features, the storage line is formed to be parallel to the gate line, and the first storage electrode is formed to branch from the storage line to surround the pixel area. In this case, one electrode of the thin film transistor is formed overlapping with the first storage electrode is characterized in that the overlapping portion forms a second storage electrode.

In addition, the first to third partial pixel electrodes have the same area and are electrically connected to each other by first and second connection patterns made of the same material.

A method of manufacturing a vertical alignment mode liquid crystal display device according to a first aspect of the present invention includes forming a gate wiring extending in one direction on a first substrate having a pixel region and a gate electrode connected to the gate wiring in the pixel region. Wow; Forming a gate insulating film over the gate wiring and the gate electrode; Forming a semiconductor layer and a source and drain electrode spaced apart from each other over the gate insulating layer, and a data line connected to the source electrode and crossing the gate line to define the pixel region; Applying an organic insulating material over the data line and the source and drain electrodes to form a protective layer having a flat surface; Forming a plurality of holes or convex portions in the pixel region by patterning the protective layer; And forming a pixel electrode including a plurality of partial pixel electrodes electrically connected to each other in each pixel area over the passivation layer having the plurality of holes or convex portions.

In the forming of the plurality of holes in the pixel area by patterning the protective layer, an exposure mask having a transmissive area, a blocking area, and a transflective area is disposed on the protective layer and exposed through the exposure mask. Making a step; Developing the exposed protective layer to form a first hole having a first depth and exposing the drain electrode, and second and third holes having a depth lower than the first depth and having the same depth as each other; The method may further include forming a pixel electrode having the plurality of partial pixel electrodes, and depositing a transparent conductive material on the entire surface of the protective layer to form a transparent conductive material layer; Patterning the transparent conductive material layer to contact the drain electrode through the first hole and the first partial pixel electrode and the spaced apart from the first partial pixel electrode, respectively, recesses corresponding to the second and third holes, respectively And forming second and third partial pixel electrodes having the same. In this case, the first to third pixel electrodes may be formed such that the first to third holes are positioned at the central portion thereof.

In the forming of the plurality of convex portions in the pixel region by patterning the protective layer, an exposure mask having a transmissive region, a blocking region, and a semi-transmissive region is positioned above the protective layer and exposed through the exposure mask. Making a step; The drain contact hole exposing the drain electrode, the first to third convex portions having a first thickness, and a portion having a second thickness thinner than the first thickness are formed by performing the step of developing the exposed protective layer. Forming a pixel electrode having a plurality of partial pixel electrodes; depositing a transparent conductive material on the entire surface of the protective layer to form a transparent conductive material layer; Wow; Patterning the transparent conductive material layer to contact the drain electrode through the drain contact hole and having a convex shape corresponding to the first convex portion; and a second spaced apart from the first partial pixel electrode, respectively. And forming second and third partial pixel electrodes each having a convex shape corresponding to the three convex portions.

In this case, the forming of the first to third partial pixel electrodes may include: a first connection pattern electrically connecting the first and second partial pixel electrodes; and electrically connecting the second and third partial pixel electrodes. The method may further include forming a second connection pattern.

 The forming of the gate electrode and the gate wiring may include forming a storage wiring spaced apart from the gate wiring and a first storage electrode formed to branch from the storage wiring to surround an inside of the pixel region. The forming of the source and drain electrodes may include extending the drain electrode to overlap the first storage electrode so that a portion overlapping the first storage electrode forms a second storage electrode.

The method may further include forming a common electrode on a second substrate corresponding to the first substrate; Forming a seal pattern on an edge of one of the first and second substrates; Positioning the pixel electrode of the first substrate and the common electrode of the second substrate to face each other and forming a liquid crystal layer between the two substrates; And bonding the first and second substrates together with the liquid crystal layer interposed therebetween, and prior to forming the common electrode on the second substrate, the gate of the first substrate corresponding to the second substrate. And forming a black matrix corresponding to the data line; And forming a color filter layer partially overlapping the black matrix and having a red, green, and blue color filter pattern sequentially repeated corresponding to the pixel region, wherein the surface is flat between the color filter layer and the common electrode. And forming an overcoat layer.

Hereinafter, the present invention will be described in detail through preferred embodiments.

&Lt; Embodiment 1 >

FIG. 2 is a plan view of one pixel area of a vertical alignment mode liquid crystal display according to a first embodiment of the present invention, and FIG. 3 is a cross-sectional view of a portion taken along the cutting line III-III of FIG. In this case, only the array substrate is illustrated in FIG. 2, and the color filter substrate facing the array substrate is omitted.

First, referring to FIG. 2, as illustrated, a plurality of gate lines 105 are formed in one direction, and the pixel area P is defined to cross the gate lines 105 to define a plurality of data lines ( 125) is formed.

In addition, a plurality of storage wires 110 are formed on the same layer side-by-side with the gate wires 105. At this time, the storage wires 110 branch from the storage wires 110 to surround the inside of the pixel area P. The storage electrode 113 is formed.

In addition, a thin film transistor Tr, which is a switching element, is formed for each pixel region P near the intersection of the gate line 105 and the data line 125. In this case, the thin film transistor Tr may include a gate electrode 108 branched from the gate line 105, a gate insulating layer (not shown) thereon, and an active layer (not shown) above the gate insulating layer (not shown). And a semiconductor layer 120 including an ohmic contact layer (not shown), and source and drain electrodes 127 and 129 spaced apart from each other on the semiconductor layer 120. In this case, the source electrode 127 is connected to the data line 125, and the drain electrode 129 is formed to extend to a storage area in which the first storage electrode 113 is formed. The overlapped portion forms the second storage electrode 132.

In addition, the pixel region P is divided into first to third regions P1, P2, and P3, and the first, second and third regions P1, P2, and P3 have a rectangular conductive shape as a transparent conductive material. First to third partial pixel electrodes 151, 153, and 155 are formed. In this case, the first to third partial pixel electrodes 151, 153, and 155 are made of the same material forming the partial pixel electrodes 151, 153, and 155 with respect to each of the separation regions. Are electrically connected by the first and second connection patterns 161 and 163 having a width smaller than the widths of the first and second 153 and 155. In addition, the first partial pixel electrode 151 is formed in contact with the drain electrode 129 of the thin film transistor Tr.

In this case, each of the first to third partial pixel electrodes 151, 153, and 155 in the pixel region P may have a first to third hole 142 in a protective layer (not shown) positioned below the central portion thereof. , 144, and 146 are provided to have a concave recess having a central portion thereof. In this case, the first hole 142 formed in the first region P1 exposes the drain electrode 129. The second storage electrode 132 is formed to extend, and the first partial pixel electrode 151 is formed by extending the drain electrode 129 and more precisely the drain electrode 129 through the first hole 142. It is characterized by being formed in contact with.

On the other hand, the cross-sectional structure of the vertical alignment mode liquid crystal display device having such a configuration will be described with reference to FIG. At this time, for convenience of description, an area in which the thin film transistor as a switching element is formed in the pixel area P is defined as a storage area StgA and a region in which the switching area TrA and the storage capacitor StgC are formed.

First, in the array substrate 103 which is a lower substrate, a storage wiring (not shown) is formed on the transparent substrate 103 in parallel with a gate wiring (not shown) as a first metal material, and the pixel region P is formed. In the switching region TrA, a gate electrode 108 is formed and a gate electrode 108 is formed in the switching region TrA, and a storage unit StgA is connected to the storage wiring (not shown). The electrode 113 is formed.

 Next, a gate insulating layer 117 is formed over the gate electrode 108, the gate wiring (not shown), the storage wiring (not shown), and the first storage electrode 113, and above the gate insulating layer 117. In the switching region TrA, the semiconductor layer 120 including the ohmic contact layer 120b is formed in the form of an active layer 120a and one end thereof facing each other and spaced apart from each other, and the ohmic contact layer Source and drain electrodes 127 and 129 are spaced apart from each other over 120b. In addition, a data line 125 is formed on the gate insulating layer 117 to define the pixel region P while crossing the gate line (not shown). The data line 125 and the source electrode are also formed. 127 are formed in electrical contact with each other. In this case, the gate electrode 108, the gate insulating layer 117, the active layer 120a, the ohmic contact layer 120b, and the source and drain electrodes 127 and 129 form a thin film transistor Tr as a switching element.

In the storage region StgA, a second storage electrode 132 is formed on the gate insulating layer 117, where the second storage electrode 132 and the drain electrode 129 are electrically connected to each other. It is characterized by being formed. That is, since the drain electrode 129 extends to the storage region StgA, a portion overlapping with the first storage electrode 113 forms the second storage electrode 132.

Next, an organic insulating material such as benzocyclobutene (BCB) or photo acryl is coated on the thin film transistor Tr and the second storage electrode 132 to have a relatively thick thickness of about 1.5 μm to 3.5 μm. The protective layer 140 is formed by having a surface whose surface is flat without reflecting the step difference below.

In this case, the passivation layer 140 made of the organic insulating material may have the first, second, and third regions P1, P2, and P3 defined by dividing the pixel region P into three equal parts in the length direction of the data line 125. Corresponding to each of the first, second, and third regions (P1, P2, P3), the first, second, third holes 142 (not shown, 146) are formed, of which the switching region (TrA) The first hole 142 formed in the first region P1 includes a second drain electrode 129 having a depth greater than that of the other two holes 146, and more accurately, a second storage electrode connected thereto. 132 is formed while exposing. At this time, in the drawing (FIG. 3), the depth h1 of the first hole 142 is formed deeper than the depth (h3) of the second and third holes (not shown) 146 (h1> not shown). H3), but on the contrary, the first hole 142 may have a smaller depth (h1 <not shown, h3) than the second and third holes 146 (not shown). Or all of them may have the same depth (h1 = not shown, h3).

Next, each of the first, second, and third regions P1, P2, and P3 over the passivation layer 140 including the first, second, and third holes 142 and 146, respectively. The partial pixel electrodes 151, 153, and 155 are formed. In this case, the first, second, and third partial pixel electrodes 151, 153, and 155 are formed to be electrically connected to each other by first and second connection patterns (not shown) connecting adjacent partial pixel electrodes, respectively. Each of the partial pixel electrodes 151, 153, and 155 may be formed in the hole by first, second, and third holes 142 (not shown) 146 formed in the protective layer 140 having a central portion thereof. Another feature is that it extends to the side. In this case, the first hole 141 is formed to expose the second storage electrode 132 connected to the drain electrode 129, and the first partial pixel electrode 151 is formed in the first hole 142. It is another feature that is formed in contact with the second storage electrode 132 through.

On the other hand, in the color filter substrate 171 which faces the array substrate 103 having such a structure, the black matrix 174 corresponds to the gate and data wiring (not shown) 125 on the lower array substrate 103. The black matrix 174 is formed also corresponding to the thin film transistor Tr as the switching element.

In addition, the color filter layer 177 is formed to partially overlap the black matrix 174 and to sequentially repeat the red, green, and blue color filter patterns 177a, 177b, and 177c corresponding to the pixel area P. The common electrode 183 made of a transparent conductive material is formed over the entire color filter layer 177. In this case, an overcoat layer 180 may be further formed between the color filter layer 177 and the common electrode 183 to compensate for the step difference of the color filter layer 177 and to protect the same.

In addition, a spaced interval between the array substrate 103 and the color filter substrate 171 is maintained on the entire surface of the common electrode 183 under the gate line (not shown) or the data line 125. The column spacer 185 is formed.

Meanwhile, a liquid crystal layer 190 having a negative anisotropy dielectric constant value is formed between the two substrates 103 and 171, and although not shown in the drawing, the liquid crystal layer 190 prevents leakage of the two substrates ( In order to maintain the panel state of 103 and 171, a seal pattern (not shown) is further formed along an edge to form the vertical alignment mode liquid crystal display device 100.

In this case, although not shown in the drawings, the surface of the array substrate 103 and the color filter substrate 171 which meet the liquid crystal layer 190, that is, between the liquid crystal layer 190 and the pixel electrode 158 and the liquid crystal layer 190 First and second alignment layers (not shown) are further formed between the common electrode 183 and the common electrode 183.

The vertical alignment mode liquid crystal display 100 according to the exemplary embodiment of the present invention having the above-described configuration removes the rivets provided on the color filter substrate of the conventional vertical alignment mode liquid crystal display, and instead causes the vertical electric field distortion. By forming the first to third holes 142 (not shown, 146) for the protective layer 140 on the array substrate 103 to the inside of the first to third holes 142 (not shown, 146). Each of the first and third partial pixel electrodes 151, 153, and 155 is formed to have a recess in its central portion, thereby causing electric field distortion.

Therefore, by eliminating the rivets in the color filter substrate 171, the process of manufacturing the color filter substrate 171 is simplified, and at the same time, a small bonding margin is compared with the bonding margin between the color filter substrate 171 and the array substrate 103 at the time of forming the rivet. It will have the effect of improving the aperture ratio.

Hereinafter, a method of manufacturing the vertical alignment mode liquid crystal display device according to the first embodiment of the present invention will be described.

First, the manufacturing method of the array substrate which has the characteristic part of this invention is demonstrated.

4A through 4E are cross-sectional views illustrating manufacturing processes of one pixel area P of an array substrate for a vertical alignment mode liquid crystal display according to a first exemplary embodiment of the present invention, taken along a cutting line III-III. The process cross section for one part. For convenience of description, an area where a thin film transistor as a switching element is formed in the pixel area P is defined as a switching area TrA and an area where a storage capacitor is formed as a storage area StgA, and the pixel area P The partial pixel region P divided into three equal parts in the longitudinal direction of the data line is defined as first, second and third regions P1, P2 and P3, respectively.

First, as shown in FIG. 4A, a gate electrode branched into each pixel region P in a gate wiring (not shown) and the gate wiring (not shown) by depositing and patterning a metal material on the transparent substrate 103. A storage wiring (not shown) extending alongside the gate wiring (not shown) and the inside of the pixel area (P) in the storage wiring (not shown); The storage electrode 113 is formed.

Next, as shown in FIG. 4B, an inorganic insulating material such as silicon oxide (eg, silicon oxide) is disposed on the gate wiring (not shown) and the gate electrode 108, the storage wiring (not shown), and the first storage electrode 113. The gate insulating film 217 is formed by depositing SiO ₂ ) or silicon nitride (SiNx).

Subsequently, pure amorphous silicon, impurity amorphous silicon, and a second metal material are continuously deposited on the entire surface of the gate insulating layer 217, and patterned, thereby forming the active layer 120a of pure amorphous silicon in the switching region TrA, Forming ohmic contact layers 120b of impurity amorphous silicon spaced apart from each other on the active layer 120a, and source and drain electrodes 127 and 129 spaced apart from each other over the ohmic contact layers 120b spaced apart from each other, At the same time, the data line 125 defining the pixel region P is formed to cross the gate line (not shown). In this case, a first pattern 122b of impurity amorphous silicon forming the ohmic contact layer 120b and a second pattern of pure amorphous silicon forming the active layer 120a below the data line 125 may be formed. 122a) is further formed. In this case, the data line 125 and the source electrode 127 are formed to be electrically connected by being connected to each other.

Thus, the semiconductor layer 120 including the active layer 120a and the ohmic contact layer 120b and the source and drain electrodes 127 and 129 are formed in one mask process. After vapor deposition, photoresist patterns having different thicknesses are formed by diffraction exposure or halftone exposure using an exposure mask including a transflective region thereon, and the photoresist patterns having different thicknesses are used to The second metal material layer exposed to the outside and the impurities and the pure amorphous silicon layer formed by depositing pure amorphous silicon are first etched, and after removing the thin photoresist pattern, the thick photoresist pattern remaining again As the thin photoresist pattern exposed to the outside is removed, a second etching of the newly exposed second metal material layer is performed. As described above, the semiconductor layer 120 and the source and drain electrodes 127 and 129 can be simultaneously formed in the same mask process.

In this case, the gate electrode 108, the gate insulating layer 117, the active layer 120a and the ohmic contact layer 120b formed in the switching region TrA are spaced apart from each other. The device forms a thin film transistor Tr.

In the exemplary embodiment of the present invention, the semiconductor layer 120 and the source and drain electrodes 127 and 129 of the active layer 120a and the ohmic contact layer 120b are simultaneously formed through one mask process. Although a manufacturing process is shown, the semiconductor layer, the source and the drain electrode may be formed through different mask processes, respectively. In this case, the first and second patterns 122a and 122b formed under the data line 125 are not formed.

Meanwhile, the drain electrode 129 is formed to extend to the storage region StgA during patterning so that the drain electrode 129 overlaps the first storage electrode 113 in the storage region StgA, thereby overlapping the first storage electrode 1. The portion to be made up the second storage electrode 132. In this case, the first and second storage electrodes 113 and 132 overlapping each other and the gate insulating layer 117 disposed therebetween form a storage capacitor StgC.

Next, as shown in FIG. 4C, a photosensitive organic insulating material, for example, photosensitive benzocyclobutene or photoacryl, has a thickness of about 1.5 μm to 3.5 μm over the thin film transistor Tr and the second storage electrode 132. By coating so as to have a surface, the protective layer 140 having a flat state is formed to sufficiently overcome the step between the switching element or other components.

Subsequently, an exposure mask 195 including a light transmitting area TA, a blocking area BA, and a transflective area HTA is formed on the passivation layer 140 made of the photosensitive organic insulating material. The transmissive area TA corresponds to a part corresponding to a part of the drain electrode 230 of the drain electrode 230, that is, the part to form the first hole, and the transflective area HTA to the part to form the second hole and the third hole. In this and other areas, the blocking area BA is positioned so as to correspond to each other, and then the protective layer 140 is exposed through the exposure mask 195. At this time, in the embodiment of the present invention, the protective layer 140 is formed as a positive type photosensitive organic insulating material, and if the protective layer 140 is formed of a negative type photosensitive organic insulating material In this case, if the exposure mask 195 is exposed after changing the transmission area TA and the blocking area BA, the same result can be achieved.

Next, as shown in FIG. 4D, the exposure layer (FIG. 4C of FIG. 4C) is developed by developing the protective layer 140 exposed through the exposure mask 195 of FIG. 4C including the transflective region (HTA of FIG. 4C). In the protective layer 140 region corresponding to the transmission region (TA of FIG. 4C) of 195, the second storage electrode 132 connected to the drain electrode 129 is more precisely removed from the drain electrode 129 located below. ) Is formed to expose the first hole 142, and only a part of the protective layer 140 is removed in a portion corresponding to the transflective region (HTA of FIG. 4C) of the exposure mask 195 of FIG. 4C. In this state, the second and third holes (not shown) 146 are formed, and in other portions corresponding to the blocking area (BA in FIG. 4C) of the exposure mask (195 in FIG. 4C), the thickness as it is first formed is determined. The protective layer 140 is formed.

In this case, in the drawing, the depth h1 of the first hole 142 is formed deeper than the depth (h3, h3) of the second and third holes (not shown) 146 (h1> not shown, h3). However, as a modified example, in the exposure step using the exposure mask, the positions of the transmissive region and the transflective region may be changed, that is, corresponding to a portion where the first hole to be formed to expose the second storage electrode 132 is formed. When the transflective area is exposed after the exposure mask is positioned so that the transmissive area corresponds to the portion where the second and third holes are to be formed, and is developed, the depth of the first hole is different from that shown in the drawing. It may be formed smaller than the depth (h1 <not shown, h2).

On the other hand, in another modification, when the protective layer 140 is formed of an organic insulating material having no photosensitive characteristic, a photoresist layer (positive type) is further formed on the protective layer, and the transparent region and By using an exposure mask having a blocking area, a transmissive area is located to correspond to a portion where the first to third holes are to be formed, and a blocking area is located to correspond to other areas, and then the exposure and developing processes are performed. The photoresist pattern is formed corresponding to the protective layer region except for the region where the three holes are to be formed. Subsequently, when etching is performed using the photoresist pattern as an etching mask, the protective layer of the portion where the first to third holes are to be formed is etched to form the first to third holes. In this case, when the etching is stopped at the time when the drain electrode is exposed to correspond to the first hole by adjusting the etching speed and the etching time, the first to third holes are all formed to have the same depth, and the over etching is performed. The first hole has a lower drain electrode acting as an etch stopper so that the depth thereof does not become deep, but the second and third holes have a depth greater than that of the first hole because the etching continues. After the etching process, the protective layer having the first to third holes may be formed by removing the photoresist pattern on the protective layer having the first to third holes by performing a strip or ashing.

Next, as shown in FIG. 4E, a transparent conductive material such as indium-tin over the protective layer 140 formed with the first to third holes 142 and 146 in each pixel region P is formed. -ITO or Indium-Zink Oxide (IZO) are deposited on the entire surface and subjected to a new masking process to pattern the same, respectively, in the first to third regions P1, P2, and P3 in the pixel region P. Vertical alignment according to the present invention by forming the first to third partial pixel electrodes 151, 153, and 155 electrically connected by first and second connection patterns (not shown) formed of the same material by a process. The array substrate 103 for a mode liquid crystal display device is completed. In this case, the first partial pixel electrode 151 is in contact with the second storage electrode 132 connected to the drain electrode 129 through the first hole 142.

In this case, the first to third partial pixel electrodes 151, 153, and 155 are formed of first to third holes 142 (not shown) 146 in the protective layer 140 positioned below the central portion, respectively. As a result, a transparent conductive material is formed by depositing an inner surface of the first to third holes 142 (not shown) 146 to form the first to third holes 142 (not shown). The other regions are formed to have a flat surface, and the first to third holes 142 and 146 may be formed to have concave recesses.

The vertical alignment mode liquid crystal display according to the present invention is formed in the color filter substrate of the conventional vertical alignment mode liquid crystal display by configuring the central portion of each of the first to third partial pixel electrodes 151, 153, and 155 in this way. The rivet is characterized by the same role as the rivet, which distorts the electric field.

On the other hand, the manufacturing method of the color filter substrate for a vertical alignment mode liquid crystal display device which concerns on this invention is demonstrated briefly.

The color filter substrate for a vertical alignment mode liquid crystal display device according to the present invention has a structure that does not form a rivet for electric field distortion, and is the same as the manufacturing method of a color filter substrate for a general TN mode liquid crystal display device including a column spacer. Therefore, the manufacturing method will be briefly described with reference to the cross-sectional shape of the color filter substrate shown in FIG. 3.

First, a black matrix layer (not shown) is formed by depositing a metal material such as chromium (Cr) or chromium oxide (CrOx) on the transparent substrate 171 or by applying black resin to the entire surface. The black matrix 173 is formed by forming the black matrix 173 by patterning the first mask process to correspond to the gate and data lines and the thin film transistor formed on the array substrate facing the panel.

Next, a red resist layer is formed on the black matrix 173 and the substrate 171 exposed to the outside thereof, and a second mask process is performed to pattern the red resist layer, thereby forming a red color filter pattern 177a and continuously. The green and blue color filter patterns 177b and 177c are formed in the same manner as the method of forming the red color filter pattern 177a to form the green and blue color filter patterns 177b and 177c to sequentially repeat the pixel regions P. FIG. A color filter layer 177 having red, green, and blue color filter patterns 177a, 177b, and 177c is formed.

Next, a colorless transparent organic insulating material such as benzocyclobutene (BCB) or photo acryl is coated on the entire surface of the color filter layer 177 to form an overcoat layer 180 having a flat surface. In this case, the overcoat layer 180 is formed on the entire surface of the substrate 171 and thus does not perform a separate mask process. In addition, the overcoat layer 180 may be omitted.

Next, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the overcoat layer 180 having the flat surface to form a common electrode 183. In this case, the common electrode 183 is also formed on the entire surface of the substrate 171, and like the overcoat layer 180, a separate mask process does not need to be performed.

Next, a plurality of column spacers 185 having a predetermined interval corresponding to a portion of the gate and data lines on the array substrate facing the organic insulating material are coated on the common electrode 183 and patterned by performing a fifth mask process. The color filter substrate 171 for the vertical alignment mode liquid crystal display device according to the present invention is completed by forming a.

Next, in the array substrate and the color filter substrate respectively completed by the manufacturing method as described above, after forming the alignment films on the surfaces of the two substrates facing each other, that is, the surfaces in contact with the liquid crystal layer by a later process, these The alignment pattern liquid crystal display device according to the present invention may be completed by forming a seal pattern along one of the two substrates and injecting and bonding the liquid crystal into the seal pattern.

&Lt; Embodiment 2 >

FIG. 5 is a plan view of one pixel area of a vertical alignment mode liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view of a portion taken along the cutting line VI-VI of FIG. 5. In this case, only the array substrate is shown in FIG. 5, and the color filter substrate facing the same is omitted. In the reference numerals, 100 is added to the same components as those in the first embodiment.

First, referring to FIG. 5, as illustrated, a plurality of gate lines 205 are formed in one direction, and the pixel area P is defined to cross the gate lines 205 to define a plurality of data lines ( 225 is formed.

In addition, a plurality of storage wires 210 are formed on the same layer side-by-side with the gate wires 205. At this time, the storage wires 210 branch from the storage wires 210 to surround the inside of the pixel area P. The storage electrode 213 is formed.

Also, a thin film transistor Tr, which is a switching element, is formed for each pixel region P near the intersection of the gate line 205 and the data line 225. In this case, the thin film transistor Tr may include a gate electrode 208 formed by branching from the gate line 205, a gate insulating layer (not shown), and an active layer (not shown) above the gate insulating layer (not shown). And a semiconductor layer 220 including an ohmic contact layer (not shown), and source and drain electrodes 227 and 229 spaced apart from each other on the semiconductor layer 220.

In this case, the source electrode 227 is connected to the data line 225, and the drain electrode 229 extends to a storage area in which the first storage electrode 213 is formed, thereby the first storage electrode 213. The overlapped portion forms the second storage electrode 232.

In addition, the pixel region P is divided into first to third regions P1, P2, and P3, and the first, second and third regions P1, P2, and P3 have a rectangular conductive shape as a transparent conductive material. First to third partial pixel electrodes 251, 253, and 255 are formed. In this case, the first to third partial pixel electrodes 251, 253, and 255 are made of the same material forming the partial pixel electrodes 251, 253, and 255 for each of the separation regions, and the partial pixel electrodes 251. Are electrically connected by the first and second connection patterns 261 and 263 having a width smaller than the widths of the first and second 253 and 255. In addition, the first partial pixel electrode 251 is formed in contact with the drain electrode 229 of the thin film transistor Tr through the drain contact hole 242.

On the other hand, each of the first to third partial pixel electrodes 251, 253, and 255 in the pixel region P is convex in a protective layer (not shown) positioned below the central portion thereof. By providing the three convex portions 243, 245, and 247, the central portion thereof is convex, and the other regions are formed to have a flat structure.

Next, a cross-sectional structure of a vertical alignment mode liquid crystal display device according to a second embodiment of the present invention having such a configuration will be described with reference to FIG. In this case, for convenience of description, an area in which the thin film transistor as the switching element is formed in the pixel area P is defined as a storage area StgA and a region in which the switching area TrA and the storage capacitor StgC are formed.

First, in the array substrate 203, a storage wiring (not shown) is formed on the transparent substrate 203 in parallel with a gate wiring (not shown) as a first metal material, and then into the pixel region P. A gate electrode 208 is formed in the switching region TrA and a gate electrode 208 is formed, and a first storage electrode 213 is connected to the storage wiring StgA in the storage region StgA. ) Is formed.

Next, a gate insulating film 217 is formed over the gate electrode 208, the gate wiring (not shown), the storage wiring (not shown), and the first storage electrode 213, and above the gate insulating film 217. In the switching region TrA, the semiconductor layer 220 including the ohmic contact layer 220b is formed in the form of an active layer 220a and one end thereof facing each other and spaced apart from each other, and the ohmic contact layer Source and drain electrodes 227 and 229 are spaced apart from each other over 220b. In addition, a data line 225 is formed on the gate insulating layer 217 to define the pixel region P while crossing the gate line (not shown), and the data line 225 and the source electrode ( 227 are formed in electrical contact with each other. In this case, the gate electrode 208, the gate insulating layer 217, the active layer 220a, the ohmic contact layer 220b, and the source and drain electrodes 227 and 229 form a thin film transistor Tr as a switching element.

In the storage region StgA, a second storage electrode 232 is formed on the gate insulating layer 217, and the second storage electrode 232 and the drain electrode 229 are electrically connected to each other. It is characterized by being formed. That is, since the drain electrode 229 extends to the storage region StgA, a portion overlapping with the first storage electrode 213 forms the second storage electrode 232.

Next, an organic insulating material such as benzocyclobutene (BCB) or photo acryl is coated on the thin film transistor Tr and the second storage electrode 232 to have a relatively thick thickness of about 1.5 μm to 3.5 μm. The protective layer 240 is formed by having a surface whose surface is flat without reflecting the step difference.

In this case, the passivation layer 240 made of the organic insulating material may include the first, second and third regions P1, P2, Corresponding first, second and third convex portions 243 (not shown) 247 are formed in the central portion of the first, second and third regions P1, P2 and P3 corresponding to each of P3). A drain contact hole 242 exposing a part of the drain electrode is formed.

Next, each of the first, second, and third regions P1, P2, and P3 on the passivation layer 240 including the first, second, and third convex portions 243 (not shown) 247 and the drain contact hole 242. First, second, and third partial pixel electrodes 251, 253, and 255 are formed, respectively. In this case, the first, second, and third partial pixel electrodes 251, 253, and 255 are formed to be electrically connected to each other by first and second connection patterns (not shown) connecting adjacent partial pixel electrodes, respectively. Each of the partial pixel electrodes 251, 253, and 255 corresponds to each of the partial pixel electrodes 251, 253, and 255 by the first, second, and third convex portions 243 (not shown) 247 formed in the protective layer 240 having a central portion thereof. The part is formed convexly.

Meanwhile, in the color filter substrate 271 facing the array substrate 203 having such a structure, the black matrix 274 corresponds to the gate and data wirings 225 on the lower array substrate 203. The black matrix 274 is formed also corresponding to the thin film transistor Tr which is the said switching element.

In addition, a color filter layer 277 is formed that partially overlaps the black matrix 274 and repeats the red, green, and blue color filter patterns 277a, 277b, and 277c sequentially corresponding to the pixel region P. FIG. The common electrode 283 made of a transparent conductive material is formed over the entire color filter layer 277. In this case, an overcoat layer 280 may be further formed between the color filter layer 277 and the common electrode 283 to compensate for the step difference of the color filter layer 277 and to protect the same.

In addition, a spaced interval between the array substrate 203 and the color filter substrate 271 may be maintained on the entire surface of the common electrode 283 in correspondence with a portion of the gate wiring (not shown) or the data wiring 225. Column spacers 285 are formed.

Meanwhile, a liquid crystal layer 290 having a negative anisotropy dielectric constant is formed between these array substrates and the color filter substrates 203 and 271, and although not shown in the drawing, the liquid crystal layer 290 prevents leakage. Seal patterns (not shown) are further formed along the edges of the two substrates 203 and 271 to maintain one panel state, thereby forming the vertical alignment mode liquid crystal display 200 according to the second embodiment of the present invention. have.

In this case, although not shown in the drawings, the surface of the array substrate 203 and the color filter substrate 271 that meet the liquid crystal layer 290, that is, between the liquid crystal layer 290 and the pixel electrode 258 and the liquid crystal layer 290. First and second alignment layers (not shown) are further formed between the common electrode 283 and the common electrode 283.

The vertical alignment mode liquid crystal display 200 according to the second embodiment of the present invention having the above-described configuration removes the rivets provided on the color filter substrate of the conventional vertical alignment mode liquid crystal display, and instead distorts the vertical electric field. The first, second and third convex portions 243 (not shown) are formed on the array substrate 203 by forming the first, second and third convex portions 243 (not shown) 247 on the protective layer 240. , 247 has a structure that causes electric field distortion by the first, second, and third partial pixel electrodes 251, 253, and 255 formed to protrude convexly than other portions.

Next, a method of manufacturing the vertical alignment mode liquid crystal display device according to the second embodiment having such a configuration will be described. In this case, since the process of forming the color filter substrate and the panel state is the same as in the above-described first embodiment, the description thereof will be omitted, and only the manufacturing method of the array substrate having different points will be described.

7A to 7C are cross-sectional views illustrating manufacturing processes of one pixel area P of an array substrate for a vertical alignment mode liquid crystal display according to a second exemplary embodiment of the present invention, taken along a cutting line VI-VI. The process cross section for one part. For convenience of explanation, a region in which a thin film transistor as a switching element is formed in the pixel region P is defined as a switching region TrA and a region in which a storage capacitor is formed as a storage region StgA, and the pixel region P is defined as The partial pixel regions P which are divided into three in the longitudinal direction of the data line are defined as first, second and third regions P1, P2 and P3, respectively. In this case, the steps up to forming the gate, the data line and the thin film transistor on the transparent substrate are the same as those of the first embodiment, and thus the steps after forming the thin film transistor will be described.

First, as shown in FIG. 7A, a semiconductor layer including a gate electrode 208 in the switching region TrA, a gate insulating film 217, and an active layer 220a and an ohmic contact layer 220b thereon. A photosensitive organic insulating material such as photosensitive benzocyclobutene over the thin film transistor Tr and the data wiring 225 and the second storage electrode 232, which are formed of the 220 and the source and drain electrodes 227 and 229. (BCB) or photo acryl is applied to have a first thickness t1 of about 1.5 to 3.5 μm so that the surface thereof can sufficiently overcome the step between the thin film transistor (Tr) or other components to maintain a flat state. The protective layer 240 is formed.

Subsequently, an exposure mask 295 including a light transmission area TA, a blocking area BA, and a transflective area HTA is formed on the passivation layer 240 made of the photosensitive organic insulating material. The transmissive area TA corresponds to a portion corresponding to a part of the drain electrode 229 of the drain electrode 229, that is, to form a drain contact hole. The blocking area BA is positioned so that the transflective area HTA corresponds to the other area, and then the protective layer 240 is exposed through the exposure mask 295.

At this time, in the second embodiment of the present invention, the protective layer 240 is shown as an example of using a positive type photosensitive organic insulating material, as in the first embodiment described above, if the protection When the layer 240 is formed of a negative type photosensitive organic insulating material, the exposure mask 295 may have the same exposure after changing the transmission area TA and the blocking area BA. You can get the result.

Next, as shown in FIG. 7B, the exposure mask (of FIG. 7A) is developed by developing the protective layer 240 exposed through the exposure mask 295 of FIG. 7A including the transflective region (HTA of FIG. 7A). In the protective layer 240 region corresponding to the transmission region (TA of FIG. 7A) of 295, a drain contact hole 242 is formed to completely remove and expose a portion of the drain electrode 229 disposed below the exposure layer. In the portion corresponding to the transflective region (HTA of FIG. 7A) of the mask 295 of FIG. 7A, only a part of the protective layer 240 is removed, and the first thickness of the first protective layer 240 ( A protective layer 240 having a second thickness t2 that is thinner than t1 is formed, and is formed for the first time in a portion corresponding to the blocking region (BA in FIG. 7A) of the other exposure mask (295 in FIG. 7A). A protective layer 240 having a first thickness t1 is formed.

Therefore, the protective layer 240 after the development step has a drain contact hole 242 exposing the drain electrode 229 in the switching region TrA, and the first and second in each pixel region P. FIG. And first, second, and third convex portions 243 (not shown) having a height of a first thickness t1, which is a thickness formed by initially applying the protective layer 240 in the central portion of the three regions P1, P2, and P3. ) Is formed, and for most of the other regions, the second thickness t2 is thinner than the first thickness t1 and has a flat surface state.

On the other hand, in the modification, when the protective layer 240 is formed of an organic insulating material having no photosensitive characteristic, the protective layer is formed of an organic insulating material having no photosensitive characteristic, and then a photoresist layer (positive) is formed thereon. Type), and a drain contact hole should be formed by placing an exposure mask as it is positioned during exposure to the protective layer formed of the photosensitive organic insulating material, and then exposing and developing the photoresist layer. The protective layer is exposed to correspond to the portion to be formed, the first photoresist pattern having a third thickness to correspond to the portion to which the first to third convex portions are to be formed, and the third thickness to correspond to other portions. A second photoresist pattern having a thin fourth thickness is formed. Thereafter, the first and second photoresist patterns are used as etch masks to form a drain contact hole for exposing the drain electrode by first etching the protective layer exposed to the outside of the patterns, and then ashing the fourth layer. The second photoresist pattern having the thickness is removed. Thereafter, the second photoresist pattern having the fourth thickness is removed, and the protective layer newly exposed to the outside of the first photoresist pattern is secondly etched to form a suitable thickness without being completely removed. At this time, the portion of the protective layer still covered by the first photoresist pattern maintains the thickness of the first protective layer as it is, thereby forming the first, second and third convex portions. Thereafter, the first photoresist pattern remaining on the first, second and third convex portions may be removed by ashing or stripping to form a protective layer having the same shape as illustrated in the drawing.

Thereafter, the first, second and third convex portions 243, 243 and 343 are formed by heat-treating the protective layer 240 having the first, second and third convex portions 243 (not shown) 247 formed in each pixel area P. Not shown, 247 may have a curved shape in an angular form in the corner portion of the surface, this heat treatment step may be omitted.

Next, as shown in FIG. 7C, the transparent conductive material is disposed on the passivation layer 240 having the drain contact hole 242 and the first, second and third convex portions 243 (not shown) 247 in each pixel region P. Referring to FIG. For example, the first to third regions P1 in the pixel region P may be deposited by depositing indium tin oxide (ITO) or indium zinc oxide (IZO) on the entire surface, and patterning the same by performing a new mask process. The first to third partial pixel electrodes 251, 253, and 255 electrically connected to each of P2 and P3 by first and second connection patterns (not shown) formed of the same material by the same process. Forming the array substrate 203 for the vertical alignment mode liquid crystal display device according to the second embodiment of the present invention is completed.

In this case, the first partial pixel electrode 251 is in contact with the drain electrode 229 through the drain contact hole 242, and the first, second and third partial pixel electrodes 251, 253, and 255 are respectively Due to the first, second and third convex portions 243 (not shown) 247 formed in the protective layer 240 positioned below the central portion, respectively, the central portion of each region has a convex state and a flat surface for the other regions. And are formed.

The array substrate 203 having such a configuration and the color filter substrate (not shown) manufactured by the method described in the first embodiment are bonded to each other after the liquid crystal is interposed, thereby making the vertical alignment mode according to the second embodiment of the present invention. A liquid crystal display device can be completed.

In the vertical alignment mode liquid crystal display device according to the second embodiment manufactured as described above, the first, second and third partial pixel electrodes 251 and 253 may be formed by the first, second and third convex portions 243 and 247. As the center portion of the 255 is formed to be convex, the electric field formed by these partial pixel electrodes 251, 253, and 255 with the common electrode formed on the color filter substrate (not shown) is distorted, thereby realizing a multi-domain. Will be.

In the vertical alignment mode liquid crystal display according to the present invention, one mask process can be omitted by omitting the rivets formed on the color filter substrate through one mask process, thereby reducing the process and improving productivity through the mask process. have.

In addition, a structure capable of inducing electric field distortion through the first to third holes or the first to third convex portions formed in each pixel area on the array substrate without rivets has an effect of implementing a multi-domain.

In addition, by omitting the rivet formed on the color filter substrate has a bonding margin smaller than the bonding margin required when forming the rivet bar, there is an effect of improving the opening ratio.

Claims (26)

A first substrate; A gate line and a data line formed on the first substrate and intersecting with each other to define a pixel region; A thin film transistor formed in the pixel region; A protective layer covering the thin film transistor and having a plurality of holes in the pixel region; A pixel electrode formed on the protective layer and having recesses in the plurality of holes in the pixel area, and dividing the pixel area into a plurality of partial pixel areas, and including a plurality of partial pixel electrodes formed one for each of the partial pixel areas; and; A second substrate facing the first substrate; A black matrix formed on the inner surface of the second substrate; A color filter layer formed on the inner surface exposed to the outside of the black matrix; A common electrode formed on an entire surface under the color filter layer; Liquid crystal layer interposed between the pixel electrode and the common electrode The plurality of holes and the plurality of partial pixel electrodes may include first to third holes and first to third partial pixel electrodes, respectively, and the first to third holes may include first to third parts, respectively. A vertical alignment mode liquid crystal display device characterized in that it is formed corresponding to the pixel electrode. delete The method of claim 1, And the first hole exposes one electrode of the thin film transistor. The method of claim 1, And the first to third holes are located at the center of the first to third partial pixel electrodes, respectively. A first substrate; A gate line and a data line formed on the first substrate and intersecting with each other to define a pixel region; A thin film transistor formed in the pixel region; A protective layer having a drain contact hole exposing a part of one electrode of the thin film transistor on the front surface of the thin film transistor and a plurality of convex portions in the pixel region; The pixel area is divided into a plurality of partial pixel areas over the passivation layer, and the plurality of partial pixel electrodes are formed to cover the plurality of convex parts so that a part of the pixel areas is convex. A pixel electrode; A second substrate facing the first substrate; A black matrix formed on the inner surface of the second substrate; A color filter layer formed on the inner surface exposed to the outside of the black matrix; A common electrode formed on an entire surface under the color filter layer; Liquid crystal layer interposed between the pixel electrode and the common electrode The plurality of partial pixel electrodes may include first to third partial pixel electrodes, and the first to third convex portions may be formed to correspond to the first to third partial pixel electrodes, respectively. LCD display device. delete 6. The method of claim 5, And the first to third convex portions are positioned at the centers of the first to third partial pixel electrodes, respectively. The method according to claim 1 or 5, And the protective layer is an organic insulating material, the surface of which is formed to have a flat surface. The method according to claim 1 or 5, And a plurality of column spacers formed at a predetermined interval under the common electrode of the second substrate to correspond to a part of the gate wiring or the data wiring. The method according to claim 1 or 5, And a overcoat layer having a flat surface formed between the color filter layer and the common electrode. The method according to claim 1 or 5, And a alignment layer formed on inner surfaces of each of the first and second substrates in contact with the liquid crystal layer. The method according to claim 1 or 5, And a first storage electrode formed to be parallel to the gate wiring, and a first storage electrode formed to branch from the storage wiring to surround the inside of the pixel area. 13. The method of claim 12, One electrode of the thin film transistor overlapping with the first storage electrode is formed so that the overlapping portion forms a second storage electrode. The method according to claim 1 or 5, The first to third partial pixel electrodes all have the same area and are electrically connected by first and second connection patterns made of the same material. Forming a gate wiring extending in one direction on a first substrate having a pixel region and a gate electrode connected to the gate wiring in the pixel region; Forming a gate insulating film over the gate wiring and the gate electrode; Forming a semiconductor layer and a source and drain electrode spaced apart from each other over the gate insulating layer, and a data line connected to the source electrode and crossing the gate line to define the pixel region; Applying an organic insulating material over the data line and the source and drain electrodes to form a protective layer having a flat surface; Forming a plurality of holes or convex portions in the pixel region by patterning the protective layer; Forming a pixel electrode including a plurality of partial pixel electrodes electrically connected to each other in each pixel area on the passivation layer having the plurality of holes or convex portions; And forming a plurality of holes in the pixel area by patterning the passivation layer, by placing an exposure mask having a transmissive area, a blocking area, and a transflective area over the passivation layer and exposing through the exposure mask. Performing a step; Developing the exposed protective layer to form a first hole having a first depth and exposing the drain electrode, and second and third holes having a depth lower than the first depth and having the same depth as each other; Method of manufacturing a vertical alignment mode liquid crystal display comprising a. delete 16. The method of claim 15, Forming a pixel electrode having the plurality of partial pixel electrodes, Depositing a transparent conductive material over the protective layer to form a transparent conductive material layer; Patterning the transparent conductive material layer to contact the drain electrode through the first hole and the first partial pixel electrode and the spaced apart from the first partial pixel electrode, respectively, recesses corresponding to the second and third holes, respectively Forming second and third partial pixel electrodes having Method of manufacturing a vertical alignment mode liquid crystal display comprising a. 16. The method of claim 15,  And wherein the first to third pixel electrodes are formed such that the first to third holes are located at the center thereof, respectively. 16. The method of claim 15, Forming a plurality of convex portions in the pixel region by patterning the protective layer, Positioning an exposure mask having a transmissive area, a blocking area, and a transflective area over the passivation layer, and performing exposure through the exposure mask; The drain contact hole exposing the drain electrode, the first to third convex portions having a first thickness, and a portion having a second thickness thinner than the first thickness are formed by performing the step of developing the exposed protective layer. Forming a protective layer comprising Method of manufacturing a vertical alignment mode liquid crystal display comprising a. 20. The method of claim 19, Forming a pixel electrode having the plurality of partial pixel electrodes, Depositing a transparent conductive material over the protective layer to form a transparent conductive material layer; Patterning the transparent conductive material layer to contact the drain electrode through the drain contact hole and having a convex shape corresponding to the first convex portion; and a second spaced apart from the first partial pixel electrode, respectively. And forming second and third partial pixel electrodes having convex shapes corresponding to the three convex portions, respectively. Method of manufacturing a vertical alignment mode liquid crystal display comprising a. The method of claim 17 or 20, In the forming of the first to third partial pixel electrodes, And forming a first connection pattern electrically connecting the first and second partial pixel electrodes and a second connection pattern electrically connecting the second and third partial pixel electrodes. Method for manufacturing a display device. 16. The method of claim 15, Forming the gate electrode and the gate wiring, And forming first storage electrodes spaced apart from each other in parallel with the gate lines and branching from the storage lines to surround the inside of the pixel area. 23. The method of claim 22, Wherein forming the source and drain electrodes comprises: And extending the drain electrode to overlap the first storage electrode such that a portion overlapping the first storage electrode forms a second storage electrode. 16. The method of claim 15, Forming a common electrode on a second substrate corresponding to the first substrate; Forming a seal pattern on an edge of one of the first and second substrates;  Positioning the pixel electrode of the first substrate and the common electrode of the second substrate to face each other and forming a liquid crystal layer between the two substrates; Bonding the first and second substrates with the liquid crystal layer interposed therebetween; Method of manufacturing a vertical alignment mode liquid crystal display further comprising. 25. The method of claim 24, Prior to forming the common electrode on the second substrate, Forming a black matrix on the second substrate corresponding to the gate and data wirings of the first substrate corresponding thereto; Forming a color filter layer partially overlapping the black matrix and having a red, green, and blue color filter pattern sequentially repeated corresponding to the pixel region; Method of manufacturing a vertical alignment mode liquid crystal display further comprising. 26. The method of claim 25, And forming an overcoat layer having a flat surface between the color filter layer and the common electrode.

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