CN102655156B - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN102655156B CN102655156B CN201210074221.4A CN201210074221A CN102655156B CN 102655156 B CN102655156 B CN 102655156B CN 201210074221 A CN201210074221 A CN 201210074221A CN 102655156 B CN102655156 B CN 102655156B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 title claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 64
- 239000010410 layer Substances 0.000 claims description 59
- 238000000034 method Methods 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- 239000010408 film Substances 0.000 claims description 20
- 238000009413 insulation Methods 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 238000003860 storage Methods 0.000 description 15
- 230000003071 parasitic effect Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 7
- 238000011161 development Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- VVTQWTOTJWCYQT-UHFFFAOYSA-N alumane;neodymium Chemical compound [AlH3].[Nd] VVTQWTOTJWCYQT-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention provides an array substrate and a manufacturing method thereof, which relate to the field of manufacturing of display elements and are used for reducing induced voltage of pixel electrodes to reduce screen flicker. The array substrate comprises a transparent substrate; grid lines and data lines crossed horizontally and longitudinally are arranged on the transparent substrate, and thin film transistors and the pixel electrodes are arranged in pixel units defined by the grid lines and the data lines; and grid electrodes of the thin film transistors are connected with the grid lines, source electrodes of the thin film transistors are connected with the data lines, and leakage electrodes of the thin film transistors are connected with the pixel electrodes. The array substrate is characterized in that the grid electrodes of the thin film transistors in an area just opposite to the leakage electrodes are thicker than that of the grid electrodes in an area just opposite to channels of the thin film transistors. The array substrate and the manufacturing method thereof are used in the field of manufacturing of the display elements.
Description
Technical field
The present invention relates to the manufacture field of display, particularly relate to a kind of array base palte and manufacture method thereof.
Background technology
With reference to the sectional view in the A-A direction shown in the vertical view of the array base palte shown in figure 1 and Fig. 2, the structure of array base palte 10 of the prior art is: on transparency carrier 109, be formed with transverse and longitudinal intersection grid line and data wire, be provided with thin-film transistor 104 and pixel electrode 103 in the pixel cell that described grid line and data wire limit; Wherein thin-film transistor 104 comprises: grid 105, source electrode 106 and drain electrode 107, and drain electrode 107 is electrically connected by via hole and pixel electrode 103.Can see from the angle of overlooking, grid 105 and drain electrode 107 have overlapping region, can produce parasitic capacitance C
gd.Due to the C of drain 107 and grid 105
gdthere is capacitance coupling effect, an induced potential Δ V can be produced:
ΔV＝V
α*C
gd/(C
gd+C
st+C
LC)
Wherein, V
αthe amplitude of the pulse voltage of the driving array base palte be added in grid line bus, C
stit is storage capacitance.
The appearance of induced potential can cause the asymmetric of driving voltage, causes the fluctuating of light penetration, causes low-frequency brightness change and head portrait shake, namely glimmers.For reducing induced potential impact, usually use larger storage capacitance C
stbut, conventional increase storage capacitance C
stmethod, as increased the area of storage capacitance, aperture opening ratio can be caused to reduce.In addition, although can see that reducing parasitic capacitance also can reduce induced potential by above-mentioned formula, due to relatively stricter to the specification requirement of thin-film transistor in prior art, the design reducing parasitic capacitance by changing overlapping area is made to be difficult to realize.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacture method thereof, in order to reduce the induced potential of pixel electrode thus to improve screen flicker.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, a kind of array base palte is provided, comprises: transparency carrier, this transparency carrier is provided with grid line and the data wire of transverse and longitudinal intersection, in the pixel cell that described grid line and data wire limit, is provided with thin-film transistor and pixel electrode; Wherein, the grid of described thin-film transistor is connected with grid line, and source electrode is connected with data wire, drains to be connected with pixel electrode; It is characterized in that, the grid of described thin-film transistor is just just little to the thickness in region at the raceway groove of this thin-film transistor to the Thickness Ratio in region in described drain electrode.
On the one hand, a kind of manufacture method of array base palte is provided, comprises:
Make grid metallic film on the transparent substrate, by patterning processes, described grid metal thin film patternsization is formed grid metal level; Described grid metal level comprises: grid line, and the grid that drain electrode is just just little to area thickness than raceway groove to region;
The transparency carrier being formed with grid metal level is formed gate insulation layer, active layer, source and drain metal level, protective layer and pixel electrode layer successively.
The embodiment of the present invention provides a kind of array base palte and manufacture method thereof, because the grid of thin-film transistor is just just little to the thickness in region at the raceway groove of this thin-film transistor to the Thickness Ratio in region in this drain electrode, so, increase the distance between grid and drain electrode in terms of existing technologies, the parasitic capacitance that grid and drain overlapping areas produce can be reduced, thus induced potential is reduced, and then improve screen flicker, improve product quality.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
A kind of structural representation of array base palte of Fig. 1 for providing in prior art;
A kind of cross-sectional view of array base palte of Fig. 2 for providing in prior art;
The structural representation of a kind of array base palte that Fig. 3 provides for the embodiment of the present invention;
The cross-sectional view of a kind of array base palte that Fig. 4 provides for the embodiment of the present invention;
The structural representation of the another kind of array base palte that Fig. 5 provides for the embodiment of the present invention;
The cross-sectional view of the another kind of array base palte that Fig. 6 provides for the embodiment of the present invention;
The schematic flow sheet of a kind of array substrate manufacturing method that Fig. 7 provides for the embodiment of the present invention;
The flow chart of another array substrate manufacturing method that Fig. 8 provides for the embodiment of the present invention;
The flow chart of another array substrate manufacturing method that Fig. 9 provides for the embodiment of the present invention.
Reference numeral: 10-array base palte; 101-grid line, 102-data wire, 103-pixel electrode, 104-thin-film transistor, 105-grid, 106-source electrode, 107-drains, 108-active layer, 109-transparency carrier;
20-array base palte; 201-grid line, 202-data wire, 203-pixel electrode, 204-thin-film transistor, 205-grid, 206-source electrode, 207-drains, 208-active layer, 209-transparency carrier, 300-protective layer, 301-gate insulation layer, 302-public electrode wire.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
A kind of array base palte that the embodiment of the present invention provides, exemplary, array base palte 20 as shown in Figure 3, from the angle of overlooking, source electrode 206 shape of the thin-film transistor 204 of this substrate is arc, and one end of this drain electrode 207 is in the centripetal side of arc source electrode 206.This array base palte 20 comprises:
Transparency carrier, this transparency carrier is provided with grid line 201 and the data wire 202 of transverse and longitudinal intersection, thin-film transistor 204 and pixel electrode 203 is provided with in the pixel cell that this grid line 201 and data wire 202 limit, wherein, the grid 205 of this thin-film transistor 204 is connected with grid line 201, source electrode 206 is connected with data wire 202, and drain electrode 207 is connected with pixel electrode 203; Further, the grid 205 of this thin-film transistor 204 is just just little to the thickness in region at the raceway groove of this thin-film transistor 204 to the Thickness Ratio in region in this drain electrode 207.
In order to the grid 205 that clearly describes thin-film transistor 204 in drain electrode 207 just to the Thickness Ratio in region at the raceway groove of this thin-film transistor 204 just to the thickness in region this structure little, can the sectional view that cuts along B-B direction of reference diagram 3, as shown in Figure 4, grid 205 is just little to other area thickness of Thickness Ratio in region in drain electrode 207, presents concave architecture.
Optionally, draining on the basis just to the thickness in region at reduction grid, the grid of all right this thin-film transistor of reduction further just to the thickness in region, makes the grid of described thin-film transistor just just little to the thickness in region at the raceway groove of this thin-film transistor to the Thickness Ratio in region at described source electrode at source electrode.The distance that this not only increases between grid and drain electrode also increases the distance between grid and source electrode, can reduce the parasitic capacitance of drain and gate, thus also can reduce induced potential.Further, the thickness of source electrode can be equal with the thickness of drain electrode.
Optionally, as shown in Figure 3 and Figure 4, the array base palte 20 that the embodiment of the present invention provides also is formed with public electrode wire 302, and public electrode wire 302 and data wire 202 are arranged with layer, and electric insulation between the two.Only every layer protective layer between the two-plate (public electrode wire and pixel electrode) making storage capacitance like this; compared with in prior art between two-plate across gate insulation layer and protective layer dielectric layers as shown in Figure 1; storage capacitance spacing reduces; thus increase storage capacitance; further reduce induced potential; improve screen flicker, improve product quality.For ensureing electric insulation between the public electrode wire that same layer is arranged and data wire, concrete, public electrode wire and data wire can be arranged in parallel, the setting of many via holes can be avoided like this relative to other set-up modes, simplify technique.
Further, can also be formed with active layer partial pattern below this public electrode wire 302, described active layer partial pattern supports described public electrode wire completely, further can reduce the distance between public electrode wire and pixel electrode.Optionally, active layer partial pattern overlaps with the shape of public electrode wire.
A kind of array base palte that the embodiment of the present invention provides, because the grid of thin-film transistor is just just little to the thickness in region at the raceway groove of this thin-film transistor to the Thickness Ratio in region in this drain electrode, so, increase the distance between grid and drain electrode in terms of existing technologies, the parasitic capacitance that grid and drain overlapping areas produce can be reduced, thus induced potential is reduced, and then improve screen flicker, improve the image display quality of product, further, public electrode and data wire are arranged with layer, and not electrical connection, the distance between public electrode wire and pixel electrode can be reduced, while increasing storage capacitance, also reduce induced potential, thus also improve screen flicker, improve product drawing display quality.
The embodiment of the present invention additionally provides a kind of array base palte, exemplary, array base palte 20 as shown in Figure 5, and from the angle of overlooking, the source electrode 206 of thin-film transistor 204, the shape of drain electrode 207 can also be rectangles.This array base palte 20 comprises:
Transparency carrier, this transparency carrier is provided with grid line 201 and the data wire 202 of transverse and longitudinal intersection, thin-film transistor 204 and pixel electrode 203 is provided with in the pixel cell that this grid line 201 and data wire 202 limit, wherein, the grid 205 of this thin-film transistor 204 is connected with grid line 201 with grid grid 205, source electrode 206 is connected with data wire 202, and drain electrode 207 is connected with pixel electrode 203; Further, the grid 205 of this thin-film transistor 204 is just just as shown in Figure 6 little to the thickness in region at the raceway groove of this thin-film transistor 204 to the Thickness Ratio in region in this drain electrode 207.
Shown in the sectional view cut along the B-B direction of array base palte shown in Fig. 5 and Fig. 6, reducing grid 205 on the basis of drain electrode 207 just to the thickness in region, the all right grid 205 of reduction further just to the thickness in region, makes the grid of described thin-film transistor just just little to the thickness in region at the raceway groove of this thin-film transistor to the Thickness Ratio in region at described source electrode at source electrode 206.The distance that this not only increases between grid and drain electrode also increases the distance between grid and source electrode, makes parasitic capacitance C
gdwhile reducing, C
gsalso reduce, thus further reduce parasitic capacitance, and then reduce induced potential, improve screen flicker, improve product drawing display quality.
On array base palte shown in above-mentioned Fig. 5 and Fig. 6, public electrode wire keeps and position consistency of the prior art.With reference to the position of the public electrode wire described in a upper embodiment, public electrode wire also can be arranged with layer with data wire in embodiments of the present invention, and electric insulation between the two.Only every layer protective layer between the two-plate (public electrode wire and pixel electrode) making storage capacitance like this; compared with in prior art between two-plate across gate insulation layer and protective layer dielectric layers as shown in Figure 1; storage capacitance spacing reduces; thus increase storage capacitance; reduce induced potential; improve screen flicker, improve product quality.For ensureing electric insulation between the public electrode wire that same layer is arranged and data wire, concrete, public electrode wire and data wire can be arranged in parallel, data wire and public electrode wire can be formed, Simplified flowsheet by a photoetching process simultaneously.
Further, active layer partial pattern can also be formed with below this public electrode wire, described active layer partial pattern supports described public electrode wire completely, reduces the distance of public electrode and pixel electrode further, can increase storage capacitance like this and then reduce induced potential.Optionally, active layer partial pattern overlaps with the shape of public electrode wire.The improvement on grid is only described in Fig. 5 and Fig. 6, improvement those skilled in the art for public electrode wire can by above-mentioned text description, and the structure of array base palte that the clear and beyond all doubt determination embodiment of the present invention of accompanying drawing (Fig. 3 and Fig. 4) in a upper embodiment provides.
A kind of array base palte that the embodiment of the present invention provides, because the grid of thin-film transistor is just just little to the thickness in region at the raceway groove of this thin-film transistor to the Thickness Ratio in region in this drain electrode, so, increase the distance between grid and drain electrode in terms of existing technologies, the parasitic capacitance that grid and drain overlapping areas produce can be reduced, thus induced potential is reduced, and then improve screen flicker, improve product quality.
The manufacture method of a kind of array base palte that the embodiment of the present invention provides, as shown in Figure 7, comprising:
S401, on the transparent substrate making grid metallic film, form grid metal level by patterning processes by described grid metal thin film patternsization; This grid metal level comprises: grid line, and the grid that drain electrode is just just little to area thickness than raceway groove to region.
So just make to increase in terms of existing technologies the distance between grid and drain electrode, the parasitic capacitance that grid and drain overlapping areas produce can be reduced, thus induced potential is reduced, and then improve screen flicker, improve product quality.
S402, on the transparency carrier being formed with grid metal level, form gate insulation layer, active layer, source and drain metal level, protective layer and pixel electrode layer successively.
Wherein, preferably, form described active layer, the process of source and drain metal level is specially: on the transparency carrier being formed with gate insulation layer, make semiconductive thin film and source and drain metallic film, by a mask patterning processes, described semiconductive thin film and source and drain metal thin film patterns are formed with active layer and source and drain metal level; Described source and drain metal level comprises: the source electrode of data wire, thin-film transistor and drain electrode and public electrode wire; Wherein, public electrode wire and data wire electric insulation.So, due to only alternating floor protective layer between public electrode wire and pixel electrode, compared with prior art reduce the distance between public electrode wire and pixel electrode, increase storage capacitance, thus reduce induced potential further on the basis of step S401.
Below for array base palte Fig. 3 (or Fig. 4) Suo Shi, as shown in Figure 8, provide its manufacture method.
Adopt sputtering method deposition grid metallic film on the transparent substrate, the material of this metallic film can be molybdenum, titanium, chromium, aluminium, aluminium neodymium or its combination.Secondly, after coating photoresist, semi-transparent or grayscale mask method half exposure is carried out to this transparency carrier, after development, obtain the concavely structure of the photoresist shown in Fig. 8 (a).
Use wet-etching technique, grid metallic film not covered by photoresist is etched away, obtains the structure shown in Fig. 8 (b).
Carry out ashing to photoresist, the photoresist of thinner position is ashed completely originally, exposes the grid metallic film under it, structure as Suo Shi Fig. 8 (c).
To the grid metallic film wet etching exposed, obtain the structure of Fig. 8 (d).
Stripping photoresist, obtain the grid metal level graphically, grid metal level comprises: the grid of thin-film transistor, the structure as shown in Fig. 8 (e).
Deposit substrate surface deposited semiconductor film (its material is semiconductor and doped semiconductor) and the source and drain metallic film successively of gate insulation layer 300, coating photoresist, then carry out second time exposure.This technique, first grayscale mask plate or pellicle mask board to explosure is utilized, after development, first time etching is carried out to source and drain metallic film, carry out ashing afterwards, remove the photoresist of corresponding channel region, carry out the etching of active layer again, carry out second time source and drain metallic film etching subsequently, carve the source and drain metal level in dechannelling, the active layer at array substrate raceway groove place etches again, remove semiconductor doping layer, the active layer is graphically obtained after stripping photoresist, data wire, the source electrode 206 of thin-film transistor and drain electrode 207, and public electrode wire 302, as shown in Fig. 8 (f).Wherein, public electrode wire 302 is arranged in parallel with data wire.Due to when data wire and public electrode wire are arranged with layer, if the orientation of public electrode wire is identical with original technology, namely arrange perpendicular to data wire, in order to avoid data wire and public electrode wire short circuit, then must make the public electrode wire being interrupted and arranging, every section of public electrode wire all needs mutual series connection, the position that this structural requirement corresponds to every segment public electrode wire two ends on the protection layer arranges via hole, in order to Simplified flowsheet, in the embodiment of the present invention preferably by public electrode wire and data wire arranged in parallel, avoid the manufacture craft that multiple via hole is set.
Continue Deposition of protective layer subsequently; pass through mask exposure; carry out again after development etching to arrange the via hole draining and be connected with pixel electrode thereon; after completing, its cross section is as shown in Fig. 8 (g); because institute's drawings attached in Fig. 8 is all based on the cross section in B-B direction in Fig. 3; therefore the via hole formed in Fig. 8 (g) does not identify, but those skilled in the art can the position of the beyond all doubt determination via hole of structure chart according to Fig. 3.
After having deposited the protective layer of via hole; carrying out the graphical of pixel electrode; as shown in Fig. 8 (h); be specially; deposit a transparency conducting layer on the protection layer; this conductive layer can be tin indium oxide ITO, carries out mask exposure to this conductive layer, obtains patterned pixel electrode after development etching.This pixel electrode part covers public electrode wire, both front projections region that partly overlaps is storage capacitance covering position, so, owing to being also formed with active layer partial pattern below public electrode wire, reduce the distance between public electrode wire and pixel electrode, thus increase storage capacitance, further reduce induced potential, improve screen flicker, improve product quality.
Below for the array base palte shown in Fig. 5 (or Fig. 6), as shown in Figure 9, provide its manufacture method.
As shown in Fig. 9 (a), transparency carrier 209 deposits grid metallic film and photoresist.
As shown in Fig. 9 (b), semi-transparent or grayscale mask method half exposure is carried out to photoresist, after development, obtains the photoresist of convex architecture.
As shown in Fig. 9 (c), the method for wet etching is utilized to etch away metal not covered by photoresist.
As shown in Fig. 9 (d), enter dry quarter and carry out photoresist ashing in equipment, make a part of grid metallic film exposed.
As shown in Fig. 9 (e), etch away a part of metal of exposed grid metallic film by dry method of carving, remove photoresist and form staged grid 205, as shown in Fig. 9 (f).
As shown in Fig. 9 (g), grid deposits gate insulation layer 301, semiconductive thin film 208 (can comprise semiconductor and doped semiconductor double-layer films), and coats negative photoresist.
Utilize grid to do light shield, adopt self-aligned exposure (shown in Fig. 9 (g), it is exposure from bottom to top that light injects direction) from substrate back, development, then carry out being formed with active layer 208 dry quarter; Wherein, so-called self-aligned exposure refers to that light injects the technique of carrying out using gate metal as light shield exposing from the back side of array base palte, and when adopting self-aligned exposure, the photoresist used is negative photoresist; Shown in Fig. 9 (h), it is exposure from bottom to top that light injects direction.So just using the pattern of the pattern of grid as mask plate, and can not need additionally to use mask plate just can be formed with the pattern of active layer, can mask plate be saved.Moreover, owing to adopting this back of the body exposure technology when without the need to calibrating mask plate position, the pattern consistent with grid can be made, therefore this back-exposure technique can be called self-registered technology.
Remove photoresist, form the structure shown in Fig. 9 (I).
As shown in Fig. 9 (j), active layer deposits source and drain metallic film, by third time patterning processes, first etches away the metal around and in raceway groove by the method for wet etching, etch away the doped semiconductor in raceway groove by the method at dry quarter, form source-drain electrode 206,207 and raceway groove.Afterwards, Deposition of protective layer 300, forms via hole by the 4th patterning processes.Finally, deposit transparent conductive film, forms pixel electrode 203 by the 5th patterning processes.
So, the stepped grid of formation, increase between grid and drain electrode, the distance between grid and source electrode, makes parasitic capacitance C
gdwhile reducing, C
gsalso reduce, further can reduce parasitic capacitance like this, thus reach the effect reducing screen flicker, in addition, active layer and source-drain electrode separate to be prepared, and take grid as light shield, back of the body exposure is carried out to active layer, such patterning processes can obtain the active layer all blocked by grid, avoids active layer under backlight impact and produces photoelectric current, improve processing quality.
The manufacture method of a kind of array base palte that the embodiment of the present invention provides, because the grid of thin-film transistor is just just little to the thickness in region at the raceway groove of this thin-film transistor to the Thickness Ratio in region in this drain electrode, so, increase the distance between grid and source-drain electrode in terms of existing technologies, the parasitic capacitance that grid and drain overlapping areas produce can be reduced, thus induced potential is reduced, and then improve screen flicker, improve product quality.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (10)
1. an array base palte, comprising: transparency carrier, this transparency carrier is provided with grid line and the data wire of transverse and longitudinal intersection, in the pixel cell that described grid line and data wire limit, is provided with thin-film transistor and pixel electrode; Wherein, the grid of described thin-film transistor is connected with grid line, and source electrode is connected with data wire, drains to be connected with pixel electrode; It is characterized in that, the grid of described thin-film transistor is completely just completely just little to the thickness in region at the raceway groove with this thin-film transistor to the Thickness Ratio in region with described drain electrode.
2. array base palte according to claim 1, is characterized in that, the grid of described thin-film transistor is just just little to the thickness in region at the raceway groove of this thin-film transistor to the Thickness Ratio in region at described source electrode.
3. array base palte according to claim 2, is characterized in that, the source electrode of described thin-film transistor is equal with drain electrode thickness.
4. the array base palte according to any one of claim 1-3, is characterized in that, from the angle of overlooking, the source electrode shape of described thin-film transistor is arc, and one end of the drain electrode of described thin-film transistor is in the centripetal side of arc source electrode.
5. the array base palte according to any one of claim 1-3, is characterized in that, from the angle of overlooking, the source electrode of described thin-film transistor, the shape of drain electrode are rectangle.
6. the array base palte according to any one of claim 1-3, is characterized in that, also comprises: public electrode wire; Described public electrode wire and described data wire are arranged with layer, and electric insulation between the two.
7. array base palte according to claim 6, is characterized in that, described public electrode wire is parallel with described data wire.
8. array base palte according to claim 7, is characterized in that, is formed with active layer partial pattern below described public electrode wire, and described active layer partial pattern supports described public electrode wire completely.
9. a manufacture method for array base palte, is characterized in that, comprising:
Make grid metallic film on the transparent substrate, by patterning processes, described grid metal thin film patternsization is formed grid metal level; Described grid metal level comprises: grid line, and with drain electrode completely just to region ratio and completely just little to the area thickness grid of raceway groove;
The transparency carrier being formed with grid metal level is formed gate insulation layer, active layer, source and drain metal level, protective layer and pixel electrode layer; Wherein, described source and drain metal level comprises public electrode.
10. manufacture method according to claim 9, is characterized in that, forms described active layer, the process of source and drain metal level is specially:
The transparency carrier being formed with gate insulation layer makes semiconductive thin film and source and drain metallic film, by a mask patterning processes, described semiconductive thin film and source and drain metal thin film patterns is formed with active layer and source and drain metal level; Described source and drain metal level comprises: the source electrode of data wire, thin-film transistor and drain electrode and public electrode wire; Wherein, public electrode wire and data wire are without being electrically connected.
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| CN201210074221.4A CN102655156B (en) | 2012-03-19 | 2012-03-19 | Array substrate and manufacturing method thereof |
| PCT/CN2012/086215 WO2013139148A1 (en) | 2012-03-19 | 2012-12-07 | Array substrate and manufacturing method thereof, and display device |
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| CN102655156B (en) * | 2012-03-19 | 2015-01-07 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof |
| CN103489923B (en) | 2013-10-16 | 2017-02-08 | 京东方科技集团股份有限公司 | Film transistor as well as manufacturing method and repairation method thereof and array substrate |
| CN104576523A (en) * | 2013-10-16 | 2015-04-29 | 北京京东方光电科技有限公司 | Array substrate, production method of array substrate and display device |
| CN104049799B (en) * | 2014-05-30 | 2017-04-05 | 京东方科技集团股份有限公司 | A kind of array base palte, In-cell touch panel and display device |
| CN106057736B (en) * | 2016-08-02 | 2022-12-27 | 信利半导体有限公司 | Preparation method of TFT substrate and TFT substrate |
| CN106449652B (en) * | 2016-09-26 | 2019-05-28 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel and display equipment |
| CN106449518A (en) * | 2016-10-14 | 2017-02-22 | 武汉华星光电技术有限公司 | Manufacturing method of LTPS (low temperature poly-silicon) array substrate and array substrate |
| US10957792B2 (en) * | 2018-08-14 | 2021-03-23 | Infineon Technologies Ag | Semiconductor device with latchup immunity |
| CN109143705A (en) * | 2018-09-18 | 2019-01-04 | 深圳市华星光电技术有限公司 | Improve the panel of display resolution |
| CN110931514B (en) * | 2019-11-29 | 2022-04-08 | 云谷（固安）科技有限公司 | Array substrate and display panel |
| CN111192885B (en) * | 2020-03-04 | 2023-12-19 | 合肥鑫晟光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN112635574B (en) * | 2020-12-31 | 2023-06-09 | 北海惠科光电技术有限公司 | Liquid crystal display panel, thin film transistor and preparation method thereof |
| CN112864172A (en) * | 2021-01-04 | 2021-05-28 | Tcl华星光电技术有限公司 | Photosensitive transistor, color film substrate and manufacturing method thereof |
| CN113161291B (en) * | 2021-04-08 | 2022-11-15 | 北海惠科光电技术有限公司 | Array substrate manufacturing method and array substrate |
| CN113589605B (en) * | 2021-07-29 | 2024-01-16 | 武汉京东方光电科技有限公司 | Array substrate, preparation method thereof and display panel |
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| CN102655156A (en) | 2012-09-05 |
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