CN106057736A - Preparation method of TFT substrate and TFT substrate - Google Patents
Preparation method of TFT substrate and TFT substrate Download PDFInfo
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- CN106057736A CN106057736A CN201610620519.9A CN201610620519A CN106057736A CN 106057736 A CN106057736 A CN 106057736A CN 201610620519 A CN201610620519 A CN 201610620519A CN 106057736 A CN106057736 A CN 106057736A
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- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 105
- 238000005530 etching Methods 0.000 claims description 37
- 238000009413 insulation Methods 0.000 claims description 37
- 238000001259 photo etching Methods 0.000 claims description 20
- 239000003795 chemical substances by application Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 230000035699 permeability Effects 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 230000008569 process Effects 0.000 abstract description 5
- 238000001459 lithography Methods 0.000 abstract 2
- 239000000463 material Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004568 cement Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
The invention discloses a preparation method of a TFT substrate and the TFT substrate. The TFT substrate comprises a plurality of pixel units. Each of the pixel units comprises a gate metal layer, a gate insulating layer, a semiconductor layer, a source/drain metal layer, an insulating dielectric layer and a pixel electrode layer which are orderly formed on a transparent substrate. A data line, a gate electrode and a gate line are arranged on a same layer. The data line and a source electrode are connected through the first through hole and the second through hole of the insulating dielectric layer and the first connecting line of the pixel electrode layer. According to the preparation method of a TFT substrate, two times of lithography is reduced on the basis of original five times of lithography processes, the TFT preparation process is simplified, the product cost is reduced, the production efficiency is improved, the fewer the process steps are, the higher the yield of products is, and the easier the control of quality is.
Description
Technical field
The present invention relates to field of liquid crystal display, particularly relate to preparation method and the TFT substrate of a kind of TFT substrate.
Background technology
Along with the development of the product such as smart mobile phone, panel computer, TFT-LCD liquid crystal display obtains the most widely
Application.Along with the competition of industry, the TFT-LCD screen of high performance-price ratio the most constantly pushes market, unexpectedly uses the most advanced technique
Technology, the optimization of technique is simplified, reduce production cost and become the strong guarantee of existence in market with keen competition.
TFT-LCD industry production TFT is mainly 5 photoetching techniques, and part manufacturer uses 4 photoetching techniques.And for
5 photoetching producing employing at present of TFT and 4 photoetching techniques still suffer from the problems such as Technology is complicated.
A kind of FFS type TFT-LCD array substrate is disclosed in the patent of invention that a notification number is CN 102023432B
And preparation method thereof, its preparation method carries out 3 photoetching can be completed, but it uses double tune mask plate to expose photoresist
Light and development treatment, grid line exists the semiconductor layer of residual, easily causes and the biggest deposits electric capacity, affects structural stability,
Cause the bad of product；A kind of thin film field-effect is disclosed brilliant in the patent of invention that a notification number is CN 102315130B
Body pipe and preparation method thereof, its preparation method carries out 3 photoetching can be completed, but its high temperature photoresist used is than conventional light
Photoresist cost is higher, and TFT glass substrate does not tolerates high temperature, is unfavorable for the reduction of cost and the raising of product yield.
Summary of the invention
In order to solve above-mentioned the deficiencies in the prior art, the present invention provides preparation method and the TFT base thereof of a kind of TFT substrate
Plate.Data wire and gate electrode, grid line are located at same layer, by the first via and second mistake of insulating medium layer by this TFT substrate
First connecting line of hole and pixel electrode layer connects data wire and source electrode, and its preparation method is in original 5 photoetching processes
On the basis of reduce 2 photoetching, simplify TFT preparation technology, reduce production cost, improve production efficiency, processing step is the fewest, product
Yields the highest, quality is more easily controlled.
The technical problem to be solved is achieved by the following technical programs:
The preparation method of a kind of TFT substrate, comprises the steps:
S1: be sequentially depositing grid metal level, gate insulation layer, semiconductor layer and source drain metal layer on the transparent substrate；
S2: coat the first photoresist in described source drain metal layer, carries out mask and etching, forms data wire, grid line, grid electricity
Pole, gate insulation layer, semiconductor channel, source electrode and drain electrode；
S3: deposit insulating medium layer on the substrate described in S2；
S4: coat the second photoresist on described insulating medium layer, carries out mask and etching, is formed and lays respectively at data wire, source
First via of the insulating medium layer above electrode and drain electrode, the second via and the 3rd via；
S5: pixel deposition electrode layer on the substrate described in S4；
S6: coat the 3rd photoresist on described pixel electrode layer, carry out mask and etching, formed pixel electrode, data wire and
Second connecting line of the first connecting line, drain electrode and the pixel electrode of source electrode.
Further, before step S1, also include step S0: provide a transparency carrier, clean described transparency carrier, go
Fall the dirt on described transparency carrier.
Further, described step S2 includes:
S21: described first photoresist is carried out gray level mask technique, forms the first photoetching agent pattern, wherein, source electrode region,
First photoresist of drain regions has the first thickness, grid region, data wire region and the first of semiconducting channel region
Photoresist has the second thickness, and other region covers without the first photoresist, and described first thickness is bigger than the second thickness；
S22: by etching technics, removes not by the source drain metal layer in other region described in the first photoresist covering, partly leads
Body layer and gate insulation layer, form data wire, grid line, gate electrode and gate insulation layer；
S23: described first photoresist is carried out cineration technics, removes the first photoresist of the second thickness, expose grid region,
Data wire region and the source drain metal layer of semiconducting channel region；
S24: by etching technics, source drain metal layer that etching exposes and lower semiconductor layer thereof, formed semiconductor channel,
Source electrode and drain electrode；
S25: described first photoresist is carried out demoulding, peels off remaining first photoresist.
Further, described S4 includes:
S41: described second photoresist is carried out gray level mask technique, forms the second photoetching agent pattern, wherein, source electrode region,
Drain regions, the second photoresist of grid region have the 3rd thickness, and data wire region covers without the second photoresist, other district
Second photoresist in territory has the 4th thickness, and described 4th thickness is more than the 3rd thickness；
S42: by etching technics, remove the insulating medium layer in the data wire region not covered by the second photoresist, expose
The gate insulation layer in data wire region and semiconductor layer；
S43: described second photoresist is carried out cineration technics, removes the photoresist of the 3rd thickness, expose source electrode region, leakage
Electrode zone and the insulating medium layer of grid region；
S44: by etching technics, removes the insulation on the gate insulation layer in data wire region and semiconductor layer, source/drain electrode region
Semiconductor layer in dielectric layer, grid region and the gate insulation layer on insulating medium layer, data wire region and semiconductor layer, formed
Lay respectively at the first via of insulating medium layer, the second via and the 3rd via above data wire, source electrode and drain electrode；
S45: described second photoresist is carried out demoulding, peels off remaining second photoresist.
Further, described S6 includes:
S61: described 3rd photoresist carries out gray level mask technique, forms the 3rd photoetching agent pattern, wherein, described quasiconductor ditch
Region, road and grid region no third photoresist cover；
S62: by etching technics, remove semiconducting channel region and the pixel electrode of grid region that no third photoresist covers
Layer, forms the second connecting line of the first connecting line, drain electrode and the pixel electrode of pixel electrode, data wire and source electrode；
S63: described 3rd photoresist is carried out demoulding, peels off remaining 3rd photoresist.
Further, when step S21 utilizing gray level mask plate carry out mask, data wire region, grid region and partly lead
The partial light permeability position of bulk channel region correspondence mask plate, the light tight portion of source electrode region mask plate corresponding with drain regions
Position, the complete printing opacity position of other region correspondence mask plates.
Further, when step S41 utilizing gray level mask plate carry out mask, data wire region correspondence mask plate complete
Printing opacity position, the partial light permeability position of the corresponding mask plate of source electrode region, drain regions and grid region, other regions are corresponding
The light tight position of mask plate.
A kind of TFT substrate, including multiple pixel cells, each pixel cell includes the grid sequentially formed on the transparent substrate
Metal level, gate insulation layer, semiconductor layer, source drain metal layer, insulating medium layer and pixel electrode layer, wherein:
Described grid metal level includes that gate electrode, horizontal grid line and vertical data wire, described gate electrode and grid line connect, described
Data wire and gate electrode, grid line disconnect；
Described gate insulation layer is positioned on described gate electrode and grid line, for being insulated with source/drain electrode by grid line/gate electrode；
Described semiconductor layer is positioned on the gate insulation layer of described gate electrode, and it is formed semiconductor channel；
Described source drain metal layer includes source electrode and drain electrode, lays respectively on the semiconductor channel both sides of described semiconductor layer
Side；
Described insulating medium layer, for semiconductor layer, gate electrode being insulated with pixel electrode layer, is provided with the first mistake at its data wire
It is provided with at hole, source electrode at the second via, drain electrode and is provided with the 3rd via；
Described pixel electrode layer includes pixel electrode and the first connecting line, the second connecting line.
Further, described source electrode is by the first via, the second via and the pixel electrode layer on insulating medium layer
On the first connecting line be connected with data wire, described drain electrode is by the 3rd via and pixel electrode layer on insulating medium layer
On the second connecting line be connected with pixel electrode.
There is advantages that
1. data wire and gate electrode, grid line are located at same layer, by first via and second of insulating medium layer by this TFT substrate
First connecting line of via and pixel electrode layer connects data wire and source electrode, and its preparation method is in original 5 photoetching processes
On the basis of reduce 2 photoetching, simplify TFT preparation technology, reduce production cost, improve production efficiency, processing step is the fewest,
The yields of product is the highest, and quality is more easily controlled；
2. using gray level mask plate that photoresist is carried out mask and etching, operability is higher, will not remain quasiconductor on grid line
Layer, it affects structural stability, and the yields of product is high；
3. photoresist is conventional photoresist, and production cost is low, and photoresist can perform etching and peel off at a normal temperature, no
TFT glass substrate can be caused damage, the yields of its product is higher.
Accompanying drawing explanation
The schematic diagram of the TFT substrate that Fig. 1 provides for the present invention；
Fig. 2 is the A-A profile of the TFT substrate shown in Fig. 1；
Fig. 3 is the B-B profile of the TFT substrate shown in Fig. 1；
Fig. 4 is the profile after forming grid metal level, gate insulation layer, semiconductor layer, source drain metal layer on the transparent substrate；
Fig. 5 a-5b be coat the first photoresist in the structure of Fig. 4 after, the first photoresist is carried out the section after gray level mask technique
Figure；
Fig. 6 a-6b is the profile after the structure to Fig. 5 a-5b performs etching technique；
Fig. 7 a-7b is the profile after the first photoresist in Fig. 6 a-6b carries out cineration technics；
Fig. 8 a-8b is the profile after the structure to Fig. 6 a-6b performs etching technique；
Fig. 9 a-9b is the profile after peeling off the first photoresist demoulding in Fig. 8 a-8b；
Figure 10 a-10b is the profile after the structure to Fig. 9 a-9b forms insulating medium layer；
Figure 11 a-11b is, after the structure to Figure 10 a-10b coats the second photoresist, the second photoresist to be carried out gray level mask technique
After profile；
Figure 12 a-12b is the profile after the structure to Figure 11 a-11b performs etching technique；
Figure 13 a-13b is the profile after the second photoresist in Figure 12 a-12b carries out cineration technics；
Figure 14 a-14b is the profile after the structure to Figure 13 a-13b performs etching technique；
Figure 15 a-15b is the profile after peeling off the second photoresist demoulding in Figure 14 a-14b；
Figure 16 a-16b is the profile after the structure to Figure 15 a-15b forms pixel capacitance layer；
After Figure 17 a-17b is coating the 3rd optical cement of the structure to Figure 16 a-16b, the 3rd optical cement is carried out gray level mask technique
After profile；
Figure 18 a-18b is the profile after the structure to Figure 17 a-17b performs etching technique；
Figure 19 a-19b is the profile after peeling off the 3rd photoresist demoulding in Figure 18 a-18b.
Detailed description of the invention
The present invention will be described in detail with embodiment below in conjunction with the accompanying drawings.
Embodiment 1
As shown in Fig. 4-19b, the preparation method of a kind of TFT substrate, comprise the steps:
S1: be sequentially depositing grid metal level 2, gate insulation layer 3, semiconductor layer 5 and source drain metal layer 5 on transparency carrier 1.
Grid metal level 2 and the material of source drain metal layer 5 in this step preferably but are not limited to Al, Cu, Mo or Cr etc.,
The material of gate insulation layer 3 preferably but is not limited to silicon nitride, silicon oxide or silicon oxynitride etc., the material of semiconductor layer 5 preferably but
It is not limited to monocrystal silicon, polysilicon or non-crystalline silicon etc..
S2: coat the first photoresist 8 in described source drain metal layer 5, carries out mask and etching, forms data wire 22, grid
Line 23, gate electrode 21, gate insulation layer 3, semiconductor channel 41, source electrode 52 and drain electrode 51.
Wherein, described step S2 includes:
S21: described first photoresist 8 is carried out gray level mask technique, forms the first photoresist 8 pattern, wherein, source electrode 52 district
Territory, first photoresist 8 in drain electrode 51 region have the first thickness, grid line 23 region, data wire 22 region and semiconductor channel
First photoresist 8 in 41 regions has the second thickness, and other region covers without the first photoresist 8, described first thickness ratio second
Thickness is big；
S22: by etching technics, remove not by the first photoresist 8 cover described in the source drain metal layer 5 in other region, half
Conductor layer 5 and gate insulation layer 3, form data wire 22, grid line 23, gate electrode 21 and gate insulation layer 3；
S23: described first photoresist 8 is carried out cineration technics, removes the first photoresist 8 of the second thickness, expose grid line 23
Region, data wire 22 region and the source drain metal layer 5 in semiconductor channel 41 region；
S24: by etching technics, etch the source drain metal layer 5 and lower semiconductor layer 5 thereof exposed, form semiconductor channel
41, source electrode 52 and drain electrode 51；
S25: described first photoresist 8 is carried out demoulding, peels off remaining first photoresist 8.
S3: deposit insulating medium layer 6 on the substrate described in S2.
Dielectric insulation layer in this step preferably but is not limited to silicon nitride, silicon oxide or silicon oxynitride etc..
S4: coat the second photoresist 9 on described insulating medium layer 6, carries out mask and etching, is formed and lays respectively at data
First via the 61, second via 62 and the 3rd via 63 of the insulating medium layer 6 above line 22, source electrode 52 and drain electrode 51.
Wherein, described S4 includes:
S41: described second photoresist 9 is carried out gray level mask technique, forms the second photoresist 9 pattern, wherein, source electrode 52 district
Territory, drain electrode 51 region, second photoresist 9 in grid line 23 region have the 3rd thickness, and data wire 22 region is without the second photoresist 9
Covering, second photoresist 9 in other region has the 4th thickness, and described 4th thickness is more than the 3rd thickness；
S42: by etching technics, removes the insulating medium layer 6 in data wire 22 region not covered by the second photoresist 9, cruelly
Expose gate insulation layer 3 and the semiconductor layer 5 in data wire 22 region；
S43: described second photoresist 9 is carried out cineration technics, removes the photoresist of the 3rd thickness, expose source electrode 52 district
Territory, drain electrode 51 region and the insulating medium layer 6 in grid line 23 region；
S44: by etching technics, remove on gate insulation layer 3 and semiconductor layer 5, source/drain electrode 51 region in data wire 22 region
Insulating medium layer 6, the semiconductor layer 5 on grid line 23 region and the gate insulation layer 3 on insulating medium layer 6, data wire 22 region
With semiconductor layer 5, form the first mistake laying respectively at the insulating medium layer 6 above data wire 22, source electrode 52 and drain electrode 51
Hole the 61, second via 62 and the 3rd via 63；
S45: described second photoresist 9 is carried out demoulding, peels off remaining second photoresist 9.
S5: pixel deposition electrode layer 7 on the substrate described in S4.
The material of the pixel electrode layer 7 in this step preferably but is not limited to ITO.
S6: coat the 3rd photoresist 10 on described pixel electrode layer 7, carry out mask and etching, formed pixel electrode 73,
Second connecting line 72 of the first connecting line 71, drain electrode 51 and the pixel electrode 73 of data wire 22 and source electrode 52.
Wherein, described S6 includes:
S61: described 3rd photoresist 10 carries out gray level mask technique, forms the 3rd photoresist 10 pattern, wherein, described partly leads
Bulk channel 41 region and grid line 23 region no third photoresist 10 cover；
S62: by etching technics, remove semiconductor channel 41 region and the picture in grid line 23 region that no third photoresist 10 covers
Element electrode layer 7, forms pixel electrode 73, data wire 22 and the first connecting line 71, drain electrode 51 and the pixel electrode of source electrode 52
Second connecting line 72 of 73；
S63: described 3rd photoresist 10 is carried out demoulding, peels off remaining 3rd photoresist 10.
This preparation method is by being located at same layer, by insulating medium layer 6 by data wire 22 and gate electrode 21, grid line 23
First connecting line 71 of the first via 61 and the second via 62 and pixel electrode layer 3 connects data wire 22 and source electrode 52,
Reduce by 2 photoetching on the basis of originally 5 times photoetching processes, simplify the preparation technology of TFT, reduce production cost, improve and produce effect
Rate, processing step is the fewest, and the yields of product is the highest, and quality is more easily controlled；Use gray level mask plate that photoresist is covered
Film and etching, operability is higher, will not remain semiconductor layer on grid line, and it affects structural stability, and the yields of product is high；
Photoresist is conventional photoresist, and production cost is low, and photoresist can perform etching and peel off at a normal temperature, will not be right
TFT glass substrate causes damage, and the yields of its product is higher.
Preferably, before step S1, also include step S0: provide a transparency carrier 1, clean described transparency carrier 1, go
Fall the dirt on described transparency carrier 1.
Transparency carrier 1 in this step preferably but is not limited to glass substrate.
Preferably, when step S21 utilizing gray level mask plate carry out mask, data wire 22 region, grid line 23 region and half
The partial light permeability position of conductor channel 41 region correspondence mask plate, source electrode 52 region and the corresponding mask plate in drain electrode 51 region
Light tight position, the complete printing opacity position of other region correspondence mask plates.
Preferably, when step S41 utilizing gray level mask plate carry out mask, data wire 22 region correspondence mask plate complete
Printing opacity position, the partial light permeability position of source electrode 52 region, drain electrode 51 region and the corresponding mask plate in grid line 23 region, other districts
The light tight position of territory correspondence mask plate.
Embodiment 2
As Figure 1-3, a kind of TFT substrate, including multiple pixel cells, each pixel cell includes being sequentially formed at transparent base
Grid metal level 2, gate insulation layer 3, semiconductor layer 5, source drain metal layer 5, insulating medium layer 6 and pixel electrode layer 7 on plate 1, its
In:
Described grid metal level 2 includes gate electrode 21, horizontal grid line 23 and vertical data wire 22, described gate electrode 21 and grid line
23 connect, and described data wire 22 and gate electrode 21, grid line 23 disconnect；
Described gate insulation layer 3 is positioned on described gate electrode 21 and grid line 23, for by grid line 23/ gate electrode 21 and source electrode 52/
Drain electrode 51 insulate；
Described semiconductor layer 5 is positioned on the gate insulation layer 3 of described gate electrode 21, and it is formed semiconductor channel 41；
Described source drain metal layer 5 includes source electrode 52 and drain electrode 51, lays respectively at the semiconductor channel of described semiconductor layer 5
Above 41 both sides；
Described insulating medium layer 6, for semiconductor layer 5, gate electrode 21 being insulated with pixel electrode layer 7, is provided with at its data wire 22
It is provided with at first via 61, source electrode 52 at second via 62, drain electrode 51 and is provided with the 3rd via 63；
Described pixel electrode layer 7 includes pixel electrode 73 and first connecting line the 71, second connecting line 72.
Data wire 22 and gate electrode 21, grid line 23 are located at same layer, by the first of insulating medium layer 6 by this TFT substrate
First connecting line 31 of via 61 and the second via 62 and pixel electrode layer 7 connects data wire 22 and source electrode 52, and it is prepared
Method reduces by 2 photoetching on the basis of original 5 photoetching processes, simplifies the preparation technology of TFT, reduces production cost, improves
Production efficiency, processing step is the fewest, and the yields of product is the highest, and quality is more easily controlled；Use gray level mask plate to photoresist
Carrying out mask and etching, operability is higher, will not remain semiconductor layer on grid line, and it affects structural stability, product good
Product rate is high；Photoresist is conventional photoresist, and production cost is low, and photoresist can perform etching and peel off at a normal temperature,
TFT glass substrate will not be caused damage, the yields of its product is higher.
Wherein, described source electrode 52 is by first via the 61, second via 62 and pixel electrode on insulating medium layer 6
The first connecting line 71 on layer 7 is connected with data wire 22, described drain electrode 51 pass through the 3rd via 63 on insulating medium layer 6 with
And the second connecting line 72 on pixel electrode layer 7 is connected with pixel electrode 73.
The material of grid metal level 2 and source drain metal layer 5 preferably but is not limited to Al, Cu, Mo or Cr etc., gate insulation layer 3
Material preferably but is not limited to silicon nitride, silicon oxide or silicon oxynitride etc., and the material of semiconductor layer 5 preferably but is not limited to monocrystalline
Silicon, polysilicon or non-crystalline silicon etc., dielectric insulation layer preferably but is not limited to silicon nitride, silicon oxide or silicon oxynitride etc., pixel electricity
The material of pole layer 7 preferably but is not limited to ITO.
Embodiment described above only have expressed embodiments of the present invention, and it describes more concrete and detailed, but can not
Therefore the restriction to the scope of the claims of the present invention it is interpreted as, as long as using the skill that the form of equivalent or equivalent transformation is obtained
Art scheme, all should fall within the scope and spirit of the invention.
Claims (9)
1. the preparation method of a TFT substrate, it is characterised in that comprise the steps:
S1: be sequentially depositing grid metal level, gate insulation layer, semiconductor layer and source drain metal layer on the transparent substrate；
S2: coat the first photoresist in described source drain metal layer, carries out mask and etching, forms data wire, grid line, grid electricity
Pole, gate insulation layer, semiconductor channel, source electrode and drain electrode；
S3: deposit insulating medium layer on the substrate described in S2；
S4: coat the second photoresist on described insulating medium layer, carries out mask and etching, is formed and lays respectively at data wire, source
First via of the insulating medium layer above electrode and drain electrode, the second via and the 3rd via；
S5: pixel deposition electrode layer on the substrate described in S4；
S6: coat the 3rd photoresist on described pixel electrode layer, carry out mask and etching, formed pixel electrode, data wire and
Second connecting line of the first connecting line, drain electrode and the pixel electrode of source electrode.
The preparation method of TFT substrate the most according to claim 1, it is characterised in that before step S1, also includes step
S0: provide a transparency carrier, cleans described transparency carrier, removes the dirt on described transparency carrier.
The preparation method of TFT substrate the most according to claim 1, it is characterised in that described step S2 includes:
S21: described first photoresist is carried out gray level mask technique, forms the first photoetching agent pattern, wherein, source electrode region,
First photoresist of drain regions has the first thickness, grid region, data wire region and the first of semiconducting channel region
Photoresist has the second thickness, and other region covers without the first photoresist, and described first thickness is bigger than the second thickness；
S22: by etching technics, removes not by the source drain metal layer in other region described in the first photoresist covering, partly leads
Body layer and gate insulation layer, form data wire, grid line, gate electrode and gate insulation layer；
S23: described first photoresist is carried out cineration technics, removes the first photoresist of the second thickness, expose grid region,
Data wire region and the source drain metal layer of semiconducting channel region；
S24: by etching technics, source drain metal layer that etching exposes and lower semiconductor layer thereof, formed semiconductor channel,
Source electrode and drain electrode；
S25: described first photoresist is carried out demoulding, peels off remaining first photoresist.
The preparation method of TFT substrate the most according to claim 1, it is characterised in that described S4 includes:
S41: described second photoresist is carried out gray level mask technique, forms the second photoetching agent pattern, wherein, source electrode region,
Drain regions, the second photoresist of grid region have the 3rd thickness, and data wire region covers without the second photoresist, other district
Second photoresist in territory has the 4th thickness, and described 4th thickness is more than the 3rd thickness；
S42: by etching technics, remove the insulating medium layer in the data wire region not covered by the second photoresist, expose
The gate insulation layer in data wire region and semiconductor layer；
S43: described second photoresist is carried out cineration technics, removes the photoresist of the 3rd thickness, expose source electrode region, leakage
Electrode zone and the insulating medium layer of grid region；
S44: by etching technics, removes the insulation on the gate insulation layer in data wire region and semiconductor layer, source/drain electrode region
Semiconductor layer in dielectric layer, grid region and the gate insulation layer on insulating medium layer, data wire region and semiconductor layer, formed
Lay respectively at the first via of insulating medium layer, the second via and the 3rd via above data wire, source electrode and drain electrode；
S45: described second photoresist is carried out demoulding, peels off remaining second photoresist.
The preparation method of TFT substrate the most according to claim 1, it is characterised in that described S6 includes:
S61: described 3rd photoresist carries out gray level mask technique, forms the 3rd photoetching agent pattern, wherein, described quasiconductor ditch
Region, road and grid region no third photoresist cover；
S62: by etching technics, remove semiconducting channel region and the pixel electrode of grid region that no third photoresist covers
Layer, forms the second connecting line of the first connecting line, drain electrode and the pixel electrode of pixel electrode, data wire and source electrode；
S63: described 3rd photoresist is carried out demoulding, peels off remaining 3rd photoresist.
The preparation method of TFT substrate the most according to claim 3, it is characterised in that utilize gray level mask plate in step S21
When carrying out mask, the partial light permeability position of the corresponding mask plate in data wire region, grid region and semiconducting channel region, source electrode
The light tight position of region mask plate corresponding with drain regions, the complete printing opacity position of other region correspondence mask plates.
The preparation method of TFT substrate the most according to claim 4, it is characterised in that utilize gray level mask plate in step S41
When carrying out mask, the complete printing opacity position of data wire region correspondence mask plate, source electrode region, drain regions and grid region
The partial light permeability position of corresponding mask plate, the light tight position of other region correspondence mask plates.
8. a TFT substrate, including multiple pixel cells, it is characterised in that each pixel cell includes being sequentially formed at transparent
Grid metal level, gate insulation layer, semiconductor layer, source drain metal layer, insulating medium layer and pixel electrode layer on substrate, wherein:
Described grid metal level includes that gate electrode, horizontal grid line and vertical data wire, described gate electrode and grid line connect, described
Data wire and gate electrode, grid line disconnect；
Described gate insulation layer is positioned on described gate electrode and grid line, for being insulated with source/drain electrode by grid line/gate electrode；
Described semiconductor layer is positioned on the gate insulation layer of described gate electrode, and it is formed semiconductor channel；
Described source drain metal layer includes source electrode and drain electrode, lays respectively on the semiconductor channel both sides of described semiconductor layer
Side；
Described insulating medium layer, for semiconductor layer, gate electrode being insulated with pixel electrode layer, is provided with the first mistake at its data wire
It is provided with at hole, source electrode at the second via, drain electrode and is provided with the 3rd via；
Described pixel electrode layer includes pixel electrode and the first connecting line, the second connecting line.
TFT substrate the most according to claim 8, it is characterised in that described source electrode is by first on insulating medium layer
The first connecting line on via, the second via and pixel electrode layer is connected with data wire, and described drain electrode passes through dielectric
The 3rd via on layer and the second connecting line on pixel electrode layer are connected with pixel electrode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101078842A (en) * | 2006-05-23 | 2007-11-28 | 京东方科技集团股份有限公司 | TFT LCD array substrate structure and its production method |
| US20090225249A1 (en) * | 2008-03-07 | 2009-09-10 | Zhangtao Wang | Thin film transistor array substrate and manufacturing method thereof |
| CN101630098A (en) * | 2008-07-18 | 2010-01-20 | 北京京东方光电科技有限公司 | TFT-LCD array substrate and manufacturing method thereof |
| CN102023432A (en) * | 2009-09-18 | 2011-04-20 | 北京京东方光电科技有限公司 | FFS type TFT-LCD array substrate and manufacturing method thereof |
| WO2013139148A1 (en) * | 2012-03-19 | 2013-09-26 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display device |
| WO2013189160A1 (en) * | 2012-06-21 | 2013-12-27 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display devicearray substrate, manufacturing method therefor and display device thereof |
| CN205828364U (en) * | 2016-08-02 | 2016-12-21 | 信利半导体有限公司 | A kind of TFT substrate |
-
2016
- 2016-08-02 CN CN201610620519.9A patent/CN106057736B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101078842A (en) * | 2006-05-23 | 2007-11-28 | 京东方科技集团股份有限公司 | TFT LCD array substrate structure and its production method |
| US20090225249A1 (en) * | 2008-03-07 | 2009-09-10 | Zhangtao Wang | Thin film transistor array substrate and manufacturing method thereof |
| CN101630098A (en) * | 2008-07-18 | 2010-01-20 | 北京京东方光电科技有限公司 | TFT-LCD array substrate and manufacturing method thereof |
| CN102023432A (en) * | 2009-09-18 | 2011-04-20 | 北京京东方光电科技有限公司 | FFS type TFT-LCD array substrate and manufacturing method thereof |
| WO2013139148A1 (en) * | 2012-03-19 | 2013-09-26 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display device |
| WO2013189160A1 (en) * | 2012-06-21 | 2013-12-27 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display devicearray substrate, manufacturing method therefor and display device thereof |
| CN205828364U (en) * | 2016-08-02 | 2016-12-21 | 信利半导体有限公司 | A kind of TFT substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340489A (en) * | 2016-11-29 | 2017-01-18 | 信利半导体有限公司 | Preparation method of TFT substrate |
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