CN113589605B

CN113589605B - Array substrate, preparation method thereof and display panel

Info

Publication number: CN113589605B
Application number: CN202110866526.8A
Authority: CN
Inventors: 孔曾杰; 郭会斌; 乔亚峥; 沈鹭; 代耀
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2024-01-16
Anticipated expiration: 2041-07-29
Also published as: CN113589605A

Abstract

The application provides an array substrate, a preparation method thereof and a display panel, and relates to the technical field of display. The array substrate comprises a plurality of sub-pixels which are arranged in an array manner; the sub-pixel includes: a substrate, and a first electrode layer and a second electrode layer sequentially stacked on the substrate; the first electrode layer at least comprises a driving electrode and a buffer part; the buffer part is positioned at one side of the driving electrode; the second electrode layer at least comprises a grid line; the grid line is arranged on one side of the buffer part far away from the substrate, covers the buffer part and is not overlapped with the driving electrode along the direction perpendicular to the substrate. The method and the device are suitable for manufacturing the array substrate.

Description

Array substrate, preparation method thereof and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel.

Background

Compared with VA (Vertical Alignment ) type liquid crystal displays, ADS (Advanced Super Dimension Switch, advanced super-dimensional field switching) type or HADS type liquid crystal displays have advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low color difference, and the like.

In an ADS type or HADS type lcd formed by the existing technology, a tail phenomenon exists in a gate line, so that a capacitance between the gate line and an ITO (Indium Tin Oxide) electrode is increased (in the ADS type, the ITO electrode refers to a common electrode; in the HADS type, the ITO electrode refers to a pixel electrode), resulting in poor reliability of a product, and further, product quality is reduced.

Disclosure of Invention

The embodiment of the application provides an array substrate, a preparation method thereof and a display panel, wherein the array substrate can avoid the problem of capacitance increase between a grid line and a driving electrode caused by the tailing phenomenon of the grid line, so that the reliability of a product is reduced, and the quality of the product is improved.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in one aspect, an array substrate is provided, the array substrate including a plurality of sub-pixels arranged in an array;

the sub-pixel includes: a substrate, and a first electrode layer and a second electrode layer sequentially stacked on the substrate;

the first electrode layer at least comprises a driving electrode and a buffer part; the buffer part is positioned at one side of the driving electrode;

the second electrode layer at least comprises a grid line; the gate line is arranged on one side of the buffer part far away from the substrate, covers the buffer part and is not overlapped with the driving electrode along the direction perpendicular to the substrate.

Optionally, the second electrode layer further includes a driving electrode line; the driving electrode wire is arranged on one side of the driving electrode far away from the substrate;

wherein the driving electrode overlaps the driving electrode line in a direction perpendicular to the substrate, and a portion of the driving electrode overlapping the driving electrode line in the direction perpendicular to the substrate is an overlapping electrode, the driving electrode line covering the overlapping electrode.

Optionally, the gate line, the driving electrode line, and the buffer portion extend along a first direction, respectively;

the sub-pixel further includes: a data line extending in a second direction; wherein the first direction and the second direction intersect; the orthographic projection of the data line on the substrate is positioned on a first side of the orthographic projection of the driving electrode on the substrate, the orthographic projection of the grid line on the substrate is positioned on a second side of the orthographic projection of the driving electrode on the substrate, and the first side is adjacent to the second side;

the first electrode layer further comprises a drive connection portion; the driving connection part is connected with the driving electrode; the driving electrode wire also covers the driving connection part;

wherein the data line overlaps the gate line in a direction perpendicular to the substrate and overlaps a portion of the driving electrode line covering the driving connection portion.

Optionally, the gate lines of the sub-pixels in each row are in an integrated structure, and the driving electrode lines of the sub-pixels in each row are in an integrated structure.

Optionally, the gate line and the driving electrode line are disposed in the same layer.

Optionally, the driving electrode and the buffer portion are disposed in the same layer.

Optionally, the materials of the driving electrode and the buffer portion respectively include transparent metal oxide, and the material of the gate line includes metal.

In another aspect, there is provided a display panel including: the array substrate.

In still another aspect, a method for manufacturing an array substrate is provided, including:

forming a plurality of sub-pixels arranged in an array;

forming the sub-pixel includes:

sequentially forming a first electrode film and a second electrode film which are arranged in a laminated manner on a substrate;

depositing a first optical cement at least over a portion of the second electrode film for forming a gate line;

patterning the second electrode film by using the first optical cement as a first mask plate to at least form the grid line;

removing the first optical cement;

depositing a second optical paste at least over a portion of the first electrode film for forming a driving electrode;

patterning the first electrode film by using the second optical cement and the grid line as a second mask plate to at least form a driving electrode and a buffer part; the grid line is arranged on one side, far away from the substrate, of the buffer part, and the grid line covers the buffer part and is not overlapped with the driving electrode along the direction perpendicular to the substrate.

Optionally, the second electrode layer further includes a driving electrode line;

the depositing a first optical paste over at least a portion of the second electrode film for forming a gate line includes:

respectively depositing first optical cement above the parts of the second electrode film for forming the grid lines and the driving electrode lines;

the patterning the second electrode film by using the first optical cement as a first mask plate, at least forming the gate line includes:

patterning the second electrode film by using the first optical cement as a first mask plate to form the grid line and the driving electrode line;

the depositing a second optical paste over at least a portion of the first electrode film for forming a driving electrode includes:

depositing a second optical paste in the first electrode film above the portion for forming the driving electrode and the driving electrode line, wherein the second optical paste covers one side of the driving electrode line away from the gate line;

the patterning the first electrode film by using the second optical cement and the gate line as a second mask, at least forming a driving electrode and a buffer portion includes:

patterning the first electrode film by using the second optical cement, the grid line and the driving electrode line as a second mask plate to form a driving electrode and a buffer part; the grid line is arranged on one side, far away from the substrate, of the buffer part, and the grid line covers the buffer part and is not overlapped with the driving electrode along the direction perpendicular to the substrate; the driving electrode overlaps the driving electrode line in a direction perpendicular to the substrate, and a portion of the driving electrode overlapping the driving electrode line in a direction perpendicular to the substrate is an overlapping electrode, the driving electrode line covering the overlapping electrode.

The embodiment of the application provides an array substrate, a preparation method thereof and a display panel, wherein in the array substrate, grid lines cover buffer parts, so that trailing phenomena are not generated at edges of two sides of the grid lines, and on one hand, the problem of capacitance increase between the grid lines and a driving electrode caused by the trailing phenomena of the grid lines can be avoided; on the other hand, the capacitance between the grid line and the driving electrode is reduced, so that the line capacitance of the grid line is reduced, the circuit delay phenomenon of the grid line can be reduced, the input effect of the grid line is improved, the charging rate and the display effect of the sub-pixel are finally improved, and the problem of poor product reliability such as poor low-temperature starting, poor water ripple and the like is greatly solved; on the other hand, the buffer part can be used as a buffer layer of the grid line, the grid line only needs to be formed into a single-layer structure, and the buffer layer is not required to be additionally formed, so that the process is greatly simplified, and the improvement of productivity is facilitated.

The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

In fig. 1, a-h are the preparation flow chart of a process of "0+" provided in the embodiment of the present application;

FIG. 2 is a diagram of a substrate structure formed using a "0+" process;

FIG. 3 is an electron microscope image corresponding to the structure of FIG. 2;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

FIG. 5 is a cross-sectional view taken along the direction B2B3 in FIG. 4;

FIG. 6 is an electron microscope image corresponding to the structure of FIG. 4;

fig. 7 is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a layout of shorting defects generated in a substrate formed by a "0+" process;

FIG. 9 is a schematic diagram of a layout corresponding to the structure of FIG. 4 according to an embodiment of the present application;

in fig. 10, a-h are diagrams of a preparation flow chart of an array substrate provided in an embodiment of the present application;

in fig. 11, a-h are the preparation flow chart structure diagrams of a "1+" process provided in the embodiments of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In the embodiments of the present application, the words "first," "second," and the like are used to distinguish between the same item or similar items that have substantially the same function and function, and are merely used to clearly describe the technical solutions of the embodiments of the present application, and are not to be construed as indicating or implying relative importance or implying an indication of the number of technical features indicated.

In the embodiments of the present application, the meaning of "a plurality of" means two or more, and the meaning of "at least one" means one or more, unless specifically defined otherwise.

In the embodiments of the present application, the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of description and simplification of the description, and are not indicative or implying that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.

In order to further improve the aperture ratio, HADS type liquid crystal displays have been developed, as compared with ADS type liquid crystal displays. The greatest difference between the ADS type and the HADS type is the electrode positions of the common electrode (common) and the pixel electrode (pixel).

The manufacturing process of the ADS type and the HADS type liquid crystal display comprises a '0+' process, and specifically, the '0+' process comprises the following steps with reference to a-h diagrams in fig. 1:

s10, referring to fig. 1 a, an Indium Tin Oxide (ITO) thin film 11 is deposited on a glass substrate 10.

S11, referring to fig. 1 b, a metal film 12 is deposited on an ITO (Indium Tin Oxide) film 11.

S12, referring to a graph c in FIG. 1, a halftone mask (HGA) 13 is formed.

And S13, etching the metal film 12 by adopting a half-tone mask (HGA) 13 to obtain a first grid layer shown in a d diagram in fig. 1, wherein the first grid layer comprises a first pattern 14 and a second pattern 15.

And S14, etching the ITO film 11 by adopting a halftone mask (HGA) 13 to obtain a second grid layer shown in an e diagram in FIG. 1, wherein the second grid layer comprises a first ITO pattern 16 and a second ITO pattern 17.

S15, ashing is carried out on the half-tone mask (HGA) 13, so as to obtain a mask 18 shown in the f diagram in FIG. 1. This step requires the use of a dry etching process.

And S16, etching the first pattern 14 and the second pattern 15 by using a mask 18 to obtain a gate metal line 19 and an electrode line 20 shown in a graph g in fig. 1.

S17, stripping the mask 18 to obtain the structure shown in the h diagram in fig. 1.

Fig. 2 is a layout plan view of a substrate formed by the "0+" process, and a cross-sectional view along the direction BB1 in fig. 2 can be referred to as a h-diagram in fig. 1. As shown in fig. 1 h and fig. 2, both side edges of the gate metal line 19 exist ITO tail (i.e., A1 and A2 in the first ITO pattern 16), and one side edge of the electrode line 20 near the gate line exists ITO tail (i.e., A3 in the second ITO pattern 17). Fig. 3 is an electron microscope image (SEM image) of a substrate formed by the "0+" process, and referring to fig. 3, ITO tail23 is present at both side edges of the gate metal line 19, and ITO tail22 is present at one side edge of the electrode line 20 close to the gate metal line. This causes an increase in capacitance between the gate metal line and the ITO electrode (in ADS type, the ITO electrode refers to the common electrode; in HADS type, the ITO electrode refers to the pixel electrode), resulting in poor reliability of the product.

Note that, if the substrate shown in fig. 2 is applied to an ADS type liquid crystal display, the second ITO pattern 17 is a common electrode (common electrode), and the electrode 21 is a pixel electrode (pixel electrode); if the substrate shown in fig. 2 is applied to the HADS type liquid crystal display, the second ITO pattern 17 is a pixel electrode and the electrode 21 is a common electrode. In addition, as the thickness of the gate metal line increases, the size of the ITO tail increases, and the resulting reliability defect is more serious. For example, if the gate metal lines are made of copper, the thickness of the copper layers is respectivelyAnd->The dimensions of the gate metal lines ITO tail are 1.2 μm, 1.4 μm, and 1.7 μm, respectively.

Based on the foregoing, an embodiment of the present application provides an array substrate, as shown in fig. 4 and 5, including a plurality of sub-pixels 100 arranged in an array; the sub-pixel 100 includes: a substrate 9, and a first electrode layer and a second electrode layer provided on the substrate 9 in this order.

Referring to fig. 5, the first electrode layer includes at least a driving electrode 1 and a buffer portion 2; the buffer 2 is located on one side of the drive electrode 1.

Referring to fig. 4 and 5, the second electrode layer includes at least a gate line 3; the gate line 3 is disposed on a side of the buffer portion 2 away from the substrate 9, and the gate line 3 covers the buffer portion 2 and does not overlap the driving electrode 1 in a direction perpendicular to the substrate.

The gate line covering buffer portion refers to: referring to fig. 5, the orthographic projection D2 of the grid line on the substrate 9 covers the orthographic projection D1 of the buffer portion 2 on the substrate 9, that is, the orthographic projection D1 of the buffer portion 2 on the substrate 9 is located within the orthographic projection D2 of the grid line on the substrate 9.

If the array substrate is applied to an ADS type liquid crystal display, the driving electrode is a common electrode; if the array substrate is applied to the HADS type liquid crystal display, the driving electrode is a pixel electrode. The shape of the driving electrode is not limited, and the driving electrode may be a plate electrode as shown in fig. 4, for example. If the array substrate is applied to a liquid crystal display, the array substrate may further include a slit electrode when the driving electrode is a plate electrode, and a multidimensional electric field is formed between the plate electrode and the slit electrode to drive the liquid crystal to deflect, thereby realizing display.

Fig. 6 is an electron microscope diagram corresponding to the structure of fig. 4, and referring to fig. 6, edges at both sides of the gate line 3 are clean, and compared with fig. 3, there is no tailing phenomenon, so that the problem of increasing capacitance between the gate line and the driving electrode due to the tailing phenomenon of the gate line can be avoided, margin (boundary range) of design and process is improved, and further bad reliability of products is reduced, thereby improving product quality.

The principle of the present application of reducing the capacitance between the gate line and the driving electrode is specifically described below.

The calculation formula of the capacitance C between the grid line and the driving electrode is as follows: c=εs/(4πkd), where ε is the dielectric constant, S is the relative area of the gate line and the drive electrode, 4πk is a constant, and d is the distance between the gate line and the drive electrode.

The capacitance between the gate line and the driving electrode belongs to non-overlapping capacitance, and if the distance between the gate line and the driving electrode is reduced under the condition that the relative area between the gate line and the driving electrode is kept unchanged, the capacitance between the gate line and the driving electrode is increased. In the related art, the tailing phenomenon occurs at the edges of both sides of the gate line, resulting in a smaller actual distance between the gate line and the driving electrode than the design value, thereby increasing the capacitance between the gate line and the driving electrode. In the application, the grid line covers the buffer part, so that the trailing phenomenon is not generated at the edges of two sides of the grid line, and the problem of the increase of the capacitance between the grid line and the driving electrode caused by the trailing phenomenon of the grid line can be avoided.

In addition, the capacitance between the gate line and the driving electrode directly affects the line capacitance Cgate of the gate line, and the larger Cgate, the circuit Delay (RC Delay) is generated. And the circuit delay value is the product value of the resistor and the capacitor, namely, the larger the capacitor is, the more serious the circuit delay is. In large-size and high-frequency products, the line capacitance Cgate of the grid line is larger, and the circuit delay phenomenon is more serious, so that the voltage input of the grid line is directly influenced, the charging and display of the sub-pixels are further influenced, and the problem of poor product reliability such as poor low-temperature starting and poor water ripple is easily caused. Therefore, in practical designs, it is necessary to reduce the value of the line capacitance Cgate as much as possible.

Fig. 7 is an equivalent circuit structure of a sub-pixel, and referring to fig. 7, the sub-pixel includes pixel electrodes (pixel electrodes), TFTs (thin film transistors), gate lines Gate, common electrode lines Com, and the like, and capacitances between the structures are shown in fig. 7. In a state where the TFT is ON (ON), the calculation formula of Cgate is illustrated with the lowermost Gate line in fig. 7 as an example.

C _gate ＝C _{gdx_on} +C _{gd_on} +C _{gs_on} +C _gc +C _gdx +C _pg (1)

Wherein C is _{gdx_on} Representing capacitance between Gate line (Gate line) and left Data line (Data line) at left part of left Data line in on state, C _{gd_on} Representing capacitance between Gate line (Gate line) and left Data line (Data line) located at right portion of left Data line in on state, C _{gs_on} Representing the capacitance between the Gate line (Gate line) and the storage capacitance (Cst) in the on state, C _gc Representing the capacitance between the Gate line and the common electrode, C _gdx Representing the Gate line and the right sideCapacitance between data lines, C _pg Representing the capacitance between the Gate line (Gate line) and the pixel electrode.

From the above formula (1), C _gc Or C _pg The larger the line capacitance Cgate of the gate line is, the larger. Fig. 7 is an equivalent to an ADS type structure, in which the driving electrode is a common electrode. In the structure provided by the application, C can be reduced _gc Further, the line capacitance Cgate of the gate line can be reduced, so that the circuit delay phenomenon of the gate line can be reduced, the input effect of the gate line is improved, the charging rate and the display effect of the sub-pixel are finally improved, and the problem of poor product reliability such as poor low-temperature starting, poor water ripple (water ripple) and the like is greatly reduced.

Generally, the grid line is mostly made of metal, but the adsorption force between the metal and the substrate is poor, and the film forming effect is poor. In order to improve the film forming quality of the gate line, it is necessary to manufacture the gate line having a composite layer (including a buffer layer and a metal layer), and the buffer layer is manufactured by using MoNb (molybdenum-niobium), mo (molybdenum), ti (titanium), etc., which will certainly increase the manufacturing process, thereby increasing the production cost. In the application, the buffer part can be used as the buffer layer of the grid line, the grid line only needs to be formed into a single-layer structure, the buffer layer is not required to be additionally formed, the process is greatly simplified, and the improvement of productivity is facilitated.

According to the array substrate provided by the application, the grid lines cover the buffer parts, so that the tailing phenomenon is not generated at the edges of two sides of the grid lines, and the problem of capacitance increase between the grid lines and the driving electrodes caused by the tailing phenomenon of the grid lines can be avoided; on the other hand, the capacitance between the grid line and the driving electrode is reduced, so that the line capacitance of the grid line is reduced, the circuit delay phenomenon of the grid line can be reduced, the input effect of the grid line is improved, the charging rate and the display effect of the sub-pixel are finally improved, and the problem of poor product reliability such as poor low-temperature starting, poor water ripple and the like is greatly solved; on the other hand, the buffer part can be used as a buffer layer of the grid line, the grid line only needs to be formed into a single-layer structure, and the buffer layer is not required to be additionally formed, so that the process is greatly simplified, and the improvement of productivity is facilitated.

Optionally, referring to fig. 4 and 5, the second electrode layer further includes a driving electrode line 4; the drive electrode line 4 is arranged at a side of the drive electrode 1 remote from the substrate.

Wherein the drive electrode 1 overlaps the drive electrode line 4 in a direction perpendicular to the substrate 9, and a portion of the drive electrode 1 overlapping the drive electrode line 4 in the direction perpendicular to the substrate 9 is an overlap electrode 8, the drive electrode line 4 covering the overlap electrode 8.

The driving electrode line covering the overlapping electrode means that: referring to fig. 5, the front projection D4 of the drive electrode wire 4 onto the substrate 9 covers the front projection D3 of the overlap electrode 8 onto the substrate 9, i.e. the front projection D3 of the overlap electrode 8 onto the substrate 9 is located within the front projection D4 of the drive electrode wire 4 onto the substrate 9.

It should be noted that, if the array substrate is applied to an ADS type liquid crystal display, the driving electrode lines are common electrode lines; if the array substrate is applied to the HADS type liquid crystal display, the driving electrode lines are pixel electrode lines.

In the related art, as shown in fig. 2, the gate metal line 19 and the electrode line 20 have ITO tail phenomenon, so that during the manufacturing process, the ITO tail between them is easily connected together in the short-circuit defective region as shown in fig. 8, and thus short-circuit defect is generated. In the application, the grid line covers the buffer part, the driving electrode line covers the overlapped electrode, and the edges of the grid line 3 and the driving electrode line 4 are not trailing, so that poor short is avoided, and the product performance is further improved.

Further alternatively, as shown in fig. 4 and 5, the gate line 3, the driving electrode line 4, and the buffer portion 2 extend in the first direction OA direction, respectively.

Referring to fig. 4, the sub-pixel 100 further includes: a data line 5, the data line 5 extending in the second direction OC; wherein the first direction and the second direction intersect; the front projection of the data line 5 onto the substrate 9 is located on a first side of the front projection of the drive electrode 1 onto the substrate 9 (i.e. the left side of the drive electrode 1 in fig. 4) and the front projection of the gate line 3 onto the substrate 9 is located on a second side of the front projection of the drive electrode 1 onto the substrate 9 (i.e. the upper side of the drive electrode 1 in fig. 4), the first side being adjacent to the second side.

Referring to fig. 4, the first electrode layer further includes a driving connection part 6; the driving connection part 6 is connected with the driving electrode 1; the drive electrode lines 4 also cover the drive connection portions 6.

Wherein the data line 5 overlaps the gate line 3 in a direction perpendicular to the substrate 9 and overlaps a portion of the driving electrode line 3 covering the driving connection portion 6.

In fig. 4, the drive connection portion 6 is covered with the drive electrode wire 4 and indicated by a broken line frame. The drive electrode lines also cover the drive connection, i.e. the front projection of the drive connection on the substrate is located within the front projection of the drive electrode lines on the substrate.

The first direction may be parallel to a short side direction of the array substrate, and at this time, the second direction may be parallel to a long side direction of the array substrate; alternatively, the first direction may be parallel to the long side direction of the array substrate, and the second direction may be parallel to the short side direction of the array substrate.

In the related art, the data lines overlap the gate lines and the driving electrode lines, and the edges of the gate lines and the driving electrode lines have tailing, so that the overlapping area of the data lines and the gate lines and the overlapping area of the data lines and the driving electrode lines are correspondingly increased, thereby increasing the parasitic capacitance of the data lines and the gate lines and the parasitic capacitance of the data lines and the driving electrode lines, and further increasing the line capacitance Cdata on the data lines

Referring to fig. 7, a calculation formula of Cdata is illustrated with the Data line on the left side in fig. 7 in a state where the TFT is turned OFF (OFF).

Wherein C is _{gdx_off} Representing the capacitance between the Gate line (Gate line) and the left Data line (Data line) at the left portion of the left Data line in the off state,representing the capacitance between the Gate line (Gate line) and the left Data line (Data line) at the right portion of the left Data line in the off state, C _dcx Representation ofCapacitance between common electrode line (Com line) and left data line, C _dc Representing capacitance between left data line and common electrode, C _pd Representing the capacitance between the left data line and the pixel electrode.

The parasitic capacitance C of the data line and the gate line can be obtained by the above formula (2) _gd And parasitic capacitance C of the data line and the driving electrode line _dcx The larger the line capacitance Cdata of the data line is, the larger the line capacitance Cdata is. Fig. 7 is an equivalent of an ADS type structure, in which the driving electrode lines are common electrode lines.

The larger the line capacitance Cdata of the data line, the more serious the circuit delay on the data line, thereby directly affecting the voltage input of the data line. In fig. 7, the pixel charging rate Wherein C is _st Representing storage capacitance, C _pd The capacitance between the data line and the pixel electrode is represented by VD, the voltage of the data line, vt, the voltage of the storage capacitor after the charging time t, and V0, the initial voltage of the storage capacitor. The voltage of the data line directly affects the pixel charging rate, and the line capacitance Cdata of the data line directly affects the voltage of the data line. Therefore, in practical designs, it is necessary to reduce the value of the line capacitance Cdata of the data line as much as possible.

In the structure provided by the application, parasitic capacitance of the data line and the grid line and parasitic capacitance of the data line and the driving electrode line can be reduced, and further line capacitance of the data line can be reduced, so that circuit delay phenomenon of the data line can be reduced, input effect of the data line is improved, charging rate and display effect of sub-pixels are finally improved, and product reliability bad problems such as bad low-temperature starting and bad water ripple are greatly reduced.

Optionally, in order to facilitate driving and simplify the structure, the gate lines of the sub-pixels in each row are in an integrated structure, and the driving electrode lines of the sub-pixels in each row are in an integrated structure.

Optionally, in order to reduce the number of patterning processes and reduce the manufacturing cost, the gate line and the driving electrode line are arranged on the same layer.

The same layer arrangement refers to the one-time patterning process. The one-time patterning process refers to a process of forming a desired layer structure through one exposure. The primary patterning process comprises masking, exposing, developing, etching, stripping and other processes.

Optionally, in order to reduce the number of patterning processes and reduce the manufacturing cost, the driving electrode and the buffer portion are arranged on the same layer.

Further alternatively, the materials of the driving electrode and the buffer portion respectively include transparent metal oxide, and the material of the gate line includes metal.

By way of example, the transparent metal oxide may be ITO (indium tin oxide), and the metal may be molybdenum (Mo), copper (Cu), aluminum (Al), or the like.

The buffer part can be used as a buffer layer of the grid line, so that the grid line is only provided with one metal layer, thereby simplifying the manufacturing process of the grid line and reducing the manufacturing cost.

It should be noted that the array substrate may further include other film structures, for example: thin film transistors, etc., only the structures and film layers related to the invention are described herein, and the remaining structures can be obtained by referring to the related art.

The embodiment of the application also provides a display panel, which comprises the array substrate.

The display panel may be an ADS type or HADS type liquid crystal display panel, and any product or part having a display function including a television, a digital camera, a mobile phone, a tablet computer, etc. including the display panel. The display panel has the characteristics of short signal delay, high response speed, low cost, excellent display picture and the like.

The embodiment of the application also provides a preparation method of the array substrate, which comprises the following steps:

s01, forming a plurality of sub-pixels arranged in an array.

Wherein forming the sub-pixel includes:

s20, sequentially forming a first electrode film and a second electrode film which are stacked on a substrate.

The material of the substrate may be a rigid material such as glass or a flexible material such as PI (polyimide). The first electrode film may be an Indium Tin Oxide (ITO) film; the second electrode film may be a metal film of molybdenum (Mo), copper (Cu), or aluminum (Al).

S21, depositing first optical cement at least above a part of the second electrode film for forming the grid line.

Of course, the first optical paste may also be simultaneously deposited over the portion of the second electrode film for forming the driving electrode lines.

And S22, patterning the second electrode film by using the first optical cement as a first mask plate to at least form a grid line.

The patterning includes: exposing, developing, etching and other processes; it should be noted that, the patterning process may use dry etching or may use wet etching, so as to improve etching efficiency.

S23, removing the first optical cement.

And S24, depositing a second optical cement at least above a part of the first electrode film for forming the driving electrode.

S25, patterning the first electrode film by using the second optical cement and the grid line as a second mask plate to at least form a driving electrode and a buffer part; the grid line is arranged on one side of the buffer part far away from the substrate, covers the buffer part and is not overlapped with the driving electrode along the direction perpendicular to the substrate.

By executing the array substrate formed in the steps S20-S25, the grid lines cover the buffer parts, so that the trailing phenomenon is not generated at the edges of the two sides of the grid lines, and on one hand, the problem of the increase of the capacitance between the grid lines and the driving electrodes caused by the trailing phenomenon of the grid lines can be avoided; on the other hand, the capacitance between the grid line and the driving electrode is reduced, so that the line capacitance of the grid line is reduced, the circuit delay phenomenon of the grid line can be reduced, the input effect of the grid line is improved, the charging rate and the display effect of the sub-pixel are finally improved, and the problem of poor product reliability such as poor low-temperature starting, poor water ripple and the like is greatly solved; on the other hand, the buffer part can be used as a buffer layer of the grid line, the grid line only needs to be formed into a single-layer structure, and the buffer layer is not required to be additionally formed, so that the process is greatly simplified, and the improvement of productivity is facilitated. The manufacturing method is simple and easy to realize. In the steps S20 to S25, the preparation can be completed only by wet etching, and compared with the process of "0+", the productivity of the dry etching process can be effectively released, the production productivity is improved, and the equipment investment is reduced.

Optionally, the second electrode layer further includes a driving electrode line.

S21, depositing a first optical cement at least above a part of the second electrode film for forming the grid line comprises:

s21', referring to fig. 10 c, a first optical paste 33 is deposited over portions of the second electrode film 32 for forming the gate lines and the driving electrode lines, respectively.

S22, patterning the second electrode film by using the first optical cement as a first mask, wherein at least forming the grid line comprises the following steps:

s12', referring to fig. 10 d, the second electrode film 32 is patterned by using the first optical cement 33 as a first mask to form the gate line 3 and the driving electrode line 4.

S24, depositing a second optical paste over at least a portion of the first electrode film for forming the driving electrode includes:

s24', referring to fig. 10 f, a second optical paste 34 is deposited in the first electrode film 31 above the portion for forming the driving electrode and the driving electrode line, wherein the second optical paste 34 covers the side of the driving electrode line 4 away from the gate line 3.

S25, patterning the first electrode film by using the second optical cement and the grid line as a second mask, wherein at least forming the driving electrode and the buffer part comprises the following steps:

s25', referring to the graph g in FIG. 10, the second optical cement 34, the grid line 3 and the driving electrode line 4 are used as a second mask plate to pattern the first electrode film, so as to form a driving electrode 1 and a buffer part 2; wherein the grid line 3 is arranged on one side of the buffer part 2 far away from the substrate 9, and the grid line 3 covers the buffer part 2 and is not overlapped with the driving electrode 1 along the direction vertical to the substrate 9; the drive electrode 1 overlaps the drive electrode line 4 in a direction perpendicular to the substrate 9, and a portion of the drive electrode 1 overlapping the drive electrode line 4 in the direction perpendicular to the substrate 9 is an overlap electrode, and the drive electrode line 4 covers the overlap electrode 8.

In the array substrate formed by the method, the grid line covers the buffer part, the driving electrode line covers the overlapped electrode, and trailing phenomenon does not exist at the edges of the grid line and the driving electrode line, so that poor short of the grid line and the driving electrode line is avoided, and the product performance is further improved.

The following describes the preparation method in detail, taking the structure of the array substrate shown in fig. 5 as an example. The method comprises the following steps:

s100, referring to fig. 10 a, a first electrode film 31 is sequentially formed on a substrate 9.

Specifically, an Indium Tin Oxide (ITO) thin film may be formed on a glass substrate.

S101, referring to fig. 10 b, a second electrode film 32 is formed on the first electrode film 31.

Specifically, a metal film such as molybdenum (Mo), copper (Cu), or aluminum (Al) may be formed on an Indium Tin Oxide (ITO) film.

S102, referring to fig. 10 c, a first optical paste 33 is deposited over portions of the second electrode film 32 for forming the gate lines and the driving electrode lines, respectively.

S103, referring to the d diagram in fig. 10, the first optical cement 33 is used as a first mask to pattern the second electrode film 32, so as to form the gate line 3 and the driving electrode line 4.

Specifically, the first optical cement can be used as a first mask plate to expose, develop, wet etch and other processes of the second electrode film, so as to form the grid line and the driving electrode line.

S104, removing the first optical cement to obtain the substrate shown in the figure e in fig. 10.

S105, referring to f in fig. 10, a second optical paste 34 is deposited on the portion of the first electrode film 31 for forming the driving electrode and above the driving electrode line, wherein the second optical paste 34 covers the side of the driving electrode line 4 away from the gate line 3.

S106, referring to a graph g in FIG. 10, the second optical cement 34, the grid line 3 and the driving electrode line 4 are used as a second mask plate to pattern the first electrode film, so as to form the driving electrode 1 and the buffer part 2.

And S107, removing the second optical cement to obtain the substrate shown in the h diagram in fig. 10. In the substrate, as shown in fig. 10 h, the gate line 3 is disposed on a side of the buffer portion 2 away from the substrate 9, and the gate line 3 covers the buffer portion 2 and does not overlap the driving electrode 1 in a direction perpendicular to the substrate 9; the drive electrode 1 overlaps the drive electrode line 4 in a direction perpendicular to the substrate 9, and a portion of the drive electrode 1 overlapping the drive electrode line 4 in the direction perpendicular to the substrate 9 is an overlap electrode, and the drive electrode line 4 covers the overlap electrode 8.

In the steps S100 to S107, the preparation can be completed only by wet etching, and compared with the process of "0+", the productivity of the dry etching process can be effectively released, the production productivity is improved, and the equipment investment is reduced. Meanwhile, the edges of the formed grid line and the driving electrode line have no tailing phenomenon, so that the problem of capacitance increase between the grid line and the driving electrode and poor short circuit between the grid line and the driving electrode line caused by the tailing phenomenon of the grid line can be avoided.

In addition, a "1+" process is also proposed to solve the tailing phenomenon, where the "1+" process includes:

s30, referring to fig. 11 a, an ITO thin film 11 is deposited on a glass substrate 10.

S31, referring to fig. 11 b, a first photoresist 41 is deposited on the ITO film 11.

S32, referring to fig. 11 c, the ITO film 11 is patterned by using the first photoresist 41 to form an ITO pattern 40.

S33, removing the first photoresist 41, and obtaining the substrate shown in the d diagram in fig. 11.

After the first photoresist is removed, annealing, crystallization and other processes are required to be performed, so that the next process can be performed.

S34, referring to fig. 11, a metal film 12 covering the ITO pattern 40 is formed, wherein the metal film 12 includes a buffer layer (black bold line in fig. e) and a metal layer two-layer structure.

S35, referring to fig. 11 f, a second photoresist 42 is formed on the metal film 12.

S36, referring to fig. 11 g, the metal thin film is patterned by using the second photoresist 42 to form a gate pattern 43 and an electrode pattern 44.

In order to improve the adhesion of the gate line to the glass substrate by the substrate formed through the "1+" process, the gate pattern needs to be additionally formed with a buffer layer, i.e., the gate pattern includes a buffer layer and a metal layer. Meanwhile, in the preparation process, an annealing crystallization process is needed, so that the production period is increased by one day compared with a 0+ process.

In the substrate formed by executing steps S100-S107, the buffer portion may be used as a buffer layer for the gate line, and the gate line may be formed only by forming a single-layer metal structure; compared with the process of '1+', the process is greatly simplified without forming an additional buffer layer, thereby being beneficial to improving the productivity. Meanwhile, compared with the process of '1+', the preparation can be completed without adopting an annealing crystallization process, thereby greatly shortening the process production period and reducing the production cost.

Reference herein to "one embodiment," "an embodiment," or "one or more embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Furthermore, it is noted that the word examples "in one embodiment" herein do not necessarily all refer to the same embodiment.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.

Claims

1. An array substrate is characterized by comprising a plurality of sub-pixels which are arranged in an array manner;

the second electrode layer at least comprises a grid line; the grid line is arranged on one side of the buffer part far away from the substrate, covers the buffer part and is not overlapped with the driving electrode along the direction perpendicular to the substrate; the front projection of the buffer part on the substrate is positioned in the front projection of the grid line on the substrate, and the size of the front projection of the buffer part on the substrate is smaller than the size of the front projection of the grid line on the substrate in the direction parallel to the substrate and perpendicular to the extending direction of the grid line.

2. The array substrate of claim 1, wherein the second electrode layer further comprises a driving electrode line; the driving electrode wire is arranged on one side of the driving electrode far away from the substrate;

3. The array substrate of claim 2, wherein the gate lines, the driving electrode lines, and the buffer portions extend in a first direction, respectively;

4. The array substrate of claim 2, wherein the gate lines of the sub-pixels of each row are of an integrated structure, and the driving electrode lines of the sub-pixels of each row are of an integrated structure.

5. The array substrate of claim 2, wherein the gate lines and the driving electrode lines are disposed in the same layer.

6. The array substrate of claim 1, wherein the driving electrode and the buffer portion are disposed in the same layer.

7. The array substrate of claim 6, wherein the materials of the driving electrode and the buffer part respectively include transparent metal oxides, and the material of the gate line includes a metal.

8. A display panel comprising the array substrate of any one of claims 1-7.

9. A method for manufacturing the array substrate according to any one of claims 1 to 7, comprising:

forming a plurality of sub-pixels arranged in an array;

forming the sub-pixel includes:

removing the first optical cement;

patterning the first electrode film by using the second optical cement and the grid line as a second mask plate to at least form a driving electrode and a buffer part; the grid line is arranged on one side, far away from the substrate, of the buffer part, and the grid line covers the buffer part and is not overlapped with the driving electrode along the direction perpendicular to the substrate; the front projection of the buffer part on the substrate is positioned in the front projection of the grid line on the substrate, and the size of the front projection of the buffer part on the substrate is smaller than the size of the front projection of the grid line on the substrate in the direction parallel to the substrate and perpendicular to the extending direction of the grid line.

10. The method of claim 9, wherein the second electrode layer further comprises a drive electrode line;