CN113589605A

CN113589605A - Array substrate, preparation method thereof and display panel

Info

Publication number: CN113589605A
Application number: CN202110866526.8A
Authority: CN
Inventors: 孔曾杰; 郭会斌; 乔亚峥; 沈鹭; 代耀
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2021-11-02
Anticipated expiration: 2041-07-29
Also published as: CN113589605B

Abstract

The application provides an array substrate, a preparation method of the array substrate and a display panel, and relates to the technical field of display. The array substrate comprises a plurality of sub-pixels arranged in an array; the sub-pixel includes: the electrode structure comprises a substrate, a first electrode layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are sequentially stacked on the substrate; the first electrode layer at least comprises a driving electrode and a buffer part; the buffer part is positioned on one side of the driving electrode; the second electrode layer at least comprises a grid line; the gate line is arranged on one side of the buffer part far away from the substrate, covers the buffer part and does not overlap with the driving electrode along the direction vertical to the substrate. The method is suitable for manufacturing the array substrate.

Description

Array substrate, preparation method thereof and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.

Background

Compared with a VA (Vertical Alignment) type liquid crystal display, an ADS (Advanced Super Dimension Switch) type or HADS type liquid crystal display has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low color difference, and the like.

In the ADS type or HADS type liquid crystal display formed by the existing process, tail (tailing) phenomenon exists in the grid line, so that capacitance between the grid line and an ITO (Indium Tin Oxide) electrode is increased (in the ADS type, the ITO electrode refers to a common electrode, and in the HADS type, the ITO electrode refers to a pixel electrode), poor reliability of a product is caused, and further product quality is reduced.

Disclosure of Invention

The embodiment of the application provides an array substrate, a preparation method thereof and a display panel, wherein the array substrate can avoid the problem that capacitance between a grid line and a driving electrode is increased due to the trailing phenomenon of the grid line, so that poor reliability of a product is reduced, and the quality of the product is improved.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in one aspect, an array substrate is provided, which includes a plurality of sub-pixels arranged in an array;

the sub-pixel includes: the electrode structure comprises a substrate, a first electrode layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are sequentially arranged on the substrate in a laminated mode;

the first electrode layer at least comprises a driving electrode and a buffer part; the buffer part is positioned on one side of the driving electrode;

the second electrode layer at least comprises a grid line; the grid line is arranged on one side, far away from the substrate, of the buffer part, covers the buffer part and does not overlap with the driving electrode along the direction perpendicular to the substrate.

Optionally, the second electrode layer further includes a driving electrode line; the driving electrode wire is arranged on one side of the driving electrode, which is far away from the substrate;

wherein the driving electrode overlaps the driving electrode line in a direction perpendicular to the substrate, and a portion of the driving electrode overlapping the driving electrode line in the direction perpendicular to the substrate is an overlapping electrode, and the driving electrode line covers the overlapping electrode.

Optionally, the gate line, the driving electrode line and the buffer portion extend along a first direction respectively;

the sub-pixel further includes: a data line extending in a second direction; wherein the first direction and the second direction intersect; the orthographic projection of the data line on the substrate is positioned on a first side of the orthographic projection of the driving electrode on the substrate, the orthographic projection of the grid line on the substrate is positioned on a second side of the orthographic projection of the driving electrode on the substrate, and the first side is adjacent to the second side;

the first electrode layer further comprises a driving connection part; the driving connecting part is connected with the driving electrode; the driving electrode wire also covers the driving connecting part;

wherein the data line overlaps the gate line in a direction perpendicular to the substrate and overlaps a portion of the driving electrode line covering the driving connection part.

Optionally, the gate lines of the sub-pixels in each row are of an integrated structure, and the driving electrode lines of the sub-pixels in each row are of an integrated structure.

Optionally, the gate line and the driving electrode line are disposed on the same layer.

Optionally, the driving electrode and the buffer portion are disposed in the same layer.

Optionally, the materials of the driving electrode and the buffer portion respectively include transparent metal oxides, and the material of the gate line includes a metal.

In another aspect, there is provided a display panel including: the array substrate is provided.

In another aspect, a method for manufacturing an array substrate is provided, including:

forming a plurality of sub-pixels arranged in an array;

forming the sub-pixel includes:

sequentially forming a first electrode film and a second electrode film which are stacked on a substrate;

depositing a first optical glue at least above the part of the second electrode film for forming the grid line;

patterning the second electrode film by using the first optical cement as a first mask to at least form the grid line;

removing the first optical cement;

depositing a second optical paste at least over a portion of the first electrode film for forming a driving electrode;

patterning the first electrode film by using the second optical adhesive and the grid line as a second mask to form at least a driving electrode and a buffer part; the grid line is arranged on one side of the buffer part far away from the substrate, covers the buffer part and does not overlap with the driving electrode along the direction vertical to the substrate.

Optionally, the second electrode layer further includes a driving electrode line;

the depositing of the first optical paste at least over the portion of the second electrode thin film for forming the gate line includes:

respectively depositing first optical cement above parts, used for forming the grid lines and the driving electrode lines, of the second electrode film;

patterning the second electrode film by using the first optical cement as a first mask, and at least forming the gate line includes:

patterning the second electrode film by using the first optical cement as a first mask to form the grid line and the driving electrode line;

the depositing of the second optical paste at least over the portion of the first electrode film for forming the driving electrode includes:

depositing a second optical adhesive on the part of the first electrode film for forming the driving electrode and above the driving electrode line, wherein the second optical adhesive covers one side of the driving electrode line far away from the grid line;

the patterning of the first electrode film by using the second optical adhesive and the grid line as a second mask to form at least a driving electrode and a buffer part comprises:

patterning the first electrode film by using the second optical cement, the grid line and the driving electrode line as a second mask to form a driving electrode and a buffer part; the grid line is arranged on one side of the buffer part far away from the substrate, covers the buffer part and does not overlap with the driving electrode along the direction vertical to the substrate; the driving electrode overlaps the driving electrode line in a direction perpendicular to the substrate, and a portion of the driving electrode overlapping the driving electrode line in the direction perpendicular to the substrate is an overlapping electrode, and the driving electrode line covers the overlapping electrode.

The embodiment of the application provides an array substrate, a preparation method thereof and a display panel, wherein in the array substrate, a gate line covers a buffer part, so that the trailing phenomenon is not generated at the edges of two sides of the gate line, and on one hand, the problem of capacitance increase between the gate line and a driving electrode caused by the trailing phenomenon of the gate line can be avoided; on the other hand, the capacitance between the grid line and the driving electrode is reduced, and the line capacitance of the grid line is reduced, so that the circuit delay phenomenon of the grid line can be reduced, the input effect of the grid line is improved, the charging rate and the display effect of the sub-pixels are finally improved, and the problems of poor product reliability such as poor low-temperature starting and poor water ripple are greatly reduced; on the other hand, the buffer part can be used as a buffer layer of the grid line, the grid line only needs to form a single-layer structure, and an extra buffer layer is not needed, so that the process is greatly simplified, and the yield is favorably improved.

The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

In FIG. 1, a-h are diagrams illustrating a structure of a process flow for preparing a "0 +" process according to an embodiment of the present disclosure;

FIG. 2 is a diagram of a substrate structure formed using a "0 +" process;

FIG. 3 is an electron micrograph of a structure corresponding to FIG. 2;

fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

FIG. 5 is a cross-sectional view taken along line B2B3 in FIG. 4;

FIG. 6 is an electron micrograph of a structure corresponding to FIG. 4;

FIG. 7 is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present disclosure;

FIG. 8 is a layout diagram of a short circuit failure generated in a substrate formed by a "0 +" process;

fig. 9 is a layout diagram corresponding to the structure of fig. 4 provided in the embodiment of the present application;

in fig. 10, a-h are diagrams illustrating a process of fabricating an array substrate according to an embodiment of the present disclosure;

in fig. 11, a-h are diagrams illustrating a structure of a preparation flow of a "1 +" process according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the embodiments of the present application, the terms "first", "second", and the like are used for distinguishing identical items or similar items having substantially the same functions and actions, and are used only for clearly describing technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

In the embodiments of the present application, "a plurality" means two or more, and "at least one" means one or more unless specifically limited otherwise.

In the embodiments of the present application, the terms "upper", "lower", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

In order to further increase the aperture ratio compared to the ADS type lcd, the HADS type lcd has been developed. The ADS type is largely different from the HADS type in that the electrode positions of the common electrode (common) and the pixel electrode (pixel) are different.

The manufacturing process of the ADS type and HADS type liquid crystal displays includes a "0 +" process, and specifically, referring to a-h diagram in fig. 1, the "0 +" process includes:

s10, referring to a diagram in fig. 1, an ITO (Indium Tin Oxide) film 11 is deposited on the glass substrate 10.

S11, referring to b of fig. 1, a metal film 12 is deposited on the ITO (Indium Tin Oxide) film 11.

S12, referring to fig. 1 c, a halftone mask (HGA)13 is formed.

S13, etching the metal film 12 by using a half-tone mask (HGA)13 to obtain a first gate layer shown in d of fig. 1, where the first gate layer includes a first pattern 14 and a second pattern 15.

S14, etching the ITO film 11 by using a half-tone mask (HGA)13 to obtain a second gate layer shown in e of fig. 1, where the second gate layer includes the first ITO pattern 16 and the second ITO pattern 17.

Ashing of the halftone mask (HGA)13 is performed at S15, resulting in mask 18 shown in f of fig. 1. This step requires the use of a dry etching process.

S16, etching the first pattern 14 and the second pattern 15 by using the mask 18, and obtaining the gate metal line 19 and the electrode line 20 as shown in g of fig. 1.

S17, stripping the mask 18 to obtain the structure shown as h in figure 1.

Fig. 2 is a layout plan view of a substrate formed by the "0 +" process, and a cross-sectional view along the direction BB1 in fig. 2 can be referred to as h in fig. 1. Referring to fig. 1 h and 2, ITO tails (i.e., a1 and a2 in the first ITO pattern 16) are present at both side edges of the gate metal line 19, and ITO tails (i.e., A3 in the second ITO pattern 17) are present at one side edge of the electrode line 20 close to the gate line. Fig. 3 is an electron microscope (SEM) image of the substrate formed by the "0 +" process, and referring to fig. 3, ITO tails 23 are present at both side edges of the gate metal line 19, and ITO tails 22 are present at one side edge of the electrode line 20 close to the gate metal line. This results in an increase in capacitance between the gate metal line and the ITO electrode (in the ADS type, the ITO electrode is a common electrode; and in the HADS type, the ITO electrode is a pixel electrode), resulting in poor reliability of the product.

If the substrate shown in fig. 2 is applied to an ADS-type liquid crystal display, the second ITO pattern 17 is a common electrode (common electrode), and the electrode 21 is a pixel electrode (pixel electrode); if the substrate shown in fig. 2 is applied to a HADS type liquid crystal display, the second ITO pattern 17 is a pixel electrode and the electrode 21 is a common electrode. In addition, as the thickness of the gate metal line increases, the size of the ITO tail increases, and the reliability is further deteriorated. For example, if the gate metal line is made of copper, the thickness of the copper layer is as thick as possibleAre respectively as

And

the sizes of the gate metal line ITO tail are 1.2 μm, 1.4 μm and 1.7 μm, respectively.

In view of the above, the embodiment of the present application provides an array substrate, which is shown in fig. 4 and 5, and includes a plurality of sub-pixels 100 arranged in an array; the sub-pixel 100 includes: a substrate 1, and a first electrode layer and a second electrode layer which are sequentially stacked and provided on the substrate 1.

Referring to fig. 5, the first electrode layer includes at least a driving electrode 1 and a buffer 2; the buffer 2 is located on the side of the drive electrode 3.

Referring to fig. 4 and 5, the second electrode layer includes at least a gate line 3; the gate line 3 is disposed on a side of the buffer portion 2 away from the substrate 1, and the gate line 3 covers the buffer portion 2 and does not overlap with the driving electrode 1 in a direction perpendicular to the substrate.

The above-mentioned grid line covers the buffer portion and indicates: referring to fig. 5, the orthographic projection D2 of the grid line on the substrate 9 covers the orthographic projection D1 of the buffer 2 on the substrate 9, i.e. the orthographic projection D1 of the buffer 2 on the substrate 9 is located within the orthographic projection D2 of the grid line on the substrate 9.

If the array substrate is applied to an ADS type liquid crystal display, the driving electrode is a common electrode; if the array substrate is applied to a HADS type liquid crystal display, the driving electrodes are pixel electrodes. The shape of the driving electrode is not limited, and the driving electrode may be a plate-shaped electrode as shown in fig. 4, for example. If the array substrate is applied to a liquid crystal display, the array substrate may further include a slit electrode when the driving electrode is a plate electrode, and a multi-dimensional electric field is formed between the plate electrode and the slit electrode to drive liquid crystal to deflect, thereby realizing display.

Fig. 6 is an electron microscope image corresponding to the structure of fig. 4, and referring to fig. 6, the two side edges of the gate line 3 are clean, and compared with fig. 3, there is no tailing phenomenon, so that the problem of capacitance increase between the gate line and the driving electrode caused by the tailing phenomenon of the gate line can be avoided, the margin (boundary range) of the design and process is improved, the reliability of the product is reduced, and the product quality is improved.

The principle of reducing the capacitance between the gate line and the driving electrode according to the present invention will be described in detail below.

The calculation formula of the capacitance C between the grid line and the driving electrode is as follows: c ═ S/(4 pi kd), where epsilon is the dielectric constant, S is the relative area of the gate lines and the drive electrodes, 4 pi k is a constant, and d is the distance between the gate lines and the drive electrodes.

The capacitance between the gate line and the driving electrode is a non-overlapping capacitance, and under the condition that the relative area of the gate line and the driving electrode is not changed, if the distance between the gate line and the driving electrode is reduced, the capacitance between the gate line and the driving electrode is increased. In the related art, the trailing phenomenon may occur at edges of both sides of the gate line, resulting in a smaller actual distance between the gate line and the driving electrode than a design value, thereby increasing capacitance between the gate line and the driving electrode. In the application, the buffering part is covered by the grid line, so that the trailing phenomenon is not generated at the edges of two sides of the grid line, and the problem that the capacitance between the grid line and the driving electrode is increased due to the trailing phenomenon of the grid line can be avoided.

In addition, the capacitance between the gate line and the driving electrode directly affects the line capacitance Cgate of the gate line, and the larger Cgate is, a circuit Delay (RC Delay) is generated. And the circuit delay value is the product value of the resistance and the capacitance, namely the larger the capacitance is, the more serious the circuit delay is. In large-size and high-frequency products, the line capacitance Cgate of the grid line is larger, and the circuit delay phenomenon is more serious, so that the voltage input of the grid line is directly influenced, further the charging and displaying of the sub-pixels are influenced, and the problems of poor product reliability such as poor low-temperature starting, poor water ripple and the like are easily caused. Therefore, in practical designs, it is desirable to reduce the value of the line capacitance Cgate as much as possible.

Fig. 7 is an equivalent circuit structure of a sub-pixel, and referring to fig. 7, the sub-pixel includes a pixel electrode (pixel electrode), a TFT (thin film transistor), a Gate line Gate, a common electrode line Com, and the like, and capacitances between the structures are shown in fig. 7. In the state where the TFT is ON, the calculation formula of Cgate is explained by taking the lowermost Gate line in fig. 7 as an example.

C_gate＝C_{gdx_on}+C_{gd_on}+C_{gs_on}+C_gc+C_gdx+C_pg (1)

Wherein, C_{gdx_on}Representing the capacitance between the Gate line (Gate line) and the left Data line (Data line) at the left part of the left Data line in the on state, C_{gd_on}Representing the capacitance between the Gate line (Gate line) and the left Data line (Data line) at the right part of the left Data line in the on state, C_{gs_on}Denotes the capacitance between the Gate line (Gate line) and the storage capacitor (Cst) in the on state, C_gcRepresenting the capacitance between the Gate line (Gate line) and the common electrode, C_gdxRepresenting the capacitance between the Gate line (Gate line) and the right data line, C_pgRepresenting the capacitance between the Gate line (Gate line) and the pixel electrode.

Obtained by the above formula (1), C_gcOr C_pgThe larger the line capacitance Cgate of the gate line. Fig. 7 is equivalent to the ADS type structure as an example, in which the driving electrode is a common electrode. In the structure provided by the application, C can be reduced_gcAnd further, the line capacitance Cgate of the grid line can be reduced, so that the circuit delay phenomenon of the grid line can be reduced, the input effect of the grid line is improved, the charging rate and the display effect of the sub-pixels are finally improved, and the problems of poor product reliability such as poor low-temperature starting and poor water ripple (waterfall) are greatly reduced.

Generally, the grid line is mostly made of metal, but the adsorption force between the metal and the substrate is poor, and the film forming effect is poor. In order to improve the film forming quality of the grid line, the grid line with a composite layer (including a buffer layer and a metal layer) needs to be manufactured, and the buffer layer is made of MoNb (molybdenum niobium), Mo (molybdenum), Ti (titanium) and the like, so that the manufacturing process is increased undoubtedly, and the production cost is increased. In the application, the buffer part can be used as a buffer layer of the grid line, the grid line only needs to form a single-layer structure, the buffer layer does not need to be additionally formed, the process is greatly simplified, and the yield is favorably improved.

According to the array substrate provided by the application, the gate line covers the buffer part, so that the trailing phenomenon is not generated at the edges of two sides of the gate line, and the problem of capacitance increase between the gate line and the driving electrode caused by the trailing phenomenon of the gate line can be avoided; on the other hand, the capacitance between the grid line and the driving electrode is reduced, and the line capacitance of the grid line is reduced, so that the circuit delay phenomenon of the grid line can be reduced, the input effect of the grid line is improved, the charging rate and the display effect of the sub-pixels are finally improved, and the problems of poor product reliability such as poor low-temperature starting and poor water ripple are greatly reduced; on the other hand, the buffer part can be used as a buffer layer of the grid line, the grid line only needs to form a single-layer structure, and an extra buffer layer is not needed, so that the process is greatly simplified, and the yield is favorably improved.

Optionally, referring to fig. 4 and 5, the second electrode layer further includes a driving electrode line 4; the driving electrode line 4 is arranged on the side of the driving electrode 1 away from the substrate.

Wherein, the driving electrode 1 overlaps the driving electrode line 4 along the direction perpendicular to the substrate 9, and the overlapping electrode 8 is the part of the driving electrode 1 overlapping the driving electrode line 4 along the direction perpendicular to the substrate 9, and the driving electrode line 4 covers the overlapping electrode 8.

The above-mentioned driving electrode line covering the overlapping electrode means: referring to fig. 5, the orthographic projection D4 of the driving electrode line 4 on the substrate 9 covers the orthographic projection D3 of the overlap electrode 8 on the substrate 9, i.e. the orthographic projection D3 of the overlap electrode 8 on the substrate 9 is located within the orthographic projection D4 of the driving electrode line 4 on the substrate 9.

It should be noted that, if the array substrate is applied to the ADS type lcd, the driving electrode lines are common electrode lines; if the array substrate is applied to a HADS type liquid crystal display, the driving electrode lines are pixel electrode lines.

In the related art, as shown in fig. 2, an ITO tail phenomenon occurs in both the gate metal line 19 and the electrode line 20, and during the manufacturing process, the ITO tails between the gate metal line and the electrode line are easily connected together in a short-circuit failure region as shown in fig. 8, thereby causing short (short-circuit) failure. In this application, the grid line covers buffer portion, and drive electrode line covers overlapping electrode, and it is shown with reference to fig. 9, and grid line 3 and drive electrode line 4's edge does not all have the trailing phenomenon to avoid both to take place short bad, further improved product property ability.

Further alternatively, as shown in fig. 4 and 5, the gate lines 3, the driving electrode lines 4, and the buffer parts 2 extend in the first direction OA direction, respectively.

Referring to fig. 4, the sub-pixel 100 further includes: a data line 5, the data line 5 extending in a second direction OC; wherein the first direction and the second direction intersect; the orthographic projection of the data line 5 on the substrate 9 is positioned on a first side (namely, the left side of the driving electrode 1 in fig. 4) of the orthographic projection of the driving electrode 1 on the substrate 9, the orthographic projection of the gate line 3 on the substrate 9 is positioned on a second side (namely, the upper side of the driving electrode 1 in fig. 4) of the orthographic projection of the driving electrode 1 on the substrate 9, and the first side is adjacent to the second side.

Referring to fig. 4, the first electrode layer further includes a driving connection part 6; the driving connection part 6 is connected with the driving electrode 1; the drive electrode line 4 also covers the drive connection 6.

Wherein the data lines 5 overlap the gate lines 3 in a direction perpendicular to the substrate 9 and overlap portions of the driving electrode lines 3 covering the driving connection parts 6.

In fig. 4, the drive connection portion 6 is covered with the drive electrode line 4 and indicated by a dashed line frame. The driving electrode wires also cover the driving connecting parts, namely the orthographic projection of the driving connecting parts on the substrate is positioned within the orthographic projection of the driving electrode wires on the substrate.

The first direction may be parallel to a short side direction of the array substrate, and at this time, the second direction may be parallel to a long side direction of the array substrate; alternatively, the first direction may be parallel to a long side direction of the array substrate, and in this case, the second direction may be parallel to a short side direction of the array substrate, which is not limited herein.

In the related art, the data line overlaps the gate line and the driving electrode line, and the trailing phenomenon exists at the edge of the gate line and the driving electrode line, so that the overlapping area of the data line and the gate line and the overlapping area of the data line and the driving electrode line are correspondingly increased, thereby increasing the parasitic capacitance of the data line and the gate line and the parasitic capacitance of the data line and the driving electrode line, and further increasing the line capacitance Cdata on the data line

Referring to fig. 7, in a state where the TFT is OFF (OFF), a calculation formula of Cdata is described taking the Data line on the left side in fig. 7 as an example.

C_data＝C_{gdx_off}+C_{gd_off}+C_dcx+C_dc+C_pd (2)

Wherein, C_{gdx_off}Representing the capacitance between the Gate line (Gate line) and the left Data line (Data line) at the left part of the left Data line in the off state, C_{gd_off}Representing the capacitance between the Gate line (Gate line) and the left Data line (Data line) at the right part of the left Data line in the off state, C_dcxRepresenting the capacitance between the common electrode line (Com line) and the left data line, C_dcRepresenting the capacitance between the left data line and the common electrode, C_pdRepresenting the capacitance between the left data line and the pixel electrode.

The parasitic capacitance C of the data line and the gate line can be obtained by the above formula (2)_gdAnd parasitic capacitance C of data line and driving electrode line_dcxThe larger the line capacitance Cdata of the data line. Fig. 7 is equivalent by taking an ADS type structure as an example, and in this case, the driving electrode line is a common electrode line.

And the larger the line capacitance Cdata of the data line is, the more serious the circuit delay on the data line is, thereby directly affecting the voltage input of the data line. In FIG. 7, the pixel charging rate

Wherein, C_stDenotes a storage capacitance, C_pdWhich indicates the capacitance between the data line and the pixel electrode, VD indicates the voltage of the data line, Vt indicates the voltage of the storage capacitor after the charging time t, and V0 indicates the initial voltage of the storage capacitor. The voltage of the data line directly affects the pixel charging rate, and the line capacitance Cdata of the data line directly affects the voltage of the data line. Therefore, in practical design, it is necessary to reduce the value of the line capacitance Cdata of the data line as much as possible.

In the structure that this application provided, can reduce the parasitic capacitance of data line and grid line and the parasitic capacitance of data line and drive electrode line, and then can reduce the line capacitance of data line to can alleviate the circuit delay phenomenon of data line, improve the input effect of data line, finally promote sub-pixel's charge rate and display effect, alleviate the bad problem of product reliability such as the low temperature starts badly and the ripple is bad by a wide margin.

Optionally, in order to facilitate driving and simplify the structure, the gate lines of each row of sub-pixels are of an integrated structure, and the driving electrode lines of each row of sub-pixels are of an integrated structure.

Optionally, in order to reduce the number of patterning processes and reduce the manufacturing cost, the gate line and the driving electrode line are disposed in the same layer.

The same layer setting refers to manufacturing by adopting a one-time composition process. The one-step patterning process refers to a process of forming a desired layer structure through one exposure. The primary patterning process includes masking, exposing, developing, etching, and stripping processes.

Optionally, in order to reduce the number of patterning processes and reduce the manufacturing cost, the driving electrode and the buffer portion are disposed in the same layer.

Further optionally, the materials of the driving electrode and the buffer portion respectively include transparent metal oxide, and the material of the gate line includes metal.

For example, the transparent metal oxide may be ITO (indium tin oxide), and the metal may be molybdenum (Mo), copper (Cu), aluminum (Al), or the like.

The buffer part can be used as a buffer layer of the grid line, so that the grid line only needs to be provided with one metal layer, the manufacturing process of the grid line is simplified, and the manufacturing cost is reduced.

It should be noted that the array substrate may further include other film structures, such as: thin film transistors, etc., and only the structures and film layers relevant to the point of the invention will be described herein, and the remaining structures can be obtained with reference to the related art.

The embodiment of the application also provides a display panel which comprises the array substrate.

The display panel can be an ADS type or HADS type liquid crystal display panel, and any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer and the like, comprising the display panel. The display panel has the characteristics of short signal delay, high response speed, low cost, excellent display picture and the like.

The embodiment of the application further provides a preparation method of the array substrate, which comprises the following steps:

and S01, forming a plurality of sub-pixels arranged in an array.

Wherein forming the sub-pixels comprises:

s20, the first electrode film and the second electrode film are sequentially formed on the substrate.

The substrate may be made of a rigid material such as glass, or may be made of a flexible material such as PI (polyimide). The first electrode thin film may be an Indium Tin Oxide (ITO) thin film; the second electrode thin film may be a metal thin film of molybdenum (Mo), copper (Cu), aluminum (Al), or the like.

And S21, depositing a first optical glue at least above the part of the second electrode film for forming the grid line.

Of course, the first optical paste may also be deposited simultaneously over the portion of the second electrode film for forming the driving electrode line.

And S22, patterning the second electrode film by using the first optical cement as a first mask to form at least a grid line.

The patterning includes: exposure, development, etching process and the like; it should be noted that the patterning process may adopt dry etching, or may also adopt wet etching, and in order to improve the etching efficiency, wet etching may be adopted.

And S23, removing the first optical cement.

And S24, depositing a second optical glue at least above the part of the first electrode film for forming the driving electrode.

S25, patterning the first electrode film by using the second optical glue and the grid line as a second mask to form at least a driving electrode and a buffer part; the grid line is arranged on one side of the buffer part far away from the substrate, covers the buffer part and does not overlap with the driving electrode along the direction vertical to the substrate.

By executing the array substrate formed in the steps S20-S25, the gate line covers the buffer portion, so that the trailing phenomenon is not generated at the edges of the two sides of the gate line, and on one hand, the problem of capacitance increase between the gate line and the driving electrode caused by the trailing phenomenon of the gate line can be avoided; on the other hand, the capacitance between the grid line and the driving electrode is reduced, and the line capacitance of the grid line is reduced, so that the circuit delay phenomenon of the grid line can be reduced, the input effect of the grid line is improved, the charging rate and the display effect of the sub-pixels are finally improved, and the problems of poor product reliability such as poor low-temperature starting and poor water ripple are greatly reduced; on the other hand, the buffer part can be used as a buffer layer of the grid line, the grid line only needs to form a single-layer structure, and an extra buffer layer is not needed, so that the process is greatly simplified, and the yield is favorably improved. The manufacturing method is simple and easy to realize. In the steps S20-S25, the preparation can be completed only by wet etching, and compared with the "0 +" process, the production capacity of the dry etching process can be effectively released, the production capacity is improved, and the equipment investment is reduced.

Optionally, the second electrode layer further includes a driving electrode line.

S21, depositing a first optical paste at least over a portion of the second electrode film for forming the gate line includes:

s21', referring to fig. 10 c, first optical glues 33 are respectively deposited over portions of the second electrode film 32 for forming the gate lines and the driving electrode lines.

S22, patterning the second electrode film by using the first optical glue as a first mask, and at least forming the gate line includes:

s12', referring to fig. 10 d, the second electrode film 32 is patterned by using the first optical glue 33 as a first mask to form the gate lines 3 and the driving electrode lines 4.

S24, depositing a second optical paste at least over the portion of the first electrode film for forming the driving electrode includes:

s24', referring to fig. 10 f, a second optical paste 34 is deposited over the portion of the first electrode film 31 for forming the driving electrode and the driving electrode line, wherein the second optical paste 34 covers one side of the driving electrode line 4 away from the gate line 3.

S25, patterning the first electrode film by using the second optical glue and the gate line as a second mask, and forming at least a driving electrode and a buffer portion includes:

s25', referring to fig. 10, g, patterning the first electrode thin film by using the second optical glue 34, the gate line 3 and the driving electrode line 4 as a second mask to form the driving electrode 1 and the buffer portion 2; wherein, the gate line 3 is arranged at one side of the buffer part 2 far away from the substrate 9, and the gate line 3 covers the buffer part 2 and does not overlap with the driving electrode 1 along the direction vertical to the substrate 9; the driving electrode 1 overlaps the driving electrode line 4 in a direction perpendicular to the substrate 9, and a portion of the driving electrode 1 overlapping the driving electrode line 4 in the direction perpendicular to the substrate 9 is an overlapping electrode, and the driving electrode line 4 covers the overlapping electrode 8.

In the array substrate formed by the method, the gate line covers the buffer part, the drive electrode line covers the overlapped electrodes, and the trailing phenomenon does not exist at the edges of the gate line and the drive electrode line, so that the short defect of the gate line and the drive electrode line is avoided, and the product performance is further improved.

The following describes the preparation method in detail by taking the array substrate structure shown in fig. 5 as an example. The method comprises the following steps:

s100, referring to a diagram a in fig. 10, the first electrode thin film 31 is sequentially formed on the substrate 9.

Specifically, an Indium Tin Oxide (ITO) thin film may be formed on a glass substrate.

S101, referring to fig. 10 b, a second electrode film 32 is formed on the first electrode film 31.

Specifically, a metal thin film of molybdenum (Mo), copper (Cu), aluminum (Al), or the like may be formed on the Indium Tin Oxide (ITO) thin film.

S102, referring to fig. 10 c, depositing first optical glues 33 respectively on the portions of the second electrode film 32 for forming the gate lines and the driving electrode lines.

S103, referring to fig. d in fig. 10, patterning the second electrode thin film 32 by using the first optical glue 33 as a first mask to form the gate line 3 and the driving electrode line 4.

Specifically, the first optical glue can be used as a first mask to perform processes such as exposure, development, wet etching and the like on the second electrode film, so as to form the gate line and the driving electrode line.

And S104, removing the first optical cement to obtain the substrate shown as an e diagram in figure 10.

S105, referring to fig. 10 f, depositing a second optical paste 34 over the portion of the first electrode film 31 for forming the driving electrode and the driving electrode line, wherein the second optical paste 34 covers a side of the driving electrode line 4 away from the gate line 3.

S106, referring to fig. 10 g, the first electrode thin film is patterned by using the second optical glue 34, the gate line 3 and the driving electrode line 4 as a second mask to form the driving electrode 1 and the buffer portion 2.

And S107, removing the second optical cement to obtain the substrate shown as h in the figure 10. In the substrate, referring to fig. 10 h, the gate line 3 is arranged on one side of the buffer part 2 far away from the substrate 9, and the gate line 3 covers the buffer part 2 and does not overlap with the driving electrode 1 along the direction vertical to the substrate 9; the driving electrode 1 overlaps the driving electrode line 4 in a direction perpendicular to the substrate 9, and a portion of the driving electrode 1 overlapping the driving electrode line 4 in the direction perpendicular to the substrate 9 is an overlapping electrode, and the driving electrode line 4 covers the overlapping electrode 8.

In the steps S100 to S107, the preparation can be completed only by wet etching, and compared with the "0 +" process, the productivity of the dry etching process can be effectively released, the production capacity is improved, and the equipment investment is reduced. Meanwhile, the formed edges of the grid lines and the drive electrode lines do not have trailing phenomena, so that the problem that capacitance between the grid lines and the drive electrodes is increased due to the trailing phenomena of the grid lines and the short circuit between the grid lines and the drive electrode lines is poor can be avoided.

In addition, a '1 +' process is also provided for solving the tailing phenomenon, and the '1 +' process comprises the following steps:

s30, referring to a diagram a in fig. 11, the ITO thin film 11 is deposited on the glass substrate 10.

S31, referring to fig. 11 b, a first photoresist 41 is deposited on the ITO film 11.

S32, referring to fig. 11 c, the ITO thin film 11 is patterned by using the first photoresist 41 to form an ITO pattern 40.

S33, removing the first photoresist 41, and obtaining the substrate shown as d in fig. 11.

After the first photoresist is removed, processes such as annealing, crystallization and the like are required to perform the next process.

S34, referring to fig. 11 e, forming a metal film 12 covering the ITO pattern 40, wherein the metal film 12 includes a two-layer structure of a buffer layer (black and thick lines in the e diagram) and a metal layer.

S35, referring to fig. 11 f, a second photoresist 42 is formed on the metal film 12.

S36, referring to fig. 11 g, the metal thin film is patterned using the second photoresist 42 to form the gate pattern 43 and the electrode pattern 44.

In the substrate formed through the "1 +" process, in order to improve the adhesion of the gate line to the glass substrate, the gate pattern needs to be additionally formed with a buffer layer, that is, the gate pattern includes the buffer layer and a metal layer. Meanwhile, in the preparation process, an annealing crystallization process is required, so that the production period is increased by one day compared with a '0 +' process.

In the substrate formed by performing the steps S100 to S107, the buffer portion may serve as a buffer layer for the gate line, and the gate line only needs to be formed in a single-layer metal structure; compared with the 1 plus process, the process does not need to additionally form a buffer layer, greatly simplifies the process and is beneficial to the improvement of the productivity. Meanwhile, compared with the 1 plus process, the preparation can be finished without adopting an annealing crystallization process, so that the process production period is greatly shortened, and the production cost is reduced.

Reference herein to "one embodiment," "an embodiment," or "one or more embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Moreover, it is noted that instances of the word "in one embodiment" are not necessarily all referring to the same embodiment.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. The array substrate is characterized by comprising a plurality of sub-pixels arranged in an array;

2. The array substrate of claim 1, wherein the second electrode layer further comprises a driving electrode line; the driving electrode wire is arranged on one side of the driving electrode, which is far away from the substrate;

3. The array substrate of claim 2, wherein the gate lines, the driving electrode lines and the buffer portions extend in a first direction, respectively;

4. The array substrate of claim 2, wherein the gate lines of the sub-pixels of each row are of an integral structure, and the driving electrode lines of the sub-pixels of each row are of an integral structure.

5. The array substrate of claim 2, wherein the gate lines and the driving electrode lines are disposed in the same layer.

6. The array substrate of claim 1, wherein the driving electrode and the buffer portion are disposed in the same layer.

7. The array substrate of claim 6, wherein the materials of the driving electrode and the buffer portion respectively comprise transparent metal oxide, and the material of the gate line comprises metal.

8. A display panel comprising the array substrate according to any one of claims 1 to 7.

9. A method for preparing the array substrate according to any one of claims 1 to 7, comprising:

forming a plurality of sub-pixels arranged in an array;

forming the sub-pixel includes:

removing the first optical cement;

10. The method of claim 9, wherein the second electrode layer further comprises a driving electrode line;