WO2013124956A1 - Appareil de capture d'image à l'état solide - Google Patents

Appareil de capture d'image à l'état solide Download PDF

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WO2013124956A1
WO2013124956A1 PCT/JP2012/053995 JP2012053995W WO2013124956A1 WO 2013124956 A1 WO2013124956 A1 WO 2013124956A1 JP 2012053995 W JP2012053995 W JP 2012053995W WO 2013124956 A1 WO2013124956 A1 WO 2013124956A1
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Prior art keywords
region
semiconductor region
signal
pixel
solid
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PCT/JP2012/053995
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English (en)
Japanese (ja)
Inventor
舛岡　富士雄
原田　望
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ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
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Priority to JP2013537989A priority Critical patent/JP5547853B2/ja
Priority to KR1020137021916A priority patent/KR20130121947A/ko
Priority to PCT/JP2012/053995 priority patent/WO2013124956A1/fr
Priority to CN2012800096431A priority patent/CN103384916A/zh
Priority to TW102105499A priority patent/TW201336062A/zh
Publication of WO2013124956A1 publication Critical patent/WO2013124956A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/779—Circuitry for scanning or addressing the pixel array

Definitions

  • the present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device that achieves high pixel density, low power consumption, and low light leakage.
  • solid-state imaging devices are widely used for video cameras, still cameras, and the like.
  • performance improvements such as higher pixel density, higher resolution, lower color mixing and higher sensitivity in color imaging are always required.
  • technological innovations such as higher pixel density have been performed in order to achieve higher resolution of solid-state imaging devices.
  • FIG. 9A and 9B show a conventional solid-state imaging device.
  • FIG. 9A shows a cross-sectional structure diagram of a conventional solid-state imaging device in which one pixel is formed in one island-like semiconductor (see, for example, Patent Document 1).
  • a signal line N + region 102 (hereinafter referred to as “N + region”) is a semiconductor region containing a lot of donor impurities on a substrate 101. ) Is formed.
  • a P region 103 (hereinafter, a semiconductor region containing an acceptor impurity is referred to as a “P region”) is formed on the signal line N + region 102, and an insulating layer 104 is formed on the outer periphery of the P region 103.
  • a gate conductor layer 105 is formed with this insulating layer 104 interposed.
  • An N region (hereinafter, a semiconductor region containing donor impurities is referred to as an “N region”) 106 is formed on the outer periphery of the P region 103 above the gate conductor layer 105.
  • a P + region (hereinafter, a semiconductor region containing a lot of acceptor impurities is referred to as a “P + region”) 107 is formed on the N region 106 and the P region 103.
  • the P + region 107 is connected to the pixel selection line conductor layer 108.
  • the insulating layers 104 described above are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 100.
  • the gate conductor layers 105 are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 100.
  • a photodiode region is formed from a P region 103 and an N region 106 in the island-shaped semiconductor 100.
  • signal charges here, free electrons
  • This signal charge is accumulated mainly in the N region 106 of the photodiode region.
  • a junction field effect transistor is configured with the N region 106 as a gate, the P + region 107 as a source, and the P region 103 near the signal line N + region 102 as a drain.
  • the drain-source current (output signal) of the junction field effect transistor changes corresponding to the amount of signal charge accumulated in the N region 106, and a signal is output from the signal line N + region 102. As taken out.
  • the N region 106 of the photodiode region is the source
  • the gate conductor layer 105 is the reset gate
  • the signal line N + region 102 is the drain
  • a reset MOS transistor having the region 103 as a channel is formed (hereinafter, this gate conductor layer is referred to as “reset gate conductor layer”).
  • this gate conductor layer is referred to as “reset gate conductor layer”.
  • the signal charges accumulated in the N region 106 are applied with an on-voltage (high level voltage) to the reset gate conductor layer 105 of the reset MOS transistor, whereby the signal line N + region 102 is applied. Removed.
  • the “high level voltage” indicates a higher level positive voltage when the signal charge is a free electron
  • the “low level voltage” used hereinafter in this specification refers to this “high level voltage”.
  • the voltage is lower than “voltage”.
  • “high level voltage” means a lower level negative voltage
  • “low level voltage” means a voltage closer to 0V than the “high level voltage”.
  • FIG. 9B shows a pixel region in which island-shaped semiconductors P11 to P33 (corresponding to the island-shaped semiconductor 100 in FIG. 9A) constituting the pixel are two-dimensionally arranged, and a drive / output circuit around the pixel region.
  • the schematic plan view of the solid-state imaging device of the prior art example which has is shown.
  • a cross-sectional structure taken along line FF ′ in FIG. 9B is shown in FIG. 9A.
  • Island-like semiconductors P11 to P33 constituting pixels are formed on the signal line N + regions 102a, 102b, and 102c (corresponding to the signal line N + region 102 in FIG. 9A).
  • the pixel selection line conductor layers 108a, 108b, and 108c are formed so as to be connected to each other in each row extending in the horizontal direction of the island-shaped semiconductors P11 to P33. Are connected to a pixel selection line vertical scanning circuit 110 provided in the periphery of the pixel selection line.
  • the reset gate conductor layers 105a, 105b, and 105c are connected to each other in each row extending in the horizontal direction of the island-shaped semiconductors P11 to P33 constituting the pixel.
  • the reset line vertical scanning circuit 112 formed and provided around the pixel region is connected.
  • each signal line N + region 102a, 102b, 102c is connected to the switch MOS transistors 115a, 115b, 115c, and the gate of each switch MOS transistor 115a, 115b, 115c is connected to the signal line horizontal scanning circuit 116. ing.
  • the drains of the switch MOS transistors 115a, 115b, and 115c are connected to the output circuit 117.
  • the switch circuits 118a, 118b, and 118c are connected to the upper portions of the signal line N + regions 102a, 102b, and 102c.
  • a high level voltage Vr for reset-on is applied during the removal operation.
  • the signal charge accumulation operation is performed by applying a ground voltage to the signal line N + regions 102a, 102b, and 102c, a low level voltage for reset-off to the reset gate conductor layers 105a, 105b, and 105c, and a pixel selection line conductor layer 108a, 108b, and 108c. It is executed in a state where a ground voltage is applied.
  • the reset gate conductor layers 105a, 105b, and 105c have a low level voltage for reset-off, and the pixel selection line conductor layers 108a, 108b, and 108c of the pixel that reads the signal charges have a high level voltage and a signal charge.
  • ON voltage high level voltage
  • the voltage / output circuit 117 is executed when the output circuit 117 takes in the source / drain current of the junction field effect transistor of the pixel to be read out while the input terminal of the output circuit 117 is at a low level voltage.
  • the signal charge removal operation is performed in the island-shaped semiconductors P11 to P33 in a state where all the pixel selection line conductor layers 108a, 108b, and 108c are grounded and all the switch MOS transistors 115a, 115b, and 115c are off.
  • a high level voltage for reset-on is applied to the reset gate conductor layers 105a, 105b, and 105c connected to the pixel from which the accumulated signal charge is removed, and the output terminals of the switch circuits 118a, 118b, and 118c are at the high level for reset-on. It is executed by reaching the voltage Vr.
  • the height of the island-shaped semiconductor 100 is mainly determined by the height Ld of the N layer 106 of the photodiode.
  • light enters from the upper surface of the P + layer 107 on the island-shaped semiconductor 100.
  • the signal charge generation rate due to the incident light has a characteristic that decreases from an upper surface of the P + layer 121 with an exponential curve with respect to the Si depth.
  • the depth of the photoelectric conversion region needs to be 2.5 to 3 ⁇ m in order to efficiently extract signal charges that contribute to sensitivity (see, for example, Non-Patent Document 1). .
  • the height Ld of the N layer 106 of the photoelectric conversion photodiode is required to be at least 2.5 to 3 ⁇ m.
  • a reset gate conductor layer 105 is formed under the N layer 106. Since the reset gate conductor layer 105 can operate normally even when the solid-state imaging device is 0.1 ⁇ m, for example, the reset gate conductor layer 105 is formed in a region near the bottom of the island-shaped semiconductor 100.
  • the reset gate conductor layers 105a, 105b, and 105c are formed independently for each row, the bottoms of the island-shaped semiconductors P11 to P33 having a height of 2.5 to 3 ⁇ m are secured. It is necessary to form the reset gate conductor layers 105a, 105b, and 105c. The formation of the reset gate conductor layers 105a, 105b, and 105c requires fine processing as the degree of pixel integration increases, which makes it difficult to manufacture the solid-state imaging device.
  • FIGS. 10A and 10B are a pixel schematic diagram and an operating potential change diagram of a CMOS (Complementary Metal Oxide semiconductor) solid-state imaging device, respectively.
  • FIG. 10A shows FIG. 1 is a pixel schematic diagram as shown in FIG. In a region A surrounded by a dotted line in FIG. 10A, one pixel is configured.
  • an N region 121 for forming a photodiode in the P region 120 and a P + region 122 are formed on the N region 121.
  • a gate insulating layer 124 is formed on the P region 120, and a transfer electrode ⁇ T is formed on the gate insulating layer 124 so as to be adjacent to the N region 121.
  • N + region 123 is formed on the surface of the P region 120 in a state adjacent to the transfer electrode ⁇ T.
  • the P + region 122 is fixed at the ground potential.
  • the photodiode is formed by a P region 120 and an N region 121.
  • the transfer MOS transistor M1 having the N region 121 as the source, the N + region 123 as the drain, and the transfer electrode ⁇ T as the gate is formed.
  • the source of the reset MOS transistor M2 and the gate of the amplification MOS transistor M3 are connected to the N + region 123, and the drain of the reset MOS transistor M1 and the source of the amplification MOS transistor M3 are connected to the power supply voltage line VDD.
  • the source of the column selection MOS transistor M4 is connected to the drain of the amplification MOS transistor M3, and the drain is connected to the signal line 125.
  • a signal current flows from the power supply voltage line VDD to the signal line 125, and this signal current is read out as a pixel signal. Then, when an ON voltage (high level voltage) is applied to the gate electrode ⁇ R of the reset MOS transistor M2, the signal charge existing in the N + region 123 is removed to the power supply voltage line VDD.
  • FIG. 10B shows a potential distribution change diagram of the photodiode N region 121, the transfer MOS transistor M1, and the reset MOS transistor M2 (see, for example, FIG. 2 of Non-Patent Document 3).
  • FIG. 10B shows a cross-sectional view of the photodiode formed by the P region 120 and the N region 121, the transfer MOS transistor M1 region, and the reset MOS transistor M2 region.
  • An N + region 123 forming a floating diode FD adjacent to the gate electrode Tx of the transfer MOS transistor M1 (corresponding to the transfer electrode ⁇ T in FIG.
  • FIG. 10B (b) shows a potential distribution along the line GG ′ in FIG. 10B during the signal charge accumulation operation.
  • the solid line indicates the bottom of the potential of each region, and the shaded area indicates the charge (in this case, free electrons).
  • An off voltage (low level voltage) is applied to the transfer electrode Tx and the reset electrode RST, and the accumulated signal charge 128 is transferred from the photodiode N region 121 to the N + region 123 and the drain N + region 126 of the reset MOS transistor. It is not transferred.
  • FIG. 10C shows a potential distribution when the signal charge 128 accumulated in the N region 121 of the photodiode is transferred to the N + region 123.
  • This transfer is performed by applying an ON voltage (high level voltage) to the transfer electrode Tx.
  • the accumulated signal charge 128 is transferred from the N region 121 to the N + region 123 through the surface layer of the P region 123 below the transfer electrode Tx.
  • the signal charge 130a in the N region 121 decreases and the signal charge 130c in the N + region 123 increases.
  • the signal charges 130a and 130b are exhausted, the signal charge transfer operation is finished.
  • signal charge 128 is transferred to the N + region 123, the potential of the gate electrode changes the amplification MOS transistor M3 connected to N + region 123, in accordance with the amount of potential change, the signal during the signal charge readout operation
  • the signal current flowing through the line 125 changes and is read out as a signal output.
  • an on-voltage (high level voltage) is applied to the gate electrode RST of the reset MOS transistor M2, and the signal charge 130c of the floating diode N + region 123 is applied. It is removed in the N + region 126 which is the drain of the reset MOS transistor M2. During this signal charge removal operation, the potential of the N + region 123 is reset to the same potential as the potential 131 of the surface layer of the P region 120 below the reset electrode RST.
  • the transfer MOS transistor M1 and the reset MOS transistor M2 are required in the pixel.
  • the presence of the transfer MOS transistor M1 and the reset MOS transistor M2 causes a reduction in pixel integration.
  • 11A shows a cross-sectional structure of one pixel in a CCD solid-state imaging device (see, for example, FIG. 1 of Non-Patent Document 4).
  • a P region well 141 is formed on the N region substrate 140, and an N region 142 is formed on the P region well 141.
  • the P region well 141 and the N region 142 form a photodiode portion.
  • a CCD portion is formed adjacent to the photodiode portion.
  • a P region 144 and an N region 145 which are channels of the CCD unit are formed on the surface of the P region well 141 of the CCD unit.
  • a transfer channel 146 is formed on the surface layer of the P region well 141 between the channel of the CCD unit and the photodiode N region 142 to transfer the signal charge accumulated in the photodiode unit to the N region 145 of the CCD unit channel.
  • An insulating film 147 is formed on the P + region 143, the transfer channel 146, and the N region 145 of the CCD portion channel.
  • a CCD transfer electrode 148 is formed in the insulating film 147 of the CCD portion, and a light shielding metal layer 149 is formed on the CCD transfer electrode 148 so as to cover the CCD portion.
  • a transparent resin microlens 150 is formed above the photodiode portion and the CCD portion.
  • One pixel includes a photodiode portion and a CCD portion shown in FIG. 11A. The pixels are two-dimensionally arranged over the entire pixel area of the CCD solid-state imaging device. An N region substrate 140 and a P region well 141 are continuously formed over the entire pixel region.
  • the above-described operation of transferring the signal charge accumulated in the photodiode portion to the CCD is performed by applying a predetermined voltage to the CCD transfer electrode 148.
  • the signal charge removal operation is performed by removing the signal charge accumulated in the N region 142 by applying a high level voltage to the N region substrate 140 after the signal charge accumulation operation.
  • the timing of the shutter operation can be changed by performing the signal charge accumulation operation and the signal charge removal operation in synchronism with the pixels in the entire pixel region and changing the signal charge accumulation time. This shutter operation is called an electronic shutter.
  • FIG. 11B shows a potential distribution during signal charge removal along the line HH ′ of FIG. 11A (see FIG. 14 of Non-Patent Document 4).
  • the potential distribution 151 a is obtained by applying the low level voltage VRL to the N region substrate 140.
  • the signal charge 152a generated by the light irradiated from the microlens 150 side (in this figure, the signal charge is represented by “e ⁇ ” described in Non-Patent Document 3, and the hatched line in FIG. 10B.
  • Signal charges 128, 130 a, 130 b, and 130 c) are stored in potential wells in the N region 142 and the P region well 141.
  • the potential distribution 152b is obtained by applying the high level voltage VRH to the N region substrate 140, and the potential becomes deeper from the P + region 143 of the ground potential toward the N region substrate 140. As a result, the accumulated signal charge 152 b is removed to the N region substrate 140.
  • the signal charge generated in the potential well becomes effective as a signal, and the signal charge generated in the P region well 141 and the N region substrate 140 below the potential well is applied to the N region substrate 140. Since it is removed, it becomes invalid as a signal.
  • the depth Lph of the potential well is 2.5 to 3 ⁇ m as described in Non-Patent Document 1 because of the required spectral sensitivity characteristics.
  • the applied voltage VRH to the N region substrate 140 is set to 18 to 30V.
  • the height of the island-shaped semiconductor 100 is mainly determined by the height Ld of the N layer 106 of the photodiode.
  • the signal charge generation rate due to light irradiation has a characteristic that decreases along the exponential function curve from the upper surface of the P + layer 121 with respect to the Si depth, and thus contributes to sensitivity in a solid-state imaging device that senses visible light.
  • the depth of the photoelectric conversion region needs to be 2.5 to 3 ⁇ m (see, for example, Non-Patent Document 1).
  • the height Ld of the N layer 106 of the photoelectric conversion photodiode is required to be at least 2.5 to 3 ⁇ m.
  • a reset gate conductor layer 105 is formed under the N layer 106. Since the reset gate conductor layer 105 operates normally even at 0.1 ⁇ m, for example, the reset gate conductor layer 105 is formed almost at the bottom of the island-shaped semiconductor 100. As shown in FIG. 9B, since the reset gate conductor layers 105a, 105b, and 105c are independent for each row, the reset gate is formed at the bottom of the island-shaped semiconductors P11 to P33 having a height of 2.5 to 3 ⁇ m. It is necessary to form the conductor layers 105a, 105b, and 105c. The presence of the reset gate conductor layers 105a, 105b, and 105c makes it difficult to manufacture the solid-state imaging device as the degree of pixel integration increases.
  • a reset MOS transistor M2 is required in the pixel.
  • the presence of the reset MOS transistor M2 reduces the pixel integration degree.
  • the depth Lph of the potential well for accumulating signal charges as shown in FIG. 11B is 2.5 as disclosed in Non-Patent Document 1, because of the required spectral sensitivity characteristics. ⁇ 3 ⁇ m.
  • the potential distribution during the signal charge removal operation requires that a potential barrier be generated in the transfer of the signal charge 151 from the P + region 143 to the N region substrate 140.
  • the applied voltage VRH to the N region substrate 140 needs to be as high as 18 to 30V. This increases the power consumption of the CCD solid-state imaging device.
  • the solid-state imaging device of the present invention is In the solid-state imaging device in which a plurality of pixels are two-dimensionally arranged in the pixel region, A first semiconductor region formed on the substrate; A second semiconductor region formed on the first semiconductor region; A third semiconductor region formed on an upper side surface of the second semiconductor region; A fourth semiconductor region formed on a side surface of the third semiconductor region not facing the side surface of the second semiconductor region, and having a conductivity opposite to the third semiconductor region; A fifth semiconductor region having a conductivity opposite to that of the third semiconductor region on the second semiconductor region;
  • the second semiconductor region is composed of a semiconductor or an intrinsic semiconductor opposite to the third semiconductor region, At least the upper part of the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are formed in an island-shaped semiconductor, A photodiode is formed by the second semiconductor region and the third semiconductor region, A signal charge accumulation operation for accumulating signal charges generated by electromagnetic energy waves incident on the photodiode region in the third semiconductor region is performed, A junction field effect transistor is formed
  • a pixel signal read operation is performed to read a current flowing between the source and drain of the junction field effect transistor as a signal output
  • the fourth semiconductor region and the fifth semiconductor region are set to a low level voltage
  • the first semiconductor region is set to a high level voltage higher than the low level voltage, whereby the first semiconductor region and the first semiconductor region
  • the potential barrier is eliminated in the second semiconductor region existing between the three semiconductor regions, and the signal charge accumulated in the third semiconductor region is passed through the second semiconductor region without the potential barrier.
  • a signal charge removing operation for removing from a third semiconductor region to the first semiconductor region is performed. It is characterized by that.
  • the fourth semiconductor region is connected to the fifth semiconductor region; It is preferable.
  • the third semiconductor region and the fourth semiconductor region are separated from the fifth semiconductor region, and a first conductor layer is formed on the outer periphery of the fourth semiconductor region via an insulating layer.
  • the fourth semiconductor region has a low level voltage lower than the high level voltage, and the A high level voltage is applied to one semiconductor region, and a predetermined voltage for storing the signal charge is applied to the first conductor layer; It is preferable.
  • the first semiconductor region is A sixth semiconductor region serving as a source or drain of the junction field effect transistor, and a seventh semiconductor region for removing signal charges accumulated in the third semiconductor region,
  • the second semiconductor region extends between the sixth semiconductor region and the seventh semiconductor region. It is preferable.
  • a voltage applied to the seventh semiconductor region during a period when the signal charge accumulation operation and the pixel signal readout operation are performed is applied to the seventh semiconductor region during a period when the signal charge removal operation is performed.
  • the pixels are two-dimensionally arranged, and signal currents of pixels arranged in at least one row of the pixels of the two-dimensional arrangement are arranged along a column of pixels arranged in a vertical direction, and the first semiconductor region Are simultaneously read into a row pixel signal capturing circuit provided outside the pixel region via a signal line that connects to each other, and a signal output of pixels arranged in the at least one row is provided in the row pixel signal capturing circuit.
  • the low-level voltage is applied to the pixel selection line connected to the fifth semiconductor region of the pixels arranged in the at least one row during a period in which the operation of reading out from the output circuit is performed and the signal charge removal operation is performed.
  • a high level voltage is applied to the signal line connected to the columns of the pixels, It is preferable.
  • An insulating layer is formed so as to surround the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, and a light shielding conductor layer is formed so as to surround the insulating layer. It is preferable.
  • the light shielding conductor layer is formed on the island-shaped semiconductor side surface of the pixel in the pixel region and continuously formed over the entire pixel region. It is preferable.
  • the light shielding conductor layer is formed on the pixels in the pixel region and continuously formed over the pixel region, and a ground voltage or the low level voltage is applied to the light shielding conductor layer. Configured to, It is preferable.
  • the light shielding conductor layer is connected to the pixels in the pixel region and formed over the entire pixel region, and the light shielding conductor layer has the signal charge removal operation in a period in which the signal charge removal operation is performed. Excluding a period during which the high-level voltage is applied and the signal charge removal operation is performed so as to overlap a part of the period during which the high-level voltage is applied to the signal line or the entire period. In the period, a ground voltage or a low level voltage is applied to the signal line. It is preferable.
  • the light shielding conductor layer is formed so as to surround an insulating layer on the outer periphery of the second semiconductor region, the third semiconductor region, and the fourth semiconductor region, and is separated into at least two independent portions. ing, It is preferable.
  • the light shielding conductor layer is connected to the fifth semiconductor layer; It is preferable.
  • the reset conductor layer is unnecessary, the pixel integration degree is improved, and the manufacture of the solid-state imaging device is facilitated.
  • the reset MOS transistor required in the CMOS solid-state imaging device is not necessary, the pixel integration degree is improved, and the applied voltage in the signal charge removing operation is reduced.
  • FIG. 1 is a pixel cross-sectional structure diagram of a solid-state imaging device according to a first embodiment of the present invention.
  • 2 shows potential distributions during a signal charge accumulation operation and a signal charge removal operation along the line A-A ′ of FIG. 1A of the solid-state imaging device according to the first embodiment.
  • It is a schematic plan view of the solid-state imaging device which concerns on the 2nd Embodiment of this invention.
  • It is a schematic circuit top view of the solid-state imaging device concerning a 2nd embodiment.
  • FIG. 10 is a voltage waveform diagram showing a relationship between a drive voltage waveform applied to pixel selection lines ⁇ p1 to ⁇ p3 and signal lines ⁇ s1 to ⁇ s3 and a voltage waveform at a signal output terminal Vout in the solid-state imaging device according to the second embodiment. It is a pixel cross-section figure of the solid-state imaging device concerning the 3rd Embodiment of this invention. It is a schematic plan view of the solid-state imaging device which concerns on 3rd Embodiment. It is a schematic plan view of the solid-state imaging device which concerns on the 4th Embodiment of this invention.
  • FIG. 10B is a potential distribution change diagram during signal charge signal charge removal operation in a region along the C-C ′ line of the pixel cross-sectional structure diagram of FIG. 3A in the solid-state imaging device according to the fourth embodiment of the present invention. It is a pixel cross-section figure of the solid-state imaging device concerning the 5th Embodiment of this invention.
  • FIG. 1A and 1B show a solid-state imaging device according to the first embodiment.
  • FIG. 1A shows a cross-sectional structure diagram of one pixel of the solid-state imaging device.
  • a signal line N + region 2 is formed on the substrate 1, and an island-shaped semiconductor SP is formed on the signal line N + region 2.
  • a P region 3 is formed on the signal line N + region 2 of the island-shaped semiconductor SP, and an N region 4 is formed on the outer periphery of the P region 3.
  • a P + region 5 is formed on the side surface of the island-shaped semiconductor SP surrounding the N region 4.
  • a P + region 7 connected to the P + region 5 is formed on the upper surface of the island-shaped semiconductor SP.
  • a pixel selection line conductor layer 7 is connected to the P + region 6.
  • An insulating layer 8 is formed so as to surround the signal line N + region 2 and the outer periphery of the island-shaped semiconductor SP.
  • the reset conductor layer 105 required in the conventional solid-state imaging device shown in FIG. 9A does not exist.
  • the P + region 5 formed on the outer periphery of the N region 4 is connected to the P + region 6 of the island-shaped semiconductor SP.
  • a photodiode region is formed from the P region 3 and the N region 4, and when incident light is irradiated from the P + region 6 side of the island-shaped semiconductor SP, signal charges are generated in the photodiode region. (Here, free electrons) are generated. This signal charge is accumulated mainly in the N region 4 of the photodiode region.
  • a junction field effect transistor is formed with the N region 4 as a gate, the P + region 6 as a source, and the P region 3 near the signal line N + region 2 as a drain.
  • FIG. 1B shows the potential distribution during the signal charge accumulation operation and the signal charge removal operation along the line AA ′ in FIG. 1A.
  • FIG. 1B (a) shows an enlarged cross-sectional view along the line AA ′ in FIG. 1A.
  • the N region 4 of the photodiode and the P + region 5 connected to the P + region 6 are formed on one side of the P region 3, and the signal line N + region 2 is formed on the other side.
  • An insulating layer 8 is formed on the P + region 5, the signal line N + region 2, and the P region 3 existing therebetween.
  • FIG. 1B shows a potential distribution 9a during the signal charge accumulation operation.
  • This potential distribution 9a is represented by the potential at the bottom of the conduction band in which free electrons as signal charges exist or move.
  • a potential distribution 9a having a potential well is generated in the N region 4 of the photodiode.
  • the signal charge 10 a generated by light irradiation is accumulated in the potential well and does not move to the signal line N + region 2.
  • FIG. 1B (c) shows a potential distribution 9b during the signal charge removal operation.
  • the P + region 5 is at the ground potential, and the high level voltage Vrh is applied to the signal line N + region 2.
  • a potential distribution 9b in which the potential increases from the N region 4 toward the signal line N + region 2 is formed.
  • the signal charge 10b in the N region 4 is removed to the signal line N + region 2.
  • the potential distribution 9b of the P region 3 between the N region 4 and the signal line N + region 2 is configured so that no potential barrier is generated against the movement of the signal charge (free electrons).
  • FIG. 1B (c) shows a potential distribution 9b during the signal charge removal operation.
  • the photoelectric conversion region composed of the N region 142 and the P region well 141 and the signal charge removal region composed of the P region well 141 and the N region substrate 140 overlap.
  • the photoelectric conversion region is formed from the N region 4 of the photodiode, and the signal charge removal region is P between the N region 4 and the signal line N + region 2. Since the region 3 is formed, the regions where the photoelectric conversion region and the signal charge removal region are formed do not overlap each other. For this reason, the signal charge removal region is composed of the potential distribution 9a (potential well) shown in FIG. 1B (b) during the signal charge accumulation operation by the P region 3 between the N region 4 and the signal line N + region 2. Is formed.
  • the length of the P region 3 between the N region 4 and the signal line N + region 2 can be made as short as possible. Therefore, the applied voltage Vrh to the N + region 2 can be made smaller than that of the CCD solid-state imaging device shown in FIG. 11A, that is, it can be lowered to 3 to 5 V, for example.
  • an increase in power consumption by the solid-state imaging device of the present embodiment is suppressed, and a signal charge removal operation can be performed.
  • the signal charge accumulation operation, the signal charge read operation, and the signal charge removal operation are performed.
  • the P + layer 6 connected to the signal line N + layer 2 and the pixel selection line conductor layer 7 is used.
  • the reset line vertical scanning circuit 112 provided around the pixel region in FIG. 9B becomes unnecessary.
  • the area of the semiconductor substrate forming the solid-state imaging device can be reduced, and the price of the solid-state imaging device can be reduced.
  • the pixel according to the present embodiment does not require a reset MOS transistor that lowers the pixel integration degree like the conventional CMOS solid-state imaging device shown in FIG. 10A.
  • (Second Embodiment) 2A to 2C show a driving method of the solid-state imaging device according to the second embodiment.
  • FIG. 2A shows a schematic plan view of the solid-state imaging device of the present embodiment.
  • the cross-sectional structure along the line BB ′ in the figure corresponds to FIG. 1A.
  • the pixel selection line conductor layers 7a, 7b and 7c (corresponding to 7 in FIG. 1A) are connected to each other in the horizontal direction of the island-shaped semiconductors P11 to P33, and are connected to the pixel selection line vertical scanning circuit 13 around the pixel region. It is connected.
  • Lower portions of the signal line N + layers 2a, 2b, and 2c are connected to the row pixel signal capturing / output circuit 14.
  • the row pixel signal capturing / output circuit 14 simultaneously captures signals in one vertical column of the island-shaped semiconductors P11 to P33.
  • the row pixel signal capturing / output circuit 14 is driven by the horizontal scanning circuit 15 connected thereto, and the output signal of one pixel column of the island-shaped semiconductors P11 to P33 is sequentially supplied to the signal output terminal 17 in the horizontal effective period. Read from.
  • Switch circuits 16a, 16b, and 16c to which the high level voltage Vrh is applied are formed.
  • FIG. 2B shows a schematic circuit plan view of the solid-state imaging device of the present embodiment.
  • the signal lines ⁇ s1, ⁇ s2, and ⁇ s3 are N + layers D11 to D33 (corresponding to the signal line N + layer 2 in FIG. 1A) of each of the island-shaped semiconductors P11 to P33, the row pixel signal capturing / output circuit 14, and a switch. It is connected to the circuits 16a, 16b, 16c.
  • the pixel selection lines ⁇ p1, ⁇ p2, and ⁇ p3 are P + layers S11 to S33 (P in FIG. 1A) of the island-shaped semiconductors P11 to P33.
  • the signal output from the row pixel signal capturing / output circuit 14 is read out from the signal output terminal Vout (corresponding to 17 in FIG. 2A).
  • the island-shaped semiconductors P11 to P33 are driven by drive voltages applied to the pixel selection lines ⁇ p1, ⁇ p2, ⁇ p3 and the signal lines ⁇ s1, ⁇ s2, ⁇ s3.
  • FIG. 2C shows the relationship between the waveform of the drive voltage applied to the pixel selection lines ⁇ p1, ⁇ p2, and ⁇ p3 and the signal lines ⁇ s1, ⁇ s2, and ⁇ s3 and the waveform of the voltage at the signal output terminal Vout.
  • a second horizontal scanning period Th2 is set subsequent to the first horizontal scanning period Th1.
  • the first horizontal scanning period Th1 includes a first invalid blanking period Thb1 and a first valid period The1.
  • pixel signals from the island-shaped semiconductors P11, P12, and P13 connected to the pixel selection line ⁇ p1 are captured by the row pixel signal capturing / output circuit 14.
  • the first invalid blanking period Thb1 is a first pixel signal reading period Tr11 for reading out pixel signals of the pixels P11, P12, P13 (in this period, the accumulated signal charges of the island-shaped semiconductors P11, P12, P13 are island-shaped semiconductors).
  • Tr11, P12, and P13 a signal charge removal period Tre1 that removes the accumulated signal charges of the island-shaped semiconductors P11, P12, and P13 to the signal lines ⁇ s1, ⁇ s2, and ⁇ s3, and the island-shaped semiconductors P11 and P12. , P13, and a second pixel signal readout period Tr12 for reading out the pixel signal after the signal charge removal.
  • a difference signal between the pixel signal of the first pixel signal readout period Tr11 and the pixel signal of the second pixel signal readout period Tr12 is generated by, for example, a correlated double sampling CDS (Correlated double sampling) circuit.
  • CDS Correlated double sampling
  • the high level voltage Vrh is applied to the pixel selection lines ⁇ p2 and ⁇ p3 in the period tph including before and after the period tsh in which the high level voltage Vrh is applied to the signal line ⁇ s1 in the first signal charge removal period Tre1.
  • the same high level voltage Vrh is applied to the signal lines ⁇ s2 and ⁇ s3 in the same period tsh as the signal line ⁇ s1.
  • the pixel selection lines ⁇ p2, ⁇ p3 are at the high level voltage Vrh
  • the signal lines ⁇ s1, ⁇ s2, ⁇ s3 are at the ground potential.
  • the accumulated signal charges of the island-shaped semiconductors P21, P22, P23, P31, P32, and P33 other than the island-shaped semiconductors P11, P12, and P13 are stored in the island-shaped semiconductors P21, P22, P23, P31, P32, and P33.
  • the junction field effect transistor current flows through the signal lines ⁇ s1, ⁇ s2, and ⁇ s3 to the switch circuits 16a, 16b, and 16c that are at the ground potential.
  • the solid-state imaging device according to the third embodiment will be described below with reference to FIGS. 3A and 3B.
  • the solid-state imaging device of the present embodiment reduces leakage of light incident on the island-shaped semiconductors SP, P11, P12, and P13 constituting the pixel to adjacent pixels. There is a feature that can be.
  • FIG. 3A is a pixel cross-sectional structure diagram of the solid-state imaging device of the present embodiment.
  • a signal line N + region 2 is formed at the bottom of the island-shaped semiconductor SP formed on the substrate 1.
  • a P region 3 is formed on the signal line N + region 2, and an N region 4 is formed on the outer periphery of the P region 3.
  • a P + region 5 is formed on the side surface of the island-shaped semiconductor SP so as to surround the N region 4.
  • a P + region 6 is formed on the upper surface of the island-shaped semiconductor SP so as to be connected to the P + region 5.
  • a pixel selection line conductor layer 7 is connected to the P + region 6.
  • An insulating layer 8 is formed so as to surround the signal line N + region 2 and the outer periphery of the island-shaped semiconductor SP.
  • a light shielding conductor layer 18 is formed on the outer periphery of the insulating layer 8 so as to surround the P region 3, the N region 4, and the P + region 5.
  • the light shielding conductor layer 18 surrounds the island-shaped semiconductors P11, P12, P13, P21, P22, P23, P31, P32, and P33 throughout the pixel region, and is formed so as to be connected to each other.
  • FIG. 3B shows a schematic plan view of the solid-state imaging device of the present embodiment.
  • a light shielding conductor layer 18a (corresponding to the light shielding conductor layer 18 in FIG. 3A) that surrounds the island-shaped semiconductors P11 to P33 in the entire pixel region and is connected to the entire pixel region is formed.
  • the light shielding conductor layer 18 does not exist. In this case, it is necessary to prevent light incident from the P + region 6 side of the island-shaped semiconductor SP from leaking to the adjacent island-shaped semiconductor.
  • a light-shielding layer having a gap on the P + region 6 is provided on the island-shaped semiconductor SP, and a microlens formed thereon. It is necessary to optically design the above shape so that incident light does not leak to the adjacent island-shaped semiconductor.
  • such countermeasures by designing and forming the light shielding layer and the microlens cause a reduction in the light collection rate on the island-shaped semiconductor SP.
  • the solid-state imaging device according to the third embodiment can significantly reduce the light leakage to the adjacent island-shaped semiconductor as compared with the solid-state imaging device according to the first embodiment shown in FIG. 1A.
  • the light shielding conductor layer 18a may be formed so as to be connected to each other over the entire pixel region. Fine processing in the pixel region, which is necessary when forming the gate conductor layers 105, 105a, 105b, and 105c in the solid-state imaging device of the example, becomes unnecessary.
  • the solid-state imaging device according to the present embodiment has a feature that the solid-state imaging device can be driven with lower power consumption than the solid-state imaging device according to the third embodiment.
  • FIG. 4A shows a schematic plan view of the solid-state imaging device of the present embodiment.
  • the potential of the light shielding conductor layer 18a is the ground potential.
  • a pulse voltage is applied to the light shielding conductor layer 18a.
  • a pulse voltage source ⁇ n is connected.
  • FIG. 4B shows the relationship between the voltage waveform of the pulse voltage source ⁇ n, the drive voltage waveform applied to the pixel selection lines ⁇ p1, ⁇ p2, and ⁇ p3, the signal lines ⁇ s1, ⁇ s2, and ⁇ s3, and the voltage waveform at the signal output terminal Vout.
  • a high level voltage Vb and a higher level voltage Vrh1 application period is tsh
  • Vrh1 application period is tsh
  • the high level voltage Vrh1 is applied to the pixel selection lines ⁇ p2 and ⁇ p3, and the same high level voltage Vrh1 is applied to the signal lines ⁇ s2 and ⁇ s3 in the same period tsh as the signal line ⁇ s1.
  • the pulse voltage source ⁇ n voltage is at the high level voltage Va during the period tph applied to the pixel selection lines ⁇ p2 and ⁇ p3 in the first invalid blanking period Thb1. In the second invalid blanking period Thb2, the same operation is repeated.
  • FIGS. 4A to 4D show changes in the potential distribution during the signal charge signal charge removal operation in the region along the line CC ′ of the pixel cross-sectional structure shown in FIG. 3A.
  • FIG. 4C is an enlarged view of a region along the line CC ′ in FIG. 3A.
  • a photodiode N region 4 and a P + region 5 connected to the P + region 6 exist on one side of the P region 3, and a signal line N + region 2 exists on the other side.
  • An insulating layer 8 is formed on the surfaces of the P + region 5, the P region 3, and the signal line N + region 2. Further, a light shielding conductor layer 18 a is formed on the insulating layer 8.
  • FIG. 4C (b) shows the potential distribution 20 during the signal charge accumulation operation.
  • the potentials of the P + region 5, the signal line N + region 2, and the light shielding conductor layer 18a are the ground potential.
  • a large number of free electrons exist in the signal line N + region 2.
  • a potential distribution 20 having a potential well is generated in the N region 4 of the photodiode.
  • the signal charge 21 a generated by light irradiation is accumulated in the potential well and does not move to the signal line N + region 2.
  • FIG. 4C (c) shows potential distributions 22a and 22b in the first invalid blanking period Thb1.
  • a solid line represents the potential distribution 22a in the first signal charge removal period Tre1 in which the pulse voltage source ⁇ n voltage is the high level voltage Va and the signal lines ⁇ s1, ⁇ s2, and ⁇ s3 are the low level voltage Vb.
  • the potential distribution 22b when the voltage of the pulse voltage source ⁇ n, the pixel selection lines ⁇ p1, ⁇ p2, ⁇ p3, and the signal lines ⁇ s1, ⁇ s2, ⁇ s3 are all at the ground potential is indicated by dotted lines (third embodiment). Corresponding to).
  • the potential between the photodiode N region 4 and the signal line N + region 2 is as shown in the potential distribution 22a. This is higher than the potential distribution 22b when the layer 18a is at the ground potential.
  • the solid line shows the potential distribution 23a in the signal charge removal period tsh in which the high level voltage Vrh1 is applied to the signal lines ⁇ s1, ⁇ s2, and ⁇ s3.
  • the potential distribution 23b when the pulse voltage source ⁇ n voltage is set to the ground potential and the high level voltage Vrh is applied to the signal lines ⁇ s1, ⁇ s2, and ⁇ s3 is indicated by a dotted line (corresponding to the third embodiment). .
  • the potential distribution 23b indicated by the dotted line changes to the potential distribution 23a indicated by the solid line, and the accumulated signal charge 21b is removed in the signal line N + region 2.
  • Such a reduction in voltage of 1 V greatly contributes to a reduction in driving power consumption of the solid-state imaging device at a driving voltage of 3 to 5 V in the signal line N + region 2. Then, the driving voltage of the solid-state imaging device is reduced, and the power consumption of the solid-state imaging device of the present embodiment is further promoted.
  • 4B includes the period tsh before and after the period tsh in which the high level voltage Vrh1 is applied to the signal lines ⁇ s1, ⁇ s2, and ⁇ s3, and the same period tph in which the high level voltage Vrh1 is applied to the pixel selection lines ⁇ p2 and ⁇ p3.
  • the potential distribution 23a shown in (d) of FIG. 4C is realized if Va is applied to the light shielding conductor layer 18a and the high level voltage Vrh1 is applied to the signal line N + region 2.
  • the low level voltage Vb is applied to the signal lines ⁇ s1, ⁇ p2, and ⁇ p3.
  • the signal lines ⁇ s1, ⁇ s2, and ⁇ s3 are at the ground potential during the period other than the period tph, but the low level voltage Vb may be applied.
  • the low level voltage Vb In the period in which the low level voltage Vb is applied, a potential distribution in which the signal charge 21a shown in FIG. 4C (b) is accumulated in the potential well is obtained. For this reason, the voltage Vrh1 applied to the signal lines ⁇ s1, ⁇ s2, and ⁇ s3 in the first signal charge removal period Tre1 is reduced.
  • the solid-state imaging device according to the fifth embodiment will be described below with reference to FIGS. 5A and 5B.
  • the solid-state imaging device of the present embodiment is characterized in that a more reliable signal charge removal operation and higher speed driving are realized as compared with the solid-state imaging device of the fourth embodiment.
  • FIG. 5A shows a pixel cross-sectional structure diagram of the solid-state imaging device of the present embodiment.
  • a signal line N + region 2 is formed on the substrate 1, and an island-shaped semiconductor SP is formed on the signal line N + region 2.
  • a P region 3 is formed on the signal line N + region 2 of the island-shaped semiconductor SP, and an N region 4 is formed on the outer periphery of the P region 3.
  • a P + region 5 is formed on the side surface of the island-shaped semiconductor SP so as to surround the N region 4.
  • An insulating layer 8 is formed on the outer periphery of the island-shaped semiconductor SP so as to surround the P + region 5, the P region 3, and the signal line N + region 2.
  • a P + region 6 is formed on the upper surface of the island-shaped semiconductor SP so as to be connected to the P + region 5.
  • a pixel selection line conductor layer 7 is connected to the P + region 6.
  • a first light shielding conductor layer 25a is formed surrounding the insulating layer 8 formed in the P region 3 between the N region 4 and the signal line N + region 2.
  • a second light shielding conductor layer 25b is formed surrounding the insulating layer 8 formed on the outer periphery of the N region 4 and the P + region 5.
  • the second light shielding conductor layer 25 b is separated from the pixel selection line conductor layer 7.
  • Each of the first light shielding conductor layer 25a and the second light shielding conductor layer 25b is connected to each other over the entire pixel region.
  • FIG. 5B shows a schematic plan view of the solid-state imaging device of the present embodiment.
  • a cross-sectional structure taken along line E-E 'in FIG. 5B corresponds to FIG. 5A.
  • the first light shielding conductor layer 25a surrounds the island-shaped semiconductors P11 to P33 in the pixel region, and is formed so as to be connected to each other over the entire pixel region.
  • a pulse voltage source ⁇ n is connected to the first light shielding conductor layer 25a.
  • a second light shielding conductor layer 25b is formed so as to surround the island-shaped semiconductors P11 to P33 in the pixel region and to be connected to each other over the entire pixel region.
  • a ground potential is applied to the second light shielding conductor layer 25a.
  • a voltage having the same waveform as the voltage applied to the pulse power supply ⁇ n shown in FIG. 4B is applied to the first light shielding conductor layer 25a.
  • the first light shielding conductor layer 25a and the second light shielding conductor layer 25b may be formed so as to be connected to the entire pixel region.
  • fine processing in the pixel region necessary for forming the gate conductor layers 105, 105a, 105b, and 105c in the conventional solid-state imaging device shown in FIGS. 9A and 9B is unnecessary. It becomes.
  • the first light shielding conductor layer 25a and the second light shielding conductor layer 25b are separated, and the load capacity of the pulse voltage power supply ⁇ n during the signal charge removal operation is
  • the capacitance is connected to the first light shielding conductor layer 25a.
  • This load capacity is mainly a capacity due to the insulating layer 8 between the first light shielding conductor layer 25 a and the P region 3.
  • the height of the island-shaped semiconductors SP and P11 to P33 constituting the pixel is determined mainly by the height Ld of the N region 4 of the photodiode from the required spectral sensitivity characteristics.
  • a second light shielding conductor layer 25 b is formed so as to surround this N region 4.
  • the load capacity of the pulse voltage power supply ⁇ n during the signal charge removal operation is significantly reduced as compared with the solid-state imaging device of the fourth embodiment shown in FIG. 4A.
  • reliable signal charge removal operation is realized.
  • the present embodiment contributes to speeding up of such a solid-state imaging device.
  • the pixel selection line conductor layer 7 in the first embodiment shown in FIG. 1A is also used as a light shielding conductor layer, so that the light incident on the island-shaped semiconductors P11 to P33 constituting the pixel is transferred to adjacent pixels. There is a feature that can reduce leakage.
  • FIG. 6A shows a pixel cross-sectional structure diagram of the solid-state imaging device of the present embodiment.
  • a signal line N + region 2 is formed at the bottom of the island-shaped semiconductor SP formed on the substrate 1.
  • a P region 3 is formed on the signal line N + region 2, and an N region 4 is formed on the outer periphery of the P region 3.
  • a P + region 5 is formed on the side surface of the island-shaped semiconductor SP so as to surround the N region 4.
  • a P + region 6 is formed on the upper surface of the island-shaped semiconductor SP so as to be connected to the P + region 5.
  • An insulating layer 8 is formed so as to surround the signal line N + region 2 and the outer periphery of the island-shaped semiconductor SP.
  • a light shielding pixel selection line conductor layer 26 is formed on the outer peripheral portion of the insulating layer 8, surrounding the P region 3, the N region 4, and the P + region 5 and connected to the P + region 6.
  • the pixel selection line conductor layer 26 has both a function as a pixel selection line and a function of preventing light leakage to an adjacent island-shaped semiconductor.
  • FIG. 6B shows a schematic plan view of the solid-state imaging device of the present embodiment.
  • a pixel cross-sectional structure taken along line F-F ′ in FIG. 6B corresponds to FIG. 6A.
  • the pixel selection line conductor layers 7a, 7b, 7c in the schematic plan view of the solid-state imaging device of the second embodiment shown in FIG. 2A are replaced with the light shielding pixel selection line conductor layers 26a, 26b, 26c in the schematic plan view of FIG. 6B. has been edited.
  • the other configuration shown in FIG. 6B is the same as FIG. 2A.
  • the pixel selection line conductor layers 26a, 26b, and 26c have both functions. Thereby, manufacture of a solid-state imaging device is facilitated.
  • This embodiment can also be applied to the case where the second light shielding conductor layer 25b and the pixel selection line conductor layer 7 in the fifth embodiment shown in FIG. 5A are integrated.
  • the bottom of the light shielding pixel selection line conductor layer 26 is formed so as to be positioned at the upper end of the signal line N + region 2 of the island-shaped semiconductor SP constituting the pixel. It may be located above or below the upper end of the + region 2.
  • FIG. 7A shows a cross-sectional structure of the first solid-state imaging device of the seventh embodiment.
  • a band-shaped semiconductor 27 including a signal line P + region 28, a P region 3, and a signal charge removal N + region 29 is formed on the substrate 1.
  • An island-shaped semiconductor SP is formed on the band-shaped semiconductor 27.
  • the P region 3 is formed so as to be connected to the island-shaped semiconductor SP on the band-shaped semiconductor 27.
  • An N region 4 is formed on the outer periphery of the P region 3.
  • a P + region 5 is formed on the side surface of the island-shaped semiconductor SP so as to surround the N region 4.
  • a P + region 7 connected to the P + region 5 is formed on the upper surface of the island-shaped semiconductor SP.
  • a pixel selection line conductor layer 7 is connected to the P + region 6.
  • An insulating layer 8 is formed so as to surround the signal line N + region 2 and the outer periphery of the island-shaped semiconductor SP.
  • a photodiode region including a P region 3 and an N region 4 is formed.
  • signal charges here, free electrons
  • This signal charge is accumulated mainly in the N region 4 of the photodiode region.
  • a junction field effect transistor is formed with the N region 4 as a gate, the P + region 6 as a source, and the signal line P + region 28 as a drain.
  • the signal line N + region 2 has a function of extracting a drain-source current (output signal) of the junction field effect transistor and a function of removing signal charges.
  • the signal line N + region 2 instead of the signal line N + region 2, the signal line P + region 28, the P region 3, and the signal charge removal N + region 29 are formed. Then, the drain-source current (output signal) of the junction field effect transistor is taken out by the signal line P + region 28, and the signal charge removal N + region 29 is executed.
  • the drain-source voltage of the junction field effect transistor for starting to flow the drain-source current of the junction field effect transistor is a diode formed by the signal line N + region and the P region 3.
  • the signal line is reduced to near 0 V by using the P + region 28 as a voltage required for forward biasing of the semiconductor layer. be able to.
  • the driving voltage By reducing the driving voltage, the driving power consumption of the solid-state imaging device is reduced.
  • a high applied to the signal charge removed N + region 29 in the signal charge removal period tsh By applying a low level voltage lower than the level voltage Vph, excess signal charges generated by light incident on the island-shaped semiconductor SP with excessive illuminance are removed by the signal charge removal N + region 29. Can do.
  • FIG. 7B shows a cross-sectional structure of the second solid-state imaging device of the present embodiment.
  • the signal line P + region 28 in FIG. 7A is the signal line N + region 30.
  • Other configurations are the same as those in FIG. 7A.
  • the signal line N + region 2 instead of the signal line N + region 2, the signal line N + region 30, the P region 3, and the signal charge removal N + region 29 are formed, and the drain-source current (output signal) of the junction field effect transistor is formed. ) Is taken out by the signal line N + region 30 and the signal charge removing operation is executed by the signal charge removing N + region 29.
  • the solid-state imaging device of this embodiment does not have the advantage that it can be driven with low power consumption unlike the solid-state imaging device shown in FIG. 7A, but the signal line N + region 30 compared to the solid-state imaging device shown in FIG. 1A.
  • the signal charge removal N + region 29 is maintained at a predetermined voltage even during a period in which the signal current is read from the signal current, and excess signal charge generated by excessive light irradiation can be removed from the signal charge removal N + region 29.
  • FIG. 8 shows a cross-sectional structure of the solid-state imaging device of the present embodiment.
  • a signal line N + region 2 is formed.
  • an island-shaped semiconductor SP constituting a pixel is formed.
  • a P region 3 is formed on the signal line N + region 2 of the island-shaped semiconductor SP, and an N region 4 a is formed on the outer periphery of the P region 3.
  • a P + region 5a is formed on the side surface of the island-shaped semiconductor SP so as to surround the N region 4a.
  • An insulating layer 8 is formed so as to surround the signal line N + region 2 and the outer periphery of the island-shaped semiconductor SP.
  • a conductor layer 31 is formed on the outer periphery of the N region 4a and the P + region 5a with the insulating layer 8 interposed therebetween.
  • a P + region 7 is formed on the upper surface of the island-shaped semiconductor SP so as to be separated from the N region 4 a and the P + region 5 a.
  • a pixel selection line conductor layer 7 is connected to the P + region 6.
  • the conductor layer 31 is formed away from the pixel selection line conductor layer 7.
  • the voltage at which holes are accumulated is applied to the conductor layer 31 after the P + region 5 a on the outer peripheral portion of the island-shaped semiconductor SP becomes a low level voltage. Apply. Then, the ground voltage to the P + region 6, the high-level voltage is applied to the signal line N + region 2, to remove the signal charge accumulated in the N region 4a to the signal line N + region 2. As described above, even by applying a voltage to the conductor layer 31, the signal charge accumulated in the N region 4a is removed to the signal line N + region 2 as in the solid-state imaging device shown in FIG. 1A.
  • the conductor layer 31 has a function of a light shielding conductor layer that prevents light incident on the island-shaped semiconductor SP from leaking to the adjacent island-shaped semiconductor.
  • the signal line N + region 2 is provided as shown in FIG. 1A.
  • the N + region is the P + region
  • the P region 3 is the N region
  • the N region 4 is the P region.
  • the signal line N + region 2 is formed on the substrate 1.
  • the substrate 1 may be an insulating layer or a semiconductor layer as long as it is a material layer that can execute the operation of the solid-state imaging device in each of the above embodiments. This aspect can be applied in common to the above embodiments.
  • a transparent conductor material such as indium tin (InSnO) may be used to connect to the P + region 7 from the upper surface of the island-shaped semiconductor SP. This aspect can be applied in common to the above embodiments.
  • the driving method shown in FIG. 2C for explaining the second embodiment can be commonly applied to the embodiments according to the present invention after the second embodiment.
  • the signal line semiconductor regions 28 and 30 and the signal charge removal N + region 29 are separated as in the seventh embodiment shown in FIGS. 7A and 7B, the signal lines ⁇ s1, ⁇ s2, and FIG.
  • the voltage waveform applied to ⁇ s 3 is applied to the signal charge removal N + region 29.
  • a structure in which a metal layer or a silicide layer is provided between the substrate 1 and the signal line N + layer region 2 to reduce the resistance value of the signal line N + region can be employed. This aspect can be similarly applied to the above embodiments.
  • the P region 2 may be composed of an intrinsic semiconductor layer.
  • This genuine semiconductor is a semiconductor substantially composed of one kind of element.
  • An authentic semiconductor is manufactured so that impurities are not mixed therein, but actually includes an extremely small amount of impurities.
  • the P region 2 made of a genuine semiconductor may contain a very small amount of acceptor or donor impurities as long as the function as a solid-state imaging device is not hindered. This aspect can be applied in common to the above embodiments.
  • the solid-state imaging device in which the N + region 2 is a signal line and the pixel selection line is connected to the P + region 6 is shown.
  • the N + region is a pixel selection line and the P + region 6. May be connected to the signal line.
  • the N region 4 and the P + region 6 are in contact with each other.
  • the present invention is not limited to this, and the same effect can be obtained even if the N region 4 and the P + region 6 are separated.
  • a solid-state imaging device having one pixel or a 3 ⁇ 3 pixel configuration is used.
  • the technical idea of the present invention is also applied to a solid-state imaging device in which pixels are arranged one-dimensionally or two-dimensionally. Needless to say, it can be applied.
  • the pixel arrangement is preferably linear, zigzag, etc. if it is a one-dimensional pixel arrangement, and if it is a two-dimensional pixel arrangement, it is a linear grid, honeycomb, etc. However, it is not limited to each.
  • the shape of the island-shaped semiconductors SP and P11 to P33 according to each of the above embodiments can be a cylinder, a hexagon, or other shapes.
  • the operation shown by the voltage waveform shown in FIG. 2C is for the solid-state imaging device having the cross-sectional structure shown in FIG. 1A, but the signal lines N + region 2, P + region 5 and P + region 6 as shown in FIG. Any solid-state imaging device whose potential relationship can be obtained in the signal charge removal period can be applied to each of the above embodiments.
  • the present invention is not limited to this. Even when a low level voltage close to the ground voltage is applied, the same effects as those of the above embodiments can be obtained.
  • a solid-state imaging device that generates a signal charge in a pixel by light irradiation.
  • electromagnetic energy such as visible light, ultraviolet light, infrared light, X-rays, other electromagnetic rays, radiation, and electron beams is used. It goes without saying that the technical idea of the present invention can also be applied to other semiconductor devices in which signal charges are generated in pixels by wave irradiation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

L'appareil de capture d'image à l'état solide selon l'invention a une pluralité de pixels disposés dans un état bidimensionnel dans une zone de pixels. Chacun des pixels est formé sur un semi-conducteur en forme d'îlot dans une zone de pixels. Dans le semi-conducteur en forme d'îlot, une zone de type N+ de ligne de signal (2) et une zone de type P (3) sont formées dans cet ordre depuis la partie inférieure, et sur la surface latérale d'une partie supérieure de la zone de type P (3), une zone de type N (4) et une zone de type P+ (5) sont formées dans cet ordre depuis la partie intérieure du semi-conducteur en forme d'îlot. Sur la zone de type P (3), une zone de type P+ (6) est formée. Des charges de signal accumulées dans la zone de type N (4) sont retirées vers la zone de type N+ de ligne de signal (2) à travers la zone de type P (3) en ayant la zone de type P+ (5) et la zone de type P+ (6) à une tension de bas niveau, et la zone de type N+ de ligne de signal (2) à une tension de haut niveau qui est supérieure à la tension de bas niveau.
PCT/JP2012/053995 2012-02-20 2012-02-20 Appareil de capture d'image à l'état solide WO2013124956A1 (fr)

Priority Applications (5)

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JP2013537989A JP5547853B2 (ja) 2012-02-20 2012-02-20 固体撮像装置
KR1020137021916A KR20130121947A (ko) 2012-02-20 2012-02-20 고체 촬상 장치
PCT/JP2012/053995 WO2013124956A1 (fr) 2012-02-20 2012-02-20 Appareil de capture d'image à l'état solide
CN2012800096431A CN103384916A (zh) 2012-02-20 2012-02-20 固体摄像器件
TW102105499A TW201336062A (zh) 2012-02-20 2013-02-18 固體攝像裝置

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PCT/JP2012/053995 WO2013124956A1 (fr) 2012-02-20 2012-02-20 Appareil de capture d'image à l'état solide

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WO2018167567A1 (fr) * 2017-03-17 2018-09-20 ActLight SA Systèmes photo-détecteurs et leurs procédés de fabrication
US10269855B2 (en) 2013-03-15 2019-04-23 ActLight SA Photo detector systems and methods of operating same
US10964837B2 (en) 2013-03-15 2021-03-30 ActLight SA Photo detector systems and methods of operating same
US11251217B2 (en) 2019-04-17 2022-02-15 ActLight SA Photodetector sensor arrays
US11587960B2 (en) 2013-03-15 2023-02-21 ActLight SA Photodetector
US11837669B2 (en) 2013-03-15 2023-12-05 ActLight SA Photo detector systems and methods of operating same

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KR102190108B1 (ko) 2014-12-31 2020-12-11 에스에프씨주식회사 고효율과 장수명을 갖는 유기 발광 소자
KR101974860B1 (ko) 2015-02-04 2019-09-05 에스에프씨주식회사 저전압구동이 가능하며 장수명을 갖는 유기 발광 소자
KR101969415B1 (ko) 2015-02-23 2019-08-13 에스에프씨주식회사 저전압구동이 가능하며 고효율을 갖는 유기 발광 소자

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269855B2 (en) 2013-03-15 2019-04-23 ActLight SA Photo detector systems and methods of operating same
US10964837B2 (en) 2013-03-15 2021-03-30 ActLight SA Photo detector systems and methods of operating same
US11587960B2 (en) 2013-03-15 2023-02-21 ActLight SA Photodetector
US11837669B2 (en) 2013-03-15 2023-12-05 ActLight SA Photo detector systems and methods of operating same
WO2018167567A1 (fr) * 2017-03-17 2018-09-20 ActLight SA Systèmes photo-détecteurs et leurs procédés de fabrication
EP4283684A3 (fr) * 2017-03-17 2024-02-14 Actlight S.A. Systèmes de photo-détecteur et leurs procédés de fonctionnement
US11251217B2 (en) 2019-04-17 2022-02-15 ActLight SA Photodetector sensor arrays

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JP5547853B2 (ja) 2014-07-16
KR20130121947A (ko) 2013-11-06
JPWO2013124956A1 (ja) 2015-05-21
CN103384916A (zh) 2013-11-06

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