WO2013123795A1 - 一种像素单元驱动电路和方法、像素单元以及显示装置 - Google Patents

一种像素单元驱动电路和方法、像素单元以及显示装置 Download PDF

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Publication number
WO2013123795A1
WO2013123795A1 PCT/CN2012/086019 CN2012086019W WO2013123795A1 WO 2013123795 A1 WO2013123795 A1 WO 2013123795A1 CN 2012086019 W CN2012086019 W CN 2012086019W WO 2013123795 A1 WO2013123795 A1 WO 2013123795A1
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Prior art keywords
film transistor
thin film
driving
gate
storage capacitor
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Ceased
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PCT/CN2012/086019
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English (en)
French (fr)
Inventor
祁小敬
青海刚
李天马
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US13/993,637 priority Critical patent/US9355595B2/en
Publication of WO2013123795A1 publication Critical patent/WO2013123795A1/zh
Anticipated expiration legal-status Critical
Priority to US15/141,166 priority patent/US9852693B2/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/60—Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a pixel unit driving circuit and method, a pixel unit, and a display device. Background technique
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the ability to emit light is driven by the current generated when the driving TFT is saturated. Because the same gray voltage is input, different threshold voltages will generate different drive currents, resulting in current inconsistency.
  • the uniformity of Vth (transistor threshold voltage) on the LTPS (low temperature polysilicon) process is very poor, and Vth also drifts, so the brightness uniformity of the conventional 2T1C pixel unit drive circuit has been poor.
  • the conventional 2T1C pixel unit driving circuit is shown in Figure 1.
  • the circuit contains only two TFTs, T1 is used as a switch, and DTFT is used for pixel driving.
  • the conventional 2T1C pixel unit driving circuit is also relatively simple to operate.
  • the control timing diagram of the 2T1C pixel unit driving circuit is as shown in FIG. 2. When the scanning level Vscan on the scanning line Scan is low, T1 is turned on, and the data line Data is on the data line Data. The gray scale voltage Vdata charges the capacitor C. When the scan level Vscan is high, T1 is turned off, and the capacitor C is used to store the gray scale voltage.
  • VDD the output voltage of the high-level output of the driving power supply
  • ) 2 K(VDD - Vdata-1 Vth
  • Vdata is the data voltage output by the data line Data
  • K is a constant related to the transistor size and carrier mobility.
  • K is determined.
  • the driving current formula of the 2T1C circuit includes Vth.
  • Vth of the TFTs at different positions of the fabricated panel is greatly different, resulting in the same gray.
  • the driving current of the OLED is different under the step voltage, so the brightness of the panel at different positions of the driving scheme will be different, and the brightness uniformity is poor. Summary of the invention
  • the invention provides a pixel unit driving circuit and method, a pixel unit and a display device to improve the uniformity of brightness of the OLED panel.
  • the present invention provides a pixel unit driving circuit for driving an OLED, including a driving thin film transistor, a matching thin film transistor, a signal clearing thin film transistor, a charging control unit, a driving control unit, and a storage capacitor, wherein
  • a gate of the driving thin film transistor is connected to the first end of the storage capacitor and connected to a low level output end of the driving power source through the charging control unit, and a source and a low level output end of the driving power source Connecting, the drain is connected to the cathode of the OLED;
  • the gate and the drain of the matching thin film transistor are connected to the data line through the charging control unit, and the source is connected to the second end of the storage capacitor;
  • a gate and a drain of the signal clearing thin film transistor are connected to a second end of the storage capacitor; a source of the signal clearing thin film transistor is connected to a gate and a drain of the matching thin film transistor, and passes through
  • the charging control unit is connected to the data line;
  • the second end of the storage capacitor is connected to the high-level output end of the driving power source through the driving control unit;
  • the driving thin film transistor, the matching thin film transistor, and the signal removing thin film transistor are n-type TFTs.
  • the charge control unit includes a first thin film transistor and a second thin film transistor, and the drive control unit includes a third thin film transistor;
  • a gate of the driving thin film transistor is connected to a low level output end of the driving power source through the second thin film transistor;
  • the second end of the storage capacitor is connected to the high level output terminal of the driving power source through the third thin film transistor.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor are n-type TFTs;
  • a gate of the first thin film transistor is connected to the first control line, and a drain is connected to the data line; a source of the first thin film transistor is respectively connected to a gate, a drain and a gate of the matching thin film transistor a source connection of the signal clearing thin film transistor;
  • a gate of the second thin film transistor is connected to the first control line, a source thereof is connected to a low level output end of the driving power source, and a drain is connected to a gate of the driving thin film transistor;
  • a gate of the third thin film transistor is connected to a second control line, a source thereof and the storage capacitor The second end is connected, and the drain is connected to the high level output of the driving power source.
  • the present invention further provides a pixel unit driving method, which is applied to the above pixel unit driving circuit, and the pixel unit driving method includes the following steps:
  • Controlling the charge control unit causes the signal clearing thin film transistor to be turned on, and the storage capacitor discharges the data line through the signal clearing thin film transistor until the voltage of the second end of the storage capacitor is lowered such that the signal clearing film transistor is turned off, and the charging control is controlled
  • the unit causes the gate of the driving thin film transistor to be pulled down to the voltage VSS outputted by the low level output terminal of the driving power source;
  • the present invention further provides a pixel unit, comprising: an OLED and the pixel unit driving circuit, wherein a cathode of the OLED is connected to a drain of a driving thin film transistor in the pixel unit driving circuit, The anode of the OLED is connected to the high level output of the driving power supply.
  • the present invention also provides a display device comprising the above pixel unit.
  • the present invention further provides a pixel unit driving circuit for driving an OLED, including a driving thin film transistor, a matching thin film transistor, a signal clearing thin film transistor, a charging control unit, a driving control unit, and a storage capacitor, wherein
  • a gate of the driving thin film transistor is connected to a first end of the storage capacitor and connected to a high level output end of the driving power source through the charging control unit, and a source and a high level output end of the driving power source Connecting, the drain is connected to the anode of the OLED;
  • a gate and a source of the matching thin film transistor are connected to the data line through the charging control unit, and a drain thereof is connected to the second end of the storage capacitor;
  • a gate and a source of the signal clearing thin film transistor are connected to a second end of the storage capacitor; the signal clears a drain of the thin film transistor, is connected to a gate and a source of the matching thin film transistor, and passes through
  • the charging control unit is connected to the data line;
  • a second end of the storage capacitor passes through the driving control unit and a low level of the driving power source Output connection;
  • the driving thin film transistor, the matching thin film transistor, and the signal removing thin film transistor are p-type TFTs.
  • the charge control unit includes a first thin film transistor and a second thin film transistor, and the drive control unit includes a third thin film transistor;
  • a gate of the driving thin film transistor is connected to a high level output terminal of the driving power source through the second thin film transistor;
  • the second end of the storage capacitor is connected to the low level output of the driving power source through the third thin film transistor.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor are p-type TFTs
  • the gate of the first thin film transistor is connected to the first control line, and the source thereof is connected to the data line;
  • a drain of the first thin film transistor is respectively connected to a gate of the matching thin film transistor, a source, and a drain of the signal clearing thin film transistor;
  • a gate of the second thin film transistor is connected to the first control line, a source thereof is connected to a high level output end of the driving power source, and a drain is connected to a gate of the driving thin film transistor;
  • the gate of the third thin film transistor is connected to the second control line, the source thereof is connected to the second end of the storage capacitor, and the drain is connected to the low level output end of the driving power source.
  • the present invention further provides a pixel unit driving method, which is applied to a pixel unit driving circuit as described above, wherein the pixel unit driving method includes the following steps: controlling a charging control unit to cause a signal clearing thin film transistor to be turned on, And the data line charges the storage capacitor through the signal clearing thin film transistor until the voltage of the second end of the storage capacitor rises to cause the signal clearing film transistor to be turned off, and controls the charging control unit to cause the gate of the driving thin film transistor to be pulled up The voltage VDD output to the high level output of the driving power supply;
  • the present invention also provides a pixel unit including an OLED and the pixel unit driving circuit described above, the anode of the OLED and the drain of the driving thin film transistor in the pixel unit driving circuit.
  • the invention further provides a display device , including the above pixel unit.
  • the pixel unit driving circuit and method, the pixel unit and the display device of the present invention compensate the threshold voltage of the OLED driving tube by using the principle that the TFTs of the same design in the same pixel are matched. Improved brightness non-uniformity of the OLED panel.
  • 1 is a circuit diagram of a conventional 2T1C pixel unit driving circuit
  • 2 is a control timing chart of the conventional 2T1C pixel unit driving circuit
  • FIG. 3 is a circuit diagram of a pixel unit driving circuit according to a first embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a pixel unit driving circuit according to a second embodiment of the present invention.
  • FIG. 5 is a circuit diagram of a pixel unit driving circuit according to a third embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a pixel unit driving circuit according to a fourth embodiment of the present invention.
  • FIG. 7 is a circuit diagram of a pixel unit driving circuit according to a fifth embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a pixel unit driving circuit according to a sixth embodiment of the present invention.
  • 9A is an equivalent circuit diagram of a pixel unit driving circuit in a first period of time when the third embodiment of the present invention operates;
  • 9B is an equivalent circuit diagram of the pixel unit driving circuit in the second period of time when the third embodiment of the present invention operates;
  • 9C is an equivalent circuit diagram of the pixel unit driving circuit in the third period of time when the third embodiment of the present invention operates;
  • FIG. 10 is a timing chart of the first control signal S1, the data line Data output signal, and the second control signal S2 during operation of the pixel unit driving circuit according to the third embodiment of the present invention
  • FIG. 11 is a timing chart of the first control signal S1, the signal output from the data line Data, and the second control signal S2 during operation of the pixel unit driving circuit according to the sixth embodiment of the present invention. detailed description
  • the pixel unit driving circuit is configured to drive an OLED, including a driving thin film transistor DTFT, a matching thin film transistor MTFT, a signal clearing thin film transistor ETFT, a charging control unit 31, and a driving control unit. And a storage capacitor Cs, wherein a gate of the driving thin film transistor DTFT is connected to a first end of the storage capacitor Cs, and is further connected to a low-level output end of the driving power source by the charging control unit 31;
  • the source of the driving thin film transistor DTFT is connected to a low level output terminal of the driving power source, and the drain electrode is connected to the cathode of the OLED;
  • the gate and the drain of the matching thin film transistor MTFT are connected to the data line Data through the charging control unit 31, and the source is connected to the second end of the storage capacitor Cs;
  • a gate and a drain of the signal clearing thin film transistor ETFT are connected to a second end of the storage capacitor Cs;
  • a source of the signal clearing thin film transistor ETFT is connected to a gate and a drain of the matching thin film transistor MTFT, and is connected to the data line Data through the charging control unit 31;
  • the second end of the storage capacitor Cs is connected to the high-level output terminal of the driving power source through the driving control unit 32;
  • the anode of the OLED is connected to a high level output end of the driving power source
  • the driving thin film transistor DTFT, the matching thin film transistor MTFT and the signal clearing thin film transistor ETFT are n-type TFTs; the output voltage of the high-level output terminal of the driving power source is VDD, and the low-level output of the driving power source The output voltage of the terminal is VSS.
  • FIG. 4 a circuit diagram of a pixel unit driving circuit according to a second embodiment of the present invention.
  • the pixel unit driving circuit according to the second embodiment of the present invention is based on the pixel unit driving circuit of the first embodiment of the present invention.
  • the charging control unit 31 includes a first thin film transistor T1 and a second thin film transistor T2, and the driving control unit 32 includes a third thin film transistor T3 ;
  • a second end of the storage capacitor Cs passes through the third thin film transistor T3 and the driving power source The high level output is connected.
  • FIG. 5 a circuit diagram of a pixel unit driving circuit according to a third embodiment of the present invention.
  • the pixel unit drive circuit according to the third embodiment of the present invention is based on the pixel unit drive circuit of the second embodiment of the present invention.
  • the first thin film transistor In the pixel unit driving circuit according to the third embodiment of the present invention, the first thin film transistor
  • the second thin film transistor T2 and the third thin film transistor T3 are n-type TFTs;
  • the gate of the first thin film transistor T1 is connected to the first control line outputting the first control signal S1, and the drain thereof is connected to the data line Data;
  • a source of the first thin film transistor T1 is respectively connected to a gate and a drain of the matching thin film transistor MTFT and a source of the signal clearing thin film transistor ETFT;
  • a gate of the second thin film transistor T2 is connected to the first control line, a source is connected to a low level output end of the driving power source, and a drain is connected to a gate of the driving thin film transistor DTFT;
  • the gate of the third thin film transistor T3 is connected to the second control line outputting the second control signal S2, the source is connected to the second end of the storage capacitor Cs, and the drain is connected to the high level output terminal of the driving power source.
  • the pixel unit driving circuit is configured to drive an OLED, including a driving thin film transistor DTFT, a matching thin film transistor MTFT, a signal clearing thin film transistor ETFT, a charging control unit 61, and a driving control unit. And a storage capacitor Cs, wherein a gate of the driving thin film transistor DTFT is connected to a first end of the storage capacitor Cs, and is further connected to a high-level output end of the driving power source by the charging control unit 61;
  • the source of the driving thin film transistor DTFT is connected to a high level output terminal of the driving power source, and the drain electrode is connected to the anode of the OLED;
  • the gate and the source of the matching thin film transistor MTFT are connected to the data line Data through the charge control unit 61, and the drain thereof is connected to the second end of the storage capacitor Cs;
  • a gate and a source of the signal clearing thin film transistor ETFT are connected to a second end of the storage capacitor Cs;
  • a drain of the signal clearing thin film transistor ETFT is connected to a gate and a source of the matching thin film transistor MTFT, and is connected to the data line Data through the charging control unit 61;
  • the second end of the storage capacitor Cs is connected to the low-level output end of the driving power source through the driving control unit 62;
  • the driving thin film transistor DTFT, the matching thin film transistor MTFT, and the signal clearing thin film transistor ETFT are p-type TFTs;
  • the output voltage of the high level output terminal of the driving power source is VDD, and the output voltage of the low level output terminal of the driving power source is VSS.
  • the charging control unit 61 includes a first thin film transistor T1 and a second thin film transistor T2, and the driving control unit 62 includes a third Thin film transistor T3;
  • the second end of the storage capacitor Cs is connected to the low-level output terminal of the driving power source through the third thin film transistor T3.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are p-type TFTs;
  • the gate of the first thin film transistor T1 is connected to a first control line outputting the first control signal S1, and the source thereof is connected to the data line Data;
  • a drain of the first thin film transistor T1 is respectively connected to a gate and a source of the matching thin film transistor MTFT and a drain of the signal clearing thin film transistor ETFT;
  • a gate of the second thin film transistor T2 is connected to the first control line, a source is connected to a high level output end of the driving power source, and a drain thereof is connected to a gate of the driving thin film transistor DTFT;
  • the gate of the third thin film transistor T3 is connected to the second control line outputting the second control signal S2, the source thereof is connected to the second end of the storage capacitor Cs, and the drain thereof and the low level of the driving power source The output is connected.
  • FIG. 10 is a diagram showing the output of the first control signal S1 and the data line Data during operation of the pixel unit driving circuit according to the third embodiment of the present invention.
  • T1 and ⁇ 2 are both turned on, and ⁇ 3 is turned off. Since T1 is turned on, the data line Data inputs a very low voltage Vdl; since the ETFT is diode-connected, and the old The signal voltage is much larger than Vdl, so the ETFT is turned on.
  • Vthm is the threshold voltage of MTFT
  • Vgs is the gate-source voltage of DTFT
  • Vthd is the threshold voltage of DTFT
  • Vthe is the threshold voltage of ETFT
  • Vdata is the data voltage
  • VDD is the output voltage of the high-level output of the driving power supply
  • VSS is the output voltage of the low-level output of the driving power supply; it can be found that the current I flowing through the DTFT has nothing to do with the threshold voltage Vth of the DTFT, so that the uniformity of the current can be improved and the brightness can be uniform.
  • FIG. 11 is a timing chart of the first control signal S1, the signal output by the data line Data, and the second control signal S2 during operation of the pixel unit driving circuit according to the sixth embodiment of the present invention, wherein A, B, and C respectively Refers to the first time period, the second time period, and the third time period.
  • the pixel unit driving circuit according to the sixth embodiment of the present invention is in operation: during the first time period, T1, ⁇ 2 are turned on, ⁇ 3 is turned off, the voltage of the DTFT gate is pulled to VDD, and the DTFT is turned off. , the voltage on the data line is Vdh, which is a voltage higher than all Vdata. Since the ETFT is diode-connected, the ETFT is turned on, the potential at point P is charged to Vdh-
  • T1 and T2 are turned on, T3 is turned off, and the voltage on the data line is changed from Vdh to Vdata. Since Vdata is much lower than Vdh, the connection of MTFT forms a diode, MTFT is turned on, and P is passed through MTFT. Discharge the data line until the potential at point P drops to Vdata+
  • Tl, T2 are turned off, T3 is turned on, and the gate of the DTFT is in a floating state, and the potential of the P point jumps from Vdata+
  • Vg VDD + VSS - ( Vdata +
  • Vsg VDD +
  • I K (Vsg -
  • ) 2 (Vdata+
  • Vthm is the threshold voltage of the MTFT
  • Vsg is the voltage difference between the source and the gate of the DTFT
  • Vthd is the threshold voltage of the DTFT
  • Vthe is the threshold voltage of the ETFT
  • Vdata is the data voltage
  • VDD is the driving The output voltage of the high-level output of the power supply
  • VSS is the output voltage of the low-level output of the drive power supply.
  • the most characteristic feature of the pixel unit driving circuit of the present invention is that the principle of matching the TFTs of two identical designs in the same pixel is used to compensate the threshold voltage of the OLED driving tube (in the same pixel, two TFTs of the same design) Because the mutual positions are very close, even under the existing immature process conditions, their process environment is very consistent, so the electrical difference caused by the process is very small, which can be regarded as equivalent, that is, the threshold value of the matched thin film transistor.
  • the voltage Vthm is the same as the threshold voltage Vthd of the driving transistor DTFT).

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Abstract

一种像素单元驱动电路和方法、像素单元以及显示装置，可以提高OLED面板亮度的均匀性。像素单元驱动电路包括驱动薄膜晶体管（DTFT）、匹配薄膜晶体管（MTFT）、信号清除薄膜晶体管（ETFT）、充电控制单元（31）、驱动控制单元（32）和存储电容（Cs）。驱动薄膜晶体管（DTFT）的栅极与存储电容（Cs）的第一端连接并通过充电控制单元（32）与驱动电源（VDD）连接，其源极与驱动电源（VSS）连接，其漏极与OLED连接。信号清除薄膜晶体管（ETFT）的栅极和漏极与存储电容（Cs）的第二端连接，其源极与匹配薄膜晶体管（MTFT）的栅极和漏极连接，并通过充电控制单元（31）与数据线连接。匹配薄膜晶体管（MTFT）的源极与存储电容（Cs）的第二端连接。

Description

一种像素单元驱动电路和方法、 像素单元以及显示装置 技术领域
本发明涉及液晶显示领域， 尤其涉及一种像素单元驱动电路和方法、 像 素单元以及显示装置。 背景技术
AMOLED ( Active Matrix Organic Light Emitting Diode , 有源矩阵有 机发光二极体 ) 能够发光是由于驱动 TFT在饱和状态时产生的电流所驱动。 因为输入相同的灰阶电压时， 不同的临界电压会产生不同的驱动电流， 造成 电流的不一致性。 LTPS (低温多晶硅）制程上 Vth (晶体管阔值电压） 的均 匀性非常差， 同时 Vth也有漂移， 因此传统的 2T1C像素单元驱动电路亮度均 匀性一直很差。
传统的 2T1C像素单元驱动电路如图 1所示， 电路只含有两个 TFT, T1 用作开关， DTFT用于像素驱动。 传统的 2T1C像素单元驱动电路操作也比较 简单，对该 2T1C像素单元驱动电路的控制时序图如图 2所示 ，当扫描线 Scan 上的扫描电平 Vscan为低时， T1开启， 数据线 Data上的灰阶电压 Vdata对电 容 C充电， 当扫描电平 Vscan为高时， T1关断， 电容 C用来保存灰阶电压。 由于 VDD (驱动电源的高电平输出端的输出电压）较高， 因此 DTFT处于饱 和状态， OLED的驱动电流 I=K(Vsg- 1 Vth |)2 = K(VDD - Vdata- 1 Vth |)2 , Vdata为 数据线 Data输出的数据电压， K是与晶体管尺寸和载流子迁移率有关的常数， 一旦 TFT尺寸和工艺确定， K确定。 该 2T1C电路的驱动电流公式中包含了 Vth, 如前所述， 由于 LTPS工艺的不成熟， 即便是同样的工艺参数， 制作出 来的面板不同位置的 TFT的 Vth也有较大差异，导致了同一灰阶电压下 OLED 的驱动电流不一样， 因此该驱动方案下的面板不同位置亮度会有差异， 亮度 均匀性差。 发明内容
本发明提供一种像素单元驱动电路和方法、 像素单元以及显示装置， 以 提高 OLED面板亮度的均匀性。 根据一个方面， 本发明提供了一种像素单元驱动电路， 用于驱动 0LED, 包括驱动薄膜晶体管、 匹配薄膜晶体管、 信号清除薄膜晶体管、 充电控制单 元、 驱动控制单元和存储电容， 其中，
所述驱动薄膜晶体管的栅极与所述存储电容的第一端连接并通过所述充 电控制单元与所述驱动电源的低电平输出端连接， 其源极与驱动电源的低电 平输出端连接， 漏极与所述 OLED的阴极连接；
所述匹配薄膜晶体管的栅极和漏极通过所述充电控制单元与数据线连 接， 源极与所述存储电容的第二端连接；
所述信号清除薄膜晶体管的栅极和漏极与所述存储电容的第二端连接； 所述信号清除薄膜晶体管的源极， 与所述匹配薄膜晶体管的栅极和漏极 连接， 并通过所述充电控制单元与所述数据线连接；
所述存储电容的第二端通过所述驱动控制单元与所述驱动电源的高电平 输出端连接；
所述驱动薄膜晶体管、 所述匹配薄膜晶体管和所述信号清除薄膜晶体管 是 n型 TFT。
根据本发明的一个实施例， 所述充电控制单元包括第一薄膜晶体管和第 二薄膜晶体管， 所述驱动控制单元包括第三薄膜晶体管；
所述匹配薄膜晶体管的栅极和漏极， 以及所述信号清除薄膜晶体管的源 极， 通过所述第一薄膜晶体管与所述数据线连接；
所述驱动薄膜晶体管的栅极通过所述第二薄膜晶体管与所述驱动电源的 低电平输出端连接；
所述存储电容的第二端通过所述第三薄膜晶体管与所述驱动电源的高电 平输出端连接。
根据本发明的一个实施例， 所述第一薄膜晶体管、 所述第二薄膜晶体管 和所述第三薄膜晶体管是 n型 TFT;
所述第一薄膜晶体管的栅极与第一控制线连接， 漏极与所述数据线连接; 所述第一薄膜晶体管的源极， 分别与所述匹配薄膜晶体管的栅极、 漏极 以及所述信号清除薄膜晶体管的源极连接；
所述第二薄膜晶体管的栅极与所述第一控制线连接， 其源极与所述驱动 电源的低电平输出端连接， 漏极与所述驱动薄膜晶体管的栅极连接；
所述第三薄膜晶体管的栅极与第二控制线连接， 其源极与所述存储电容 的第二端连接， 漏极与所述驱动电源的高电平输出端连接。
根据一个方面， 本发明还提供了一种像素单元驱动方法， 应用于上述的 像素单元驱动电路， 所述像素单元驱动方法包括以下步骤：
控制充电控制单元使得信号清除薄膜晶体管开启 , 并且存储电容通过信 号清除薄膜晶体管对数据线放电， 直到所述存储电容的第二端的电压降低到 使得所述信号清除薄膜晶体管关断 , 并且控制充电控制单元使得驱动薄膜晶 体管的栅极下拉到驱动电源的低电平输出端输出的电压 VSS;
控制充电控制单元使得匹配薄膜晶体管开启， 并且所述数据线输出的数 据电压 Vdata对所述存储电容进行充电，直到所述存储电容的第二端的电压上 升至等于所述数据电压与所述匹配薄膜晶体管的阔值电压之差的电压
Vdata- Vthm;
控制所述驱动控制单元使得所述存储电容的第二端的电压上拉到所述驱 动电源的高电平输出端输出的电压 VDD, 并且控制所述充电控制单元使得所 述驱动薄膜晶体管的栅极处于悬空状态， 以使得所述驱动薄膜晶体管导通。
根据一个方面， 本发明还提供了一种像素单元， 其中， 包括 OLED和上 述的像素单元驱动电路， 所述 OLED的阴极与所述像素单元驱动电路中的驱 动薄膜晶体管的漏极连接， 所述 OLED的阳极与驱动电源的高电平输出端连 接。
根据一个方面， 本发明还提供了一种显示装置， 包括上述的像素单元。 根据一个方面，本发明还提供了一种像素单元驱动电路，用于驱动 OLED, 包括驱动薄膜晶体管、 匹配薄膜晶体管、 信号清除薄膜晶体管、 充电控制单 元、 驱动控制单元和存储电容， 其中，
所述驱动薄膜晶体管的栅极与所述存储电容的第一端连接并通过所述充 电控制单元与所述驱动电源的高电平输出端连接， 其源极与驱动电源的高电 平输出端连接， 漏极与所述 OLED的阳极连接；
所述匹配薄膜晶体管的栅极和源极通过所述充电控制单元与数据线连 接， 其漏极与所述存储电容的第二端连接；
所述信号清除薄膜晶体管的栅极和源极与所述存储电容的第二端连接； 所述信号清除薄膜晶体管的漏极， 与所述匹配薄膜晶体管的栅极和源极 连接， 并通过所述充电控制单元与所述数据线连接；
所述存储电容的第二端通过所述驱动控制单元与所述驱动电源的低电平 输出端连接；
所述驱动薄膜晶体管、 所述匹配薄膜晶体管和所述信号清除薄膜晶体管 是 p型 TFT。
根据本发明的一个实施例， 所述充电控制单元包括第一薄膜晶体管和第 二薄膜晶体管， 所述驱动控制单元包括第三薄膜晶体管；
所述匹配薄膜晶体管的栅极和源极， 以及所述信号清除薄膜晶体管的漏 极， 通过所述第一薄膜晶体管与所述数据线连接；
所述驱动薄膜晶体管的栅极通过所述第二薄膜晶体管与所述驱动电源的 高电平输出端连接；
所述存储电容的第二端通过所述第三薄膜晶体管与所述驱动电源的低电 平输出端连接。
根据本发明的一个实施例， 所述第一薄膜晶体管、 所述第二薄膜晶体管 和所述第三薄膜晶体管是 p型 TFT;
所述第一薄膜晶体管的栅极与第一控制线连接， 其源极与所述数据线连 接；
所述第一薄膜晶体管的漏极， 分别与所述匹配薄膜晶体管的栅极、 源极 以及所述信号清除薄膜晶体管的漏极连接；
所述第二薄膜晶体管的栅极与所述第一控制线连接， 其源极与所述驱动 电源的高电平输出端连接， 漏极与所述驱动薄膜晶体管的栅极连接；
所述第三薄膜晶体管的栅极与第二控制线连接， 其源极与所述存储电容 的第二端连接， 漏极与所述驱动电源的低电平输出端连接。
根据一个方面， 本发明还提供了一种像素单元驱动方法， 应用于如上所 述的像素单元驱动电路， 其中， 所述像素单元驱动方法包括以下步骤： 控制充电控制单元使得信号清除薄膜晶体管开启 , 并且数据线通过信号 清除薄膜晶体管对存储电容进行充电， 直到所述存储电容的第二端的电压上 升到使得所述信号清除薄膜晶体管关断， 并且控制充电控制单元使得驱动薄 膜晶体管的栅极上拉到驱动电源的高电平输出端输出的电压 VDD;
控制所述充电控制单元使得匹配薄膜晶体管开启， 并且所述存储电容通 过所述匹配薄膜晶体管对数据线放电， 直到所述存储电容的第二端的电压降 低到等于所述数据线输出的数据电压与所述匹配薄膜晶体管的阔值电压之和 的电压 Vdata+|Vthm|; 控制所述驱动控制单元使得所述存储电容的第二端的电压下拉到所述驱 动电源的低电平输出端输出的电压 VSS, 并且控制所述充电控制单元使得所 述驱动薄膜晶体管的栅极处于悬空状态， 以使得所述驱动薄膜晶体管导通。
本发明还提供了一种像素单元， 包括 OLED和上述的像素单元驱动电路， 所述 OLED的阳极与所述像素单元驱动电路中的驱动薄膜晶体管的漏极连 本发明还提供了一种显示装置， 包括上述的像素单元。
与现有技术相比， 本发明所述的像素单元驱动电路和方法、 像素单元以 及显示装置， 利用同一像素内两个相同设计的 TFT电性较匹配的原理， 补偿 OLED驱动管的临界电压， 改善了 OLED面板亮度不均匀性。 附图说明
图 1是传统的 2T1C像素单元驱动电路的电路图；
图 2是对该传统的 2T1C像素单元驱动电路的控制时序图；
图 3是本发明第一实施例所述的像素单元驱动电路的电路图；
图 4是本发明第二实施例所述的像素单元驱动电路的电路图；
图 5是本发明第三实施例所述的像素单元驱动电路的电路图；
图 6是本发明第四实施例所述的像素单元驱动电路的电路图；
图 7是本发明第五实施例所述的像素单元驱动电路的电路图；
图 8是本发明第六实施例所述的像素单元驱动电路的电路图；
图 9A是本发明第三实施例所述的像素单元驱动电路工作时在第一时间 段的等效电路图；
图 9B 是本发明第三实施例所述的像素单元驱动电路工作时在第二时间 段的等效电路图；
图 9C 是本发明第三实施例所述的像素单元驱动电路工作时在第三时间 段的等效电路图；
图 10是本发明第三实施例所述的像素单元驱动电路在工作时， 第一控制 信号 Sl、 数据线 Data输出的信号以及第二控制信号 S2的时序图；
图 11是本发明第六实施例所述的像素单元驱动电路在工作时， 第一控制 信号 Sl、 数据线 Data输出的信号以及第二控制信号 S2的时序图。 具体实施方式
如图 3所示， 本发明第一实施例所述的像素单元驱动电路， 用于驱动 OLED, 包括驱动薄膜晶体管 DTFT、 匹配薄膜晶体管 MTFT、 信号清除薄膜 晶体管 ETFT、 充电控制单元 31、 驱动控制单元 32和存储电容 Cs, 其中， 所述驱动薄膜晶体管 DTFT的栅极与所述存储电容 Cs的第一端连接， 还 通过所述充电控制单元 31与所述驱动电源的低电平输出端连接；
所述驱动薄膜晶体管 DTFT的源极与驱动电源的低电平输出端连接， 漏 极与所述 OLED的阴极连接；
所述匹配薄膜晶体管 MTFT的栅极和漏极通过所述充电控制单元 31与数 据线 Data连接， 源极与所述存储电容 Cs的第二端连接；
所述信号清除薄膜晶体管 ETFT的栅极和漏极与所述存储电容 Cs的第二 端连接；
所述信号清除薄膜晶体管 ETFT的源极与所述匹配薄膜晶体管 MTFT的 栅极和漏极连接， 并通过所述充电控制单元 31与数据线 Data连接；
所述存储电容 Cs的第二端通过所述驱动控制单元 32与所述驱动电源的 高电平输出端连接；
所述 OLED的阳极与所述驱动电源的高电平输出端连接；
所述驱动薄膜晶体管 DTFT、 所述匹配薄膜晶体管 MTFT和所述信号清 除薄膜晶体管 ETFT是 n型 TFT; 所述驱动电源的高电平输出端的输出电压 为 VDD, 所述驱动电源的低电平输出端的输出电压为 VSS。
如图 4所示， 本发明第二实施例所述的像素单元驱动电路的电路图。 本 发明第二实施例所述的像素单元驱动电路基于本发明第一实施例所述的像素 单元驱动电路。
在本发明第二实施例所述的像素单元驱动电路中， 所述充电控制单元 31 包括第一薄膜晶体管 T1和第二薄膜晶体管 T2, 所述驱动控制单元 32包括第 三薄膜晶体管 T3;
所述匹配薄膜晶体管 MTFT的栅极和漏极， 以及所述信号清除薄膜晶体 管 ETFT的源极， 通过所述第一薄膜晶体管 T1与所述数据线 Data连接； 所述驱动薄膜晶体管 DTFT的栅极通过所述第二薄膜晶体管 T2与所述驱 动电源的低电平输出端连接；
所述存储电容 Cs的第二端通过所述第三薄膜晶体管 T3与所述驱动电源 的高电平输出端连接。
如图 5所示， 本发明第三实施例所述的像素单元驱动电路的电路图。 本 发明第三实施例所述的像素单元驱动电路基于本发明第二实施例所述的像素 单元驱动电路。
在本发明第三实施例所述的像素单元驱动电路中， 所述第一薄膜晶体管
Tl、 所述第二薄膜晶体管 Τ2和所述第三薄膜晶体管 Τ3是 η型 TFT;
所述第一薄膜晶体管 T1的栅极与输出第一控制信号 S1的第一控制线连 接， 其漏极与所述数据线 Data连接；
所述第一薄膜晶体管 T1的源极分别与所述匹配薄膜晶体管 MTFT的栅 极、 漏极以及所述信号清除薄膜晶体管 ETFT的源极连接；
所述第二薄膜晶体管 T2的栅极与所述第一控制线连接， 源极与所述驱动 电源的低电平输出端连接， 漏极与所述驱动薄膜晶体管 DTFT的栅极连接； 所述第三薄膜晶体管 T3的栅极与输出第二控制信号 S2的第二控制线连 接， 源极与所述存储电容 Cs的第二端连接， 漏极与所述驱动电源的高电平输 出端连接。
如图 6所示， 本发明第四实施例所述的像素单元驱动电路， 用于驱动 OLED, 包括驱动薄膜晶体管 DTFT、 匹配薄膜晶体管 MTFT、 信号清除薄膜 晶体管 ETFT、 充电控制单元 61、 驱动控制单元 62和存储电容 Cs, 其中， 所述驱动薄膜晶体管 DTFT的栅极与所述存储电容 Cs的第一端连接， 还 通过所述充电控制单元 61与所述驱动电源的高电平输出端连接；
所述驱动薄膜晶体管 DTFT的源极与驱动电源的高电平输出端连接， 漏 极与所述 OLED的阳极连接；
所述匹配薄膜晶体管 MTFT的栅极和源极通过所述充电控制单元 61与数 据线 Data连接， 其漏极与所述存储电容 Cs的第二端连接；
所述信号清除薄膜晶体管 ETFT的栅极和源极与所述存储电容 Cs的第二 端连接；
所述信号清除薄膜晶体管 ETFT的漏极与所述匹配薄膜晶体管 MTFT的 栅极和源极连接， 并通过所述充电控制单元 61与数据线 Data连接；
所述存储电容 Cs的第二端通过所述驱动控制单元 62与所述驱动电源的 低电平输出端连接； 所述驱动薄膜晶体管 DTFT、 所述匹配薄膜晶体管 MTFT和所述信号清 除薄膜晶体管 ETFT是 p型 TFT;
所述驱动电源的高电平输出端的输出电压为 VDD, 所述驱动电源的低电 平输出端的输出电压为 VSS。
如图 7所示， 在本发明第五实施例所述的像素单元驱动电路中， 所述充 电控制单元 61包括第一薄膜晶体管 T1和第二薄膜晶体管 T2, 所述驱动控制 单元 62包括第三薄膜晶体管 T3;
所述匹配薄膜晶体管 MTFT的栅极和源极， 以及所述信号清除薄膜晶体 管 ETFT的漏极， 通过所述第一薄膜晶体管 T1与所述数据线 Data连接； 所述驱动薄膜晶体管 DTFT的栅极通过所述第二薄膜晶体管 T2与所述驱 动电源的高电平输出端连接；
所述存储电容 Cs的第二端通过所述第三薄膜晶体管 T3与所述驱动电源 的低电平输出端连接。
如图 8所示， 在本发明第六实施例所述的像素单元驱动电路中， 所述第 一薄膜晶体管 Tl、 所述第二薄膜晶体管 Τ2和所述第三薄膜晶体管 Τ3是 ρ型 TFT;
所述第一薄膜晶体管 T1的栅极与输出第一控制信号 S1的第一控制线连 接， 其源极与所述数据线 Data连接；
所述第一薄膜晶体管 T1的漏极分别与所述匹配薄膜晶体管 MTFT的栅 极、 源极以及所述信号清除薄膜晶体管 ETFT的漏极连接；
所述第二薄膜晶体管 T2的栅极与所述第一控制线连接， 源极与所述驱动 电源的高电平输出端连接， 其漏极与所述驱动薄膜晶体管 DTFT的栅极连接； 所述第三薄膜晶体管 T3的栅极与输出第二控制信号 S2的第二控制线连 接， 其源极与所述存储电容 Cs的第二端连接， 其漏极与所述驱动电源的低电 平输出端连接。
下面介绍本发明第三实施例所述的像素单元驱动电路的工作过程： 图 10是本发明第三实施例所述的像素单元驱动电路在工作时， 第一控制 信号 Sl、 数据线 Data输出的信号以及第二控制信号 S2的时序图， 其中， A、 B、 C分别指的是第一时间段、 第二时间段、 第三时间段。
如图 10所示， 本发明第三实施例所述的像素单元驱动电路在工作时， 在第一时间段， 即开始阶段， 如图 9A所示， Tl、 Τ2均开启， Τ3为关断， 由于 T1开启， 数据线 Data输入一个很低的电压 Vdl; 由于 ETFT为二极管连 接， 且旧的信号电压远大于 Vdl, 因此 ETFT开启。 此时由于 T2开启， DTFT 的栅极被下拉为 VSS, DTFT关断； 由于 ETFT开启，存储电容 Cs通过 ETFT 对数据线放电以清除上一帧的信号， 放电直到 P点（即与所述存储电容 Cs的 第二端连接的节点） 的电位 Vp为 Vdl+Vthe, 此时 ETFT关断；
接着在第二时间段， 如图 9B所示， Tl、 Τ2开启，Τ3为关断。 DTFT由于 栅极的下拉仍然关断， 处于工作停止状态； 数据线 Data输出的电压从 Vdl跳 变为 Vdata, 由于 Vdata远大于 Vdl, 因此 MTFT开启， 数据线 Data输出的数 据电压 Vdata对存储电容 Cs 充电， 直到 P 点电位上升为 Vdata-Vthm, Vc=Vg-Vp=VSS- ( Vdata-Vthm );
在第三时间段， 如图 9C所示， Tl、 Τ2关断， Τ3开启， 由于 Ρ点电位由 Vdata-Vthm跳变至 VDD, T2关断， DTFT的栅极处于悬空状态， 因此 G点 (即与 DTFT的栅极和存储电容 Cs的第一端连接的节点 ) 的电位 Vg跳变为 Vg=VSS- ( Vdata-Vthm ) +VDD ,此时 Vgs=Vg-VSS=VSS- ( Vdata-Vthm ) +VDD -VSS=VDD- ( Vdata-Vthm ); DTFT工作， 流过 DTFT的电流 I=K(Vgs-Vthd)2= K(VDD- ( Vdata-Vthm ) -Vthd) 2=K(VDD- Vdata) 2, 其中 Vthm=Vthd; OLED 开始发光， 直到下一帧；
Vthm为 MTFT的阔值电压， Vgs 为 DTFT的栅源电压， Vthd为 DTFT 的阔值电压， Vthe为 ETFT的阔值电压， Vdata为数据电压， VDD为驱动电 源的高电平输出端的输出电压， VSS为驱动电源的低电平输出端的输出电压； 可以发现流过 DTFT的电流 I 和 DTFT的阔值电压 Vth没有关系了 , 如 此可以改善电流的均匀性， 达到亮度的均匀。
图 11是本发明第六实施例所述的像素单元驱动电路在工作时， 第一控制 信号 Sl、 数据线 Data输出的信号以及第二控制信号 S2的时序图， 其中， A、 B、 C分别指的是第一时间段、 第二时间段、 第三时间段。
如图 11所示， 本发明第六实施例所述的像素单元驱动电路在工作时： 第一时间段， Tl、 Τ2开启， Τ3关断， DTFT栅极的电压被拉到 VDD, DTFT关断， 此时数据线上的电压为 Vdh, 该电压是比所有 Vdata高的电压， 由于 ETFT是二极管连接， 因此 ETFT开启， P点电位被充电至 Vdh-|Vthe|,然 后 ETFT关断。
第二时间段，T1、T2开启，T3关断， 数据线上的电压从 Vdh跳变到 Vdata, 由于 Vdata相比 Vdh要低很多， 因此 MTFT的连接形成一个二极管， MTFT 开启， P点通过 MTFT对数据线放电 , 直到 P点电位下降到 Vdata+| Vthm| , 此 时 MTFT关断。
第三时间段， Tl , T2关断， T3开启， 此时 DTFT的栅极处于悬空状态， 而 P点的电位从 Vdata+| Vthm|跳变到 VSS , 因此 G点的电位 Vg的电位也跳 变为 Vg=VDD+VSS- ( Vdata+|Vthm| ), DTFT 的源极和栅极之间的电压差值 Vsg= VDD-Vg= Vdata+| Vthm|-VSS , 流过 DTFT 的电流 I=K(Vsg-|Vthd|)2= (Vdata+|Vthm卜 VSS-|Vthd|)2=(Vdata-VSS)2; 其中， Vthm=Vthd; OLED开始发 光， 直到下一帧；
其中 , Vthm为 MTFT的阔值电压 , Vsg为 DTFT的源极和栅极之间的电 压差值， Vthd为 DTFT的阔值电压， Vthe为 ETFT的阔值电压， Vdata为数 据电压， VDD为驱动电源的高电平输出端的输出电压， VSS为驱动电源的低 电平输出端的输出电压。
本发明所述的像素单元驱动电路的最大特点是利用同一像素内两个相同 设计的 TFT电性较匹配的原理， 补偿 OLED驱动管的临界电压（在同一个像 素内部， 两个相同设计的 TFT由于相互的位置非常接近， 即使在现有的不成 熟的工艺条件下， 它们的工艺环境也非常一致， 因此工艺上引起的电性差异 非常小， 可以视为等同， 即匹配薄膜晶体管的阔值电压 Vthm与驱动管 DTFT 的阔值电压 Vthd相同）。
以上说明对本发明而言只是说明性的， 而非限制性的， 本领域普通技术 人员理解， 在不脱离所附权利要求所限定的精神和范围的情况下， 可做出许 多修改、 变化或等效， 但都将落入本发明的保护范围内。

Claims

权 利 要 求 书
1、 一种像素单元驱动电路， 用于驱动 0LED, 包括驱动薄膜晶体管、 匹 配薄膜晶体管、 信号清除薄膜晶体管、 充电控制单元、 驱动控制单元和存储 电容， 其中，
所述驱动薄膜晶体管的栅极与所述存储电容的第一端连接并通过所述充 电控制单元与所述驱动电源的低电平输出端连接， 其源极与驱动电源的低电 平输出端连接， 漏极与所述 OLED的阴极连接；
所述匹配薄膜晶体管的栅极和漏极通过所述充电控制单元与数据线连 接， 源极与所述存储电容的第二端连接；
所述信号清除薄膜晶体管的栅极和漏极与所述存储电容的第二端连接， 其源极与所述匹配薄膜晶体管的栅极和漏极连接， 并通过所述充电控制单元 与所述数据线连接；
所述存储电容的第二端通过所述驱动控制单元与所述驱动电源的高电平 输出端连接；
所述驱动薄膜晶体管、 所述匹配薄膜晶体管和所述信号清除薄膜晶体管 是 n型 TFT。
2、 如权利要求 1所述的像素单元驱动电路， 其中， 所述充电控制单元包 括第一薄膜晶体管和第二薄膜晶体管， 所述驱动控制单元包括第三薄膜晶体 管；
所述匹配薄膜晶体管的栅极和漏极， 以及所述信号清除薄膜晶体管的源 极， 通过所述第一薄膜晶体管与所述数据线连接；
所述驱动薄膜晶体管的栅极通过所述第二薄膜晶体管与所述驱动电源的 低电平输出端连接；
所述存储电容的第二端通过所述第三薄膜晶体管与所述驱动电源的高电 平输出端连接。
3、如权利要求 2所述的像素单元驱动电路，其中，所述第一薄膜晶体管、 所述第二薄膜晶体管和所述第三薄膜晶体管是 n型 TFT;
所述第一薄膜晶体管的栅极与第一控制线连接，漏极与所述数据线连接; 所述第一薄膜晶体管的源极分别与所述匹配薄膜晶体管的栅极、 漏极以 及所述信号清除薄膜晶体管的源极连接； 所述第二薄膜晶体管的栅极与所述第一控制线连接， 其源极与所述驱动 电源的低电平输出端连接， 其漏极与所述驱动薄膜晶体管的栅极连接；
所述第三薄膜晶体管的栅极与第二控制线连接， 其源极与所述存储电容 的第二端连接， 其漏极与所述驱动电源的高电平输出端连接。
4、 一种像素单元驱动方法， 应用于如权利要求 1所述的像素单元驱动电 路， 其中， 所述像素单元驱动方法包括以下步骤：
控制充电控制单元使得信号清除薄膜晶体管开启 , 并且存储电容通过信 号清除薄膜晶体管对数据线放电， 直到所述存储电容的第二端的电压降低到 使得所述信号清除薄膜晶体管关断 , 并且控制充电控制单元使得驱动薄膜晶 体管的栅极下拉到驱动电源的低电平输出端输出的电压 （VSS );
控制所述充电控制单元使得匹配薄膜晶体管开启， 并且所述数据线输出 的数据电压（Vdata )对所述存储电容进行充电， 直到所述存储电容的第二端 的电压上升至等于所述数据电压与所述匹配薄膜晶体管的阔值电压之差的电 压 ( Vdata- Vthm );
控制所述驱动控制单元使得所述存储电容的第二端的电压上拉到所述驱 动电源的高电平输出端输出的电压（ VDD ) ,并且控制所述充电控制单元使得 所述驱动薄膜晶体管的栅极处于悬空状态，以使得所述驱动薄膜晶体管导通。
5、 一种像素单元， 其中， 包括 OLED和如权利要求 1至 3中任一权利要 求所述的像素单元驱动电路， 所述 OLED的阴极与所述像素单元驱动电路中 的驱动薄膜晶体管的漏极连接， 所述 OLED的阳极与驱动电源的高电平输出 端连接。
6、 一种显示装置， 其中， 包括如权利要求 5所述的像素单元。
7、 一种像素单元驱动电路， 用于驱动 OLED, 其中， 包括驱动薄膜晶体 管、 匹配薄膜晶体管、 信号清除薄膜晶体管、 充电控制单元、 驱动控制单元 和存储电容， 其中，
所述驱动薄膜晶体管的栅极与所述存储电容的第一端连接并通过所述充 电控制单元与所述驱动电源的高电平输出端连接， 其源极与驱动电源的高电 平输出端连接， 漏极与所述 OLED的阳极连接；
所述匹配薄膜晶体管的栅极和源极通过所述充电控制单元与数据线连 接， 其漏极与所述存储电容的第二端连接；
所述信号清除薄膜晶体管的栅极和源极与所述存储电容的第二端连接， 其漏极与所述匹配薄膜晶体管的栅极和源极连接， 并通过所述充电控制单元 与所述数据线连接；
所述存储电容的第二端通过所述驱动控制单元与所述驱动电源的低电平 输出端连接；
所述驱动薄膜晶体管、 所述匹配薄膜晶体管和所述信号清除薄膜晶体管 是 p型 TFT。
8、 如权利要求 7所述的像素单元驱动电路， 其中， 所述充电控制单元包 括第一薄膜晶体管和第二薄膜晶体管， 所述驱动控制单元包括第三薄膜晶体 管；
所述匹配薄膜晶体管的栅极和源极， 以及所述信号清除薄膜晶体管的漏 极， 通过所述第一薄膜晶体管与所述数据线连接；
所述驱动薄膜晶体管的栅极通过所述第二薄膜晶体管与所述驱动电源的 高电平输出端连接；
所述存储电容的第二端通过所述第三薄膜晶体管与所述驱动电源的低电 平输出端连接。
9、如权利要求 8所述的像素单元驱动电路，其中，所述第一薄膜晶体管、 所述第二薄膜晶体管和所述第三薄膜晶体管是 p型 TFT;
所述第一薄膜晶体管的栅极与第一控制线连接，源极与所述数据线连接; 所述第一薄膜晶体管的漏极， 分别与所述匹配薄膜晶体管的栅极、 源极 以及所述信号清除薄膜晶体管的漏极连接；
所述第二薄膜晶体管的栅极与所述第一控制线连接， 其源极与所述驱动 电源的高电平输出端连接， 漏极与所述驱动薄膜晶体管的栅极连接；
所述第三薄膜晶体管的栅极与第二控制线连接， 其源极与所述存储电容 的第二端连接， 漏极与所述驱动电源的低电平输出端连接。
10、 一种像素单元驱动方法， 应用于如权利要求 7所述的像素单元驱动 电路， 其中， 所述像素单元驱动方法包括以下步骤：
控制充电控制单元使得信号清除薄膜晶体管开启 , 并且数据线通过信号 清除薄膜晶体管对存储电容进行充电， 直到所述存储电容的第二端的电压上 升到使得所述信号清除薄膜晶体管关断， 并且控制充电控制单元使得驱动薄 膜晶体管的栅极上拉到驱动电源的高电平输出端输出的电压 （VDD );
控制所述充电控制单元使得匹配薄膜晶体管开启， 并且所述存储电容通 过所述匹配薄膜晶体管对数据线放电， 直到所述存储电容的第二端的电压降 低到等于所述数据线输出的数据电压与所述匹配薄膜晶体管的阔值电压之和 的电压 （ Vdata+|Vthm| );
控制所述驱动控制单元使得所述存储电容的第二端的电压下拉到所述驱 动电源的低电平输出端输出的电压（VSS ), 并且控制所述充电控制单元使得 所述驱动薄膜晶体管的栅极处于悬空状态，以使得所述驱动薄膜晶体管导通。
11、 一种像素单元， 其中， 包括 OLED和如权利要求 7至 9中任一权利 要求所述的像素单元驱动电路， 所述 OLED的阳极与所述像素单元驱动电路 中的驱动薄膜晶体管的漏极连接， 所述 OLED的阴极与驱动电源的低电平输 出端连接。
12、 一种显示装置， 其中， 包括如权利要求 11所述的像素单元。
PCT/CN2012/086019 2012-02-21 2012-12-06 一种像素单元驱动电路和方法、像素单元以及显示装置 Ceased WO2013123795A1 (zh)

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